Voltage converter with improved load transient response speed

Abstract

A voltage converter for improving load transient response speed is characterized in that: the voltage converter includes a load detection unit, a load detection signal processing unit, and a discharge unit; wherein, the load detection unit generates a hysteresis signal based on a comparison of a reference voltage and a feedback voltage, and outputs the hysteresis signal to the load detection signal processing unit; the load detection signal processing unit controls the level of a load enhancement signal based on the hysteresis signal and the PFM signal of the voltage converter, and shields the output of the PFM signal when the load enhancement signal is at a high level, and instructs the discharge unit to discharge the compensation capacitor; the discharge unit conducts discharge under the control of the load detection signal processing unit. This invention achieves stable circuit output during heavy-load to light-load switching at a relatively low cost.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically, to a voltage converter that improves the transient response speed of a load. Background Technology

[0002] DC-DC (Direct Current-to-Direct Current) converters are widely used in integrated circuits as voltage converters capable of transforming input voltage and effectively outputting a fixed voltage. To extend the operating range of voltage converters, some voltage converters incorporate multiple operating modes, such as PWM (Pulse Width Modulation) mode and PFM (Pulse Frequency Modulation) mode. Typically, PWM mode is used when the voltage converter operates under heavy load, while PFM mode is used under light load.

[0003] However, during the brief period of switching between the two modes, the voltage converter's response speed cannot fully keep up with the load changes, which can easily lead to overshoot or undershoot in the output. In addition, for such unstable output, the time required for the voltage converter's output signal to recover to a normal state is also relatively long.

[0004] To address the above problems, there is an urgent need for a voltage converter that can improve the transient response speed of the load. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a voltage converter that improves the transient response speed of a load. This converter controls the accurate switching time of PWM and PFM through a load detection unit, a load detection signal processing unit, and a discharge unit, and discharges the compensation capacitor, thereby avoiding output overshoot and ensuring the stability of the voltage converter.

[0006] The present invention adopts the following technical solution.

[0007] This invention relates to a voltage converter for improving the transient response speed of a load. The voltage converter includes a load detection unit, a load detection signal processing unit, and a discharge unit. The load detection unit generates a hysteresis signal based on a comparison of a reference voltage and a feedback voltage, and outputs the hysteresis signal to the load detection signal processing unit. The load detection signal processing unit controls the level of a load enhancement signal based on the hysteresis signal and the PFM signal of the voltage converter. When the load enhancement signal is at a high level, it shields the output of the PFM signal and instructs the discharge unit to discharge the compensation capacitor. The discharge unit conducts discharge under the control of the load detection signal processing unit.

[0008] Preferably, the load detection unit is located in the error amplifier of the voltage converter; and the hysteresis signal is realized based on the mirror image of the error amplification signal output by the error amplifier.

[0009] Preferably, the load detection unit includes a mirror PMOS transistor, a mirror NMOS transistor, a filter capacitor, and a hysteresis module; wherein, the mirror PMOS transistor is mirror-connected to the PMOS transistor at the output of the error amplifier, the mirror NMOS transistor is mirror-connected to the NMOS transistor at the output of the error amplifier, and the drains of the mirror PMOS transistor and the mirror NMOS transistor are interconnected and connected to the upper plate of the filter capacitor and the input of the hysteresis module; the lower plate of the filter capacitor is grounded, and the output of the hysteresis module outputs a hysteresis signal.

[0010] Preferably, the load detection signal processing unit includes a first AND gate, a second AND gate, a D flip-flop, a counter, a first delay unit, a NOT gate, and a second delay unit; wherein, the input terminals of the first AND gate are respectively connected to the PFM signal and the hysteresis signal, and the output terminal is connected to the input terminal of the second AND gate; the other input terminal of the second AND gate is connected to the output terminal of the first delay unit, and the output terminal of the second AND gate is connected to the clock terminal of the D flip-flop; the D terminal of the D flip-flop is connected to the power supply voltage, the Q terminal is respectively connected to the reset terminal RDN of the counter and the input terminal of the second delay unit, and the output terminal is connected to the input terminal of the NOT gate; the output terminal of the NOT gate is respectively connected to the reset terminal of the D flip-flop and the input terminal of the first delay unit; the output terminal of the second delay unit outputs the load enhancement signal.

[0011] Preferably, the load enhancement signal generated by the load detection signal processing unit is output to the control terminal of the discharge unit and the zero-crossing detection unit respectively; and the discharge unit is simultaneously connected between the upper plate of the compensation capacitor and ground.

[0012] Preferably, when the outputs of both the PFM signal and the hysteresis signal are high, the load enhancement signal is high and remains high until the end of N cycles of the counter; when the outputs of either the PFM signal or the hysteresis signal are low, the load enhancement signal is low.

[0013] Preferably, when the load enhancement signal is in a low-level state, it does not affect the output of the voltage converter.

[0014] Preferably, when the load enhancement signal is at a high level, the discharge unit is turned on, and the inductor current threshold of the zero-crossing detection unit is reduced.

[0015] Preferably, the load enhancement signal generated by the load detection signal processing unit is also input into the logic unit simultaneously with the PFM signal through an OR gate, so as to realize the switching of the voltage converter between PFM and PWM modes.

[0016] The beneficial effects of this invention are that, compared with the prior art, the voltage converter of this invention improves the transient response speed of the load. This converter controls the accurate switching time of PWM and PFM through a load detection unit, a load detection signal processing unit, and a discharge unit, respectively, and discharges the compensation capacitor, thereby avoiding output overshoot and ensuring the stability of the voltage converter. The circuit structure of this invention is simple and the concept is clear. It makes full use of the existing circuits of voltage converters in the prior art, achieving output stability during the heavy-load to light-load switching process at a relatively low cost. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the circuit structure of a voltage converter in the prior art;

[0018] Figure 2 This is a signal timing diagram of a voltage converter in the prior art during the transition from heavy load to light load.

[0019] Figure 3 This is a schematic diagram of the circuit structure of a voltage converter for improving the transient response speed of a load according to the present invention;

[0020] Figure 4 This is a schematic diagram of the circuit structure of the error amplifier in a voltage converter for improving the transient response speed of a load according to the present invention;

[0021] Figure 5 This is a schematic diagram of the circuit structure of the load detection signal processing unit in a voltage converter for improving load transient response speed according to the present invention;

[0022] Figure 6 This is a signal timing diagram of a voltage converter for improving load transient response speed during the transition from heavy load to light load, as described in this invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this invention. The embodiments described in this invention are merely some embodiments of this invention, and not all embodiments. Based on the spirit of this invention, all other embodiments not described in this invention obtained by those skilled in the art based on the embodiments described in this invention without creative effort should fall within the protection scope of this invention.

[0024] Figure 1 This is a schematic diagram of the circuit structure of a voltage converter in the prior art. For example... Figure 1As shown, in the prior art, voltage converters require a feedback loop to control the output signal in order to achieve a relatively stable output voltage. The feedback circuit of a pre-improved voltage converter, similar to the improved voltage converter in this invention, typically includes an error amplifier, a first comparator, a second comparator, a third comparator, a zero-crossing detection unit, and a second delay unit. The output signal Vea of ​​the error amplifier is input to the positive inverting inputs of the first, second, and third comparators, respectively. The negative inverting inputs of the first and second comparators are connected to a slope compensation signal Vslope. The output of the first comparator Comp1 is processed by a driver and logical module to determine whether the voltage comparator enters Buck mode, while the output of the second comparator Comp2 is processed by the same module to determine whether it enters Boost mode. Additionally, the negative inverting input of the third comparator is connected to a clamping voltage Vclamp, which serves as a reference to determine whether the circuit operates in PFM or PWM mode.

[0025] Figure 2 This is a signal timing diagram of a voltage converter in the prior art during the transition from heavy load to light load. For example... Figure 2 As shown, when the circuit switches between PFM and PWM modes, a slow response time occurs. Specifically, when the load connected to the circuit changes from heavy to light, the circuit switches from PWM mode to PFM mode. After the switch, limited by the circuit's duty cycle, the inductor current slowly decreases until it reaches the appropriate inductor current for PFM mode and remains stable. However, because the inductor current repeatedly decreases and increases over multiple cycles, the output voltage overshoots at the switching moment and takes some time to return to stability.

[0026] To address the above problems, the present invention provides an improved voltage converter.

[0027] Figure 3 This is a schematic diagram of the circuit structure of a voltage converter for improving the transient response speed of a load according to the present invention. Figure 3 As shown, this invention relates to a voltage converter for improving the transient response speed of a load. The voltage converter includes a load detection unit, a load detection signal processing unit, and a discharge unit. The load detection unit generates a hysteresis signal based on a comparison of a reference voltage and a feedback voltage, and outputs the hysteresis signal to the load detection signal processing unit. The load detection signal processing unit controls the level of a load enhancement signal based on the hysteresis signal and the PFM signal of the voltage converter. When the load enhancement signal is at a high level, it shields the output of the PFM signal and instructs the discharge unit to discharge the compensation capacitor. The discharge unit conducts discharge under the control of the load detection signal processing unit.

[0028] It is understood that the load detection signal processing unit and the discharge unit in this invention are respectively Figure 3 The load detection unit processes and discharges the load detection signal. The output of the load detection unit is represented by a sleep signal.

[0029] Preferably, the load detection unit is located in the error amplifier of the voltage converter; and the hysteresis signal is realized based on the mirror image of the error amplification signal output by the error amplifier.

[0030] Figure 4 This is a schematic diagram of the circuit structure of the error amplifier in a voltage converter for improving the transient response speed of a load, according to the present invention. Figure 4 As shown, the improved error amplifier in this invention not only includes a general input pair and output terminal, but also adds a load detection unit on the output terminal side.

[0031] Preferably, the load detection unit includes a mirror PMOS transistor, a mirror NMOS transistor, a compensation capacitor, and a delay module; wherein, the mirror PMOS transistor is mirror-connected to the PMOS transistor at the output of the error amplifier, the mirror NMOS transistor is mirror-connected to the NMOS transistor at the output of the error amplifier, and the drains of the mirror PMOS transistor and the mirror NMOS transistor are interconnected and connected to the upper plate of the filter capacitor and the input of the hysteresis module; the lower plate of the filter capacitor is grounded, and the output of the hysteresis module outputs a hysteresis signal.

[0032] Understandably, the load sensing unit can be mirrored with the PMOS transistor Mp2 and NMOS transistor Mn3 that implement the output of the error amplifier. In this way, the load sensing unit can obtain a proportional current on Mp2 and Mn3, which allows the load sensing unit to obtain the relationship between the output voltage divider VFB and the reference voltage of the error amplifier.

[0033] Under the control of this load detection unit, when the load switches from heavy load to light load, the converter's output voltage rises rapidly, and VFB rises synchronously. By setting appropriate ratios for MP2 and MP3, and MN3 and MN4, Sleep can be set to high when the output exceeds a certain value, and appropriate hysteresis can be set to avoid repeated switching. Therefore, when the load switches from heavy load to light load, the converter's output voltage rises rapidly, VFB rises synchronously, and Sleep outputs 1.

[0034] Figure 5 This is a schematic diagram of the circuit structure of the load detection signal processing unit in a voltage converter for improving load transient response speed according to the present invention. Figure 5As shown, preferably, the load detection signal processing unit includes a first AND gate, a second AND gate, a D flip-flop, a counter, a first delay unit, a NOT gate, and a second delay unit; wherein, the input terminals of the first AND gate are respectively connected to the PFM signal and the hysteresis signal, and the output terminal is connected to the input terminal of the second AND gate; the other input terminal of the second AND gate is connected to the output terminal of the first delay unit, and the output terminal of the second AND gate is connected to the clock terminal of the D flip-flop; the D terminal of the D flip-flop is connected to the power supply voltage, the Q terminal is respectively connected to the reset terminal RDN of the counter and the input terminal of the second delay unit, and the output terminal is connected to the input terminal of the NOT gate; the output terminal of the NOT gate is respectively connected to the reset terminal of the D flip-flop and the input terminal of the first delay unit; the output terminal of the second delay unit outputs the load enhancement signal.

[0035] It is understood that the load detection signal processing unit in this invention can selectively shield the PFM signal based on the hysteresis signal generated by the load detection unit, thereby extending the time the circuit is in PWM working mode, so that the change of inductor current is not greatly restricted, thereby allowing the output capacitor to discharge charge quickly enough, and improving the transient response speed of the voltage converter for load changes.

[0036] Preferably, when the outputs of both the PFM signal and the hysteresis signal are high, the load enhancement signal is high and remains high until the end of N cycles of the counter; when the outputs of either the PFM signal or the hysteresis signal are low, the load enhancement signal is low.

[0037] It's easy to understand that when either PFM or Sleep is low, the D flip-flop outputs Q = load_enhance, which is 0, the counter stops counting, and outputs 0; Rset is 1; this does not affect the system's operating mode. When both PFM and Sleep are high, the D flip-flop outputs Q, which is 1, and load_enhance = 1; the counter starts counting; after the counter has counted for N cycles, count outputs 1, then Rset is 0, setting the D flip-flop, Q = 0; Q = 0 resets the counter count, outputting 0, and Rset returns to 1; if PFM and Sleep are still detected to be high at this time, load_enhance remains 1, and the D flip-flop samples and outputs 1; count starts the next round of counting, and after N cycles, PFM and Sleep are checked again; if Sleep or PFM is detected to be low, counting stops, and load_enhance is 0.

[0038] Preferably, the load enhancement signal generated by the load detection signal processing unit is output to the control terminal of the discharge unit and the zero-crossing detection unit, respectively; and the discharge unit is simultaneously connected between the upper plate of the compensation capacitor and ground. When the load enhancement signal is in a high-level state, the discharge unit is turned on, and the inductor current threshold of the zero-crossing detection unit decreases.

[0039] like Figure 3 As shown, in this voltage converter, the load detection signal processing unit generates a load enhancement signal, load_enhance, which is input to the zero-crossing detection unit and the discharge unit, respectively.

[0040] The discharge unit can be composed of a simple switching transistor or a bias current. For example, the load_enhance signal can be used to control the conduction or cutoff of the discharge unit. When the load_enhance signal is high, the discharge unit will be turned on, thereby achieving discharge at its connection point. In the circuit of this invention, the voltage of the compensation capacitor C will be rapidly discharged, accelerating the decrease of Vea, thereby reducing the system duty cycle and causing the inductor current to decrease rapidly.

[0041] On the other hand, zero-crossing detection units are typically used to control the switching transistors in a voltage converter through logic units. Zero-crossing detection units, a common module in voltage converters in the prior art, are used to detect the magnitude of the inductor current and control the state switching of the switching transistors in the voltage converter based on the magnitude of the inductor current, such as controlling the on and off times of the switching transistors in each cycle. Normally, the zero-crossing detection unit switches the switching transistors on and off when the inductor current is equal to 0. However, in this invention, the threshold value of the inductor current is switched under the control of the load_enhance signal.

[0042] Specifically, when the load boosting signal is at a high level, the inductor current threshold of the zero-crossing detection unit decreases. At this time, when the inductor current can reach a more negative value, the circuit can discharge excess charge on the output voltage to ground through the negative inductor current.

[0043] Preferably, the load enhancement signal generated by the load detection signal processing unit is also input into the logic unit simultaneously with the PFM signal through an OR gate, so as to realize the switching of the voltage converter between PFM and PWM modes.

[0044] It is understood that the present invention adds an OR gate at the output of the third comparator. This OR gate receives the load enhancement signal and the PFM signal respectively. Therefore, after load_enhance outputs 1, the PFM signal will be blocked, preventing the system from entering PFM mode and keeping it in PWM mode. This prevents the inductor current from stopping and may even reach a negative value, forcing the output capacitor to discharge charge.

[0045] Figure 6 This is a signal timing diagram of a voltage converter for improving load transient response speed during the transition from heavy load to light load, according to the present invention. Figure 6 As shown, after the improvement of the circuit of the present invention, when the load changes from heavy load to light load, the circuit will still maintain the PWM working mode during the time period between the two vertical dotted lines. At this time, the threshold of the zero-crossing detection unit is reduced to negative, and the inductor current IL can be reduced rapidly. As a result of this improvement, the output voltage Vout of the circuit will no longer remain in the overshoot state for a long time. After a short overshoot, Vout quickly returns to the normal state.

[0046] Preferably, when the load enhancement signal is in a low-level state, it does not affect the output of the voltage converter.

[0047] Under the action of the first delay unit, if the duration of PFM is short, the Sleep signal will also shield the load_enhance signal from rising briefly, thereby preventing the load_enhance signal from causing the compensation capacitor to discharge or the output voltage to drop too quickly, thus ensuring the stability of the output voltage from the opposite perspective.

[0048] The beneficial effects of this invention are that, compared with the prior art, the voltage converter of this invention improves the transient response speed of the load. This converter controls the accurate switching time of PWM and PFM through a load detection unit, a load detection signal processing unit, and a discharge unit, respectively, and discharges the compensation capacitor, thereby avoiding output overshoot and ensuring the stability of the voltage converter. The circuit structure of this invention is simple and the concept is clear. It makes full use of the existing circuits of voltage converters in the prior art, achieving output stability during the heavy-load to light-load switching process at a relatively low cost.

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A voltage converter for improving load transient response speed, characterized in that: The voltage converter includes a load detection unit, a load detection signal processing unit, and a discharge unit; wherein... The load detection unit generates a hysteresis signal based on the comparison between the reference voltage and the feedback voltage, and outputs the hysteresis signal to the load detection signal processing unit. The load detection signal processing unit controls the level of the load enhancement signal based on the hysteresis signal and the PFM signal of the voltage converter, and shields the output of the PFM signal when the load enhancement signal is at a high level, and instructs the discharge unit to discharge the compensation capacitor. The discharge unit is turned on and discharged under the control of the load detection signal processing unit.

2. A voltage converter for improving load transient response speed according to claim 1, characterized in that: The load detection unit is disposed in the error amplifier of the voltage converter; The hysteresis signal is realized based on the mirror image of the error amplification signal output by the error amplifier.

3. A voltage converter for improving load transient response speed according to claim 2, characterized in that: The load detection unit includes a mirrored PMOS transistor, a mirrored NMOS transistor, a filter capacitor, and a hysteresis module; wherein... The mirrored PMOS transistor is mirror-connected to the PMOS transistor at the output of the error amplifier, and the mirrored NMOS transistor is mirror-connected to the NMOS transistor at the output of the error amplifier. The drains of the mirrored PMOS transistor and the mirrored NMOS transistor are connected to each other and connected to the upper plate of the filter capacitor and the input of the hysteresis module. The lower plate of the filter capacitor is grounded, and the output terminal of the hysteresis module outputs a hysteresis signal.

4. A voltage converter for improving load transient response speed according to claim 3, characterized in that: The load detection signal processing unit includes a first AND gate, a second AND gate, a D flip-flop, a counter, a first delay unit, a NOT gate, and a second delay unit; wherein... The input terminals of the first AND gate are respectively connected to the PFM signal and the hysteresis signal, and the output terminal is connected to the input terminal of the second AND gate; The other input of the second AND gate is connected to the output of the first delay unit, and the output of the second AND gate is connected to the clock terminal of the D flip-flop. The D terminal of the D flip-flop is connected to the power supply voltage, the Q terminal is connected to the reset terminal of the counter and the input terminal of the second delay unit, and the output terminal is connected to the input terminal of the NOT gate. The output of the NOT gate is connected to the reset terminal of the D flip-flop and the input terminal of the first delay unit, respectively. The second delay unit outputs the load enhancement signal.

5. A voltage converter for improving load transient response speed according to claim 4, characterized in that: The load enhancement signal generated by the load detection signal processing unit is output to the control terminal of the discharge unit and the zero-crossing detection unit, respectively; and... The discharge unit is simultaneously connected between the upper plate of the compensation capacitor and ground.

6. A voltage converter for improving load transient response speed according to claim 5, characterized in that: When the outputs of the PFM signal and the hysteresis signal are both high, the load enhancement signal is high and remains high until the N cycles of the counter end. When the output of the PFM signal or the hysteresis signal is low, the load enhancement signal is low.

7. A voltage converter for improving load transient response speed according to claim 6, characterized in that: When the load enhancement signal is in a low-level state, it does not affect the output of the voltage converter.

8. A voltage converter for improving load transient response speed according to claim 6, characterized in that: When the load enhancement signal is at a high level, the discharge unit is turned on, and the inductor current threshold of the zero-crossing detection unit is reduced.

9. A voltage converter for improving load transient response speed according to claim 6, characterized in that: The load enhancement signal generated by the load detection signal processing unit is also input into the logic unit simultaneously with the PFM signal through an OR gate, so as to realize the switching of the voltage converter between PFM and PWM modes.

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