Drive circuit and operational amplifier

Abstract

The application discloses a driving circuit and an operational amplifier, and the driving circuit comprises a main operational amplifier first-stage output circuit, a bias control circuit and a driving circuit; the main operational amplifier first-stage output circuit is electrically connected with the bias control circuit; the bias control circuit is electrically connected with the driving circuit; the main operational amplifier first-stage output circuit is used for amplifying an input voltage to obtain a reference voltage; the bias control circuit is used for receiving the reference voltage and controlling an output voltage based on the reference voltage to control a power supply voltage; and the driving circuit is used for outputting the output voltage. The application not only realizes the basic function of the driving circuit, but also reduces the minimum working voltage and static power consumption of the driving circuit.

Description

Technical Field

[0001] This invention relates to the field of operational amplifier technology, and more particularly to a driving circuit and an operational amplifier. Background Technology

[0002] Currently, portable electronic products have become mainstream consumer products. To extend battery life, IC (Integrated Circuit Chip) products are developing towards lower voltage and lower power consumption, resulting in increasingly lower power supply voltages. However, the threshold voltage of transistors has not decreased significantly, posing a major challenge to analog circuit design. Furthermore, lowering the power supply voltage also reduces circuit power consumption. Due to noise and offset limitations, the smallest possible devices cannot be used. Moreover, the reduction in power supply voltage forces a significant decrease in the dynamic range, circuit speed, and other performance characteristics of analog circuits, thus making circuit design more complex.

[0003] Operational amplifiers, as the most basic unit in most analog systems, are widely used in many mixed signal processing circuits. Traditional amplifier structures can no longer meet the output requirements due to the reduced supply voltage. Therefore, it is necessary to redesign a driver circuit to meet the usage requirements of operational amplifiers. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the defects of high minimum operating voltage and high static power consumption of the power supply of the driving circuit in the prior art, and to provide a driving circuit and operational amplifier.

[0005] The present invention solves the above-mentioned technical problems through the following technical solution:

[0006] This invention provides a driving circuit, the driving circuit comprising:

[0007] Main operational amplifier first-stage output circuit, bias control circuit, and drive circuit;

[0008] The first-stage output circuit of the main operational amplifier is electrically connected to the bias control circuit.

[0009] The bias control circuit is electrically connected to the drive circuit.

[0010] The first stage output circuit of the main operational amplifier is used to amplify the input voltage to obtain a reference voltage;

[0011] The bias control circuit is used to receive the reference voltage and control the output voltage based on the reference voltage to control the power supply voltage.

[0012] The drive circuit is used to output the output voltage.

[0013] Preferably, the bias control circuit includes a differential operational amplifier circuit and a current acquisition circuit;

[0014] The differential operational amplifier circuit is electrically connected to the current acquisition circuit;

[0015] The differential operational amplifier circuit is used to receive the reference voltage and obtain the voltage difference based on the reference voltage;

[0016] The differential operational amplifier circuit is also used to feed the voltage difference back to the first stage output circuit of the main operational amplifier;

[0017] The current acquisition circuit is used to acquire the current in the drive circuit.

[0018] Preferably, the differential operational amplifier circuit includes a comparator;

[0019] The comparator includes a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor;

[0020] The source of the fifth NMOS transistor is electrically connected to the source of the sixth NMOS transistor and the drain of the seventh NMOS transistor, respectively.

[0021] The source of the seventh NMOS transistor is grounded.

[0022] Preferably, the differential operational amplifier circuit further includes a fifth PMOS transistor and a sixth PMOS transistor;

[0023] The drain of the fifth PMOS transistor and the drain of the fifth NMOS transistor are electrically connected;

[0024] The drain of the sixth PMOS transistor and the drain of the sixth NMOS transistor are electrically connected;

[0025] The source of the fifth PMOS transistor and the sixth PMOS transistor are both connected to the power supply.

[0026] Preferably, the current acquisition circuit includes a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, an eighth NMOS transistor, a first resistor, and a second resistor;

[0027] The source of the seventh PMOS transistor, the source of the eighth PMOS transistor, the ninth PMOS transistor, and the tenth PMOS transistor are all connected to the power supply.

[0028] The drain of the seventh PMOS transistor and the gate of the twelfth PMOS transistor are electrically connected.

[0029] The drain of the eighth PMOS transistor is electrically connected to the source of the twelfth PMOS transistor and the source of the thirteenth PMOS transistor, respectively.

[0030] The gate of the twelfth PMOS transistor is electrically connected to the first resistor.

[0031] The gate of the thirteenth PMOS transistor is electrically connected to the second resistor;

[0032] The gate of the ninth PMOS transistor is electrically connected to the gate and drain of the tenth PMOS transistor, respectively.

[0033] The source of the twelfth PMOS transistor, the source of the thirteenth PMOS transistor, and the gate of the sixth NMOS transistor are electrically connected.

[0034] The first resistor, the drain of the twelfth PMOS transistor, the drain of the thirteenth PMOS transistor, the second resistor, and the source of the eighth NMOS transistor are all grounded.

[0035] Preferably, the first-stage output circuit of the main operational amplifier includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;

[0036] Both the first PMOS transistor and the second PMOS transistor are electrically connected to the power supply;

[0037] The drain of the first PMOS transistor is electrically connected to the source of the third PMOS transistor;

[0038] The drain of the second PMOS transistor is electrically connected to the source of the fourth PMOS transistor;

[0039] The drain of the third PMOS transistor is electrically connected to the drain of the third NMOS transistor.

[0040] The drain of the fourth PMOS transistor is electrically connected to the drain of the fourth NMOS transistor.

[0041] The source of the third NMOS transistor is electrically connected to the drain of the first NMOS transistor;

[0042] The source of the fourth NMOS transistor and the drain of the second NMOS transistor are electrically connected;

[0043] The source of the third PMOS transistor is electrically connected to the drain of the fifth PMOS transistor;

[0044] The source of the fourth PMOS transistor is electrically connected to the drain of the sixth PMOS transistor.

[0045] The source of the first NMOS transistor and the source of the second NMOS transistor are grounded.

[0046] Preferably, the driving circuit includes an eleventh PMOS transistor and a ninth NMOS transistor;

[0047] The source of the eleventh PMOS transistor is electrically connected to the power supply;

[0048] The gate of the eleventh PMOS transistor is electrically connected to the gate of the seventh PMOS transistor, the drain of the third PMOS transistor, and the drain of the third NMOS transistor.

[0049] The gate of the ninth NMOS transistor is electrically connected to the gate of the eighth NMOS transistor, the drain of the fourth PMOS transistor, and the drain of the fourth NMOS transistor, respectively.

[0050] The drains of the eleventh PMOS transistor and the ninth NMOS transistor are both electrically connected to the output terminal.

[0051] The present invention also provides an operational amplifier, the operational amplifier including the driving circuit as described above.

[0052] The positive and progressive effects of this invention are as follows:

[0053] This invention provides a driver circuit and an operational amplifier. The driver circuit not only implements the basic functions of a driver circuit but also reduces the minimum operating voltage and static power consumption. Furthermore, by superimposing the current of the bias control circuit with the current source of the main circuit, the bias control circuit only needs to control the current of one of the devices, either the eleventh PMOS transistor mp11 or the ninth NMOS transistor mn9. The current of the other device can be controlled by the main operational amplifier control loop, simplifying the complexity of the bias control circuit. In addition, the DC current in the eleventh PMOS transistor mp11 and the ninth NMOS transistor mn9 can be flexibly adjusted using three parameters: Vref, the voltage drop across the first resistor R1, and the mirror current ratio (i.e., the mirror current ratio between the eleventh PMOS transistor mp11 and the seventh PMOS transistor mp7, and the mirror current ratio between the ninth NMOS transistor mn9 and the eighth NMOS transistor mn8). Adjusting any one or any combination of these parameters will yield the required DC current values ​​for the eleventh PMOS transistor mp11 and the ninth NMOS transistor mn9. Attached Figure Description

[0054] Figure 1 This is a circuit structure diagram of the driving circuit of Embodiment 1 of the present invention. Detailed Implementation

[0055] The present invention will be further illustrated by way of embodiments below, but the present invention is not limited to the scope of the embodiments described herein.

[0056] Example 1

[0057] like Figure 1 As shown, this embodiment provides a driving circuit, which includes:

[0058] Main operational amplifier first-stage output circuit, bias control circuit, and drive circuit;

[0059] The first-stage output circuit of the main operational amplifier is electrically connected to the bias control circuit.

[0060] Specifically, the bias control circuit includes a differential operational amplifier circuit and a current acquisition circuit; the differential operational amplifier circuit is electrically connected to the current acquisition circuit; the differential operational amplifier circuit is used to receive the reference voltage and obtain the voltage difference based on the reference voltage; the differential operational amplifier circuit is also used to feed the voltage difference back to the first stage output circuit of the main operational amplifier; the current acquisition circuit is used to acquire the current in the drive circuit.

[0061] The differential operational amplifier circuit includes a comparator; the comparator includes a fifth NMOS transistor mn5, a sixth NMOS transistor mn6, and a seventh NMOS transistor mn7; the source of the fifth NMOS transistor mn5 is electrically connected to the source of the sixth NMOS transistor mn6 and the drain of the seventh NMOS transistor mn7, respectively; the source of the seventh NMOS transistor mn7 is grounded.

[0062] The differential operational amplifier circuit further includes a fifth PMOS transistor mp5 and a sixth PMOS transistor mp6; the drain of the fifth PMOS transistor mp5 and the drain of the fifth NMOS transistor mp5 are electrically connected; the drain of the sixth PMOS transistor mp6 and the drain of the sixth NMOS transistor mn6 are electrically connected; the source of the fifth PMOS transistor mp5 and the sixth PMOS transistor mp6 are both connected to a power supply.

[0063] The bias control circuit is electrically connected to the drive circuit.

[0064] The first stage output circuit of the main operational amplifier is used to amplify the input voltage to obtain a reference voltage;

[0065] Specifically, the first-stage output circuit of the main operational amplifier includes a first PMOS transistor mp1, a second PMOS transistor mp2, a third PMOS transistor mp3, a fourth PMOS transistor mp4, a first NMOS transistor mn1, a second NMOS transistor mn2, a third NMOS transistor mn3, and a fourth NMOS transistor mn4; the first PMOS transistor mp1 and the second PMOS transistor mp2 are both electrically connected to the power supply; the drain of the first PMOS transistor mp1 is electrically connected to the source of the third PMOS transistor mp3; the drain of the second PMOS transistor mp2 is electrically connected to the source of the fourth PMOS transistor mp4; the drain of the third PMOS transistor mp3 is electrically connected to the source of the fourth PMOS transistor mp4; and the drain of the third PMOS transistor mp3 is electrically connected to the source of the fourth PMOS transistor mp4. The drain of the third NMOS transistor mn3 is electrically connected; the drain of the fourth PMOS transistor mp4 is electrically connected to the drain of the fourth NMOS transistor mn4; the source of the third NMOS transistor mn3 is electrically connected to the drain of the first NMOS transistor mn1; the source of the fourth NMOS transistor mn4 is electrically connected to the drain of the second NMOS transistor mn2; the source of the third PMOS transistor mp3 is electrically connected to the drain of the fifth PMOS transistor mp5; the source of the fourth PMOS transistor mp4 is electrically connected to the drain of the sixth PMOS transistor mp6; the source of the first NMOS transistor mn1 and the source of the second NMOS transistor mn2 are grounded.

[0066] The bias control circuit is used to receive the reference voltage and control the output voltage based on the reference voltage to control the power supply voltage.

[0067] The drive circuit is used to output the output voltage.

[0068] Specifically, the driving circuit includes an eleventh PMOS transistor mp11 and a ninth NMOS transistor mn9. The source of the eleventh PMOS transistor mp11 is electrically connected to the power supply. The gate of the eleventh PMOS transistor mp11 is electrically connected to the gate of the seventh PMOS transistor mp7, the drain of the third PMOS transistor mp3, and the drain of the third NMOS transistor mn3. The gate of the ninth NMOS transistor mn3 is electrically connected to the gate of the eighth NMOS transistor mn8, the drain of the fourth PMOS transistor mp4, and the drain of the fourth NMOS transistor mn4. The drains of the eleventh PMOS transistor mp11 and the ninth NMOS transistor mn9 are both electrically connected to the output terminal.

[0069] Figure 1 The working principle of the driving circuit shown is as follows: the first PMOS transistor mp1, the second PMOS transistor mp2, the third PMOS transistor mp3, the fourth PMOS transistor mp4, the first NMOS transistor mn1, the second NMOS transistor mn2, the third NMOS transistor mn3, and the fourth NMOS transistor mn4 are the fold cascode structure of the main operational amplifier.

[0070] The fifth PMOS transistor mp5, the sixth PMOS transistor mp6, the fifth NMOS transistor mn5, and the sixth NMOS transistor mn6 form a unipolar operational amplifier. The eleventh PMOS transistor mp11 and the ninth NMOS transistor mn9, which are used to set the bias control circuit, provide DC bias current. The fifth NMOS transistor mn5 and the sixth NMOS transistor mn6 form a differential input pair. The fifth PMOS transistor mp5 and the sixth PMOS transistor mp6 form an output gain load.

[0071] The seventh PMOS transistor mp7 and the first resistor R1 are DC mirror currents of the eleventh PMOS transistor mp11, which are converted into voltages. The seventh PMOS transistor mp7 mirrors the channel current of the eleventh PMOS transistor mp11, and the first resistor R1 converts the channel current of the seventh PMOS transistor mp7 into voltages.

[0072] The eighth NMOS transistor mn8, the ninth PMOS transistor mp9, the tenth PMOS transistor mp10, and the second resistor R2 convert the DC current mirrored by the ninth PMOS transistor mp9 into voltage. The ninth PMOS transistor mp9 and the tenth PMOS transistor mp10 are current mirror sources. The eighth NMOS transistor mn8 mirrors the channel current of the ninth NMOS transistor mn9, and the second resistor R2 converts the channel current of the eighth NMOS transistor mn8 into voltage.

[0073] The twelfth PMOS transistor mp12 and the thirteenth PMOS transistor mp13 form a follower, which follows the voltage drop across the first resistor R1 and the second resistor R2.

[0074] Specifically, if the DC current of the eleventh PMOS transistor mp11 is low, the current mirrored to the seventh PMOS transistor mp7 will also be proportionally low, resulting in a low voltage across the first resistor R1. The output voltage of the twelfth PMOS transistor mp12, i.e., the gate voltage of the sixth NMOS transistor mn6, will be lower than Vref, i.e., the gate voltage of the fifth NMOS transistor mn5. Because the total current flowing through the fifth NMOS transistor mn5 and the sixth NMOS transistor mn6 remains constant, and the load impedances of the fifth PMOS transistor mp5 and the sixth PMOS transistor mp6 are equal, the current of the sixth NMOS transistor mn6 is less than the current of the fifth NMOS transistor mn5. Furthermore, because the currents of the first PMOS transistor mp1 and the second PMOS transistor mp2 are equal, the current of the third PMOS transistor mp3 is less than the current of the fourth PMOS transistor mp4. Meanwhile, the currents of the first NMOS transistor mn1 and the second NMOS transistor mn2 remain constant, causing the gate voltage of the seventh PMOS transistor mp7 to decrease and the gate voltage of the eighth NMOS transistor mn8 to increase. The decrease in the gate voltage of the seventh PMOS transistor mp7 causes the AC current to increase, resulting in a voltage drop across the first resistor R1. Consequently, the gate voltage of the sixth NMOS transistor mn6 also increases, making the gate voltage of the sixth NMOS transistor mn6 equal to the gate voltage of the fifth NMOS transistor mn5, i.e., Vref.

[0075] Conversely, if the DC current of the eleventh PMOS transistor mp11 is too high, the current mirrored to the seventh PMOS transistor mp7 will also be proportionally higher, resulting in a higher voltage across the first resistor R1. The output voltage of the twelfth PMOS transistor mp12, i.e., the gate voltage of the sixth NMOS transistor mn6, will be higher than Vref, i.e., the gate voltage of the fifth NMOS transistor mn5. Because the total current flowing through the fifth NMOS transistor mn5 and the sixth NMOS transistor mn6 remains constant, and the load impedances of the fifth PMOS transistor mp5 and the sixth PMOS transistor mp6 are equal, the current of the sixth NMOS transistor mn6 is greater than the current of the fifth NMOS transistor mn5. Furthermore, because the currents of the first PMOS transistor mp1 and the second PMOS transistor mp2 are equal, the current of the third PMOS transistor mp3 is greater than the current of the fourth PMOS transistor mp4. Since the currents of the first NMOS transistor mn1 and the second NMOS transistor mn2 remain equal and constant, this causes the gate voltage of the seventh PMOS transistor mp7 to rise, and the gate voltage of the eighth NMOS transistor mn8 to fall. The rise in the gate voltage of the seventh PMOS transistor mp7 causes the AC current to decrease, and the voltage drop across the first resistor R1, i.e. the gate voltage of the sixth NMOS transistor mn6, also decreases accordingly, causing the gate voltage of the sixth NMOS transistor mn6 to be equal to the gate voltage of the fifth NMOS transistor mn5, i.e., Vref.

[0076] Similarly, if the DC current of the ninth NMOS transistor mn9 is too low, the current mirrored to the eighth NMOS transistor mn8 will also be proportionally lower, and the voltage across the second resistor R2 will also be lower. The output voltage of the thirteenth PMOS transistor mp13, which is the gate voltage of the sixth NMOS transistor mn6, will be lower than Vref, which is the gate voltage of the fifth NMOS transistor mn5. The subsequent operation is the same as that of the eleventh PMOS transistor mp11.

[0077] The driving circuit provided in this embodiment not only realizes the basic functions of a driving circuit, but also reduces the minimum operating voltage and static power consumption of the driving circuit. Furthermore, by superimposing the current of the bias control circuit with the current source of the main circuit, the bias control circuit only needs to control the current of one of the devices, either the eleventh PMOS transistor mp11 or the ninth NMOS transistor mn9. The current of the other device can be controlled by the main operational amplifier control loop, simplifying the complexity of the bias control circuit. In addition, the DC current in the eleventh PMOS transistor mp11 and the ninth NMOS transistor mn9 can be flexibly adjusted by three parameters: Vref, the voltage drop across the first resistor R1, and the mirror current ratio (i.e., the mirror current ratio between the eleventh PMOS transistor mp11 and the seventh PMOS transistor mp7, and the mirror current ratio between the ninth NMOS transistor mn9 and the eighth NMOS transistor mn8). Adjusting any one or any combination of these parameters will yield the required DC current values ​​for the eleventh PMOS transistor mp11 and the ninth NMOS transistor mn9.

[0078] Example 2

[0079] The operational amplifier of this invention, by incorporating the driving circuit of Embodiment 1, not only achieves the basic functions of a driving circuit but also reduces the minimum operating voltage and static power consumption of the driving circuit. Furthermore, by superimposing the current of the bias control circuit with the current source of the main circuit, the bias control circuit only needs to control the current of one of the devices, either the eleventh PMOS transistor mp11 or the ninth NMOS transistor mn9. The current of the other device can be controlled by the main operational amplifier control loop, simplifying the complexity of the bias control circuit. In addition, the DC current in the eleventh PMOS transistor mp11 and the ninth NMOS transistor mn9 can be flexibly adjusted using three parameters: Vref, the voltage drop across the first resistor R1, and the mirror current ratio (i.e., the mirror current ratio between the eleventh PMOS transistor mp11 and the seventh PMOS transistor mp7, and the mirror current ratio between the ninth NMOS transistor mn9 and the eighth NMOS transistor mn8). Adjusting any one or any combination of these parameters can yield the required DC current values ​​for the eleventh PMOS transistor mp11 and the ninth NMOS transistor mn9, thus enabling the operational amplifier to also possess the effects of the aforementioned driving circuit.

[0080] While specific embodiments of the present invention have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of the present invention is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but all such changes and modifications fall within the scope of protection of the present invention.

Claims

1. A driving circuit, characterized in that, The driving circuit includes: Main operational amplifier first-stage output circuit, bias control circuit, and drive circuit; The first-stage output circuit of the main operational amplifier is used to amplify the input voltage to obtain a reference voltage; The bias control circuit is used to receive the reference voltage and control the output voltage based on the reference voltage to control the power supply voltage. The drive circuit is used to output the output voltage; The bias control circuit includes a differential operational amplifier circuit and a current acquisition circuit; The differential operational amplifier circuit is used to receive the reference voltage and obtain the voltage difference based on the reference voltage; The differential operational amplifier circuit is also used to feed the voltage difference back to the first stage output circuit of the main operational amplifier; The current acquisition circuit is used to acquire the current in the driving circuit, generate a corresponding voltage drop based on the current, and input the voltage drop to the differential operational amplifier circuit. Differential operational amplifier circuits include comparators; The comparator includes a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor; The source of the fifth NMOS transistor is electrically connected to the source of the sixth NMOS transistor and the drain of the seventh NMOS transistor, respectively. The source of the seventh NMOS transistor is grounded; The gate of the fifth NMOS transistor is electrically connected to the output terminal of the first stage output circuit of the main operational amplifier, and the gate of the sixth NMOS transistor is electrically connected to the current acquisition circuit. The differential operational amplifier circuit also includes a fifth PMOS transistor and a sixth PMOS transistor; The drain of the fifth PMOS transistor and the drain of the fifth NMOS transistor are electrically connected; The drain of the sixth PMOS transistor and the drain of the sixth NMOS transistor are electrically connected; The source of the fifth PMOS transistor and the source of the sixth PMOS transistor are both connected to the power supply. The current acquisition circuit includes a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, an eighth NMOS transistor, a first resistor, and a second resistor; The source of the seventh PMOS transistor, the source of the eighth PMOS transistor, the ninth PMOS transistor, and the tenth PMOS transistor are all connected to the power supply. The drain of the seventh PMOS transistor and the gate of the twelfth PMOS transistor are electrically connected. The drain of the eighth PMOS transistor is electrically connected to the source of the twelfth PMOS transistor and the source of the thirteenth PMOS transistor, respectively. The gate of the twelfth PMOS transistor is electrically connected to the first resistor. The gate of the thirteenth PMOS transistor is electrically connected to the second resistor; The gate of the ninth PMOS transistor is electrically connected to the gate and drain of the tenth PMOS transistor, respectively. The source of the twelfth PMOS transistor, the source of the thirteenth PMOS transistor, and the gate of the sixth NMOS transistor are electrically connected. The first resistor, the drain of the twelfth PMOS transistor, the drain of the thirteenth PMOS transistor, the second resistor, and the source of the eighth NMOS transistor are all grounded; The gate of the seventh PMOS transistor is electrically connected to the output node of the first stage output circuit of the main operational amplifier. The drain of the eighth NMOS transistor is electrically connected to the gate of the ninth PMOS transistor and the gate of the tenth PMOS transistor. The gate of the eighth NMOS transistor is electrically connected to the other output terminal of the first stage output circuit of the main operational amplifier.

2. The driving circuit as described in claim 1, characterized in that, The first-stage output circuit of the main operational amplifier includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; The sources of both the first PMOS transistor and the second PMOS transistor are electrically connected to the power supply. The drain of the first PMOS transistor is electrically connected to the source of the third PMOS transistor; The drain of the second PMOS transistor is electrically connected to the source of the fourth PMOS transistor; The drain of the third PMOS transistor is electrically connected to the drain of the third NMOS transistor. The drain of the fourth PMOS transistor is electrically connected to the drain of the fourth NMOS transistor. The source of the third NMOS transistor is electrically connected to the drain of the first NMOS transistor; The source of the fourth NMOS transistor and the drain of the second NMOS transistor are electrically connected; The source of the third PMOS transistor is electrically connected to the drain of the fifth PMOS transistor; The source of the fourth PMOS transistor is electrically connected to the drain of the sixth PMOS transistor. The source of the first NMOS transistor and the source of the second NMOS transistor are grounded.

3. The driving circuit as described in claim 2, characterized in that, The driving circuit includes an eleventh PMOS transistor and a ninth NMOS transistor; The source of the eleventh PMOS transistor is electrically connected to the power supply; The gate of the eleventh PMOS transistor is electrically connected to the gate of the seventh PMOS transistor, the drain of the third PMOS transistor, and the drain of the third NMOS transistor. The gate of the ninth NMOS transistor is electrically connected to the gate of the eighth NMOS transistor, the drain of the fourth PMOS transistor, and the drain of the fourth NMOS transistor, respectively. The drains of the eleventh PMOS transistor and the ninth NMOS transistor are both electrically connected to the output terminal.

4. An operational amplifier, characterized in that, The operational amplifier includes the driving circuit as described in any one of claims 1 to 3.

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