Elastic wave device

Abstract

An elastic wave device includes a chip bonding surface wiring pattern, a package substrate having an internal wiring pattern, and a device chip electrically connected to the package substrate. The internal wiring pattern is embedded in the inside of the package substrate. Further, the elastic wave device also includes a metal layer covering the device chip and connecting the internal wiring pattern. By this, a high-quality elastic wave device can be provided.

Description

Technical Field

[0001] This disclosure relates to an elastic wave device comprising an elastic wave device chip. Background Technology

[0002] Japanese Patent Document 1 (JP2015-41680) illustrates an elastic wave device in which an elastic wave device chip is sealed with a metal sealing portion. To suppress the problem of insufficient grounding of the metal sealing portion, the elastic wave device allows the metal sealing portion to contact the metal pattern of the wiring substrate.

[0003] In elastic wave devices that cover the chip with a metal layer, there is a need to further improve quality. For example, there is a need for miniaturization of the package, improved hermeticity, improved shielding against external electromagnetic interference, improved heat dissipation, and improved isolation characteristics through grounding enhancement. Summary of the Invention

[0004] In view of the above-mentioned problems, the present disclosure aims to improve the quality of elastic wave devices with metal layers.

[0005] The present invention discloses an elastic wave device comprising a packaging substrate having a chip bonding surface wiring pattern and an internal wiring pattern, a device chip electrically connected to the packaging substrate, and a metal layer covering the device chip and connected to the internal wiring pattern.

[0006] In one embodiment of this disclosure, the metal layer is not connected to the wiring pattern on the chip bonding surface.

[0007] In one embodiment of this disclosure, the metal layer is connected to the wiring pattern on the chip bonding surface.

[0008] In one embodiment of this disclosure, the metal layer is connected to the side of the packaging substrate, and the length of the contact portion between the metal layer and the side of the packaging substrate is more than half the thickness of the packaging substrate.

[0009] In one embodiment of this disclosure, the internal wiring pattern is a grounding wiring pattern.

[0010] In one embodiment of this disclosure, an insulating layer is further disposed between the device chip and the metal layer.

[0011] In one embodiment of this disclosure, the insulating layer is connected to the chip bonding surface of the packaging substrate, and the metal layer is connected to the chip bonding surface via the insulating layer, but is not connected to the wiring pattern of the chip bonding surface.

[0012] In one embodiment of this disclosure, the wiring pattern on the chip bonding surface is formed of gold or a gold-containing alloy, and the internal wiring pattern is formed of copper or a copper-containing alloy.

[0013] In one embodiment of this disclosure, the substrate of the device chip is a substrate formed by bonding a piezoelectric substrate and a support substrate made of sapphire, silicon, alumina, spinel, crystal or glass.

[0014] In one embodiment of this disclosure, the elastic wave device further includes a passive component mounted on the packaging substrate and an integrated circuit mounted on the packaging substrate.

[0015] The beneficial effect of the present invention is that, according to this disclosure, a high-quality elastic wave device can be provided. Attached Figure Description

[0016] Figure 1 This is a cross-sectional view of the elastic wave device of the first embodiment.

[0017] Figure 2 This is a cross-sectional view of the elastic wave device of the comparative example.

[0018] Figure 3 This is a cross-sectional view of the elastic wave device of the second embodiment.

[0019] Figure 4 This is a comparison chart of device dimensions.

[0020] Figure 5 This is a cross-sectional view of the elastic wave device of the third embodiment. Detailed Implementation

[0021] The specific embodiments of the present invention will be described below with reference to the accompanying drawings. Identical or corresponding parts in each drawing are labeled with the same reference numerals. Repeated descriptions of the same or corresponding parts will be simplified or omitted.

[0022] (First Embodiment)

[0023] Figure 1 This is a longitudinal cross-sectional view of the elastic wave device 10 according to the first embodiment. The elastic wave device 10 includes a packaging substrate 12. The upper surface of the packaging substrate 12 is a chip bonding surface. Chip bonding surface wiring patterns 12a, 12f, and 12h are formed on the chip bonding surface. The chip bonding surface wiring patterns 12a, 12f, and 12h are wiring patterns exposed on the upper surface of the packaging substrate 12. According to one example, the chip bonding surface wiring patterns 12a, 12f, and 12h are formed of gold or an alloy containing gold.

[0024] The packaging substrate 12 includes multiple wiring structures. For example... Figure 1As shown, the wiring structure includes a first structure 12A, a second structure 12B, and a third structure 12C. The first structure 12A has a through-hole conductor 12b connecting the chip bonding surface wiring pattern 12a. Through the through-hole conductor 12b, the chip bonding surface wiring pattern 12a above the through-hole conductor 12b is electrically connected to the internal wiring pattern 12c below the through-hole conductor 12b. The internal wiring pattern 12c is a wiring pattern embedded inside the substrate of the packaging substrate 12. Furthermore, the material of the substrate is, for example, an insulator such as ceramic or resin.

[0025] The first structure 12A has a through-hole conductor 12d that connects to the internal wiring pattern 12c. Through the through-hole conductor 12d, the internal wiring pattern 12c above the through-hole conductor 12d is electrically connected to the lower surface wiring pattern 12e below the through-hole conductor 12d. The lower surface wiring pattern 12e is a wiring pattern exposed on the lower surface of the packaging substrate 12.

[0026] The packaging substrate 12 includes a second structure 12B located next to the first structure 12A. The second structure 12B has the chip bonding surface wiring pattern 12f, the lower surface wiring pattern 12g, and a through-hole conductor and an internal wiring pattern that electrically connect the chip bonding surface wiring pattern 12f and the lower surface wiring pattern 12g.

[0027] The packaging substrate 12 includes a third structure 12C located next to the second structure 12B. The third structure 12C, from top to bottom, sequentially includes a chip bonding surface wiring pattern 12h, a via conductor 12i, an internal wiring pattern 12j, a via conductor 12k, and a lower surface wiring pattern 12m. According to one example, the internal wiring patterns of the first to third structures 12A, 12B, and 12C are formed of copper or a copper-containing alloy. According to one example, the chip bonding surface wiring patterns 12a, 12f, and 12h are gold-plated patterns, and the portions of the first structure 12A, the second structure 12B, and the third structure 12C other than the chip bonding surface wiring patterns 12a, 12f, and 12h are formed of copper or a copper-containing alloy.

[0028] According to other examples, the packaging substrate 12 may also be a multilayer wiring substrate or PCB with different structures. For example, the total number of wiring patterns may be changed, or the number of wiring structures in the first to third structural examples may be increased or decreased.

[0029] Device chip 20 is mounted on the chip bonding surface of the packaging substrate 12 using flip-chip bonding technology via bumps 40 and 42. The material of the bumps 40 and 42 is, for example, gold. The device chip 20 is, for example, a surface acoustic wave (SAW) device chip having comb-shaped electrodes that can excite elastic waves disposed on one side of its piezoelectric substrate. The piezoelectric substrate can be, for example, a lithium tantalate substrate or a lithium niobate substrate. According to other examples, the substrate of the device chip 20 is a substrate formed by bonding a piezoelectric substrate and a support substrate made of sapphire, silicon, alumina, spinel, crystal, or glass.

[0030] According to one example, bump 40 is connected to the terminals of the device chip 20 and the chip bonding surface wiring pattern 12a. Bump 42 is connected to the terminals of the device chip 20 and the chip bonding surface wiring pattern 12f. Any of the wiring structures of the first structure 12A, the second structure 12B, and the third structure 12C can be used as grounding wiring. For example, the second structure 12B can be used as grounding wiring. In this case, the internal wiring pattern of the second structure 12B is a grounding pattern. According to another example, the first structure 12A can be used as grounding wiring. In this case, the internal wiring pattern 12c of the first structure 12A is a grounding pattern. Therefore, the device chip 20 and the package substrate 12 can be electrically connected by the bumps 40 and 42.

[0031] The device chip 20 is covered by an insulating layer 22 and a metal layer 24. Figure 1 In one example, the insulating layer 22 connects to the device chip 20, and the metal layer 24 connects to the device chip 20 across the insulating layer 22. By covering the device chip 20 with the insulating layer 22 and the metal layer 24, a sealed space can be formed between the device chip 20 and the packaging substrate 12. According to one example, the metal layer 24 is made of nickel or a nickel-containing alloy.

[0032] according to Figure 1For example, because the insulating layer 22 is directly connected to the chip bonding surface wiring patterns 12a and 12h, the insulating layer 22 can connect to the chip bonding surface of the packaging substrate 12. On the other hand, the metal layer 24 is not connected to the chip bonding surface wiring patterns 12a and 12h. In other words, the metal layer 24 connects to the chip bonding surface through the insulating layer 22 and is not connected to the chip bonding surface wiring patterns. The metal layer 24 connects to the internal wiring patterns 12c and 12j. By providing a stepped structure on the packaging substrate 12 and exposing the upper surfaces of the internal wiring patterns 12c and 12j on the steps, the upper surfaces of the internal wiring patterns 12c and 12j can be connected to the metal layer 24. Figure 1 In this design, the area where the metal layer 24 connects to the internal wiring pattern 12c is designated as a joint 30. Furthermore, the area where the metal layer 24 connects to the internal wiring pattern 12j is designated as a joint 32. According to one example, the joints 30 and 32 are an alloy of the metal layer 24 and the internal wiring patterns 12c and 12j. According to other examples, the joints 30 and 32 are a portion of either the metal layer 24 or the internal wiring patterns 12c and 12j.

[0033] Figure 2 This is a cross-sectional view of the elastic wave device of the comparative example. The elastic wave device of the comparative example is... Figure 1 The difference between the elastic wave device 10 and the comparative example lies in the connection method between the metal layer 24 and the packaging substrate 12. In the elastic wave device of the comparative example, the metal layer 24 is connected to the wiring patterns 12a and 12h on the chip bonding surface. The connected areas are indicated by joints 38 and 39 in the figure. The metal layer 24 of the comparative example is not connected to the internal wiring patterns 12c and 12j.

[0034] Based on one example, Figure 1 , 2 The insulating layer 22 of the elastic wave device is formed by the following method. First, a resin layer is placed on the device chip 20. The resin layer is, for example, obtained by pressing liquid epoxy resin into a sheet. According to other examples, the resin layer can be a synthetic resin such as polyimide, which is different from epoxy resin. A protective film made of polyethylene terephthalate (PET) can be provided on the upper surface of the resin layer, or a base film made of polyester fiber can be provided on the lower surface of the resin layer. By placing the resin layer on multiple device chips 20, the resin layer is temporarily fixed to one or more of the device chips.

[0035] Next, resin is supplied to the side of the chip using a vacuum coating method. For example, in a vacuum environment, pressure is applied to the resin layer in the direction toward the packaging substrate 12, gradually supplying resin to the area on the side of the chip. Pressure in the direction toward the packaging substrate 12 can be applied to the resin layer by silicone expanded by compressed air, or by a rubber sheet. When multiple chips are present, resin can also be supplied between the chips.

[0036] Alternatively, other methods can be used to provide resin to the sides of the chip or between the chips instead of vacuum coating. For example, a method known as hot rolling can be used. Hot rolling is a process in which a resin layer is passed between an upper roller and a lower roller heated to at least the softening temperature of the resin layer. This provides the resin layer to the upper surface of one or more of the device chips and fills the sides of the device chips and the upper surface of the packaging substrate 12.

[0037] As described above, with the device chip covered by the resin, the resin is thermally cured to form the insulating layer 22. In this case, the resin in the comparative example is thermally cured only on the upper surface of the packaging substrate 12, and according to the distribution of the wiring pattern on the chip bonding surface, the resin penetrates into the area between the device chip 20 and the packaging substrate 12. In contrast, Figure 1 The encapsulation substrate 12 has the steps provided. The resin is thermosetting after reaching the side of the steps, thereby stabilizing the shape of the resin wall around the device chip 20. In other words, it can prevent the resin from penetrating into the area between the device chip 20 and the encapsulation substrate 12.

[0038] Conversely, when the wiring pattern on the chip bonding surface is gold-plated, the adhesion between the gold plating and the resin is poor. Therefore, in the comparative example, the insulating layer 22 exhibits poor adhesion, primarily connecting only to the wiring pattern on the chip bonding surface of the packaging substrate 12. However, as... Figure 1 As shown, if the insulating layer 22 contacts not only the wiring pattern on the chip bonding surface, but also the substrate of the packaging substrate 12 and the internal wiring patterns 12c and 12j, the insulating layer 22 can adhere to the packaging substrate 12. According to one example, the copper-containing internal wiring pattern contacts the nickel-containing metal layer 24 and the insulating layer 22, which can improve connectivity.

[0039] Therefore, by strengthening the connection between the insulating layer 22, the metal layer 24, and the packaging substrate 12, the airtightness of the elastic wave device can be improved, the shielding effect against external electromagnetic interference can be enhanced, and the grounding connection can be strengthened.

[0040] (Second Embodiment)

[0041] Figure 3 This is a cross-sectional view of the elastic wave device according to the second embodiment. In the second embodiment, the metal layer 24 is connected to the wiring patterns 12a, 12h on the chip bonding surface and the internal wiring patterns 12c, 12j. Figure 3 In the example, the metal layer 24 is connected to the sides of the chip bonding surface wiring patterns 12a and 12h and the sides of the internal wiring patterns 12c and 12j. The areas where the metal layer 24 is connected to the sides of the chip bonding surface wiring patterns 12a, 12h, and 12j are respectively marked as joints 50, 52, 54, and 56.

[0042] By connecting the metal layer 24 to the wiring patterns 12a, 12h on the chip bonding surface and the internal wiring patterns 12c, 12j, the connection between the metal layer 24 and the packaging substrate 12 can be strengthened.

[0043] According to one example, in a cross-sectional view, the length of the contact portion between the metal layer 24 and the side of the packaging substrate 12 can be more than half the thickness of the packaging substrate 12. In other words, the longitudinal length of the connection portion between the metal layer 24 and the packaging substrate 12 is more than half the thickness of the packaging substrate 12. Therefore, the contact length between the side of the packaging substrate 12 and the metal layer 24 can be sufficiently ensured, thereby improving the connectivity between the two.

[0044] Furthermore, by providing steps on the packaging substrate 12 and allowing the metal layer 24 to reach the area of ​​the steps, the position of the metal layer 24 can be stabilized.

[0045] Figure 4 This is a comparison diagram of the device dimensions of the elastic wave device of the second embodiment and the elastic wave device of the comparative example. The upper half is the elastic wave device of the comparative example, and the lower half is the elastic wave device of the second embodiment. In the comparative example, the bonding portions 38 and 39 are formed in the horizontal direction, and the distance between the portion of the metal layer 24 surrounding the device chip 20 in the vertical direction and the outer side of the packaging substrate 12 extending in the vertical direction is D1, for example, 125 μm. Conversely, in the second embodiment, the bonding portions 50, 52, 54, and 56 are formed in the vertical direction. The distance between the portion of the metal layer 24 surrounding the device chip 20 in the vertical direction and the outer side of the packaging substrate 12 extending in the vertical direction is D2, for example, 50 μm. Figure 4It can be seen that D2 is less than D1. Therefore, compared with the comparative example, the elastic wave device of the second embodiment is suitable for miniaturization.

[0046] (Third Embodiment)

[0047] Figure 5 This is a cross-sectional view of the elastic wave device according to the third embodiment. In addition to the device chip 20, the elastic wave device also includes a passive component 60 disposed on the packaging substrate 12 and an integrated circuit 62 disposed on the packaging substrate 12. According to one example, the passive component 60 is connected to the chip bonding surface wiring pattern 12n by solder 61. The integrated circuit 62 is electrically connected to the chip bonding surface wiring pattern 12n by solder balls 63.

[0048] The insulating layer 22 and the metal layer 24 cover the device chip 20, passive component 60, and integrated circuit 62. The metal layer 24 is connected at multiple points to the wiring pattern 12n on the chip bonding surface. Furthermore, the metal layer 24 connects the internal wiring pattern 12p between the passive component 60 and the integrated circuit 62. The connection positions of the metal layer 24 and the internal wiring pattern can be arbitrary, and the number of connection positions can be multiple. By connecting the metal layer 24 to the internal wiring pattern, the aforementioned various effects can be obtained. A resin layer 70 for protecting the device and improving operability is provided on the metal layer 24.

[0049] Therefore, even if the elastic wave device has multiple components, the quality of the elastic wave device can be improved by connecting the metal layer with the internal wiring pattern.

[0050] While at least one embodiment has been described above, it should be understood that various changes, modifications, or improvements will readily occur to those skilled in the art. These changes, modifications, or improvements are also part of this disclosure and fall within the scope of this invention.

[0051] It should be understood that the embodiments of the methods or apparatus described herein are not limited to the architecture and arrangement of the constituent components described above or illustrated in the accompanying drawings. The methods and apparatus can be installed or performed in other embodiments.

[0052] The embodiments described are for illustrative purposes only and are not intended to be limiting.

[0053] The descriptions and terms used in this disclosure are for illustrative purposes only and are not intended to be limiting. The use of "including," "possessing," "having," "comprise," and variations thereof here means to include the items listed below, their equivalents, and additional items.

[0054] The word “or”, or any word used in a description, may be interpreted as one, more than one, or all of the words described.

[0055] The references to front, back, left, right, top, bottom, upper, lower, and horizontal and vertical are for ease of description and are not intended to limit the position and spatial configuration of any component in this invention. Therefore, the above description and drawings are merely exemplary.

Claims

1. An elastic wave device, characterized in that: The elastic wave device includes: a packaging substrate having a chip bonding surface wiring pattern and an internal wiring pattern, a device chip electrically connected to the packaging substrate, and a metal layer covering the device chip and connected to the internal wiring pattern, wherein the metal layer is connected to the chip bonding surface wiring pattern; the metal layer contacts the side of the packaging substrate and is bonded to the side of the internal wiring pattern. In the cross-sectional view, the length of the contact portion between the metal layer and the side of the packaging substrate is more than half the thickness of the packaging substrate.

2. The elastic wave device according to claim 1, characterized in that: The internal wiring pattern is a grounding wiring pattern.

3. The elastic wave device according to claim 1, characterized in that: The elastic wave device further includes an insulating layer disposed between the device chip and the metal layer.

4. The elastic wave device according to claim 3, characterized in that: The insulating layer connects to the chip bonding surface of the packaging substrate, and the metal layer connects to the chip bonding surface via the insulating layer and is bonded to the side of the wiring pattern on the chip bonding surface.

5. The elastic wave device according to claim 1, characterized in that: The wiring pattern on the chip bonding surface is formed of gold or a gold-containing alloy, and the internal wiring pattern is formed of copper or a copper-containing alloy.

6. The elastic wave device according to claim 1, characterized in that: The substrate of the device chip is a substrate formed by bonding a piezoelectric substrate and a support substrate made of sapphire, silicon, alumina, spinel, crystal or glass.

7. The elastic wave device according to claim 1, characterized in that: The elastic wave device further includes passive components mounted on the packaging substrate and integrated circuits mounted on the packaging substrate.

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