High-precision interval response circuit

Abstract

The application provides a high-precision interval response circuit, belonging to the technical field of electronic circuits, comprising interval setting circuit, comparison summation circuit and result output circuit three parts, the interval setting circuit sets upper limit voltage U1 and lower limit voltage U2 by resistance voltage division and operational amplifier following function, U1>U2; the comparison summation circuit is used for comparing input voltage V in with the size of upper limit voltage U1 and lower limit voltage U2, and the output of voltage comparison result is realized by using integral circuit and proportional amplification circuit; the result output circuit can power amplify the signal type voltage transmitted by the previous stage circuit, so that the signal type voltage has current driving capability and voltage maintaining capability not lower than 2ms; when the input direct current voltage V in exceeds the preset upper limit voltage U1 or is lower than the lower limit voltage U2, the circuit outputs a high voltage with driving capability, and the value is approximately equal to the power supply voltage; when the input direct current voltage V in is located in the range of U1 and U2, the circuit outputs zero. The application has high precision, high speed and strong environmental adaptability.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology, specifically relating to a high-precision range response circuit, which is suitable for judging and responding to DC voltage values ​​within a certain range. Background Technology

[0002] In some electronic circuit applications, it is desirable for circuits to judge and respond to DC voltage values ​​within a certain range, thereby enabling functions such as driving subsequent circuits or reporting status information to a computer, such as airbags and temperature alarms. Current technologies generally use digital circuits to achieve range voltage response, which suffers from drawbacks such as low accuracy, slow speed, and poor environmental adaptability. Therefore, it is necessary to propose improvements. Summary of the Invention

[0003] The technical problem solved by this invention is to provide a high-precision interval response circuit. This invention uses a pure analog circuit to realize the function of interval voltage response. Compared with the prior art, it has the characteristics of high precision, fast speed and strong environmental adaptability.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] A high-precision interval response circuit includes three parts: an interval setting circuit, a comparison and summation circuit, and a result output circuit. The interval setting circuit uses resistor voltage divider and operational amplifier follower function to set the upper limit voltage U1 and the lower limit voltage U2, where U1 > U2. The comparison and summation circuit is used to compare the input voltage V. in The voltage comparison results are output using an integrator circuit and a proportional amplifier circuit, based on the magnitudes of the upper limit voltage U1 and the lower limit voltage U2. The output circuit can amplify the signal voltage transmitted from the previous stage circuit, giving it current driving capability and a voltage holding capability of not less than 2ms.

[0006] When the input DC voltage V in When the voltage exceeds the preset upper limit U1 or falls below the lower limit U2, the circuit outputs a high-level voltage with driving capability, the value of which is approximately equal to the power supply voltage; when the input DC voltage V... in When the circuit output is within the range of U1 and U2, the output is zero.

[0007] Further defining the above scheme, the interval setting circuit includes resistors R1, R2, R3, and R4, operational amplifier A1, and operational amplifier A2; wherein resistors R1, R2, R3, and R4 are connected in series with the power supply V. ccThe positive input terminal of the operational amplifier A1 is connected to the high potential terminal of the resistor R2, and the negative input terminal is connected to the output terminal; the positive input terminal of the operational amplifier A2 is connected to the high potential terminal of the resistor R4, and the negative input terminal is connected to the output terminal.

[0008] Further specifying the above scheme, the comparison and summation circuit includes resistors R5, R6, R7, R8, R9, R10, R11, and R12, capacitors C1 and C2, operational amplifiers A3, A4, and A5; wherein, one end of resistor R5 is connected to the input Vin, and the other end is connected to the positive input terminal of operational amplifier A3; one end of resistor R6 is connected to the output terminal of operational amplifier A1, and the other end is connected to the inverting input terminal of operational amplifier A3; one end of resistor R7 is connected to the output terminal of operational amplifier A2, and the other end is connected to the positive input terminal of operational amplifier A4; one end of resistor R8 is connected to the input Vin, and the other end is connected to the inverting input terminal of operational amplifier A4. The following components are connected to the input terminals: one end of capacitor C1 is connected to the inverting input terminal of operational amplifier A3, and the other end is connected to the output terminal of operational amplifier A3; one end of capacitor C2 is connected to the inverting input terminal of operational amplifier A4, and the other end is connected to the output terminal of operational amplifier A4; one end of resistor R9 is connected to the output terminal of operational amplifier A3, and the other end is connected to the non-inverting input terminal of operational amplifier A5; one end of resistor R10 is connected to the output terminal of operational amplifier A4, and the other end is connected to the non-inverting input terminal of operational amplifier A5; one end of resistor R11 is connected to the inverting input terminal of operational amplifier A5, and the other end is connected to ground; one end of resistor R12 is connected to the inverting input terminal of operational amplifier A5, and the other end is connected to the output terminal of operational amplifier A5.

[0009] Further specifying the above scheme, the output circuit includes capacitor C3, resistors R13, R14, R15, R16, R17, N-MOS transistor Q1, and P-MOS transistor Q2; resistor R13 is connected in series between the output terminal of the aforementioned operational amplifier A5 and the gate of N-MOS transistor Q1; resistor R14 is connected in series between the gate of N-MOS transistor Q1 and ground; resistor R16 is connected in series between the source of N-MOS transistor Q1 and ground; the drain of N-MOS transistor Q1 is connected to the gate of P-MOS transistor Q2; resistor R15 is connected in series between the gate of P-MOS transistor Q2 and the power supply V. cc Between; the source of the P-MOS transistor Q2 is connected to the power supply V. ccOne end of the capacitor C3 is connected to the drain of the P-MOS transistor Q2, and the other end is connected to ground; one end of the resistor R17 is connected to the drain of the P-MOS transistor Q2, and the other end is connected to ground. The drain of the P-MOS transistor Q2 is the circuit output terminal.

[0010] Preferably, resistors R1, R2, R3, and R4 are all low-temperature-drift resistors, and the temperature drift coefficient of the resistance values ​​of resistors R1, R2, R3, and R4 is less than 30ppm / ℃.

[0011] Advantages of this invention compared to existing technologies:

[0012] 1. This solution utilizes a purely analog circuit to determine and respond to DC voltage values ​​within a certain range. When the input DC voltage V... in When the voltage exceeds the preset upper limit U1 or falls below the lower limit U2 (U1>U2), the circuit outputs a high-level voltage with driving capability, the value of which is approximately equal to the power supply voltage; when the input DC voltage V... in When the circuit is within the range of U1 and U2, the output is zero. The circuit has a response accuracy of more than 1mV and has the advantages of high accuracy, fast speed and strong environmental adaptability compared with other schemes that use digital circuits to implement functions in the prior art.

[0013] 2. The design principle of this solution is simple and clear, the structure is simple, and all components can be domestically produced, thus eliminating the restriction of imported components. Attached Figure Description

[0014] Figure 1 This is the circuit schematic diagram of the present invention. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] Please see Figure 1 The embodiments of the present invention are described in detail below.

[0017] Example 1: A high-precision interval response circuit, comprising three parts: an interval setting circuit, a comparison and summation circuit, and a result output circuit.

[0018] The interval setting circuit uses resistor voltage divider and operational amplifier follower function to set the upper limit voltage U1 and lower limit voltage U2, where U1>U2; the comparison and summation circuit is used to compare the input voltage V. inThe voltage comparison results are output using an integrator circuit and a proportional amplifier circuit, based on the magnitudes of the upper limit voltage U1 and the lower limit voltage U2. The output circuit amplifies the signal voltage transmitted from the previous stage circuit to enable it to have current driving capability and a voltage holding capability of not less than 2ms.

[0019] When the input DC voltage V in When the voltage exceeds the preset upper limit U1 or falls below the lower limit U2, the circuit outputs a high-level voltage with driving capability, the value of which is approximately equal to the power supply voltage; when the input DC voltage V... in When the voltage is within the range of U1 and U2, the circuit output is zero. The circuit's response accuracy is higher than 1mV.

[0020] Example 2:

[0021] The interval setting circuit includes resistors R1, R2, R3, and R4, operational amplifier A1, and operational amplifier A2; wherein resistors R1, R2, R3, and R4 are connected in series with power supply V. cc The positive input terminal of the operational amplifier A1 is connected to the high potential terminal of the resistor R2, and the negative input terminal is connected to the output terminal; the positive input terminal of the operational amplifier A2 is connected to the high potential terminal of the resistor R4, and the negative input terminal is connected to the output terminal.

[0022] The comparison and summation circuit includes resistors R5, R6, R7, R8, R9, R10, R11, and R12, capacitors C1 and C2, operational amplifiers A3, A4, and A5. Specifically, one end of resistor R5 is connected to the input Vin, and the other end is connected to the positive input terminal of operational amplifier A3; one end of resistor R6 is connected to the output terminal of operational amplifier A1, and the other end is connected to the inverting input terminal of operational amplifier A3; one end of resistor R7 is connected to the output terminal of operational amplifier A2, and the other end is connected to the positive input terminal of operational amplifier A4; and one end of resistor R8 is connected to the input Vin, and the other end is connected to the inverting input terminal of operational amplifier A4. One end of capacitor C1 is connected to the inverting input of operational amplifier A3, and the other end is connected to the output of operational amplifier A3; one end of capacitor C2 is connected to the inverting input of operational amplifier A4, and the other end is connected to the output of operational amplifier A4; one end of resistor R9 is connected to the output of operational amplifier A3, and the other end is connected to the non-inverting input of operational amplifier A5; one end of resistor R10 is connected to the output of operational amplifier A4, and the other end is connected to the non-inverting input of operational amplifier A5; one end of resistor R11 is connected to the inverting input of operational amplifier A5, and the other end is connected to ground; one end of resistor R12 is connected to the inverting input of operational amplifier A5, and the other end is connected to the output of operational amplifier A5.

[0023] The output circuit includes capacitor C3, resistors R13, R14, R15, R16, R17, N-MOS transistor Q1, and P-MOS transistor Q2. Resistor R13 is connected in series between the output of operational amplifier A5 and the gate of N-MOS transistor Q1. Resistor R14 is connected in series between the gate of N-MOS transistor Q1 and ground. Resistor R16 is connected in series between the source of N-MOS transistor Q1 and ground. The drain of N-MOS transistor Q1 is connected to the gate of P-MOS transistor Q2. Resistor R15 is connected in series between the gate of P-MOS transistor Q2 and the power supply V. cc Between; the source of the P-MOS transistor Q2 is connected to the power supply V. cc One end of the capacitor C3 is connected to the drain of the P-MOS transistor Q2, and the other end is connected to ground; one end of the resistor R17 is connected to the drain of the P-MOS transistor Q2, and the other end is connected to ground; the drain of the P-MOS transistor Q2 is the circuit output terminal.

[0024] The resistors R1, R2, R3, and R4 are all low-temperature drift resistors. The temperature drift coefficient of the resistance values ​​of the resistors R1, R2, R3, and R4 is less than 30ppm / ℃, ensuring that the preset voltage value remains basically stable when the ambient temperature changes.

[0025] The specific value calculation is as follows:

[0026] The power supply voltage is taken as 15V.

[0027] U1 = V cc ·(R2+R3+R4) / (R1+R2+R3+R4)

[0028] U2 = V cc ·R4 / (R1+R2+R3+R4)

[0029] By selecting R1, R2, R3 and R4 with different resistance values, the upper limit voltage U1 and lower limit voltage U2 can be set. If R1=100kΩ, R2=10kΩ, R3=20kΩ, R4=10kΩ, then:

[0030] U1 = 4V

[0031] U2 = 1V

[0032] Take R5 = R6 = R7 = R8 = 10kΩ, C1 = C2 = 1nF.

[0033] When the input voltage V in > U1, according to the principle of virtual short, the voltage at the inverting input terminal of operational amplifier A3 is greater than U1, the integrating circuit formed by A3 operates in the forward direction, saturating the output of operational amplifier A3 to approximately 13.5V. The voltage at the inverting input terminal of operational amplifier A4 is equal to U2, the integrating circuit formed by A4 operates in the reverse direction, bringing the output of operational amplifier A4 close to 0V. If R9 = R10 = R11 = 10kΩ, R12 = 15kΩ, then the voltage at the non-inverting input terminal of operational amplifier A5 is approximately 6.75V, the non-inverting amplification factor is (R11+R12) / R11 = 2.5, and the output of operational amplifier A5 is saturated with a value of approximately 13.5V.

[0034] When the input voltage V in < U2, according to the principle of virtual short, the voltage at the inverting input terminal of operational amplifier A4 is equal to U2, the integrating circuit formed by A4 operates in the forward direction, saturating the output of operational amplifier A4 to approximately 13.5V. The voltage at the inverting input terminal of operational amplifier A3 is less than U1, the integrating circuit formed by A3 operates in the reverse direction, bringing the output of operational amplifier A3 close to 0V. Then, the voltage at the non-inverting input terminal of operational amplifier A5 is approximately 6.75V, and the output of operational amplifier A5 is saturated with a value of approximately 13.5V.

[0035] When the input voltage U1 > V inWhen the voltage is greater than U2, according to the principle of virtual short, the voltage at the inverting input terminal of operational amplifier A3 is less than U1, and the integrating circuit formed thereby operates in reverse, so that the output of operational amplifier A3 tends to 0V. The voltage at the inverting input terminal of operational amplifier A4 is equal to U2, and the integrating circuit formed thereby operates in reverse, so that the output of operational amplifier A4 tends to 0V. Then, the voltage at the non-inverting input terminal of operational amplifier A5 tends to 0V, and the output of operational amplifier A5 tends to 0V.

[0036] The turn-on condition of N-MOS transistor Q1 is V G1 -V S1 >4, and V G2 =V A5 ·R14 / (R13+R14), meanwhile, the turn-on condition of PMOS transistor Q2 is V S2 -V G2 >4, and V G3 ≈V G2 -4. After comprehensive consideration, it is determined that R13 is 15kΩ, R14 is 10kΩ, R15 is 100kΩ, and R16 is 5kΩ.

[0037] After P-MOS transistor Q2 is turned on, the voltage applied between resistor R17, capacitor C3 and ground is approximately V cc , then the final output of the circuit is approximately V cc , since the current allowed to pass through the MOS transistor is large, this voltage has driving capability. Let R17=50kΩ and C3=2.2μF. Through Multisim simulation, it can be seen that the circuit can still provide a voltage above 14.8V after 2ms, which proves that its output holding capacity is not less than 2ms for a subsequent circuit with a 50kΩ equivalent resistance. Increasing the capacitance of C3 can improve the output holding capacity of the circuit, but it will affect the response speed of the circuit, which needs to be comprehensively considered in practical applications.

[0038] In addition, swapping the positions of the upper and lower integrating circuits can realize the function that the circuit outputs a high-level voltage when U1>V in >U2, and outputs 0 when V in >U1 or V in <U2.

[0039] The present invention realizes the function of interval voltage response by using a pure analog circuit. Compared with the prior art, the invention has the characteristics of high precision, high speed and strong environmental adaptability.

[0040] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention, and no reference numerals in the claims should be construed as limiting the scope of the claims.

[0041] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A high-precision interval response circuit, characterized in that: The circuit comprises three parts: a range setting circuit, a comparison and summation circuit, and a result output circuit. The range setting circuit uses a resistor voltage divider and an operational amplifier follower function to set the upper limit voltage U1 and the lower limit voltage U2, where U1 > U2. The comparison and summation circuit is used to compare the input voltage V. in The voltage comparison result is output by using an integrator circuit and a proportional amplifier circuit to compare the upper limit voltage U1 and the lower limit voltage U2. The result output circuit amplifies the signal voltage transmitted from the previous stage circuit to enable it to have current driving capability and voltage holding capability of not less than 2 ms. When the input DC voltage V in When the voltage exceeds the preset upper limit U1 or falls below the lower limit U2, the circuit outputs a high-level voltage with driving capability, the value of which is approximately equal to the power supply voltage; when the input DC voltage V... in When the circuit output is within the range of U1 and U2, the output is zero. The interval setting circuit includes resistors R1, R2, R3, and R4, operational amplifier A1, and operational amplifier A2; wherein resistors R1, R2, R3, and R4 are connected in series with power supply V. cc The positive input terminal of the operational amplifier A1 is connected to the high potential terminal of the resistor R2, and the negative input terminal is connected to the output terminal; the positive input terminal of the operational amplifier A2 is connected to the high potential terminal of the resistor R4, and the negative input terminal is connected to the output terminal.

2. The high-precision interval response circuit according to claim 1, characterized in that: The comparison and summation circuit includes resistors R5, R6, R7, R8, R9, R10, R11, and R12, capacitors C1 and C2, operational amplifiers A3, A4, and A5; wherein, one end of resistor R5 is connected to the input Vin, and the other end is connected to the positive input terminal of operational amplifier A3; one end of resistor R6 is connected to the output terminal of operational amplifier A1, and the other end is connected to the inverting input terminal of operational amplifier A3; one end of resistor R7 is connected to the output terminal of operational amplifier A2, and the other end is connected to the positive input terminal of operational amplifier A4; one end of resistor R8 is connected to the input Vin, and the other end is connected to the inverting input terminal of operational amplifier A4; One end of capacitor C1 is connected to the inverting input terminal of operational amplifier A3, and the other end is connected to the output terminal of operational amplifier A3; one end of capacitor C2 is connected to the inverting input terminal of operational amplifier A4, and the other end is connected to the output terminal of operational amplifier A4; one end of resistor R9 is connected to the output terminal of operational amplifier A3, and the other end is connected to the non-inverting input terminal of operational amplifier A5; one end of resistor R10 is connected to the output terminal of operational amplifier A4, and the other end is connected to the non-inverting input terminal of operational amplifier A5; one end of resistor R11 is connected to the inverting input terminal of operational amplifier A5, and the other end is connected to ground; one end of resistor R12 is connected to the inverting input terminal of operational amplifier A5, and the other end is connected to the output terminal of operational amplifier A5.

3. The high-precision interval response circuit according to claim 2, characterized in that: The output circuit includes capacitor C3, resistors R13, R14, R15, R16, R17, an N-MOS transistor Q1, and a P-MOS transistor Q2. Resistor R13 is connected in series between the output of operational amplifier A5 and the gate of N-MOS transistor Q1. Resistor R14 is connected in series between the gate of N-MOS transistor Q1 and ground. Resistor R16 is connected in series between the source of N-MOS transistor Q1 and ground. The drain of N-MOS transistor Q1 is connected to the gate of P-MOS transistor Q2. Resistor R15 is connected in series between the gate of P-MOS transistor Q2 and the power supply V. cc Between; the source of the P-MOS transistor Q2 is connected to the power supply V. cc One end of the capacitor C3 is connected to the drain of the P-MOS transistor Q2, and the other end is connected to ground; one end of the resistor R17 is connected to the drain of the P-MOS transistor Q2, and the other end is connected to ground; the drain of the P-MOS transistor Q2 is the circuit output terminal.

4. A high-precision interval response circuit according to claim 3, characterized in that: The resistors R1, R2, R3, and R4 are all low-temperature drift resistors, and the temperature drift coefficient of the resistance values ​​of the resistors R1, R2, R3, and R4 is less than 30 ppm / ℃.

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