Spread spectrum clock circuit

Abstract

The application discloses a spread spectrum clock circuit, comprising: an oscillation circuit, which generates an output clock signal with a frequency change according to a calibration current and a feedback current; and a period counting circuit, which receives the output clock signal, sequentially triggers a plurality of trigger signals at rising edges or falling edges of the output clock signal, and outputs a feedback current with a periodic change according to the plurality of trigger signals and a first reference current. The application adopts the period counting circuit to control the size of the feedback current by triggering a plurality of trigger signals at the rising edges or the falling edges of the spread spectrum clock signal, so as to control the input current of the oscillation circuit and realize frequency modulation of the spread spectrum clock signal. The spread spectrum clock circuit has simple structure and strong stability.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design, and more specifically to a spread spectrum clock circuit. Background Technology

[0002] EMI (Electromagnetic Interference) has always been a problem in electronic equipment. It can be divided into three factors: interference source, propagation path, and sensitive components. Eliminating the interference source and cutting off the propagation path, i.e., the coupling path of the circuit, can reduce the impact of electromagnetic interference.

[0003] In switching power supplies, increasing the switching frequency reduces the size of external components. However, increasing the switching frequency brings some drawbacks, one of which is increased EMI (Electromagnetic Interference). High EMI from a switching power supply can directly affect the operation of downstream load circuits and even the entire system. Therefore, the level of EMI noise in a switching power supply has become an important indicator for evaluating its performance.

[0004] A new technique for reducing EMI is to change or modulate the frequency of the clock in a PC. This technique is called spread spectrum because the clock's spectrum is distributed over a wider frequency range. Figure 1 The graph shows the radiation intensity as a function of the frequency of the unmodulated clock signal. A spike appears at the harmonic of the clock frequency (40MHz). Since the clock always operates at its rated frequency, all the radiated energy appears in a narrow spike with a large amplitude. Figure 2 The graph shows the radiation intensity as a function of the frequency generated by the modulated clock. The clock frequency is not constant, but varies with time in the range of +5% to -5% of the rated frequency. Therefore, all the radiated energy is evenly distributed in the range of +5% to -5% of the rated frequency, and the amplitude at the rated frequency is greatly weakened.

[0005] One method for generating spread spectrum clock signals is to modulate a voltage-controlled oscillator (VCO) circuit with a triangular wave. The spectral range of the generated spread spectrum clock signal increases with the amplitude of the triangular wave. However, when the frequency of the triangular wave is low, it can generate coupling noise to analog circuits through the power supply. When the frequency of the triangular wave is too high, it can interfere with the setup and hold times of digital circuits. Especially in circuits using phase-locked loops (PLLs), the PLLs can lose their phase-locking function due to excessively rapid frequency jitter. Summary of the Invention

[0006] In view of this, the present invention provides a spread spectrum clock circuit with simple structure and strong stability.

[0007] According to a first aspect of the present invention, a spread spectrum clock circuit is provided, comprising: an oscillation circuit that generates a frequency-varying output clock signal based on a calibration current and a feedback current; and a period counting circuit that receives the output clock signal, sequentially triggers a plurality of trigger signals at the rising or falling edge of the output clock signal, and outputs a periodically varying feedback current based on the plurality of trigger signals and a first reference current.

[0008] Preferably, the period counting circuit includes a first inverter, k flip-flops, and k current mirror branches. The k flip-flops are cascaded and each of the k flip-flops is connected to one of the k current mirror branches. The kth flip-flop triggers the kth trigger signal at the kth rising or falling edge of the output clock signal. The kth trigger signal is inverted by the first inverter and output to the first flip-flop. The ith flip-flop triggers the ith trigger signal at the ith rising or falling edge of the output clock signal. The ith trigger signal is output to the (i+1)th flip-flop. Wherein, i ≤ k-1, and i and k are both positive integers. The period counting circuit controls the corresponding current mirror branches to be turned on or off according to the k trigger signals output by the k flip-flops. When the trigger signals output by the flip-flops control the corresponding current mirror branches to be turned on, the currents output by the turned-on current mirror branches are superimposed to output a periodically changing feedback current.

[0009] Preferably, the feedback current is the product of the first reference current and the count value, and the count value is the number of current mirror branches controlled by the trigger signals output by the k triggers.

[0010] Preferably, the count value is accumulated from 0 to k in each cycle and then decreased from k back to 0.

[0011] Preferably, the frequency of the output clock signal decreases as the count value decreases and increases as the count value increases.

[0012] Preferably, the first enable terminals of the k flip-flops are connected together to receive a first enable signal; the second enable terminals of the k flip-flops are connected together to receive a second enable signal; the clock terminals of the k flip-flops are connected together to receive the output clock signal; and the output terminals of the k flip-flops each output k trigger signals.

[0013] Preferably, when the k flip-flops are rising edge flip-flops, they transition on the rising edge of the output clock signal; when the k flip-flops are falling edge flip-flops, they transition on the falling edge of the output clock signal.

[0014] Preferably, when the k flip-flops are rising-edge flip-flops, when both the first enable signal and the second enable signal are at valid levels, and the output clock signal changes from an invalid level to a valid level, the output of the flip-flop will output a valid level if the input of the flip-flop is at a valid level, and the output of the flip-flop will output an invalid level if the input of the flip-flop is at an invalid level.

[0015] Preferably, when the k flip-flops are falling-edge flip-flops, when both the first enable signal and the second enable signal are active, and the output clock signal changes from active to inactive, the input terminal of the flip-flop receives an active level, and the output terminal of the flip-flop outputs an active level.

[0016] Preferably, the period counting circuit further includes: The first current mirror unit mirrors the first reference current from the k current mirror branches and controls whether the mirrored current in the k current mirror branches is output according to the k trigger signals. The second current mirror unit is connected to the output terminals of the k current mirror branches and is used to output the mirrored currents from the k current mirror branches to generate feedback current.

[0017] Preferably, the first current mirror unit includes: a first current source for providing a first reference current; a first switching transistor connected in series with the first current source between a first voltage and a ground terminal; k second switching transistors, each forming a current mirror with the first switching transistor; and k switches, each connected to the output terminal of a current mirror branch, for controlling the conduction and cutoff of the k current mirror branches according to k trigger signals to control whether the mirrored current of the k current mirror branches is output.

[0018] Preferably, the first switch and the first current source are connected in series between the first voltage and the ground terminal; the control terminal of the first switch is connected to the node between the first switch and the first current source; each second switch and its corresponding switch are connected in series between the first voltage and the second current mirror unit; the control terminal of each second switch is connected to the control terminal of the first switch; and the control terminal of each switch is connected to the output terminal of the corresponding trigger.

[0019] Preferably, when the trigger signal is at an invalid level, the corresponding switch is turned on; when the trigger signal is at an active level, the corresponding switch is turned off.

[0020] Preferably, the second current mirror unit includes a third switch and a fourth switch, wherein the first end of the third switch is connected to the output end of a plurality of current mirror branches, the second end is grounded, and its control end is connected to the first end of the third switch; the first end of the fourth switch outputs feedback current, the second end is grounded, and its control end is connected to the control end of the third switch.

[0021] Preferably, the cycle counting circuit includes multiple cycle counting units, each cycle counting unit including a first inverter, k flip-flops and k current mirror branches, the k flip-flops being cascaded, and the k flip-flops in each cycle counting unit corresponding one-to-one with the k current mirror branches.

[0022] Preferably, the number of triggers k in each cycle counting unit is different to generate different feedback currents.

[0023] Preferably, the cycle counting circuit further includes a control module for generating a plurality of first enable signals and a plurality of second enable signals, wherein the plurality of first enable signals and the plurality of second enable signals control at least one cycle counting unit to operate.

[0024] Preferably, the oscillation circuit includes: a bias module for providing a bias current; a first capacitor and a second capacitor connected in series between a first voltage and a ground terminal, a first node between the first capacitor and the second capacitor outputting a charge / discharge control signal, and the first node outputting the output clock signal via a second inverter; a charging module for charging the second capacitor according to the calibration current, feedback current, and bias current when the output clock signal is at an active level; and a discharging module for discharging the second capacitor when the output clock signal is at an inactive level.

[0025] Preferably, when the charge / discharge control signal is at an invalid level, the output clock signal is at an active level; when the charge / discharge control signal is at an active level, the output clock signal is at an invalid level.

[0026] Preferably, the charging module includes: a third current mirror unit for mirroring the calibration current, feedback current, and bias current; a fifth switch connected between the output terminal and ground terminal of the third current mirror unit, the control terminal of which receives the output clock signal; and a sixth switch connected between the second node between the third current mirror unit and the fifth switch and the first node, the control terminal of which receives the charge / discharge control signal.

[0027] Preferably, the discharge module includes: a fourth current mirror unit for mirroring the calibration current, feedback current, and bias current; a seventh switch connected in series with the fourth current mirror unit between the first voltage and the ground terminal, the control terminal of which receives the output clock signal; and an eighth switch connected between the third node between the seventh switch and the fourth current mirror unit and the first node, the control terminal of which receives the charge / discharge control signal.

[0028] Preferably, when the charge / discharge control signal is at an invalid level, the output clock signal is at an valid level, the fifth switch is turned off, the sixth switch is turned on, the seventh switch is turned on, and the eighth switch is turned off, thus charging the second capacitor.

[0029] Preferably, when the charge / discharge control signal is at an active level, the output clock signal is at an inactive level, the fifth switch is turned on, the sixth switch is turned off, the seventh switch is turned off, the eighth switch is turned on, and the second capacitor discharges.

[0030] Preferably, the spread spectrum clock circuit further includes a calibration module for generating a calibration current based on the calibration value and the second reference current.

[0031] Preferably, the calibration module includes: a calibration storage unit for storing calibration values; a reference voltage source for generating a second reference current; and a digital-to-analog conversion unit for generating a calibration current based on the calibration values ​​and the second reference current.

[0032] The spread spectrum clock circuit provided in this embodiment of the invention uses a period counting circuit to generate multiple trigger signals based on the rising or falling edge of the spread spectrum clock signal, thereby controlling the magnitude of the feedback current and controlling the input current of the oscillation circuit to achieve frequency modulation of the spread spectrum clock signal. This spread spectrum clock circuit has a simple structure and high stability.

[0033] Furthermore, the feedback current is the product of the first reference current and the count value, where the count value is the trigger signal output by multiple flip-flops that controls the number of corresponding current mirror branches that are turned on. The magnitude of the count value of the periodic counting circuit can control the maximum frequency in the spread spectrum clock signal, and thus control the frequency range of the spread spectrum clock signal.

[0034] Furthermore, the cycle counting circuit has strong scalability. Multiple cycle counting circuits can be set up, and control signals can be used to control whether each cycle counting circuit performs spread spectrum and to set the current step of each cycle counting circuit, thereby realizing the modulation of different frequency ranges of the spread spectrum clock signal. Attached Figure Description

[0035] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which: Figure 1 The graph shows the radiation intensity as a function of the frequency of the unmodulated clock signal. Figure 2 A graph showing the radiation intensity as a function of the frequency generated by the modulated clock; Figure 3 This diagram illustrates the structure of a spread spectrum clock circuit according to an embodiment of the present invention. Figure 4 A circuit diagram of the period counting circuit in an embodiment of the present invention is shown; Figure 5 The timing waveform diagram of the period counting circuit in an embodiment of the present invention is shown; Figure 6 The waveform of the output clock signal in an embodiment of the present invention is shown; Figure 7 A circuit diagram of the oscillation circuit in an embodiment of the present invention is shown; Figure 8 A circuit diagram of a period counting circuit according to another embodiment of the present invention is shown; Figure 9 A circuit diagram of the control module is shown in another embodiment of the present invention; Figure 10 The diagram shows the waveforms of the first enable signal and the second enable signal in another embodiment of the present invention. Detailed Implementation

[0036] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, and procedures are not described in detail. Furthermore, the accompanying drawings are not necessarily drawn to scale.

[0037] Figure 3 A schematic diagram of the spread spectrum clock circuit according to an embodiment of the present invention is shown. See also Figure 3 The spread spectrum clock circuit 100 includes an oscillation circuit 110 and a period counting circuit 120.

[0038] The oscillation circuit 100 is used to generate an output clock signal CLKout with varying frequency based on the calibration current Icont and the feedback current Ifb.

[0039] In this embodiment, the oscillation circuit 110 generates an output clock signal CLKout by charging and discharging a capacitor. The frequency fout of the output clock signal CLKout is controlled by the sum of the calibration current Icont and the feedback current Ifb.

[0040] The cycle counting circuit 120 is used to receive the output clock signal CLKout, and sequentially triggers multiple trigger signals at the rising or falling edge of the output clock signal CLKout, and outputs a periodically changing feedback current Ifb according to the multiple trigger signals and the first reference current Iref1.

[0041] In this embodiment, the cycle counting circuit 120 generates multiple trigger signals sequentially at the rising or falling edge of the output clock signal CLKout, and outputs a periodically changing feedback current Ifb based on the multiple trigger signals and the first reference current Iref1. The periodic change of this feedback current Ifb causes the input current of the oscillation circuit 110 to change periodically, thereby generating a periodically changing output clock signal CLKout.

[0042] Specifically, see Figure 4 Taking k flip-flops as rising edge flip-flops as an example, the cycle counting circuit 120 includes a first inverter, k flip-flops and k current mirror branches. The k flip-flops are cascaded and correspond one-to-one with the k current mirror branches.

[0043] The k-th flip-flop triggers the k-th trigger signal Qk at the k-th rising edge of the output clock signal CLKout. The k-th trigger signal Qk is inverted by the first inverter U1 and output to the first flip-flop. The i-th flip-flop triggers the i-th trigger signal Qi at the i-th rising edge of the output clock signal CLKout. The i-th trigger signal is output to the (i+1)-th flip-flop. Where i ≤ k-1, and i and k are both positive integers. The period counting circuit 120 controls the corresponding current mirror branch to be turned on or off according to the k trigger signals (Q1-Qk) output by the k flip-flops. When the trigger signal output by the flip-flop controls the corresponding current mirror branch to be turned on, the currents output by the turned-on current mirror branches are superimposed to output a periodically changing feedback current Ifb. The feedback current Ifb is the product of the first reference current Iref1 and the count value Counter, and the count value Counter is the number of current mirror branches turned on by the trigger signals output by the k flip-flops. The frequency of the output clock signal CLKout decreases as the count value Counter decreases and increases as the count value Counter increases.

[0044] In this embodiment, the first enable terminals (SDN) of the k flip-flops are connected together to receive the first enable signal (sdn); the second enable terminals (CDN) of the k flip-flops are connected together to receive the second enable signal (cdn); the clock terminals (clk) of the k flip-flops are connected together to receive the output clock signal (CLKout); the input terminal (D) of each flip-flop is connected to the output terminal (Q) of the previous flip-flop, and the output terminal (Q) is connected to the input terminal (D) of the next flip-flop; the output terminal (Q) of the kth flip-flop is connected to the input terminal (D) of the first flip-flop via the first inverter (U1); the output terminals of the k flip-flops output k trigger signals (Q1-Qk) respectively. This embodiment uses k flip-flops as an example, where k is a positive integer. The counter value (Counter) increments from 0 to k and then decrements from k to 0.

[0045] In a preferred embodiment, the clock terminals of multiple flip-flops are connected together, and the output clock signal CLKout is transmitted to the clock terminals of the multiple flip-flops via a buffer Buf.

[0046] In this embodiment, when the k flip-flops are rising edge flip-flops, when the output clock signal changes on the rising edge, when the first enable signal sdn and the second enable signal cdn are both at valid levels, and when the output clock signal CLKout changes from an invalid level to a valid level, the input terminal D inputs a valid level, and the output terminal Q of the flip-flop outputs a valid level accordingly.

[0047] In a preferred embodiment, when the k flip-flops are falling-edge flip-flops, when the output clock signal changes on the falling edge, when both the first enable signal sdn and the second enable signal cdn are at active levels, and when the output clock signal CLKout changes from active to inactive, the input terminal D inputs an active level, and the output terminal Q of the flip-flop outputs an active level accordingly.

[0048] The cycle counting circuit 120 includes a first current mirror unit 121 and a second current mirror unit 122. The first current mirror unit 121 mirrors the first reference current Iref1 from k current mirror branches and controls whether the mirrored current in the k current mirror branches is output according to k trigger signals Q1-Qk. The second current mirror unit 122 is connected to the output terminals of multiple current mirror branches and is used to output the mirrored current in multiple current mirror branches to generate a feedback current Ifb.

[0049] The first current mirror unit 121 includes a first current source, a first switch M1, and a plurality of second switches M21-M2k. The first current source is used to provide a first reference current Iref1. The first switch M1 is connected in series with the first current source between the first voltage V1 and the ground terminal. The k second switches M21-M2k form current mirrors with the first switch M1 respectively. The k switches S1-Sk are respectively connected to the output terminals of the plurality of current mirror branches, and are used to control the conduction and cutoff of the k current mirror branches according to the k trigger signals Q1-Qk to control whether the mirror current of the k current mirror branches is output.

[0050] In this embodiment, the first switch M1 and the first current source are connected in series between the first voltage V1 and the ground terminal; the control terminal of the first switch M1 is connected to the node between the first switch M1 and the first current source; each second switch M2 and its corresponding switch S are connected in series between the first voltage V1 and the second current mirror unit; the control terminal of each second switch M2 is connected to the control terminal of the first switch M1; the control terminal of each switch S is connected to the output terminal Q of the corresponding trigger. When the trigger signal Q is invalid, the corresponding switch S is turned on; when the trigger signal Q is valid, the corresponding switch S is turned off.

[0051] The second current mirror unit 122 includes a third switch M3 and a fourth switch M4. The first end of the third switch M3 is connected to the output end of multiple current mirror branches, the second end is grounded, and its control end is connected to the first end of the third switch M3. The first end of the fourth switch M4 outputs a feedback current Ifb, the second end is grounded, and its control end is connected to the control end of the third switch M3.

[0052] In this circuit, multiple trigger signals Q1-Qk have equal periods, and the effective level time (e.g., high level) and ineffective level time (e.g., low level) of the multiple trigger signals Q1-Qk are both k cycles of the output clock signal. When the trigger signal is ineffective, the corresponding current mirror branch is turned on.

[0053] See Figure 5 If k=3, the number of current mirror branches that are turned on increases sequentially with the clock cycle as follows: 3, 2, 1, 0, 1, 2, 3, and so on in a periodic cycle. Each clock cycle is not consistent. The more current mirror branches that are turned on, the larger the feedback current, the narrower the pulse width of the output clock signal CLKout, the smaller the corresponding clock cycle, and the faster the frequency.

[0054] Specifically, multiple trigger signals Q1-Qk sequentially undergo level transitions on the rising edge of the output clock signal. Within the 2k cycles of the output clock signal CLKout, the trigger signals sequentially change from invalid to valid levels in the first k cycles, and then sequentially change from valid to invalid levels in the next k cycles. In the first k cycles, the frequency of the output clock signal decreases as the count value decreases; in the next k cycles, the frequency of the output clock signal increases as the count value increases.

[0055] See Figure 5 Taking k=3 as an example, during the first to third cycles, when the rising edge of the output clock signal CLKout arrives in the first cycle, the trigger signal Q1 changes from an invalid level to an active level and remains active. When the rising edge of the output clock signal CLKout arrives in the second cycle, the trigger signal Q2 changes from an invalid level to an active level and remains active. When the rising edge of the output clock signal CLKout arrives in the third cycle, the trigger signal Q3 changes from an invalid level to an active level and remains active. When the rising edge of the output clock signal CLKout arrives in the fourth cycle, the trigger signal Q1 changes from an active level to an invalid level and remains invalid. When the rising edge of the output clock signal CLKout arrives in the fifth cycle, the trigger signal Q2 changes from an active level to an invalid level and remains invalid. When the rising edge of the output clock signal CLKout arrives in the sixth cycle, the trigger signal Q3 changes from an active level to an invalid level and remains invalid. When all trigger signals Q1-Q3 are invalid, the three current mirror branches corresponding to the trigger signals are turned on; when trigger signal Q1 is valid and trigger signals Q2 and Q3 are invalid, the two corresponding current mirror branches are turned on; when trigger signals Q1 and Q2 are valid and trigger signal Q3 is invalid, the one corresponding current mirror branch is turned on; when all trigger signals Q1-Q3 are valid, all three current mirror branches corresponding to the trigger signals are turned off, i.e., zero current mirror branches are turned on; this cycle continues periodically.

[0056] See Figure 6 Taking k=64 as an example, the number of current mirror branches that are turned on increases from 0 to 64 and then decreases from 64 back to 0. The frequency of the output clock signal CLKout changes periodically. The more current mirror branches that are turned on, the narrower the pulse width of the output clock signal CLKout and the faster the frequency.

[0057] See Figure 7The oscillation circuit 110 includes a bias module 111, a first capacitor C1, a second capacitor C2, a charging module 112, and a discharging module 113. The bias module 111 provides a bias current Ib. The first capacitor C1 and the second capacitor C2 are connected in series between the first voltage V1 and the ground terminal. A first node A1 between the first capacitor C1 and the second capacitor C2 outputs a charging / discharging control signal Sw. The first node A1 outputs the output clock signal CLKout via the second inverter U2.

[0058] In this embodiment, the charge / discharge control signal Sw and the output clock signal CLKout are completely opposite signals. That is, when the charge / discharge control signal Sw is at an invalid level, the output clock signal CLKout is at an active level; when the charge / discharge control signal Sw is at an active level, the output clock signal CLKout is at an invalid level.

[0059] The charging module 112 is used to charge the second capacitor C2 according to the calibration current Icont, the feedback current Ifb, and the bias current Ib when the output clock signal CLKout is at an active level.

[0060] In this embodiment, the charging module 112 includes a third current mirror unit 1221, a fifth switch M5, and a sixth switch M6. The third current mirror unit 1221 mirrors the calibration current Icont, the feedback current Ifb, and the bias current Ib. The fifth switch M5 is connected between the output terminal and the ground terminal of the third current mirror unit 1221, and its control terminal receives the output clock signal CLKout. The sixth switch M6 is connected between the second node A2 and the first node A1 between the third current mirror unit and the fifth switch, and its control terminal receives the charge / discharge control signal Sw.

[0061] The discharge module 113 is used to discharge the second capacitor C2 when the output clock signal CLKout is at an invalid level.

[0062] In this embodiment, the discharge module 113 includes a fourth current mirror unit 1131, a seventh switch M7, and an eighth switch M8. The fourth current mirror unit 1131 mirrors the calibration current Icont, the feedback current Ifb, and the bias current Ib. The seventh switch M7 is connected in series with the fourth current mirror unit between the first voltage V1 and the ground terminal, and its control terminal receives the output clock signal CLKout. The eighth switch M8 is connected between the third node A3 and the first node A1 between the seventh switch M7 and the fourth current mirror unit, and its control terminal receives the charge / discharge control signal Sw.

[0063] The oscillation circuit 100 operates as follows: When the charge / discharge control signal Sw is invalid, the output clock signal CLKout is valid, the fifth switch M5 is off, the sixth switch M6 is on, the seventh switch M7 is on, and the eighth switch M8 is off, charging the second capacitor C2. When the charge / discharge control signal Sw is valid, the output clock signal CLKout is invalid, the fifth switch M5 is on, the sixth switch M6 is off, the seventh switch M7 is off, and the eighth switch M8 is on, discharging the second capacitor C2.

[0064] In a preferred embodiment, the spread spectrum clock circuit 100 further includes a calibration module 130 for generating a calibration current Icont based on the calibration value Trim and the second reference current Iref2.

[0065] Specifically, the calibration module 130 includes a calibration storage unit 131, a reference voltage source 132, and a digital-to-analog converter 133. The calibration storage unit 131 is used to store the calibration value Trim; the reference voltage source 132 is used to generate a second reference current Iref2; and the digital-to-analog converter 133 is used to generate a calibration current Icont based on the calibration value Trim and the second reference current Iref2.

[0066] In this embodiment, the calibration value Trim is, for example, a 4-bit digital signal, which is converted into a corresponding calibration current Icont via the digital-to-analog converter 133. The calibration value Trim can cause the oscillation circuit 110 to output a clock signal at a preset frequency.

[0067] The spread spectrum clock circuit provided in this embodiment of the invention generates multiple trigger signals based on the rising or falling edge of the spread spectrum clock signal to control the magnitude of the feedback current, thereby controlling the input current of the oscillation circuit and achieving frequency modulation of the spread spectrum clock signal. This spread spectrum clock circuit has a simple structure and high stability.

[0068] Furthermore, the feedback current is the product of the first reference current and the count value, where the count value is the trigger signal output by multiple flip-flops that controls the number of corresponding current mirror branches that are turned on. The magnitude of the count value of the periodic counting circuit can control the maximum frequency in the spread spectrum clock signal, and thus control the frequency range of the spread spectrum clock signal.

[0069] Figure 8 A circuit diagram of a cycle counting circuit provided in another embodiment of the present invention is shown. Compared with the above embodiment, the cycle counting circuit 120 of this embodiment includes multiple cycle counting units. Each cycle counting unit includes a first inverter, k flip-flops, and k current mirror branches. The k flip-flops are cascaded, and each of the k flip-flops in the cycle counting unit corresponds one-to-one with the k current mirror branches.

[0070] The number of flip-flops k in each cycle counting unit is different to generate different feedback currents Ifb.

[0071] The cycle counting circuit further includes a control module 123 for generating multiple first enable signals sdn and multiple second enable signals cdn, wherein the multiple first enable signals sdn and multiple second enable signals cdn control at least one cycle counting unit to operate.

[0072] This embodiment uses two cycle counting units as an example for illustration. The circuit diagram of each cycle counting unit is the same as that in the above embodiment, and will not be repeated here.

[0073] The first cycle counting unit 120a has k1 flip-flops, and the second cycle counting unit has k2 flip-flops. When both the first enable signal SDN1 and the second enable signal CDN1 of the first cycle counting unit 120a are active, the first cycle counting unit 120a operates, and the count value Counter increases from 0 to k1 and then decreases back to 0. Correspondingly, the number of current mirror branches that are active increases from 0 to k1 and then decreases back to 0, meaning the feedback current Ifb increases from 0 to k1*I1 and then decreases back to 0. When both the first enable signal SDN2 and the second enable signal CDN2 of the second cycle counting unit 120b are active, the second cycle counting unit 120b operates, and the count value Counter increases from 0 to k2 and then decreases back to 0. Correspondingly, the number of current mirror branches that are active increases from 0 to k2 and then decreases back to 0, meaning the feedback current Ifb increases from 0 to k2*I2 and then decreases back to 0.

[0074] In this embodiment, see Figure 9The control module 123 includes a third inverter U3 and first OR gates OR1 to fourth OR gates OR4. Specifically, the first input of the first OR gate OR1 is connected to the extended signal Nspread via the third inverter U3, its second input receives the first selection signal SEL1, and its output outputs the second enable signal cdn1 of the first cycle counting unit 120a. The first input of the second OR gate OR2 is connected to the extended signal Nspread via the third inverter U3, its second input receives the first selection signal SEL1, and its output outputs the first enable signal sdn1 of the first cycle counting unit 120a. The first input of the third OR gate OR3 is connected to the extended signal Nspread via the third inverter U3, its second input receives the second selection signal SEL2, and its output outputs the second enable signal cdn2 of the second cycle counting unit 120b. The first input of the fourth OR gate OR4 is connected to the extended signal Nspread via the third inverter U3, its second input receives the second selection signal SEL2, and its output outputs the first enable signal sdn2 of the second cycle counting unit 120b.

[0075] See Figure 10 When the extended signal Nspread is invalid, the first enable signal sdn1 and the second enable signal cdn1 of the first cycle counting unit 120a are controlled by the first selection signal SEL1, and the first enable signal sdn2 and the second enable signal cdn2 of the second cycle counting unit 120b are controlled by the second selection signal SEL2. When the first selection signal SEL1 is active and the second selection signal SEL2 is inactive, the maximum count value Counter is k1, and the minimum step of the feedback current Ifb is I1. When the first selection signal SEL1 is inactive... When both the first and second selection signals SEL1 and SEL2 are active, the maximum counter value is k2, and the minimum step of the feedback current Ifb is I2. When both the first and second selection signals SEL1 and SEL2 are active, the maximum counter value is k1+k2, and the minimum step of the feedback current Ifb is I1+I2. When both the first and second selection signals SEL1 and SEL2 are inactive, the spread spectrum function is disabled, and the frequency of the output clock signal CLKout generated by the oscillation circuit 100 remains unchanged.

[0076] The cycle counting circuit of this invention has strong scalability. Multiple cycle counting circuits are set up and control signals are used to control whether each cycle counting circuit performs spread spectrum and to set the current step of each cycle counting circuit, thereby realizing the modulation of different frequency ranges of the spread spectrum clock signal.

[0077] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.

Claims

1. A spread spectrum clock circuit, characterized in that, include: The oscillation circuit generates an output clock signal with varying frequency based on the calibration current and the feedback current. The period counting circuit receives the output clock signal and sequentially generates multiple trigger signals at the rising or falling edge of the output clock signal. Based on the multiple trigger signals and the first reference current, it outputs a periodically changing feedback current. The cycle counting circuit includes k cascaded flip-flops. The clock terminals of the k flip-flops are connected together to receive the output clock signal. The nth flip-flop triggers the nth trigger signal on the nth rising or falling edge of the output clock signal. The feedback current is the product of the first reference current and the count value. The count value is the number of current mirror branches controlled by the trigger signals output by the k flip-flops, where n ≤ k and n and k are both positive integers.

2. The spread spectrum clock circuit according to claim 1, characterized in that, The cycle counting circuit also includes a first inverter and k current mirror branches, and the k flip-flops are connected one-to-one with the k current mirror branches; The kth trigger signal is inverted by the first inverter and then output to the first flip-flop; The i-th trigger signal is output to the (i+1)-th flip-flop; where i ≤ k-1, and i is a positive integer; The period counting circuit controls the corresponding current mirror branch to be turned on or off according to the k trigger signals output by the k triggers. When the trigger signal output by the trigger controls the corresponding current mirror branch to be turned on, the current output by the turned current mirror branch is superimposed to output a periodically changing feedback current.

3. The spread spectrum clock circuit according to claim 2, characterized in that, The feedback current is the product of the first reference current and the count value, and the count value is the number of current mirror branches that are turned on by the trigger signals output by the k triggers.

4. The spread spectrum clock circuit according to claim 3, characterized in that, The count value is accumulated from 0 to k in each cycle and then decreased from k back to 0.

5. The spread spectrum clock circuit according to claim 4, characterized in that, The frequency of the output clock signal decreases as the count value decreases and increases as the count value increases.

6. The spread spectrum clock circuit according to claim 2, characterized in that, The first enable terminals of the k flip-flops are connected together to receive a first enable signal; The second enable terminals of the k flip-flops are connected together to receive the second enable signal; The output terminals of the k flip-flops each output a trigger signal.

7. The spread spectrum clock circuit according to claim 6, characterized in that, When the k flip-flops are rising edge flip-flops, they change on the rising edge of the output clock signal; when the k flip-flops are falling edge flip-flops, they change on the falling edge of the output clock signal.

8. The spread spectrum clock circuit according to claim 7, characterized in that, When the k flip-flops are rising edge flip-flops, when both the first enable signal and the second enable signal are at valid levels, and when the output clock signal changes from an invalid level to a valid level, the output of the flip-flop will output a valid level if the input of the flip-flop is at a valid level, and the output of the flip-flop will output an invalid level if the input of the flip-flop is at an invalid level.

9. The spread spectrum clock circuit according to claim 7, characterized in that, When the k flip-flops are falling-edge flip-flops, when both the first enable signal and the second enable signal are active, and the output clock signal changes from active to inactive, the input terminal of the flip-flop receives an active level, and the output terminal of the flip-flop outputs an active level.

10. The spread spectrum clock circuit according to claim 3, characterized in that, The period counting circuit also includes: The first current mirror unit mirrors the first reference current from the k current mirror branches and controls whether the mirrored current in the k current mirror branches is output according to the k trigger signals. The second current mirror unit is connected to the output terminals of the k current mirror branches and is used to output the mirrored currents from the k current mirror branches to generate feedback current.

11. The spread spectrum clock circuit according to claim 10, characterized in that, The first current mirror unit includes: A first current source is used to provide a first reference current; The first switching transistor is connected in series with the first current source between the first voltage and the ground terminal; k second switching transistors are respectively formed with the first switching transistor to form current mirrors; k switches are connected to the output terminals of k current mirror branches respectively, and are used to control the conduction and cutoff of the k current mirror branches according to the k trigger signals to control whether the mirror current of the k current mirror branches is output.

12. The spread spectrum clock circuit according to claim 11, characterized in that, The first switching transistor and the first current source are connected in series between the first voltage and the ground terminal; The control terminal of the first switch is connected to the node between the first switch and the first current source; Each second switch and its corresponding switch are connected in series between the first voltage and second current mirror units; The control terminal of each second switch is connected to the control terminal of the first switch. The control terminal of each switch is connected to the output terminal of the corresponding trigger.

13. The spread spectrum clock circuit according to claim 11, characterized in that, When the trigger signal is at an invalid level, the corresponding switch is turned on; when the trigger signal is at an valid level, the corresponding switch is turned off.

14. The spread spectrum clock circuit according to claim 10, characterized in that, The second current mirror unit includes a third switch and a fourth switch. Among them, the first end of the third switch is connected to the output end of multiple current mirror branches, the second end is grounded, and its control end is connected to the first end of the third switch. The first terminal of the fourth switch outputs feedback current, the second terminal is grounded, and its control terminal is connected to the control terminal of the third switch.

15. The spread spectrum clock circuit according to claim 3, characterized in that, The cycle counting circuit includes multiple cycle counting units. Each cycle counting unit includes a first inverter, k flip-flops, and k current mirror branches. The k flip-flops are cascaded, and each of the k flip-flops in the cycle counting unit corresponds one-to-one with the k current mirror branches.

16. The spread spectrum clock circuit according to claim 15, characterized in that, The number of triggers k in each cycle counting unit is different to generate different feedback currents.

17. The spread spectrum clock circuit according to claim 15, characterized in that, The period counting circuit also includes: A control module is configured to generate a plurality of first enable signals and a plurality of second enable signals, wherein the plurality of first enable signals and the plurality of second enable signals control at least one cycle counting unit to operate.

18. The spread spectrum clock circuit according to claim 1, characterized in that, The oscillation circuit includes: The bias module is used to provide bias current; A first capacitor and a second capacitor are connected in series between a first voltage and a ground terminal. A first node between the first capacitor and the second capacitor outputs a charge / discharge control signal. The first node outputs the output clock signal via a second inverter. The charging module is used to charge the second capacitor according to the calibration current, feedback current and bias current when the output clock signal is at an effective level. A discharge module is used to discharge the second capacitor when the output clock signal is at an invalid level.

19. The spread spectrum clock circuit according to claim 18, characterized in that, When the charge / discharge control signal is at an invalid level, the output clock signal is at an active level; when the charge / discharge control signal is at an active level, the output clock signal is at an invalid level.

20. The spread spectrum clock circuit according to claim 18, characterized in that, The charging module includes: The third current mirror unit is used to mirror the calibration current, feedback current and bias current output. The fifth switching transistor is connected between the output terminal and the ground terminal of the third current mirror unit, and its control terminal receives the output clock signal. The sixth switch is connected between the second node and the first node between the third current mirror unit and the fifth switch, and its control terminal receives the charge and discharge control signal.

21. The spread spectrum clock circuit according to claim 20, characterized in that, The discharge module includes: The fourth current mirror unit is used to mirror the calibration current, feedback current, and bias current output. The seventh switch is connected in series with the fourth current mirror unit between the first voltage and the ground terminal, and its control terminal receives the output clock signal; The eighth switch is connected between the third node and the first node, which is between the seventh switch and the fourth current mirror unit, and its control terminal receives the charge and discharge control signal.

22. The spread spectrum clock circuit according to claim 21, characterized in that, When the charge / discharge control signal is at an invalid level, the output clock signal is at an valid level, the fifth switch is turned off, the sixth switch is turned on, the seventh switch is turned on, and the eighth switch is turned off, thus charging the second capacitor.

23. The spread spectrum clock circuit according to claim 22, characterized in that, When the charge / discharge control signal is at an active level, the output clock signal is at an inactive level, the fifth switch is turned on, the sixth switch is turned off, the seventh switch is turned off, the eighth switch is turned on, and the second capacitor discharges.

24. The spread spectrum clock circuit according to claim 1, characterized in that, Also includes: The calibration module is used to generate a calibration current based on the calibration value and the second reference current.

25. The spread spectrum clock circuit according to claim 24, characterized in that, The calibration module includes: A calibration storage unit is used to store calibration values; A reference voltage source is used to generate a second reference current; A digital-to-analog converter is used to generate a calibration current based on the calibration value and the second reference current.

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