Semiconductor device

Abstract

Embodiments provide a semiconductor device in which alignment accuracy of a high concentration diffusion region with respect to a low concentration diffusion region is improved. The semiconductor device of the embodiments has: a first region provided on a substrate and containing an impurity of a first conductivity type; a second region provided in the first region and containing an impurity of the first conductivity type at a higher concentration than the first region; a first structure body provided on the substrate on one side of the second region in a first direction, the first direction being a direction along the substrate, and having at least a first side wall on the side of the second region; a second structure body provided on the substrate on the other side of the second region in the first direction, and having at least a second side wall on the side of the second region; and a contact portion extending through between the first and second side walls facing each other with the second region interposed therebetween, and electrically connected to the second region.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Japanese Patent Application No. 2021-152926 (filed on September 21, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices. Background Technology

[0004] Semiconductor devices, including CMOS transistors, typically have a diffusion region diffused with impurities, a gate electrode disposed on the diffusion region, and a contact portion electrically connected to the diffusion region. To reduce the contact resistance between the contact portion and the diffusion region, a region with a high concentration of diffused impurities is sometimes provided within the diffusion region contacted by the contact portion. However, in order to maintain the breakdown voltage in the semiconductor device, attempting to reliably contain a high-concentration diffusion region within a low-concentration diffusion region sometimes leads to the enlargement of the semiconductor device. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a semiconductor device that can improve the alignment accuracy of a high-concentration diffusion region relative to a low-concentration diffusion region.

[0006] The semiconductor device of the embodiment includes: a first region disposed on a substrate containing impurities of a first conductivity type; a second region disposed in the first region, containing impurities of the first conductivity type at a higher concentration than those in the first region; a first structure disposed on the substrate on one side of the second region in a first direction, having a first sidewall at least on the second region side, the first direction being a direction along the substrate; a second structure disposed on the substrate on the other side of the second region in the first direction, having a second sidewall at least on the second region side; and a contact portion extending into the second region through the first and second sidewalls facing each other and sandwiching the second region, and electrically connected to the second region. Attached Figure Description

[0007] Figure 1 This is a diagram illustrating an example of the structure of the semiconductor device involved in Embodiment 1.

[0008] Figure 2 This is a diagram illustrating a portion of the sequence of the semiconductor device manufacturing method according to Embodiment 1.

[0009] Figure 3 This is a diagram illustrating a portion of the sequence of the manufacturing method of the semiconductor device according to Embodiment 1.

[0010] Figure 4 This is a diagram illustrating a portion of the sequence of the manufacturing method of the semiconductor device according to Embodiment 1.

[0011] Figure 5 This is a diagram illustrating a portion of the sequence of the manufacturing method of the semiconductor device according to Embodiment 1.

[0012] Figure 6 This is a diagram illustrating a portion of the sequence of the manufacturing method of the semiconductor device according to Embodiment 1.

[0013] Figure 7 This diagram illustrates an example of a situation where the contact portion of the semiconductor device according to Embodiment 1 is shifted.

[0014] Figure 8 This diagram illustrates a portion of the sequence of the manufacturing method of the semiconductor device according to a variation of Embodiment 1.

[0015] Figure 9 This diagram illustrates a portion of the sequence of the manufacturing method of the semiconductor device according to a variation of Embodiment 1.

[0016] Figure 10 This is a diagram illustrating an example of the structure of a semiconductor device involved in a variation 2 of Embodiment 1.

[0017] Figure 11 This diagram illustrates a portion of the manufacturing method of the semiconductor device according to a variation of Embodiment 1, Example 2.

[0018] Figure 12 This diagram illustrates a portion of the manufacturing method of the semiconductor device according to a variation of Embodiment 1, Example 2.

[0019] Figure 13 This is a diagram illustrating an example of the structure of the semiconductor device involved in Embodiment 2.

[0020] Figure 14 This is a diagram illustrating a portion of the sequence of the semiconductor device manufacturing method according to Embodiment 2.

[0021] Figure 15 This is a diagram illustrating a portion of the sequence of the semiconductor device manufacturing method according to Embodiment 2.

[0022] Figure 16 This is a diagram illustrating a portion of the sequence of the semiconductor device manufacturing method according to Embodiment 2.

[0023] Figure 17 This is a diagram illustrating an example of a situation where the contact portion of the semiconductor device according to Embodiment 2 is shifted in position.

[0024] Figure 18 This is a diagram illustrating an example of the structure of a semiconductor device involved in a variation of Embodiment 2, Example 1.

[0025] Figure 19 This is a diagram illustrating an example of the structure of a semiconductor device according to a variation of Embodiment 2.

[0026] Figure 20 This is a block diagram of a semiconductor memory device involved in other embodiments.

[0027] Figure 21 This is an equivalent circuit diagram illustrating an example of the structure of the memory cell array and row decoder of a semiconductor memory device according to other embodiments. Detailed Implementation

[0028] The present invention will now be described in detail with reference to the accompanying drawings. Furthermore, the present invention is not limited to the embodiments described below. Additionally, the constituent elements in the following embodiments include constituent elements that can be readily conceived by those skilled in the art or substantially the same constituent elements.

[0029] [Implementation Method 1]

[0030] Hereinafter, Embodiment 1 will be described in detail with reference to the accompanying drawings.

[0031] (Structure of a semiconductor device)

[0032] Figure 1 This is a diagram illustrating an example of the structure of the semiconductor device 100 according to Embodiment 1. Figure 1 (a) is a cross-sectional view of the semiconductor device 100 along the X direction. Figure 1 (b) is a schematic top view showing the layout of the semiconductor device 100. Figure 1 In (b), the main components shown are the element separation layer 111, diffusion regions 112, 113, 114, silicide layer 115, and gate electrodes 130, 150, with other structures omitted.

[0033] Furthermore, in this specification, the surface of the substrate 110 on which the transistor TRhv is formed is designated as the upper surface, and the direction of the continuously stacked gate electrode 130 of the transistor TRhv is designated as the upper side of the semiconductor device 100.

[0034] Furthermore, in this specification, both the X and Y directions refer to the directions oriented along the upper surface of the substrate 110, and the X and Y directions are orthogonal to each other. Additionally, in Embodiment 1, the gate length L direction of the gate electrode 130, described later, is sometimes referred to as the first direction, which is along the X direction. Furthermore, the gate width W direction of the gate electrode 130, which intersects the first direction, is sometimes referred to as the second direction, which is along the Y direction. However, the semiconductor device 100 may contain manufacturing errors, therefore the first and second directions are not necessarily orthogonal.

[0035] like Figure 1 As shown, the semiconductor device 100 includes a substrate 110, transistors TRhv and TRvv, an interlayer insulating layer 190, and contacts CShv, CGhv, CSvv, and CGvv.

[0036] Transistor TRhv has a diffusion region 112, a gate insulating layer 121, a gate electrode 130, a barrier layer 171, and an inner liner layer 181. The structure of transistor TRhv may include a diffusion region 114 and a silicide layer 115. Transistor TRvv has a diffusion region 112, a gate insulating layer 121, a gate electrode 150, and an inner liner layer 181. The structure of transistor TRvv may include a diffusion region 113 and a silicide layer 115.

[0037] The substrate 110 is, for example, a semiconductor substrate such as a silicon substrate. A component separation layer 111 is provided on the substrate 110 to electrically separate the formation regions of transistors TRhv and TRvv.

[0038] Furthermore, in the region of the substrate 110 where the transistor TRhv is formed after being separated by the component separation layer 111, diffusion regions 112 and 114 and a silicide layer 115 are provided. Additionally, in the region of the substrate 110 where the transistor TRvv is formed after being separated by the component separation layer 111, diffusion regions 112 and 113 and a silicide layer 115 are provided.

[0039] The diffusion region 112, which is the first region, is a region formed by diffusing impurities of a specified conductivity type, either P-type or N-type, at a specified concentration onto the substrate 110, and includes the upper surface of the substrate 110. The diffusion region 112 extends substantially over the region separated by the element separation layer 111.

[0040] The diffusion region 114, which is the second region, is a region formed by the diffusion of impurities of the same conductivity type as the diffusion region 112 within the diffusion region 112, including the upper surface of the substrate 110, at a higher concentration than the diffusion region 112. Multiple diffusion regions 114 are provided within the diffusion region 112. A predetermined distance is maintained between each diffusion region 114 and the component separation layer 111 in both the X and Y directions.

[0041] Diffusion region 113 is disposed within diffusion region 112, encompassing the upper surface of substrate 110. It is formed by the diffusion of impurities of the same conductivity type as diffusion regions 112 and 114, at a higher concentration than diffusion region 112 but a lower concentration than diffusion region 114, onto substrate 110. Multiple diffusion regions 113 are disposed within diffusion region 112. These diffusion regions 113 cover approximately the entire surface of diffusion region 112, except for the area directly below gate electrode 150, which will be described later.

[0042] Therefore, the Y-direction end of each diffusion region 113 can contact the component separation layer 111. Additionally, the diffusion region 113 located at its X-direction end among the plurality of diffusion regions 113 can contact the component separation layer 111 on the X-direction side. Therefore, the X-direction width of each diffusion region 113 can be larger than the X-direction width of the aforementioned diffusion region 114.

[0043] The silicide layer 115 is formed by including the upper surface of the substrate 110, on which diffusion regions 113 and 114 are provided. The silicide layer 115 is, for example, a tungsten silicide layer, a nickel silicide layer, or a nickel-platinum silicide layer.

[0044] Here, the center position of the silicide layer 115 along the X direction is substantially the same as the center positions of the diffusion regions 114 along the X direction. The relationship between the silicide layer 115 and the diffusion regions 114, as described above, also holds in the Y direction. That is, the center position of the silicide layer 115 along the Y direction is substantially the same as the center positions of the diffusion regions 114 along the Y direction.

[0045] Thus, the silicide layer 115 does not deviate from the diffusion region 114, but is contained within the diffusion region 114, surrounding the surrounding area through the diffusion region 114 of a specified width.

[0046] On the other hand, the silicide layer 115 covers almost the entire surface of the diffusion region 113, except for the vicinity of the gate electrode 150 described later. In this case, the center position of the silicide layer 115 in the X direction may not coincide with the respective center positions of the diffusion region 113 in the X direction.

[0047] Furthermore, the Y-direction end of each silicide layer 115 can contact the device separation layer 111. Additionally, the silicide layer 115 disposed at its X-direction end among the plurality of silicide layers 115 can contact the device separation layer 111 on the X-direction side.

[0048] Therefore, the width of the silicide layer 115 in the X direction provided in the diffusion region 113 can be larger than the width of the silicide layer 115 in the X direction provided in the diffusion region 114.

[0049] In the region between a plurality of diffusion regions 114 arranged in the X direction on the diffusion region 112 of the substrate 110, a gate insulating layer 121, a gate electrode 130, and a cap layer 141 extending in the Y direction are sequentially stacked. The gate insulating layer 121, the gate electrode 130, and the cap layer 141 are disposed in the Y direction, protruding up to the device separation layer 111.

[0050] The gate insulating layer 121 is, for example, a silicon oxide layer, a hafnium oxide layer, or a zirconium oxide layer. The cap layer 141 is, for example, an insulating layer such as a silicon nitride layer.

[0051] The gate electrode 130 has a multi-metal gate structure, which includes, for example, a polysilicon electrode 131 and a metal electrode 132 disposed on the polysilicon electrode 131. That is, the polysilicon electrode 131 is, for example, a conductive polysilicon layer, and functions as a polysilicon gate. The metal electrode 132 is, for example, a tungsten silicide layer, and functions as a metal gate.

[0052] Here, the length of the gate electrode 130 along the Y-direction, which is the extension direction of the gate electrode 130, is the gate width W. Additionally, the length of the gate electrode 130 along the X-direction, which intersects the extension direction of the gate electrode 130, is the gate length L.

[0053] A spacer layer 122 is provided on the side of the gate electrode 130 and the cap layer 141. The spacer layer 122 is, for example, an insulating layer such as a silicon oxide layer.

[0054] A barrier layer 171 is provided in the region of the substrate 110, which is separated by the component separation layer 111 and has diffusion regions 112 and 114. The barrier layer 171 is, for example, an insulating layer such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0055] The barrier layer 171 covers the diffusion region 112 except for the portion where the diffusion region 114 is provided, and substantially covers the entire gate insulating layer 121, gate electrode 130, cap layer 141, and spacer layer 122. The barrier layer 171 may also cover a portion of the element separation layer 111. According to the structure described above, the barrier layer 171 is formed on both sides of the gate electrode 130 in the X direction with the spacer layer 122 in between.

[0056] Here, for adjacent gate electrodes 130 in the X direction, the center position in the X direction between the barrier layers 171 facing each other on the sides of these gate electrodes 130 substantially coincides with the center position in the X direction of the diffusion region 114 disposed between these gate electrodes 130. Therefore, the center position in the X direction between these barrier layers 171 also substantially coincides with the center position in the X direction of the silicide layer 115 disposed in the diffusion region 114.

[0057] Furthermore, the center position in the X-direction direction between the barrier layer 171 disposed on the side opposite to the gate electrode 130 at the X-direction end and the barrier layer 171 disposed on the side opposite to the gate electrode 130 is substantially the same as the center position in the X-direction direction of the diffusion region 114. Therefore, the center position in the X-direction direction between these barrier layers 171 is also substantially the same as the center position in the X-direction direction of the silicide layer 115 disposed in the diffusion region 114.

[0058] Therefore, a predetermined distance is ensured between the gate electrode 130 and the diffusion region 114 arranged in the X direction and the diffusion region 114.

[0059] Furthermore, the relationship between the aforementioned barrier layer 171, the diffusion region 114, and the silicide layer 115 also holds in the Y direction. That is, the center position of the barrier layers 171, which are positioned opposite each other in the Y direction and sandwiching the diffusion region 114, is substantially the same as the center position of the diffusion region 114 and the center position of the silicide layer 115 in the Y direction.

[0060] An inner liner layer 181, such as a silicon nitride layer, is provided on the barrier layer 171. The inner liner layer 181 covers, through the barrier layer 171, the diffusion regions 112 and 114 (excluding the connection portion of the contact portion CShv), the gate insulating layer 121, the gate electrode 130 (excluding the connection portion of the contact portion CGhv), the upper surface of the cap layer 141, and the spacer layer 122.

[0061] Additionally, the inner liner 181 covers the side surface of the barrier layer 171 on the diffusion region 114 side, which is disposed in the X direction opposite to the gate electrode 130 and sandwiching the diffusion region 114, as well as the side surface of the element separation layer 111. Furthermore, as described later, the inner liner 181 covers the area of ​​the substrate 110 in which the diffusion regions 112 and 113 are disposed.

[0062] According to the structure described above, on both sides of the gate electrode 130 in the X direction, a sidewall 182, which serves as a first sidewall, is disposed based on the inner liner layer 181, with the spacer layer 122 and the barrier layer 171 in between.

[0063] In addition, the structure including the gate insulating layer 121, the gate electrode 130, the cap layer 141, the spacer layer 122, and the barrier layers 171 and sidewalls 182 on both sides of the gate electrode 130 in the X direction is sometimes referred to as the stack 161 as the first structure.

[0064] In addition, the inner liner 181 forms a state in which sidewalls 183, which serve as second sidewalls, are arranged on both sides of the barrier layer 171 in the X direction. The inner liner 181 covers the side of the barrier layer 171 on the side of the diffusion region 114 that is disposed in the X direction opposite to the gate electrode 130, which sandwiches the diffusion region 114, and the side of the element separation layer 111.

[0065] In addition, the structure that includes the barrier layer 171 without the gate electrode 130 and the sidewalls 183 on both sides of the barrier layer 171 in the X direction is sometimes referred to as the stack 162 as the second structure.

[0066] An interlayer insulating layer 190, such as a silicon oxide layer, is provided on the inner liner layer 181. The interlayer insulating layer 190 covers substantially the entire diffusion regions 112 and 114, the gate insulating layer 121, the gate electrode 130, the cap layer 141, and the spacer layer 122 through the barrier layer 171 and the inner liner layer 181. In addition, as described later, the interlayer insulating layer 190 also extends to the regions where the diffusion regions 112 and 113 are provided, for example, covering the entire upper surface of the substrate 110.

[0067] A contact portion CGhv, serving as a second contact portion, is connected to the upper surface of the gate electrode 130 of the transistor TRhv. This contact portion CGhv penetrates the interlayer insulating layer 190, the inner liner layer 181, the barrier layer 171, and the cap layer 141, thereby applying a gate voltage to the gate electrode 130.

[0068] A contact portion CShv, serving as a first contact portion, is connected to the silicide layer 115 on the diffusion regions 114 on both sides of the gate electrode 130 in the X direction. This contact portion CShv penetrates the interlayer insulating layer 190, the inner liner layer 181, and the barrier layer 171, applying a high voltage to the source / drain of the transistor TRhv. The contact portion CShv is shared between adjacent transistors TRhv along the X direction.

[0069] These contact parts, such as CGhv and CShv, are primarily composed of metals like tungsten.

[0070] As described above, a transistor TRhv, which is disposed near a diffusion region 114 containing a high concentration of impurities and to which a high voltage is applied, is configured, for example, as a high-voltage (HV) MOS (Metal Oxide Semiconductor) transistor. The transistor TRhv described above is also referred to as a high-voltage MOS transistor.

[0071] Here, the contact portion CShv between adjacent transistors TRhv in the X direction passes through the sidewalls 182 of each transistor TRhv arranged on both sides in the X direction and connects to the silicide layer 115. At this time, the contact portion CShv between transistors TRhv contacts at least one of the sidewalls 182 on both sides in the X direction via its side surface. Figure 1 In example (a), the contact portion CShv contacts both the sidewalls 182 on both sides in the X direction.

[0072] In other words, the thickness of the barrier layer 171 and the inner liner layer 181 is preferably adjusted such that the gap between the sidewalls 182 of each gate electrode 130 arranged on both sides in the X direction is, for example, the same as the diameter of the contact portion CShv.

[0073] In addition, among the multiple transistors TRhv arranged along the X direction, on one side of the transistor TRhv disposed at the end in the X direction, the contact portion CShv passes between the sidewall 182 of the transistor TRhv disposed on one side in the X direction and the sidewall 183 of the barrier layer 171 disposed on the other side in the X direction, and connects to the silicide layer 115.

[0074] At this time, in the transistor TRhv at the X-direction end, the contact portion CShv contacts at least one of the sidewalls 182 and 183 on both sides of the X-direction via its side surface. Figure 1 In example (a), the contact part CShv contacts both the sidewalls 182 and 183.

[0075] In other words, it is preferable to adjust the thickness of the barrier layer 171 and the inner liner layer 181 such that the gap between the gate electrode 130 disposed on both sides in the X direction and the sidewalls 182, 183 of the barrier layer 171 without the gate electrode 130 is, for example, the same as the diameter of the contact portion CShv.

[0076] As described above, the diffusion region 114 and the silicide layer 115, to which a high voltage is applied through the contact portion CShv, maintain a predetermined distance from the device separation layer 111 in both the X and Y directions. Furthermore, the silicide layer 115 is surrounded by the diffusion region 114 of a predetermined width. This maintains the withstand voltage of the transistor TRhv.

[0077] In the region between multiple diffusion regions 113 arranged in the X direction on the diffusion region 112 of the substrate 110, a gate insulating layer 121, a gate electrode 150, and a cap layer 141 extending in the Y direction are sequentially stacked. The gate insulating layer 121, the gate electrode 150, and the cap layer 141 are provided protruding in the Y direction up to the device separation layer 111. Spacer layers 122 are provided on the sides of the gate electrode 150 and the cap layer 141.

[0078] The gate electrode 150 has, for example, the same structure as the gate electrode 130. That is, the gate electrode 150 is configured as a polysilicon metal gate, which has, for example, a polysilicon electrode 151 and a metal electrode 152 disposed on the polysilicon electrode 151.

[0079] Furthermore, as described above, the inner liner 181 covers the area of ​​the substrate 110 where the diffusion regions 112 and 113 are provided. In the area where the diffusion regions 112 and 113 are provided, the inner liner 181 covers substantially the entire diffusion regions 112 and 113, the gate insulating layer 121, the gate electrode 150, the upper surface of the cap layer 141, and the spacer layer 122, except for the connection portion of the contact portion CSvv.

[0080] According to the structure described above, on both sides of the gate electrode 150 in the X direction, sidewalls 184 based on the inner liner layer 181 are arranged with spacer layer 122 between them.

[0081] Additionally, as described above, the interlayer insulating layer 190 covers, for example, the entire upper surface of the substrate 110. In the regions where diffusion regions 112 and 113 are provided, the interlayer insulating layer 190 covers substantially the entire diffusion regions 112 and 113, the gate insulating layer 121, the gate electrode 150, the cap layer 141, and the spacer layer 122 through the inner liner layer 181.

[0082] A contact portion CGvv is connected to the upper surface of the gate electrode 150 of the transistor TRvv. The contact portion CGvv passes through the interlayer insulating layer 190, the inner liner layer 181 and the cap layer 141, and applies a gate voltage to the gate electrode 150.

[0083] A silicide layer 115 disposed on the diffusion regions 113 on both sides of the gate electrode 150 in the X direction is connected to a contact portion CSvv. The contact portion CSvv penetrates the interlayer insulating layer 190 and the inner liner layer 181, and applies a voltage to the source / drain of the transistor TRvv. The contact portion CSvv is shared between adjacent transistors TRvv in the X direction.

[0084] These contact parts CGvv and CSvv, like the aforementioned contact parts CGhv and CShv, are primarily composed of metals such as tungsten.

[0085] As described above, the transistor TRvv, which is disposed near the diffusion region 113 and subjected to a relatively low voltage, is configured, for example, as a low voltage (LV: Low Voltage / VLV: Very Low Voltage) MOS transistor, and the diffusion region 113 contains a lower concentration of impurities than the diffusion region 114.

[0086] The contact portion CSvv between adjacent transistors TRvv in the X direction passes between the sidewalls 184 of each transistor TRvv arranged on both sides in the X direction and is connected to the silicide layer 115.

[0087] Additionally, on one side of the transistor TRvv, which is located at the end of the X-direction among the plurality of transistors TRvv arranged along the X-direction, a contact CSvv passes near the sidewall 184 of the transistor TRvv located on the X-direction side and connects to the silicide layer 115.

[0088] Here, the widths of the diffusion region 113 and the silicide layer 115 disposed in the diffusion region 113 in the X direction are, for example, larger than the widths of the diffusion region 114 and the silicide layer 115 disposed in the diffusion region 114 in the X direction. Furthermore, the sidewall 184 of the gate electrode 150 is disposed on the side of the spacer layer 122 without being separated by the barrier layer 171.

[0089] Therefore, a larger space than that in the transistor TRhv is ensured between the sidewalls 184 and the contacts CSvv in each transistor TRvv. Thus, these contacts CSvv are connected to the silicide layer 115, for example, without contacting any sidewalls 184 on their sides.

[0090] Furthermore, as described above, the diffusion region 113 and the silicide layer 115 are in contact with the device separation layer 111, for example, in the X direction. However, the voltage applied to the diffusion region 113 and the silicide layer 115 through the contact portion CSvv is relatively low, thus sufficiently maintaining the withstand voltage of the transistor TRvv.

[0091] (Semiconductor device manufacturing method)

[0092] Next, use Figures 2-7 The manufacturing method of the semiconductor device 100 according to Embodiment 1 will be described. Figures 2-6 This diagram illustrates a portion of the sequence of the manufacturing method of the semiconductor device 100 according to Embodiment 1. More specifically, Figures 2-6 A cross-section of a semiconductor device 100 in the manufacturing process is shown along the X direction.

[0093] like Figure 2As shown in (a), a device separation layer 111 is formed on a substrate 110 such as a silicon substrate. The device separation layer 111 is formed, for example, by forming a trench that surrounds the regions of the substrate 110 where transistors TRhv and TRvv are formed, and filling the trench with an insulating layer such as a silicon oxide layer. In addition, a gate insulating layer 120 is formed integrally on the upper surface of the substrate 110.

[0094] Additionally, gate electrodes 130 and 150 and a cap layer 141 are formed on the gate insulating layer 120 within the region surrounded by the element separation layer 111. The gate electrodes 130, 150, and cap layer 141 are formed, for example, by forming a conductive polysilicon layer on the gate insulating layer 120, forming a metal layer on the polysilicon layer, forming a silicon nitride layer on the metal layer, and etching these layers into the shape of the gate electrodes 130 and 150.

[0095] In addition, polycrystalline silicon layers, metal layers, and silicon nitride layers can be formed, for example, using CVD (Chemical Vapor Deposition) methods.

[0096] like Figure 2 As shown in (b), impurities are implanted in the region surrounded by the element separation layer 111, separated by the gate insulating layer 120. At this time, the implantation of impurities into the gate electrodes 130 and 150 is suppressed by the cap layer 141.

[0097] In addition, although the injection of impurities directly below the gate electrodes 130 and 150 is hindered, the impurities can be diffused to a predetermined depth in the substrate 110, including directly below the gate electrodes 130 and 150, by means of annealing or the like.

[0098] Thus, a diffusion region 112 is formed approximately throughout the area surrounded by the component separation layer 111.

[0099] like Figure 2 As shown in (c), a spacer layer 122 is formed on the side of the gate electrodes 130, 150 and the cap layer 141. Specifically, for example, an insulating layer such as a silicon oxide layer is formed to completely cover the gate electrodes 130, 150 and the cap layer 141, and the insulating layer is etched back until the cap layer 141 on the gate electrodes 130, 150 is exposed.

[0100] Additionally, the portion of the gate insulating layer 120 not covered by the gate electrodes 130, 150, cap layer 141, and spacer layer 122 is etched away, and a gate insulating layer 121 separated according to each gate electrode 130, 150 is formed at the position overlapping with the gate electrodes 130, 150, cap layer 141, and spacer layer 122.

[0101] like Figure 2As shown in (d), a mask layer MK1, such as a resist layer, is formed. This mask layer MK1 covers the region where the gate electrode 130 is formed within the region surrounded by the element separation layer 111, and opens the region where the gate electrode 150 is formed.

[0102] Furthermore, impurities are further implanted into the region where the gate electrode 150 is formed, and the impurities are diffused to a predetermined depth in the substrate 110 by means of annealing or the like. At this time, the implantation of impurities into the gate electrode 150 is suppressed by the cap layer 141.

[0103] Alternatively, at this time, the impurities may be introduced into the lower surface of the gate insulating layer 121 at the location overlapping with the spacer layer 122, without reaching directly below the gate electrode 150.

[0104] Thus, a diffusion region 113 is formed in the area of ​​the element separation layer 111 other than directly below the gate electrode 150.

[0105] Then, remove the mask layer MK1.

[0106] like Figure 3 As shown in (a), for example, a barrier layer 170 is formed on the entire surface of the substrate 110, covering the gate insulating layer 121, gate electrodes 130 and 150, cap layer 141, and spacer layer 122. The barrier layer 170 is preferably a single barrier layer 170 having a thickness on its side that is sufficient to form a sidewall 183 based on the inner liner layer 181.

[0107] like Figure 3 As shown in (b), a mask layer MK2, such as a resist layer, is formed. This mask layer MK2 covers the region where the gate electrode 130 is formed within the region surrounded by the element separation layer 111, and opens the region where the gate electrode 150 is formed.

[0108] like Figure 3 As shown in (c), the barrier layer 170 exposed from the mask layer MK2 is etched away. This forms a barrier layer 170 that covers the region where the gate electrode 130 is formed within the area surrounded by the element separation layer 111. Then, the mask layer MK2 is removed.

[0109] like Figure 4 As shown in (a), for example, a mask layer MK3 is formed that covers the substrate 110 substantially entirely and has openings at predetermined positions on both sides of the gate electrode 130 in the X direction.

[0110] like Figure 4 As shown in (b), the barrier layer 170 exposed from the mask layer MK2 is etched away. As a result, a barrier layer 171 with openings 171op at predetermined positions on both sides of the gate electrode 130 in the X direction is formed.

[0111] like Figure 4 As shown in (c), impurities are injected into the diffusion region 112 of the substrate 110 exposed from the opening 171op of the barrier layer 171, and the impurities are diffused to a predetermined depth of the substrate 110 by means of annealing or the like.

[0112] At this time, impurities can wrap around to a certain extent toward the lower surface of the barrier layer 171. Alternatively, they can wrap around to the lower surface of the gate insulating layer 121, which overlaps with the spacer layer 122, without reaching directly below the gate electrode 130. In other words, by adjusting the thickness of the barrier layer 171, the wrapping of impurities directly below the gate electrode 130 can be suppressed.

[0113] Thus, diffusion regions 114 are formed at predetermined positions on both sides of the gate electrode 130 in the X direction. At this time, the diffusion regions 114 are self-aligned relative to the opening 171op of the barrier layer 171.

[0114] That is, impurities mainly diffuse from the substrate 110 exposed from the opening 171op of the barrier layer 171. In addition, for example, the distance by which impurities travel from the opening 171op to the lower surface of the barrier layer 171 is approximately equal on both sides in the X direction and on both sides in the Y direction.

[0115] Therefore, as described above, the center position between the barrier layers 171 on both sides of the opening 171op in the X direction and on both sides of the opening in the Y direction is substantially the same as the center position of the diffusion region 114 in the X direction and in the Y direction.

[0116] Then, remove the mask layer MK3.

[0117] like Figure 4 As shown in (d), a silicide layer 115 is formed on the surface of the substrate 110 exposed in the region surrounded by the element separation layer 111. The silicide layer 115 is, for example, a self-aligned silicide layer formed in a self-aligned manner on the surface of the exposed substrate 110.

[0118] Specifically, for example, a metal layer such as a tungsten layer is formed on the entire surface of the substrate 110, and then annealing is performed.

[0119] Thus, in the region where the gate electrode 130 is formed, the portion of the diffusion region 114 exposed from the barrier layer 171 covering the gate insulating layer 121, the gate electrode 130, the cap layer 141 and the spacer layer 122 is silicided to form a metal compound of the metal layer and the silicon of the substrate, namely the silicide layer 115.

[0120] At this time, the silicide layer 115 formed on the diffusion region 114 is self-aligned relative to the diffusion region 114, and similarly, it is also self-aligned relative to the opening 171op of the barrier layer 171 when the diffusion region 114 is formed.

[0121] Therefore, as described above, the center position between the barrier layers 171 on both sides of the opening 171op in the X direction and on both sides of the opening in the Y direction is substantially consistent with the center position of the silicide layer 115 in the X direction and in the Y direction. In addition, the center position of the silicide layer 115 in the X direction and in the Y direction is also substantially consistent with the center position of the diffusion region 114 in the X direction and in the Y direction.

[0122] Additionally, in the region where the gate electrode 150 is formed, in the portion of the diffusion region 113 exposed from the gate insulating layer 121 below the gate electrode 130, cap layer 141 and spacer layer 122, a metal compound of the metal layer and the silicon of the substrate, namely a silicide layer 115, is formed.

[0123] At this time, the silicide layer 115 formed on the diffusion region 113 is self-aligned relative to the diffusion region 113. On the other hand, silicide formation is suppressed on the upper surface of the gate electrode 150 because it is covered by the cap layer 141.

[0124] Then, the tungsten and other metal layers, except for the siliconized portions, are removed.

[0125] like Figure 5 As shown in (a), an inner liner layer 180 is formed, for example, covering the entire surface of the substrate 110.

[0126] Thus, with the barrier layer 171 in between, the gate insulating layer 121, the gate electrode 130, the cap layer 141, and the spacer layer 122 are covered by the inner liner layer 180, forming sidewalls 182 on both sides of the gate electrode 130 in the X direction. Additionally, a stack 161 is formed, and a transistor TRhv is formed.

[0127] Additionally, the barrier layer 171, which does not contain the gate electrode 130, is covered by the inner liner layer 180, and sidewalls 183 are formed on the sides of the ends of the diffusion region 114 of the barrier layer 171 and the end of the element separation layer 111. Furthermore, a laminate 162 is formed.

[0128] Additionally, the gate insulating layer 121, gate electrode 150, cap layer 141, and spacer layer 122 are covered by an inner liner layer 180, and sidewalls 184 are formed on both sides of the gate electrode 150 in the X direction. Furthermore, a transistor TRvv is formed.

[0129] like Figure 5As shown in (b), an interlayer insulating layer 190 is formed, for example, covering the entire surface of the substrate 110. In addition, a mask layer MK4, such as a resist layer, is formed on the gate electrodes 130 and 150 and at predetermined positions on both sides of the gate electrodes 130 and 150 in the X direction.

[0130] like Figure 6 As shown, the interlayer insulating layer 190 exposed from the mask layer MK4 is etched through.

[0131] Furthermore, a hole HL is formed on the gate electrode 130, through which the inner liner layer 180, the barrier layer 171 and the cap layer 141 are penetrated to reach the gate electrode 130.

[0132] Additionally, holes HL are formed on both sides of the gate electrode 130 in the X direction, which penetrate the inner liner 180 and the barrier layer 171 to reach the silicide layer 115 on the diffusion region 114.

[0133] At this time, the hole HL between adjacent gate electrodes 130 in the X direction contacts at least one of the sidewalls 182 formed on the sidewalls of the gate electrodes 130 disposed on both sides in the X direction, and reaches the silicide layer 115 through the space between these sidewalls 182.

[0134] Additionally, at this time, the hole HL on one side of the gate electrode 130 at the X-direction end contacts at least one of the sidewall 182 formed on the side of the gate electrode 130 on one side in the X-direction and the sidewall 183 formed on the side of the barrier layer 171 on the other side in the X-direction, and reaches the silicide layer 115 through the space between these sidewalls 182 and 183.

[0135] Additionally, a hole HL is formed on the gate electrode 150, through which the inner liner layer 180 and the cap layer 141 pass to the gate electrode 150.

[0136] Additionally, holes HL are formed on both sides of the gate electrode 150 in the X direction, through which the inner liner 180 passes to the silicide layer 115 on the diffusion region 113.

[0137] At this point, as described above, there is a relatively large margin in the distance between the sidewalls 184 that are opposite each other on the sides of the adjacent gate electrodes 150 along the X direction, so that the hole HL does not contact any of the sidewalls 184 and reaches the silicide layer 115.

[0138] Additionally, at this time, the hole HL on the side of the gate electrode 150 at the X-direction end is also formed with sufficient distance relative to the sidewall 184 formed on the side of the gate electrode 150 on the X-direction side, so that it reaches the silicide layer 115 without contacting the sidewall 184 of the gate electrode 150 at the X-direction end.

[0139] Additionally, as described above, the inner liner 181 through which the hole HL is formed is created by using the etching process of the mask layer MK4.

[0140] Then, the mask layer MK4 is removed, and tungsten or the like is filled into each hole HL. This forms contact portions CGhv and CGvv that are respectively connected to the gate electrodes 130 and 150. Additionally, contact portions CShv and CSvv are formed that are respectively connected to the silicide layers 115 formed in the diffusion regions 114 and 113 near each gate electrode 130 and 150.

[0141] The above describes the manufacture of the semiconductor device 100 according to Embodiment 1.

[0142] Here, use Figure 7 The alignment accuracy of the contact portion CShv relative to the diffusion region 114 and the silicide layer 115 is explained.

[0143] Figure 7 This diagram illustrates an example of a situation where the contact portion CShv of the semiconductor device 100 according to Embodiment 1 has undergone a positional shift. More specifically, Figure 7 A cross-section along the X direction of a semiconductor device 100 having a contact portion CShv that has experienced a positional shift is shown, as described above. Figure 1 Corresponding to (a).

[0144] like Figure 7 As shown, the contacts CShv, CGhv, CSvv, and CGvv, which are respectively connected to transistors TRhv and TRvv, are formed by offsetting to the left of the paper, i.e., in the X direction, from their standard designed positions. This positional offset, as described above, is due to, for example, the aforementioned... Figure 5 The mask layer MK4 shown in (b) is formed under conditions where there is an overlap deviation with respect to transistors TRhv and TRvv.

[0145] Therefore, the contacts CGhv and CGvv are located at positions offset to the left of the paper from the center position of the gate electrodes 130 and 150 of transistors TRhv and TRvv, respectively.

[0146] In addition, the contacts CShv and CSvv are respectively formed at positions offset to the left of the paper from the center position in the X direction of the diffusion region 114 and silicide layer 115 of transistor TRhv and the diffusion region 113 and silicide layer 115 of transistor TRvv.

[0147] At this time, the diffusion region 113 and silicide layer 115 of transistor TRvv have relatively large dimensions. Therefore, the contact portion CSvv is connected to the diffusion region 113 and silicide layer 115 without deviating from them.

[0148] On the other hand, the size of the diffusion region 114 and silicide layer 115 of transistor TRhv is smaller than that of the diffusion region 113 and silicide layer 115 of transistor TRvv, and a portion of the lower end of the contact portion CShv is formed at a position offset from the diffusion region 114 and silicide layer 115.

[0149] However, between adjacent transistors TRhv along the X direction, the portion of the contact portion CShv that deviates from the diffusion region 114 and the silicide layer 115 contacts the sidewall 182 of the transistor TRhv on the X direction side, thereby terminating without reaching the upper surface of the substrate 110.

[0150] Additionally, on the X-direction side of the transistor TRhv at the X-direction end, the portion of the contact portion CShv that deviates from the diffusion region 114 and the silicide layer 115 contacts the sidewall 183 of the barrier layer 171 that does not include the gate electrode 130 on the X-direction side, thereby terminating without reaching the upper surface of the substrate 110.

[0151] As mentioned above Figure 6 As shown, the hole HL is formed by penetrating the inner liner layer 180 on the upper surface of the silicide layer 115. At this time, by adjusting the etching conditions, a hole HL is formed that penetrates the thin inner liner layer 180 on the upper surface of the silicide layer 115, but does not penetrate the sidewalls 182 and 183, which are thicker in the stacking direction of the stacked bodies 161 and 162 and formed on the sides of the gate electrode 130 and the barrier layer 171. Thus, a contact portion CShv is formed, which is partially terminated at the lower end by the sidewalls 182 and 183.

[0152] As described above, in the semiconductor device 100, when a portion of the contact portion CShv is formed at a position offset from the diffusion region 114 and the silicide layer 115, the lower end of the contact portion CShv will also self-align with the diffusion region 114 and the silicide layer 115.

[0153] (Summary)

[0154] In recent years, the miniaturization of semiconductor devices containing transistors has continued to advance. On the other hand, in HV transistors that require high voltage withstand capability, reducing the contact resistance between the contacts where high voltages are applied to the source / drain and the diffusion region has become a technical challenge. Therefore, at the contact points connecting to the diffusion region, a high concentration of impurities is sometimes implanted to reduce the contact resistance. Furthermore, on top of this, a silicide layer is sometimes formed in the high-concentration diffusion region using self-aligned silicide formation techniques, achieving a further reduction in contact resistance.

[0155] At this point, to maintain the high breakdown voltage of the transistor, it is preferable that the high-concentration diffusion region is surrounded by the low-concentration diffusion region with relatively high resistance, thereby maintaining a predetermined distance from the device separation layer and the gate electrode. Furthermore, in the silicide layer, to reduce junction leakage and maintain junction breakdown voltage, it is preferable that the silicide layer is surrounded by a high-concentration diffusion region of a predetermined width. Additionally, a sufficiently wide high-concentration diffusion region is ensured between the silicide layer and the device separation layer.

[0156] However, considering the continuous diffusion of impurities within the substrate, it is sometimes difficult to adequately ensure the distance between the high-concentration diffusion region and the device separation layer and gate electrode during the miniaturization of semiconductor devices. There are concerns that the opening size of the resist layer pattern used during impurity implantation may reach the exposure limit.

[0157] Therefore, there are limitations, for example, on how to sufficiently increase the impurity concentration. Alternatively, sometimes low-concentration diffusion regions must be formed to a sufficient size, hindering the miniaturization of semiconductor devices. Furthermore, from the viewpoint of alignment accuracy between the silicide layer and the high-concentration diffusion region, the high-concentration diffusion region must sometimes also be formed to a sufficient size, further hindering the miniaturization of semiconductor devices. Additionally, alignment between the high-concentration diffusion region or the silicide layer and the contact portion becomes difficult.

[0158] According to Embodiment 1, the semiconductor device 100 has on both sides of the diffusion region 114 in the X direction: a gate electrode 130; a stack 161 including sidewalls 182 disposed on both sides of the gate electrode 130 in the X direction separated by a barrier layer 171; and a stack 162 including: a barrier layer 171 that does not include the gate electrode 130 and sidewalls 183 disposed on both sides of the barrier layer 171 in the X direction.

[0159] When forming the diffusion region 114, the barrier layer 171 of the stack 161 and the barrier layer 171 of the stack 162 are used as masks for impurity implantation, and the diffusion region 114 is formed in a self-aligned manner. In addition, the same barrier layer 171 is used as a mask when forming the silicide layer 115.

[0160] Therefore, by unifying the alignment of the diffusion region 114 with respect to the element separation layer 111 and the gate electrode 130, and the alignment of the silicide layer 115 with respect to the diffusion region 114, their alignment accuracy can be improved. As a result, the impurity concentration of the diffusion region 114 can be sufficiently increased to reduce the contact resistance, and the size of the diffusion region 114 can be reduced to miniaturize the semiconductor device 100.

[0161] According to Embodiment 1, the semiconductor device 100 has a contact portion CShv that passes between the sidewall 182 and the sidewall 183 of the laminate 161 and is electrically connected to the diffusion region 114. Thus, the contact portion CShv is self-aligned relative to the diffusion region 114 and the silicide layer 115. This suppresses high resistance in the contact portion CShv and also suppresses poor conductivity between the contact portion CShv and the diffusion region 114 and the silicide layer 115.

[0162] (Variation Example 1)

[0163] In the above-described implementation method 1, as follows: Figure 4 As shown in (a) to (b), a barrier layer 171 with an opening 171op at the formation location of the diffusion region 114 is formed using a mask layer MK3. However, when the opening 171op is provided in the barrier layer 170, a simpler mask layer can also be used. Below, using... Figure 8 and Figure 9 An example of a method for manufacturing a semiconductor device using a simple mask layer will be illustrated.

[0164] Figure 8 and Figure 9 This diagram illustrates a portion of the sequence of the manufacturing method of the semiconductor device according to Variation 1 of Embodiment 1. More specifically, Figure 8 and Figure 9 A cross-section of the semiconductor device along the X direction is shown in the manufacturing process of Modified Example 1.

[0165] Furthermore, in the semiconductor device of Modified Example 1, the same reference numerals are used for structures identical to those in Embodiment 1 described above, and their descriptions are omitted. Additionally, in the semiconductor device of Modified Example 1, the direction along the X direction is sometimes referred to as the first direction, and the direction along the Y direction is sometimes referred to as the second direction.

[0166] The method for manufacturing the semiconductor device in Modification 1 can, for example, be configured as described above. Figure 3 The process shown in (c) is the same as that of the semiconductor device 100 in Embodiment 1.

[0167] like Figure 8 As shown in (a), replacing the above. Figure 4 The mask layer MK3 of (a) is, for example, a resist layer MK5 that forms a resist layer that substantially covers the entire substrate 110 and has an opening in the region where the gate electrode 130 is formed within the region surrounded by the element separation layer 111.

[0168] Thus, a plurality of gate electrodes 130 adjacent in the X direction and covered by the barrier layer 170 are exposed from the opening in the mask layer MK5. However, the opening in the mask layer MK5 is formed at a position that allows sufficient penetration into the inner side of the element separation layer 111 surrounding the region where the gate electrodes 130 are formed.

[0169] like Figure 8 As shown in (b), the barrier layer 170 exposed from the mask layer MK5 is etched away. As a result, a barrier layer 172 with an opening 172op is formed, which exposes a predetermined position on the upper surface of the substrate 110 on both sides of the plurality of gate electrodes 130 in the X direction and on the upper surface of the cap layer 141 on the plurality of gate electrodes 130.

[0170] That is, an opening 172op is formed in the barrier layer 172, surrounded by the barrier layer 172 remaining on the side of the element separation layer 111. However, the barrier layer 172 provided on the side of the gate electrode 130 is not removed and remains in the opening 172op.

[0171] like Figure 8 As shown in (c), while the area where the gate electrode 150 is formed is covered by the mask layer MK5, impurities are injected into the diffusion region 112 of the substrate 110 exposed from the opening 172op of the barrier layer 172, and the impurities are diffused to a predetermined depth in the substrate 110 by means of annealing or the like. At this time, by adjusting the thickness of the barrier layer 172, the infiltration of impurities directly below the gate electrode 130 is suppressed.

[0172] Additionally, at this time, the barrier layer 172 above the gate electrode 130 is removed. However, in this case, in addition to the barrier layer 172 remaining on the side of the element separation layer 111 and the barrier layer 172 remaining on the side of the gate electrode 130, the gate insulating layer 121, the gate electrode 130, the cap layer 141, and the spacer layer 122 themselves also function as masks for impurity implantation.

[0173] Therefore, a diffusion region 114 can be formed that maintains a predetermined distance from the gate electrode 130, including the region directly below the gate electrode 130, and is self-aligned relative to the opening 172op of the barrier layer 172.

[0174] In addition, as described above, although the barrier layer 172 above the gate electrode 130 is removed, the cap layer 141 on the upper surface of the gate electrode 130 suppresses the injection of impurities into the gate electrode 130.

[0175] After the diffusion region 114 is formed, and the mask layer MK5 is removed, the surface of the diffusion region 114 of the substrate 110 exposed from the opening 172op of the barrier layer 172 is siliconized in the region where the gate electrode 130 is formed, and a silicide layer 115 is formed in a self-aligned manner with respect to the diffusion region 114 and the opening 172op of the barrier layer 172.

[0176] Thus, the silicide layer 115 is also formed using the barrier layer 172 remaining on the side of the device separation layer 111, which serves as a mask for impurity implantation, the barrier layer 172 remaining on the side of the gate electrode 130, the gate insulating layer 121, the gate electrode 130, the cap layer 141, and the spacer layer 122 as masks. Furthermore, the upper surface of the gate electrode 130 is covered by the cap layer 141, thereby suppressing silicide formation.

[0177] On the other hand, in the region where the gate electrode 150 is formed, a silicide layer 115 is formed in the portion of the diffusion region 113 that exposes the gate insulating layer 121 below the gate electrode 150, the cap layer 141, and the spacer layer 122. In the gate electrode 150, silicide formation of the gate electrode 150 is also suppressed by the cap layer 141 on the upper surface.

[0178] Subsequently, the semiconductor device of Modification 1, such as Figure 8 (d) Figure 9 As shown in (b), it is manufactured in the same manner as the semiconductor device 100 of Embodiment 1 described above.

[0179] like Figure 8 As shown in (d), for example, an inner liner layer 180 is formed that covers the entire surface of the substrate 110.

[0180] Therefore, the gate insulating layer 121, the gate electrode 130, the cap layer 141, and the spacer layer 122 and barrier layer 172 on both sides of the gate electrode 130 in the X direction are covered by the inner liner layer 180, forming sidewalls 182 on both sides of the gate electrode 130 in the X direction. In addition, a stacked body 163 as the first structure is formed, and a transistor TR1hv is formed.

[0181] Additionally, the barrier layer 172, which does not include the gate electrode 130, is covered by the inner liner layer 180, and sidewalls 183 are formed on the sides of the ends of the diffusion region 114 of the barrier layer 172 and the ends of the element separation layer 111. Furthermore, a laminate 164 is formed as a second structure.

[0182] Additionally, the gate insulating layer 121, gate electrode 150, cap layer 141, and spacer layer 122 are covered by an inner liner layer 180, and sidewalls 184 are formed on both sides of the gate electrode 150 in the X direction. Furthermore, a transistor TRvv is formed.

[0183] like Figure 9 As shown in (a), for example, an interlayer insulating layer 190 is formed to cover the entire surface of the substrate 110. In addition, a mask layer MK4, such as a resist layer, is formed on the gate electrodes 130 and 150 and at predetermined positions on both sides of the gate electrodes 130 and 150 in the X direction.

[0184] In addition, the interlayer insulating layer 190, inner liner layer 180, cap layer 141, etc., which are exposed from the mask layer MK4, are appropriately etched through. As a result, a plurality of holes HL are formed that reach the gate electrodes 130 and 150 and the substrate 110 on both sides of the gate electrodes 130 and 150 in the X direction.

[0185] like Figure 9 As shown in (b), the mask layer MK4 is removed, and tungsten or the like is filled into each hole HL. This forms contact portions CGhv and CGvv that are respectively connected to the gate electrodes 130 and 150. Additionally, contact portions CShv and CSvv are formed that are respectively connected to the silicide layers 115 formed in the diffusion regions 114 and 113 near each gate electrode 130 and 150.

[0186] The above describes the manufacture of the semiconductor device 101 of Modified Example 1.

[0187] According to the manufacturing method of semiconductor device 101 of Modified Example 1, in the region surrounded by element separation layer 111, a mask layer MK5 having an opening that exposes the gate electrode 130 covered by barrier layer 170 is used to remove the barrier layer 170 exposed from the opening.

[0188] By using the mask layer MK5 as described above, it is not necessary to align the mask layer MK5 with openings at predetermined positions on both sides of the gate electrode 130 in the X direction. As a result, the exposure load during the formation of the mask layer MK5 can be reduced.

[0189] In addition, in order to reduce the exposure load, the opening of the mask layer MK5 can be reduced, and the diffusion region 114 and silicide layer 115 can be formed in a narrower area, which can further miniaturize the semiconductor device 101.

[0190] The semiconductor device 101 according to Modified Example 1, except for the above-described Embodiment 1, has the same effects.

[0191] (Variation Example 2)

[0192] In Embodiment 1 described above, for example, the transistor TRhv is configured to have a polysilicon metal gate structure, which has a polysilicon electrode 131 and a metal electrode 132. However, the structure of Embodiment 1 described above can also be applied to transistors having a polysilicon gate structure, for example. Hereinafter, using... Figures 10-12 An application example of the above structure in a transistor with a polysilicon gate structure will be described.

[0193] Figure 10 This is a diagram illustrating an example of the structure of the semiconductor device 102 according to a variation 2 of Embodiment 1. More specifically, Figure 10 A cross-section of the semiconductor device 102 along the X direction is shown, which is consistent with the above. Figure 1 Corresponding to (a).

[0194] Furthermore, in the semiconductor device 102 of Modified Example 2, the same reference numerals are used for structures identical to those in Embodiment 1 described above, and their descriptions are omitted. Additionally, in the semiconductor device 102 of Modified Example 2, the direction along the X direction is sometimes referred to as the first direction, and the direction along the Y direction is sometimes referred to as the second direction.

[0195] like Figure 10 As shown, in the region separated by the element separation layer 111, a plurality of transistors TR2hv are disposed in a region having diffusion regions 114 disposed in a direction separated from each other in the X direction. The gate electrode 130a of the transistors TR2hv extends in the Y direction in the region between the diffusion regions 114 arranged in the X direction.

[0196] The gate electrode 130a has a polysilicon electrode 131 disposed on the gate insulating layer 121 and a self-aligned silicide layer 116 disposed on the polysilicon electrode 131. As described later, the self-aligned silicide layer 116 is a tungsten silicide layer, a nickel silicide layer, or a nickel-platinum silicide layer, etc., formed by self-aligning silicide of the upper surface of the polysilicon electrode 131.

[0197] A barrier layer 172 is provided on the side of the gate electrode 130a, separated by a spacer layer 122. The barrier layer 172 is not formed on the upper surface of the gate electrode 130a, for example. Therefore, the gate electrode 130a is directly covered by the inner liner layer 181 on its upper surface, and is covered by the inner liner layer 181 on its side, separated by the spacer layer 122 and the barrier layer 172.

[0198] In addition, the structure including the gate insulating layer 121, the gate electrode 130a, the spacer layer 122, and the barrier layers 172 and sidewalls 182 on both sides of the gate electrode 130a in the X direction is referred to as the stack 165 as the first structure.

[0199] Contact CGhv penetrates the interlayer insulating layer 190 and the inner liner layer 181 and connects to the self-aligned silicide layer 116 of the gate electrode 130a. Contact CShv penetrates the interlayer insulating layer 190 and the inner liner layer 181 and connects to the silicide layers 115 on both sides of the gate electrode 130a in the X direction.

[0200] In the region separated by the element separation layer 111, a plurality of transistors TR2vv are disposed in a region having diffusion regions 113 separated from each other in the X direction. The gate electrode 150a of the transistors TR2vv extends in the Y direction in the region between the diffusion regions 113 arranged in the X direction.

[0201] The gate electrode 150a has a polysilicon electrode 151 disposed on the gate insulating layer 121 and a self-aligned silicide layer 117 disposed on the polysilicon electrode 151. As described later, the self-aligned silicide layer 117 is a layer formed by self-aligning silicide treatment of the upper surface of the polysilicon electrode 151, and is made of the same type of material as the self-aligned silicide layer 116 described above.

[0202] The gate electrode 150a is directly covered by the inner liner 181 on its upper surface and is covered by the inner liner 181 on its side across the spacer layer 122.

[0203] Contact CGvv penetrates the interlayer insulating layer 190 and the inner liner layer 181 and connects to the self-aligned silicide layer 117 of the gate electrode 150a. Contact CSvv penetrates the interlayer insulating layer 190 and the inner liner layer 181 and connects to the silicide layers 115 on both sides of the gate electrode 150a in the X direction.

[0204] Except for the steps related to the formation of the gate electrodes 130a and 150a, the semiconductor device 102 of Modification 2 can also be manufactured by the same method as the semiconductor device manufacturing method of Embodiment 1 or Modification 1 described above. Hereinafter, an example of manufacturing the semiconductor device 102 of Modification 2 using the method of Modification 1 described above will be described.

[0205] Figure 11 and Figure 12 This diagram illustrates a portion of the manufacturing process of the semiconductor device 102 according to a variation of Embodiment 1, Example 2. More specifically, Figure 11 and Figure 12 A cross-section of the semiconductor device 102 in the manufacturing process is shown along the X direction.

[0206] like Figure 11 As shown in (a), a device separation layer 111 is formed on a substrate 110 such as a silicon substrate. In addition, a gate insulating layer 120 is formed integrally on the upper surface of the substrate 110.

[0207] Additionally, polysilicon electrodes 131, 151 and a cap layer 142 are formed on the gate insulating layer 120 within the region surrounded by the element separation layer 111. The polysilicon electrodes 131, 151 and the cap layer 142 are formed, for example, by forming a conductive polysilicon layer on the gate insulating layer 120, forming a silicon nitride layer on the polysilicon layer, and etching these layers into the shape of the polysilicon electrodes 131, 151.

[0208] Furthermore, impurities are injected through the gate insulating layer 120 in the region surrounded by the device separation layer 111, and the impurities are diffused to a predetermined depth in the substrate 110, including directly below the polysilicon electrodes 131 and 151, by means of annealing or the like. As a result, a diffusion region 112 is formed substantially throughout the region surrounded by the device separation layer 111.

[0209] like Figure 11 As shown in (b), an insulating layer covering the gate insulating layer 120, polysilicon electrodes 131, 151, and cap layer 142 is formed, and then etched back to form a spacer layer 122 on the sides of the polysilicon electrodes 131, 151, and cap layer 142. Additionally, a gate insulating layer 121 is formed that is separated according to each polysilicon electrode 131, 151.

[0210] Additionally, a mask layer MK1 is formed that covers the region where the polysilicon electrode 131 is formed within the region surrounded by the element separation layer 111, and opens the region where the polysilicon electrode 151 is formed.

[0211] Then, impurities are further implanted into the region where the polysilicon electrode 151 is formed. After the impurities are diffused to a predetermined depth on the substrate 110 by means of annealing or the like, the mask layer MK1 is removed. As a result, a diffusion region 113 is formed in the area of ​​the device separation layer 111, except directly below the polysilicon electrode 151.

[0212] like Figure 11 As shown in (c), for example, a barrier layer 170 is formed on the entire surface of the substrate 110, and the barrier layer 170 is removed from the region where the polysilicon electrode 151 is formed, forming a barrier layer 170 that covers the region where the polysilicon electrode 131 is formed.

[0213] like Figure 11 As shown in (d), a mask layer MK5 with an opening in the region where polysilicon electrodes 131 are formed in the region surrounded by the element separation layer 111 is etched away from the barrier layer 170 exposed from the opening of the mask layer MK5, and a barrier layer 172 with an opening 172op is formed in a predetermined region containing a plurality of polysilicon electrodes 131.

[0214] Furthermore, while the area where the polysilicon electrode 151 is formed is covered by the mask layer MK5, impurities are injected into the diffusion region 112 of the substrate 110 exposed from the opening 172op of the barrier layer 172, and the impurities are diffused to a predetermined depth in the substrate 110 by means of annealing or the like. At this time, the injection of impurities into the polysilicon electrode 131 is suppressed by the cap layer 142 on the upper surface of the polysilicon electrode 131.

[0215] Thus, a diffusion region 114 is formed that maintains a predetermined distance from the polysilicon electrode 131 and is self-aligned with the opening 172op of the barrier layer 172. Then, the mask layer MK5 is removed.

[0216] like Figure 12 As shown in (a), the cap layer 142 on the polysilicon electrodes 131 and 151 is etched away.

[0217] like Figure 12 As shown in (b), in the region where the polysilicon electrode 131 is formed, the surface of the diffusion region 114 of the substrate 110 exposed from the opening 172op of the barrier layer 172 is silicided, and a silicide layer 115 is formed in self-alignment with the diffusion region 114 and the opening 172op of the barrier layer 172.

[0218] Additionally, in the region where the polysilicon electrode 151 is formed, a silicide layer 115 is formed in the portion of the diffusion region 113 that is exposed from the gate insulating layer 121 beneath the polysilicon electrode 151 and the spacer layer 122.

[0219] At this time, the upper surfaces of the polysilicon electrodes 131 and 151 exposed by removing the cap layer 142 are also silicided, forming self-aligned silicide layers 116 and 117, respectively. Thus, a gate electrode 130a having a polysilicon electrode 131 and a self-aligned silicide layer 116 and a gate electrode 150a having a polysilicon electrode 151 and a self-aligned silicide layer 117 are formed.

[0220] The self-aligned silicide layers 116 and 117 formed as described above, for example, compared with the silicide layers formed by CVD or the like that which are the constituent materials of the metal electrodes 132 and 152 in Embodiment 1 described above, have unclear interfaces with the polycrystalline silicon layers that are the constituent materials of the polycrystalline silicon electrodes 131 and 151. In addition, due to the deterioration of the morphology, they tend to have high surface roughness.

[0221] However, since the self-aligned silicide layers 116 and 117 are self-aligned on the polysilicon electrodes 131 and 151, they are suitable for forming finer gate structures.

[0222] like Figure 12As shown in (c), for example, an inner liner layer 180 is formed to cover the entire surface of the substrate 110. Thus, a transistor TR2hv is formed with sidewalls 182 separated by a spacer layer 122 and a barrier layer 172 on both sides of the gate electrode 130a in the X direction. Additionally, a transistor TR2vv is formed with sidewalls 184 on both sides of the gate electrode 150a in the X direction.

[0223] Additionally, for example, an interlayer insulating layer 190 is formed to cover the entire surface of the substrate 110. Furthermore, a mask layer MK4 is formed with openings at predetermined positions on the gate electrodes 130a and 150a and on both sides of the gate electrodes 130a and 150a in the X direction.

[0224] Then, multiple holes are formed that penetrate the interlayer insulating layer 190 and the inner liner layer 180, and tungsten or the like is filled into the holes HL to form contact portions CShv, CGhv, CSvv, and CGvv.

[0225] The above describes the manufacture of semiconductor device 102 of modified example 2.

[0226] The semiconductor device 102 according to Modified Example 2 has the same effects as Embodiment 1 described above.

[0227] [Implementation Method 2]

[0228] Hereinafter, Embodiment 2 will be described in detail with reference to the accompanying drawings. The difference between the semiconductor device of Embodiment 2 and Embodiment 1 described above is that dummy electrodes are used for the alignment of high-concentration diffusion regions and the silicide layers on their diffusion regions.

[0229] (Structure of a semiconductor device)

[0230] Figure 13 This is a diagram illustrating an example of the structure of the semiconductor device 200 according to Embodiment 2. Figure 13 (a) is a cross-sectional view of the semiconductor device 200 along the X direction. Figure 13 (b) is a schematic top view showing the layout of the semiconductor device 200. Figure 13 In (b), the main components shown are the element separation layer 211, diffusion regions 212 and 214, silicide layer 215, gate electrode 230 and dummy electrode 250, and other structures are omitted.

[0231] Furthermore, in the semiconductor device 200 of Embodiment 2, the direction along the X direction is sometimes referred to as the first direction, and the direction along the Y direction is referred to as the second direction.

[0232] like Figure 1As shown, the semiconductor device 100 includes a substrate 210, a transistor TR, a dummy electrode 250, an interlayer insulating layer 290, and contacts CS and CG. The transistor TR includes a diffusion region 212, a gate insulating layer 221, a gate electrode 230, and an inner liner layer 281. The structure of the transistor TR may include a diffusion region 214 and a silicide layer 215.

[0233] The substrate 210 is, for example, a semiconductor substrate such as a silicon substrate. A component separation layer 211 is provided on the substrate 210 to electrically separate the formation region of the transistor TR. In the region of the substrate 210 where the transistor TR is formed and separated by the component separation layer 211, diffusion regions 212 and 214 and a silicide layer 215 are provided.

[0234] The diffusion region 212, which is the first region, is a region formed by diffusing impurities of a specified conductivity type, either P-type or N-type, at a specified concentration onto the substrate 210, and includes the upper surface of the substrate 210. The diffusion region 212 extends substantially throughout the region separated by the element separation layer 211, except for the region directly below the gate electrode 230 of the transistor TR. However, the diffusion region 212 may also slightly extend to the lower surface side of the gate electrode 230 at both ends in the X direction.

[0235] The diffusion region 214, serving as the second region, is formed within the diffusion region 212, encompassing the upper surface of the substrate 210. It is a region formed by the diffusion of impurities of the same conductivity type as the diffusion region 212 at a higher concentration on the substrate 210 compared to the diffusion region 212. For example, a pair of diffusion regions 214 are provided within the diffusion region 212. A predetermined distance is maintained between each diffusion region 214 and the component separation layer 211 in both the X and Y directions.

[0236] The silicide layer 215 is formed on the upper surface of the substrate 210, which includes the diffusion region 114. The silicide layer 215 is, for example, a tungsten silicide layer, a nickel silicide layer, or a nickel-platinum silicide layer.

[0237] Here, the center position of the silicide layer 215 along the X direction is substantially the same as the center positions of the diffusion regions 214 along the X direction. The relationship between the silicide layer 215 and the diffusion regions 214, as described above, also holds in the Y direction. That is, the center position of the silicide layer 215 along the Y direction is substantially the same as the center positions of the diffusion regions 214 along the Y direction.

[0238] Thus, the silicide layer 215 is contained within the diffusion region 214 without deviating from it, and is surrounded by the diffusion region 214 of a specified width.

[0239] In the region separated by the element separation layer 211, a gate electrode 230 extending in the Y direction is provided between diffusion regions 214 arranged in the X direction. The gate electrode 230 protrudes in the Y direction up to the element separation layer 211. As described above, except for the two ends of the gate electrode 230 in the X direction, there is no diffusion region 112 directly below the gate electrode 230.

[0240] The gate electrode 230 has a polysilicon gate structure, which for example has a polysilicon electrode 231 and a self-aligned silicide layer 216 disposed on the polysilicon electrode 231. That is, the polysilicon electrode 231 is, for example, a conductive polysilicon layer and functions as a polysilicon gate. The self-aligned silicide layer 216 is, for example, a layer formed by silicide treatment on the upper surface of the polysilicon electrode 231, and is made of the same type of material as the silicide layer 215 described above.

[0241] Here, the length of the gate electrode 230 along the Y-direction, which is the extension direction of the gate electrode 230, is the gate width W. Additionally, the length of the gate electrode 230 along the X-direction, which intersects the extension direction of the gate electrode 230, is the gate length L.

[0242] A gate insulating layer 221 is provided below the gate electrode 230. The gate insulating layer 221 is, for example, a silicon oxide layer, a hafnium oxide layer, or a zirconium oxide layer. The gate insulating layer 221 of the gate electrode 230 is shared, for example, by a dummy electrode 250 adjacent to the gate electrode 230 in the X direction.

[0243] A spacer layer 222 is provided on the side of the gate electrode 230. The spacer layer 222 is, for example, an insulating layer such as a silicon oxide layer. The spacer layer 222 of the gate electrode 230 is connected, for example, to the spacer layer 222 of the dummy electrode 250 adjacent to the gate electrode 230 in the X direction.

[0244] In the region separated by the element separation layer 211, in addition to the region where the diffusion region 114 is provided on both sides of the gate electrode 230 in the X direction, a plurality of dummy electrodes 250 extending in the Y direction are provided at positions separated from each other in the X direction.

[0245] The width of each dummy electrode 250 in the X-direction can be set to, for example, around tens of nm. In addition, the spacing between the multiple dummy electrodes 250 in the X-direction, except near the diffusion region 214, is preferably set to be greater than or equal to the width of each dummy electrode 250 in the X-direction, for example, about twice the width of the dummy electrode 250 in the X-direction.

[0246] The dummy electrode 250 is provided in the Y direction, protruding up to the element separation layer 211. At the position where it overlaps with the diffusion region 214 in the X direction, the dummy electrode 250 is provided on both sides of the diffusion region 214 in the Y direction.

[0247] The dummy electrode 250 is a virtual structure that has the same layer structure as the gate electrode 230 but does not have an effective function. That is, the dummy electrode 250 has, for example, a polysilicon layer 251 made of the same constituent material as the polysilicon electrode 231; and a self-aligned silicide layer 217 disposed on the polysilicon layer 251, made of the same constituent material as the self-aligned silicide layer 216.

[0248] On the side of the dummy electrode 250, a spacer layer 222 is provided, similar to that of the gate electrode 230. The spacer layer 222 on the side of the dummy electrode 250 is connected to the spacer layer 222 of the gate electrode 230 or other dummy electrodes 250 adjacent in the X direction.

[0249] Furthermore, these multiple dummy electrodes 250, as described above, share the gate electrode 230 and the gate insulating layer 221. That is, the gate insulating layer 221 covers approximately the entire surface of the region separated by the element separation layer 211, except for the diffusion region 214.

[0250] Here, the center position of the dummy electrodes 250 that are adjacent to each other in the X direction between the diffusion regions 214 is substantially the same as the center position of the diffusion regions 214 in the X direction. Therefore, the center position of these dummy electrodes 250 in the X direction is also substantially the same as the center position of the silicide layer 215 disposed in the diffusion regions 214 in the X direction.

[0251] Furthermore, the relationship between the aforementioned dummy electrode 250, the diffusion region 214, and the silicide layer 215 also holds true in the Y direction. That is, the center position of the dummy electrode 250 sandwiching the diffusion region 214 in the Y direction is substantially the same as the center position of the diffusion region 214 in the Y direction and the center position of the silicide layer 215 in the Y direction.

[0252] An inner liner layer 281, such as a silicon nitride layer, is provided on approximately the entire surface of the substrate 210. The inner liner layer 281 covers approximately the entire diffusion regions 212 and 214, excluding the connection portion of the contact portion CS, the gate insulating layer 221, the upper surface of the gate electrode 230, excluding the connection portion of the contact portion CG, the upper surface of the dummy electrode 250, and the spacer layer 222.

[0253] Furthermore, several of the dummy electrodes 250, on one side in the X direction, are also covered by the inner liner layer 281 through the spacer layer 222.

[0254] Here, the structure including the gate insulating layer 221, the dummy electrode 250, the spacer layer 222, and the inner liner layer 281 is sometimes referred to as a stack 261. In the following description, the stack 261, which includes dummy electrodes 250 arranged in the X direction, will be referred to as such. Figure 13 The layers from left to right on the paper of (a) are called laminates 261a to 261j.

[0255] That is, laminate 261a is the laminate 261 furthest to the left of the paper, and laminate 261j is the laminate 261 furthest to the right of the paper. In addition, diffusion regions 214 and silicide layers 215 are respectively provided between laminates 261b and 261c arranged along the X direction and between laminates 261h and 261i arranged along the X direction.

[0256] Therefore, the spacer layers 222 of the laminates 261b and 261c are not connected on opposite sides, and an inner liner layer 281 is provided on the opposite sides of the laminates 261b and 261c, separated by the spacer layers 222.

[0257] Thus, the stack 261b, which is the second structure, has a sidewall 283 as a second sidewall, which covers the sidewall of the gate insulating layer 221, the dummy electrode 250 and the spacer layer 222 in the X direction.

[0258] In addition, the stack 261c, which is the first structure, has a side wall 282 as a first side wall, which covers the side of the gate insulating layer 221, the dummy electrode 250 and the spacer layer 222 in the X direction.

[0259] Similarly, the spacer layers 222 of the laminates 261h and 261i are not connected on opposite sides, and an inner liner layer 281 is provided on the opposite sides of the laminates 261h and 261i, separated by the spacer layers 222.

[0260] Thus, the stack 261h, which is the first structure, has a sidewall 282 as a first sidewall, which covers the sidewall of the gate insulating layer 221, the dummy electrode 250 and the spacer layer 222 in the X direction.

[0261] In addition, the stack 261i, which is the second structure, has a side wall 283 as a second side wall, which covers the side of the gate insulating layer 221, the dummy electrode 250 and the spacer layer 222 in the X direction.

[0262] Furthermore, between layers 261b and 261c, on both sides of the Y-direction where the diffusion region 214 and the silicide layer 215 are not provided, other layers 261 are arranged opposite each other in the Y-direction. Additionally, between layers 261h and 261i, on both sides of the Y-direction where the diffusion region 214 and the silicide layer 215 are not provided, other layers 261 are arranged opposite each other in the Y-direction.

[0263] An interlayer insulating layer 290, such as a silicon oxide layer, is provided on the inner liner layer 281. The interlayer insulating layer 290 covers the diffusion regions 212 and 214, the gate insulating layer 221, the gate electrode 230, the dummy electrode 250, and the spacer layer 222 through the inner liner layer 281.

[0264] A contact portion CG, serving as a second contact portion, is connected to the upper surface of the gate electrode 230 of the transistor TR. This contact portion CG penetrates the interlayer insulating layer 290 and the inner liner layer 281, applying a gate voltage to the gate electrode 230.

[0265] A contact portion CS, serving as a first contact portion, is connected to the silicide layer 215 on the diffusion region 214 on both sides of the gate electrode 230 in the X direction. The contact portion CS penetrates the interlayer insulating layer 290 and the inner liner layer 281, and applies a high voltage to the source / drain of the transistor TR.

[0266] These contact portions CG and CS are similar to the contact portions CGhv and CShv of Embodiment 1 described above, and are, for example, mainly composed of metals such as tungsten.

[0267] As described above, a transistor TR, which is placed near a diffusion region 214 containing a high concentration of impurities and subjected to a high voltage, is configured, for example, as an HV-MOS transistor or a high-voltage MOS transistor.

[0268] Here, the contact portion CS passes between the sidewalls 282 and 283 of the dummy electrodes 250 arranged on both sides in the X direction, and connects to the silicide layer 215. At this time, the contact portion CS contacts at least one of the sidewalls 282 and 283 on both sides in the X direction via its side surface. Figure 13 In example (a), the contact part CS is in contact with both sidewalls 282 and 283.

[0269] As described above, the diffusion region 214, to which a high voltage is applied, and the silicide layer 215 are maintained at a predetermined distance from the device separation layer 211 in both the X and Y directions. Furthermore, the silicide layer 215 is surrounded by the diffusion region 214 of a predetermined width. This maintains the withstand voltage of the transistor TR.

[0270] (Semiconductor device manufacturing method)

[0271] Next, use Figures 14-17 The manufacturing method of the semiconductor device 200 according to Embodiment 2 will be described. Figures 14-16 This diagram illustrates a portion of the manufacturing method of the semiconductor device 200 according to Embodiment 2. More specifically, Figures 14-16 A cross-section of a semiconductor device 200 in the manufacturing process is shown along the X direction.

[0272] like Figure 14 As shown in (a), an element separation layer 211 is formed on a substrate 210 such as a silicon substrate. In addition, a gate insulating layer 220 is formed integrally on the upper surface of the substrate 210.

[0273] Additionally, a polysilicon electrode 231 and a polysilicon layer 251 are formed on the gate insulating layer 220 within the region surrounded by the element separation layer 211. The polysilicon electrode 231 and the polysilicon layer 251 are formed, for example, by forming a conductive polysilicon layer on the gate insulating layer 220 using a CVD method, and by etching the polysilicon layer into the shape of the gate electrode 230 and the dummy electrode 250.

[0274] At this time, the polysilicon layer 251 is not disposed in the region where the diffusion region 214 is formed. As a result, the gate insulating layer 221 is provided in a predetermined region on both sides of the polysilicon electrode 231 in the X direction, which is exposed much more than in other regions.

[0275] Furthermore, as described above, the width of each polysilicon layer 251 in the X-direction can be set to, for example, around tens of nm. Additionally, the spacing between these polysilicon layers 251 in the X-direction, except for the areas near which are exposed more significantly than described above, can be set to, for example, around twice the width of the polysilicon layer 251 in the X-direction.

[0276] like Figure 14 As shown in (b), in the region surrounded by the element separation layer 211 and in the region on both sides of the polysilicon electrode 231 in the X direction where multiple polysilicon layers 251 are formed, impurities are injected through the gate insulating layer 220, and the impurities are diffused to a predetermined depth of the substrate 210 by annealing or the like, thus forming a diffusion region 212.

[0277] At this time, the impurities are injected with a target area that is deviated from the polysilicon electrode 231, thus suppressing not only the injection of impurities into the polysilicon electrode 231, but also the diffusion of impurities directly below the polysilicon electrode 231. However, near the end of the polysilicon electrode 231, impurities may also be slightly introduced into the lower surface of the polysilicon electrode 231.

[0278] Furthermore, while the polysilicon layer 251 hinders the implantation of impurities directly beneath it, the width of the polysilicon layer 251 along the X-direction is sufficiently narrow, allowing impurities to diffuse towards the lower surface of the polysilicon layer 251. In other words, the width of the polysilicon layer 251 along the X-direction is adjusted to a degree that allows the implanted impurities to sufficiently penetrate directly beneath the polysilicon layer 251.

[0279] Furthermore, although impurities are directly injected into the polysilicon layer 251, the polysilicon layer 251 is part of the dummy electrode 250 and does not have an effective function in the semiconductor device 200, so it does not affect the electrical characteristics, etc.

[0280] like Figure 14 As shown in (c), spacer layers 222 are formed on the sides of the polysilicon electrode 231 and the polysilicon layer 251. At this time, the spacer layers 222 of the polysilicon layers 251 adjacent to the polysilicon electrode 231 in the X direction are connected to each other. Furthermore, except for the polysilicon layers 251 near the areas that are more significantly exposed than others, the spacer layers 222 between other polysilicon layers 251 are connected to each other.

[0281] In other words, the spacing of the multiple polysilicon layers 251 is adjusted in such a way that they are connected to each other by the spacer layers 222.

[0282] In addition, the portion of the gate insulating layer 220 not covered by the polysilicon electrode 231, the polysilicon layer 251 and the spacer layer 222 is etched away, and the gate insulating layer 221 is formed at the position where it overlaps with the polysilicon electrode 231, the polysilicon layer 251 and the spacer layer 222.

[0283] Thus, among the multiple polysilicon layers 251, a structure is formed in which spacer layers 222 and gate insulating layers 221 are connected to each other. In addition, in the area described above where the spacer layers 222 and gate insulating layers 221 are not connected and are exposed in a larger area than others, an opening 251op is formed on the surface of the substrate 210.

[0284] like Figure 14 As shown in (d), impurities are further injected into both sides of the polysilicon electrode 231 in the X direction within the region surrounded by the element separation layer 211.

[0285] On both sides of the polysilicon electrode 231 in the X direction, a plurality of polysilicon layers 251, except near the opening 251op mentioned above, are connected by spacer layers 222 that are opposite each other in the X direction, and a gate insulating layer 221 is continuously disposed on the lower layer of these polysilicon layers 251.

[0286] Therefore, impurities are mainly injected into the openings 251op on both sides of the polysilicon electrode 231 in the X direction that are not covered by the polysilicon layer 251, the spacer layer 222 and the gate insulating layer 221.

[0287] At this time, impurities are implanted targeting the region separated from the polysilicon electrode 231 in the X direction, thus suppressing impurity implantation into the polysilicon electrode 231. Furthermore, the implantation targets an extremely limited region between the plurality of polysilicon layers 251 arranged in the X direction, thus suppressing impurity implantation directly below the polysilicon layer 251. Impurities are implanted into the polysilicon layer 251 itself, but as mentioned above, the polysilicon layer 251 is part of the dummy electrode 250, so there is no problem.

[0288] After impurity implantation, the impurities are diffused to a predetermined depth in the substrate 210 through annealing or other processes. At this time, impurities can be slightly incorporated into the lower surface of the polysilicon layer 251 adjacent to the opening 251op. This forms a diffusion region 214 with a high concentration of impurities.

[0289] As described above, the diffusion region 214 is self-aligned relative to the opening 251op, using the surrounding polysilicon layer 251, the underlying gate insulating layer 221, and the spacer layer 222 on the sides of the polysilicon layer 251 as a mask. The penetration distance of the impurities from the opening 251op toward the lower surface of the polysilicon layer 251 is approximately equal on both sides in the X direction and on both sides in the Y direction.

[0290] Therefore, as described above, the center position between the polysilicon layers 251 on both sides of the opening 251op in the X direction and on both sides of the opening in the Y direction is substantially the same as the center position of the diffusion region 214 in the X direction and in the Y direction.

[0291] like Figure 14 As shown in (a), the surface of the diffusion region 214 exposed from the opening 251op is siliconized, and a silicide layer 215 is formed in a self-aligned manner relative to the diffusion region 214 and the opening 251op.

[0292] As described above, the silicide layer 215 is also formed as a mask for the polysilicon layer 251 surrounding the diffusion region 214 of the impurity implantation mask, the gate insulating layer 221 below it, and the spacer layer 222 on the side of the polysilicon layer 251.

[0293] Therefore, as described above, the center positions of the polysilicon layers 251 on both sides of the opening 251op in the X and Y directions are substantially the same as the center positions of the silicide layer 215 in the X and Y directions. Furthermore, the center positions of the silicide layer 215 in the X and Y directions are also substantially the same as the center positions of the diffusion region 214 in the X and Y directions.

[0294] Furthermore, in the above-described manner, the upper surfaces of the polysilicon electrode 231 and the polysilicon layer 251 are also silicided, forming self-aligned silicide layers 216 and 217 respectively. This results in the formation of a gate electrode 230 comprising the polysilicon electrode 231 and the self-aligned silicide layer 216, and a dummy electrode 250 comprising the polysilicon layer 251 and the self-aligned silicide layer 217.

[0295] As described above, through the above processing, both the gate electrode 230 and the dummy electrode 250 have the same layer structure.

[0296] like Figure 15 As shown in (b), for example, an inner liner layer 280 is formed that covers the entire surface of the substrate 210.

[0297] Thus, the gate insulating layer 221, the gate electrode 230, and the spacer layer 222 are covered by the inner liner layer 280 to form the transistor TR.

[0298] Furthermore, the gate insulating layer 221, the dummy electrode 250, and the spacer layer 222 are covered by the inner liner layer 280 to form a stack 261a to 261j. At this time, sidewalls 282 are formed on the side of the diffusion region 214 of the stacks 261c and 261h adjacent to the diffusion regions 214 on both sides of the polysilicon electrode 231, and sidewalls 283 are formed on the side of the diffusion region 214 of the stacks 261b and 261i.

[0299] like Figure 15 As shown in (c), for example, an interlayer insulating layer 290 is formed to cover the entire surface of the substrate 210. In addition, a mask layer MK6 with openings at predetermined positions on the gate electrode 230 and on both sides of the gate electrode 230 in the X direction is formed.

[0300] like Figure 16 As shown in (a), the interlayer insulating layer 290 exposed from the mask layer MK6 is etched through, further penetrating the underlying liner layer 280, forming multiple holes HL2 that reach the silicide layer 215 on the upper surface of the gate electrode 230 or the diffusion region 214. Thus, an inner liner layer 281 is formed through the multiple holes HL2.

[0301] At this time, the hole HL between the dummy electrodes 250 arranged in the X direction sandwiching the diffusion region 214 contacts at least one of the sidewalls 282 and 283 formed by the sidewalls of the stacks 261b, 261c or 261h, 261i arranged on both sides in the X direction, and reaches the silicide layer 215 through the space between these sidewalls 282 and 283.

[0302] Then, remove the mask layer MK6.

[0303] like Figure 16As shown in (b), tungsten or the like is filled into each hole HL2. This forms a contact CG that connects to the gate electrode 230. Additionally, a contact CS is formed that connects to the silicide layers 215 formed on both sides of the diffusion regions 214 in the X direction of the gate electrode 230.

[0304] The above describes the manufacture of the semiconductor device 200 according to Embodiment 2.

[0305] Furthermore, positional misalignment of the contact portion CS may also occur in the semiconductor device 200 of Embodiment 2. However, similar to the case of the semiconductor device 100 of Embodiment 1 described above, the contact portion CS of the semiconductor device 200 is also self-aligned with the silicide layer 215. An example of this is... Figure 17 As shown.

[0306] Figure 17 This diagram illustrates an example of a situation where the contact portion CS of the semiconductor device 200 according to Embodiment 2 has undergone a positional shift. More specifically, Figure 17 A cross-section along the X direction of a semiconductor device 200 having a contact portion CS that has experienced a positional shift is shown, as described above. Figure 13 Corresponding to (a).

[0307] like Figure 17 As shown, the contacts CS and CG connected to the transistor TR are formed, for example, due to the overlap deviation during the formation of the mask MK6, offset to the left of the paper, i.e. to the X direction, from the standard position designed above.

[0308] Therefore, the contact portion CG is connected to the gate electrode 230 at a position offset to the left of the paper from the center position of the gate electrode 230 in the X direction from the paper. Additionally, the contact portion CS is formed at a position offset to the left of the paper from the center position of the diffusion region 214 and the silicide layer 215 in the X direction. Consequently, a portion of the lower end of the contact portion CS is formed at a position offset from the diffusion region 214 and the silicide layer 215.

[0309] However, the portion that deviates from the diffusion region 214 of the contact portion CS and the silicide layer 215 contacts the sidewall 283 of the laminate 261b or the sidewall 282 of the laminate 261h on the X-direction side, thereby not reaching the upper surface of the substrate 210 for termination.

[0310] As described above, when a portion of the contact portion CS is formed at a position offset from the diffusion region 214 and the silicide layer 215, the lower end of the contact portion CS is also self-aligned with the diffusion region 214 and the silicide layer 215.

[0311] (Summary)

[0312] As mentioned above, in the miniaturization development of semiconductor devices containing transistors, in order to maintain the high voltage withstand capability of HV transistors, it has become difficult to align them in a manner that maintains a specified distance between the high-concentration diffusion region and the element separation layer and the gate electrode, and that the silicide layer is surrounded by a high-concentration diffusion region of a specified width.

[0313] For example, when aligning a silicide layer with a high-concentration diffusion region, a silicide barrier layer, such as a silicon oxide layer or a silicon oxynitride layer, with an opening in a portion of the high-concentration diffusion region is sometimes used to ensure that the silicide layer is reliably formed within the high-concentration diffusion region.

[0314] However, sometimes it is necessary to increase the size of the high-concentration diffusion region so that the opening of the silicide barrier layer is reliably located on the high-concentration diffusion region.

[0315] Specifically, the width of the silicide layer is preferably about twice the diameter of the contact portion connected to the silicide layer. Furthermore, considering the alignment accuracy of the opening in the silicide barrier layer, in high-concentration diffusion regions, a margin of the same width as the silicide layer is sometimes required on both sides from the position overlapping with the silicide layer. Therefore, this can sometimes hinder the miniaturization of semiconductor devices.

[0316] According to the semiconductor device 200 of Embodiment 2, on both sides of the diffusion region 214 in the X direction, there are: laminates 261b and 261c, which respectively include a dummy electrode 250 and sidewalls 283 and 282 disposed on the diffusion region 214 side of the dummy electrode 250; and laminates 261h and 261i, which respectively include the dummy electrode 250 and sidewalls 282 and 283 disposed on the diffusion region 214 side of the dummy electrode 250.

[0317] When forming the diffusion region 214, these dummy electrodes 250 are primarily used as masks for impurity implantation, and the diffusion region 214 is formed in a self-aligned manner. Additionally, the same dummy electrodes 250 are used as masks when forming the silicide layer 215.

[0318] Therefore, by unifying the alignment of the diffusion region 214 with respect to the element separation layer 211, etc., and the alignment of the silicide layer 215 with respect to the diffusion region 214, their alignment accuracy can be improved. In addition, since the alignment allowance of the opening of the silicide barrier layer is not required, in principle, the width of the diffusion region 214 in the X direction can be reduced to about 1 / 3.

[0319] According to the semiconductor device 200 of Embodiment 2, the dummy electrode 250 has the same layer structure as the gate electrode 230. By using the dummy electrode 250 as a mask to form the diffusion region 214 and the silicide layer 215, the alignment accuracy of the diffusion region 214 and the silicide layer 215 can be improved without additional processes.

[0320] The semiconductor device 200 according to Embodiment 2 has a contact portion CS that is electrically connected to the diffusion region 214 through the sidewall 283 of the laminate 261b and the sidewall 282 of the laminate 261c. Additionally, it has another contact portion CS that is electrically connected to the diffusion region 214 through the sidewall 282 of the laminate 261h and the sidewall 283 of the laminate 261i. Thus, the contact portion CS is self-aligned relative to the diffusion region 214 and the silicide layer 215.

[0321] (Variation Example 1)

[0322] In Embodiment 2 described above, for example, the transistor TR is configured to have a polysilicon gate structure, which has a polysilicon electrode 231. However, the structure of Embodiment 2 described above can also be applied to a transistor having a polysilicon metal gate structure, for example. Hereinafter, using... Figure 18 An application example of the above structure in a transistor having a polysilicon metal gate structure will be described.

[0323] Figure 18 This is a diagram illustrating an example of the structure of the semiconductor device 201 according to a variation of Embodiment 2, Example 1. More specifically, Figure 18 A cross-section of the semiconductor device 201 along the X direction is shown, which is consistent with the above. Figure 13 Corresponding to (a).

[0324] Furthermore, in the semiconductor device 201 of Modified Example 1, the same reference numerals are used for structures identical to those in Embodiment 2 described above, and their descriptions are omitted. Additionally, in the semiconductor device 201 of Modified Example 1, the direction along the X direction is sometimes referred to as the first direction, and the direction along the Y direction is sometimes referred to as the second direction.

[0325] like Figure 18 As shown, a transistor TR1 is disposed in the region separated by the element separation layer 211. The gate electrode 230a of the transistor TR1 extends in the Y direction, and diffusion regions 214 are disposed on both sides of the gate electrode 230a in the X direction.

[0326] The gate electrode 230a has a polysilicon electrode 231 disposed on the gate insulating layer 221 and a metal electrode 232 disposed on the polysilicon electrode 231. The metal electrode 232 is formed by a tungsten silicide layer or the like using a CVD method. The metal electrode 232 has, for example, a better morphology than the self-aligned silicide layer 216 described above, a flat film, and a boundary with the polysilicon electrode 231 that is easily distinguishable.

[0327] On both sides of the gate electrode 230a in the X direction, there are a plurality of dummy electrodes 250a that are separated from each other in the X direction and extend in the Y direction. Like the gate electrode 230a, the dummy electrodes 250a have a layer structure of polysilicon layer 251 and metal layer 252 on polysilicon layer 251, and are dummy structures that do not have effective functions.

[0328] The gate electrode 230a and the dummy electrode 250a share a gate insulating layer 221 that extends continuously beneath them. In addition, a cap layer 241, such as a silicon nitride layer, is provided on the upper surface of each of the gate electrode 230a and the dummy electrode 250a.

[0329] Spacer layers 222 are formed on the sides of the gate electrode 230a and the dummy electrode 250a. These spacer layers 222 are connected to the spacer layers 222 of the gate electrode 230a or the dummy electrode 250a adjacent in the X direction.

[0330] In addition, the gate electrode 230a and the dummy electrode 250a are covered by the inner liner layer 281 on their upper surfaces through the cap layer 241, and are covered by the inner liner layer 281 on their sides through the spacer layer 222.

[0331] Thus, stacks 263a to 263j, including gate insulating layer 221, dummy electrode 250a, spacer layer 222 and inner liner layer 281, are disposed on substrate 210.

[0332] Among these laminates 263a to 263j, the laminates 263c and 263h, which are first structures and are located on the X-direction side of the diffusion region 214, have side walls 282, which serve as first side walls, provided by the inner lining layer 281 covering them. Furthermore, on the side of the laminates 263b and 263i, which are second structures and are located on the X-direction side of the diffusion region 214, side walls 283, which serve as second side walls, are provided by the inner lining layer 281 covering them.

[0333] Contact CG penetrates the interlayer insulating layer 290, the inner liner layer 281, and the cap layer 241 to connect with the metal electrode 232 of the gate electrode 230a. Contact CS penetrates the interlayer insulating layer 290 and the inner liner layer 281 to connect with the silicide layers 215 on both sides of the gate electrode 230a in the X direction.

[0334] Except for the process related to the formation of the gate electrode 230a, the semiconductor device 201 of Modified Example 1 can be manufactured by the same method as the semiconductor device 200 of Embodiment 2 described above.

[0335] That is, in the manufacturing process of semiconductor device 201, in the above-mentioned Figure 14 Based on the polycrystalline silicon electrode 231 shown in (a), a metal electrode 232 is formed on the polycrystalline silicon electrode 231, and a cap layer 241 is formed on the metal electrode 232.

[0336] At this time, similarly, a metal layer 252 is formed on the polysilicon layer 251, and a cap layer 241 is formed on the metal layer 252.

[0337] Furthermore, by performing the subsequent processes in the same manner as in Embodiment 2 described above, the semiconductor device 201 of Modified Example 1 is manufactured.

[0338] The semiconductor device 201 according to Modified Example 1 has the same effects as the semiconductor device 200 of Embodiment 2 described above.

[0339] (Variation Example 2)

[0340] In Embodiment 2 described above, the dummy electrode 250, for example, is configured to extend in the Y direction, similar to the gate electrode 230 of the transistor TR. However, the extending direction of the dummy electrode may differ from that of the gate electrode 230. Hereinafter, using... Figure 19 An example of a semiconductor device 202 having a dummy electrode 250b extending in a direction different from that of the gate electrode 230 will be described.

[0341] Figure 19 This is a diagram illustrating an example of the structure of the semiconductor device 202 involved in a variation 2 of Embodiment 2.

[0342] Figure 19 (a) is a cross-sectional view of the semiconductor device 202 along the X direction, which is consistent with the description of Embodiment 2 above. Figure 13 Corresponding to (a). Figure 19 (b) is a schematic top view showing the layout of the semiconductor device 202, which is consistent with the above-described embodiment 2. Figure 13 Corresponding to (b). In Figure 19In (b), the main components shown are the element separation layer 211, diffusion regions 212 and 214, silicide layer 215, gate electrode 230 and dummy electrode 250b, and other structures are omitted.

[0343] Furthermore, in the semiconductor device 202 of Modified Example 2, the same reference numerals are used for structures identical to those in Embodiment 2 described above, and their descriptions are omitted. Also, in the semiconductor device 202 of Modified Example 2, the direction along the X direction is sometimes referred to as the second direction, and the direction along the Y direction is sometimes referred to as the first direction.

[0344] like Figure 19 As shown, a transistor TR is disposed in the region separated by the element separation layer 211. The transistor TR has the same structure as in Embodiment 1 described above, except that it has a gate electrode 230 extending in the Y direction.

[0345] On both sides of the gate electrode 230 in the X direction, there are a plurality of dummy electrodes 250b that are separated from each other in the Y direction and extend in the X direction. Like the gate electrode 230, the dummy electrodes 250b have a layer structure of polysilicon layer 251 and self-aligned silicide layer 217 on polysilicon layer 251, and are dummy structures without effective function.

[0346] The gate electrode 230 and the dummy electrode 250b share a gate insulating layer 221 that extends continuously beneath them.

[0347] Spacer layers 222 are formed on the sides of the gate electrode 230 and the dummy electrode 250b. These spacer layers 222 are connected to the spacer layers 222 of the gate electrode 230 adjacent in the X direction or the dummy electrode 250b adjacent in the Y direction.

[0348] In addition, the gate electrode 230 and the dummy electrode 250b are directly covered by the inner liner layer 281 on their upper surfaces, and are covered by the inner liner layer 281 on their sides through the spacer layer 222.

[0349] Thus, a stack 265 comprising a gate insulating layer 221, a dummy electrode 250b, a spacer layer 222, and an inner liner layer 281 is disposed on a substrate 210.

[0350] Among these laminates 265, the sides of the laminates 265l and 265m disposed on the X-direction side of the diffusion region 214 are provided with sidewalls 284 by means of an inner liner 281 covering them. Additionally, the sides of the laminates 265k and 265n disposed on the other side of the diffusion region 214 are provided with sidewalls 285 by means of an inner liner 281 covering them.

[0351] Similarly, on the side of the laminate 265, which is the first structure located on the Y-direction side of the diffusion region 214, a side wall serving as a first side wall is provided by the inner lining layer 281 covering it. Furthermore, on the side of the laminate 265, which is the second structure located on the other side of the diffusion region 214, a side wall serving as a second side wall is provided by the inner lining layer 281 covering it.

[0352] Contact portion CG penetrates the interlayer insulating layer 290 and the inner liner layer 281 and connects to the self-aligned silicide layer 216 of the gate electrode 230. Contact portion CS penetrates the interlayer insulating layer 290 and the inner liner layer 281 and connects to the silicide layers 215 on both sides of the gate electrode 230 in the X direction. At this time, contact portion CS contacts at least one sidewall of the stack 261 disposed on both sides of the diffusion region 214 in the Y direction, and connects to the silicide layer 215 on the diffusion region 214 through the space between their sidewalls.

[0353] According to the semiconductor device 202 of Modification 2, the dummy electrodes 250b, which are separated from each other in the Y direction, extend in the X direction. As described above, the extension direction of the dummy electrodes 250b can also be different from the extension direction of the gate electrode 230, thereby increasing the degree of freedom in the layout of the semiconductor device 202 and reducing the design load.

[0354] The semiconductor device 202 according to Modified Example 2, except for the above, has the same effects as the semiconductor device 200 of Embodiment 2.

[0355] Furthermore, as described above, the dummy electrode can extend in any direction other than along the X direction or along the Y direction, such as in a direction oblique to the gate electrode 230.

[0356] [Application Examples of Semiconductor Devices]

[0357] The structures of Embodiments 1, 2, and their variations described above can be applied, for example, to transistors that are disposed around memory cells in a semiconductor memory device and form drive circuits that operate the memory cells. Hereinafter, an example of a semiconductor memory device having a transistor employing any of the structures of Embodiments 1, 2, and their variations described above will be described using the accompanying drawings.

[0358] (Simplified structure of a semiconductor memory device)

[0359] Figure 20 This is a block diagram of a semiconductor memory device 1 according to other embodiments. For example... Figure 20As shown, the semiconductor memory device 1 includes an input / output circuit 310, a logic control circuit 320, a status register 330, an address register 340, an instruction register 350, a sequencer 360, a ready / busy circuit 370, a voltage generation circuit 380, a memory cell array 10, a row decoder 20, a sense amplifier module 30, a data register 40, and a column decoder 50.

[0360] The input / output circuit 310 controls the input and output of the signal DQ to an external device, such as a memory controller (not shown) that controls the semiconductor storage device 1. The input / output circuit 310 includes input circuitry and output circuitry (not shown).

[0361] The input circuit sends the write data WD and other data DAT received from the external device to the data register 40, the address ADD to the address register 340, and the instruction CMD to the instruction register 350.

[0362] The output circuit sends the status information STS received from the status register 330, the read data RD received from the data register 40, and the address ADD received from the address register 340 to the external device.

[0363] The logic control circuit 320 receives signals from external devices, such as chip enable signal CEn, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, and read enable signal REn. Furthermore, the logic control circuit 320 controls the input / output circuit 310 and the sequencer 360 in accordance with the received signals.

[0364] Status register 330 temporarily holds the status information STS for data write, read, and delete operations, and notifies external devices whether the operation has ended normally.

[0365] Address register 340 temporarily holds the address ADD received from the external device via input / output circuit 310. Additionally, address register 340 forwards the row address RA to row decoder 20 and the column address CA to column decoder 50.

[0366] The instruction register 350 temporarily stores the instruction CMD received from the external device via the input / output circuit 310 and transfers it to the sequencer 360.

[0367] The sequencer 360 controls the overall operation of the semiconductor memory device 1. More specifically, the sequencer 360 controls, for example, the status register 330, the ready / busy circuit 370, the voltage generation circuit 380, the row decoder 20, the sense amplifier module 30, the data register 40, and the column decoder 50, in accordance with the instruction CMD held in the instruction register 350, to perform write operations, read operations, and delete operations.

[0368] The ready / busy circuit 370 sends a ready / busy signal R / Bn to an external device in accordance with the operating status of the sequencer 360.

[0369] The voltage generating circuit 380, in accordance with the control of the sequencer 360, generates the voltages required for write, read, and delete operations, and supplies these voltages to, for example, the memory cell array 10, the row decoder 20, and the sense amplifier module 30. The row decoder 20 and the sense amplifier module 30 apply the voltage supplied from the voltage generating circuit 380 to the memory cells within the memory cell array 10.

[0370] The memory cell array 10 contains multiple blocks BLK (BLK0 to BLKn). n is an integer of 2 or higher. A block BLK is a collection of multiple memory cells associated with bit lines and word lines, serving as a data deletion unit, for example. Memory cells are configured, for example, as transistors, to retain non-volatile data.

[0371] By having the memory cells described above, the semiconductor memory device 1 is configured, for example, as a NAND-type non-volatile memory. However, the semiconductor memory device 1 may also be configured as other non-volatile memories, such as NOR-type memories.

[0372] The row decoder 20 decodes the row address RA. Furthermore, based on the decoding result, the row decoder 20 selects any block BLK. Additionally, the row decoder 20 applies the required voltage to the block BLK.

[0373] During a read operation, the sensing amplifier module 30 senses the data read from the memory cell array 10. Additionally, the sensing amplifier module 30 sends the read data RD to the data register 40. During a write operation, the sensing amplifier module 30 sends the write data WD to the memory cell array 10.

[0374] Data register 40 has multiple latching circuits. These latching circuits hold the write data WD and the read data RRD. For example, during a write operation, data register 40 temporarily holds the write data WD received from input / output circuit 310 and sends it to sense amplifier module 30. Similarly, during a read operation, data register 40 temporarily holds the read data RD received from sense amplifier module 30 and sends it to input / output circuit 310.

[0375] The column decoder 50 decodes the column address CA during write, read, and delete operations, and selects the latch circuit in the data register 40 accordingly based on the decoding result.

[0376] Furthermore, the aforementioned structures of the semiconductor memory device 1 other than the memory cell array 10 are also referred to as peripheral circuits. Peripheral circuits are circuit groups arranged around the memory cell array 10, including input / output circuits 310, logic control circuits 320, status registers 330, address registers 340, instruction registers 350, sequencers 360, ready / busy circuits 370, voltage generation circuits 380, row decoders 20, sense amplifier modules 30, data registers 40, and column decoders 50.

[0377] As described above, the semiconductor memory device 1 includes: a memory cell array 10 containing a plurality of memory cells; and peripheral circuitry for activating the plurality of memory cells.

[0378] (Circuit structure of memory cell array and line decoder)

[0379] Figure 21 This is an equivalent circuit diagram illustrating an example of the structure of the memory cell array 10 and the row decoder 20 included in the semiconductor memory device 1 according to other embodiments. First, an example of the circuit structure of the memory cell array 10 included in the semiconductor memory device 1 will be described below.

[0380] The memory cell array 10, as described above, has multiple blocks BLK. Each block BLK has multiple string cells SU. Each string cell SU has multiple memory strings MS. One end of each memory string MS is connected to peripheral circuits such as the row decoder 20 and the sense amplifier module 30 via bit lines BL. The other end of each memory string MS is connected to peripheral circuits via a common source line SL.

[0381] The memory string (MS) has a drain-select transistor (STD) connected in series between the bit line (BL) and the source line (SL), multiple memory cells (MC), and a source-select transistor (STS). Hereinafter, the drain-select transistor (STD) and the source-select transistor (STS) are sometimes simply referred to as selection transistors (STD, STS).

[0382] Memory cells MC are, for example, field-effect transistors (FETs) with a charge accumulation layer in the gate insulating layer. The threshold voltage of the memory cell MC varies accordingly with the amount of charge in the charge accumulation layer. By setting one or more threshold voltages, the memory cell MC can store one or more bits of data. The gate electrodes of multiple memory cells MC corresponding to a memory string MS are connected to word lines WL. These word lines WL are shared by all memory strings MS in a block BLK.

[0383] The selection transistors (STD, STS) are, for example, field-effect transistors. The gate electrodes of the selection transistors (STD, STS) are connected to selection gate lines (SGD, SGS). The drain selection line SGD, connected to the drain selection transistor STD, is configured corresponding to the string unit SU and is shared with all memory strings MS in one string unit SU. The source selection line SGS, connected to the source selection transistor STS, is shared with all memory strings MS in one block BLK.

[0384] Next, the circuit structure of the line decoder 20 of the semiconductor memory device 1 will be described.

[0385] The line decoder 20 includes an address decoder 21, a block selection circuit 22, and a voltage selection circuit 23. In these circuits, the line decoder 20 includes, for example, transistors TR with any structure applying the described embodiments 1, 2, and their variations. 22 TR 23 wait.

[0386] Address decoder 21 has multiple block select lines BLKSEL and multiple voltage select lines VOLSEL.

[0387] Address decoder 21, for example, according to control signals from sequencer 360, refers to address register 340 (see above) included in the peripheral circuitry. Figure 20 Address data.

[0388] In addition, the address decoder 21 decodes the referenced address data, causing the transistor TR corresponding to the address data to... 22 and transistor TR 23 Turn on, causing the other transistor TR to conduct. 22and transistor TR 23 Cut-off. Furthermore, transistor TR 22 and transistor TR 23 These are the transistors contained in the block selection circuit 22 and the voltage selection circuit 23, which will be described later.

[0389] Additionally, the address decoder 21 sets the voltages of the block select line BLKSEL and the voltage select line VOLSEL corresponding to the address data to, for example, "H," and sets all other voltages to "L." Furthermore, by using either N-channel or P-channel transistors in the block select circuit 22 and the voltage select circuit 23, the voltages applied to these lines are reversed. The voltages described above are an example of the case where the transistor is an N-channel type.

[0390] exist Figure 21 In the example, in address decoder 21, one block select line BLKSEL is provided for each block BLK within memory cell array 10. However, this structure can be modified appropriately. For example, one block select line BLKSEL can be provided for each of two or more blocks BLK.

[0391] The block selection circuit 22 has multiple block selection sections 22a to 22c corresponding to blocks BLK of the memory cell array 10. Each of these multiple block selection sections 22a to 22c has multiple transistors TR corresponding to the word line WL and the select gate line (SGD, SGS). 22 .

[0392] transistor TR 22 This is a high-voltage N-channel MOS transistor, functioning as a block drive transistor. Transistor TR 22 The drain electrode is electrically connected to the corresponding word line WL or select gate line (SGD, SGS). Transistor TR 22 The source electrodes are electrically connected to the voltage output terminal OTM via wiring WR and voltage selection circuit 23. Transistor TR 22 The gate electrode is connected to the ground along with the corresponding block select line BLKSEL.

[0393] Additionally, the block select circuit 22 also includes multiple transistors (not shown). These transistors are high-voltage CMOS transistors connected between the select gate lines (SGD, SGS) and the ground voltage supply terminal. These transistors enable the select gate lines (SGD, SGS) of the non-selected block BLK within the memory cell array 10 to be connected to the ground voltage supply terminal. Furthermore, the multiple word lines WL of the non-selected block BLK are in a floating state.

[0394] The voltage selection circuit 23 has multiple voltage selection sections 23a to 23i corresponding to the word line WL and the select gate lines (SGD, SGS). Each of these multiple voltage selection sections 23a to 23i has multiple transistors TR. 23 .

[0395] transistor TR 23 This is a high-voltage N-channel MOS transistor, functioning as a voltage-selective transistor. (Transistor TR) 23 The drain terminals are electrically connected to the corresponding word line WL or select gate line (SGD, SGS) via wiring WR and block select circuit 22. The source terminals are electrically connected to the corresponding voltage output terminal OTM. The gate electrode is connected to the corresponding voltage select line VOLSEL.

[0396] As described above, the line decoder 20, which belongs to the peripheral circuitry, has multiple transistors TR. 22 TR23, etc. However, Figure 21 The circuit structure of the line decoder 20 shown is an example, and the line decoder 20 includes transistors TR. 22 TR 23 The number and types of these vary and may differ.

[0397] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as set forth in the claims and its equivalents.

[0398] Explanation of reference numerals in the attached figures

[0399] 100, 101, 102, 200, 201, 202… Semiconductor devices; 110, 210… Substrates; 112, 113, 114, 212, 214… Diffusion regions; 115, 215… Silicate layers; 116, 117, 216, 217… Self-aligned silicide layers; 130, 130a, 150, 150a, 230, 230a… Gate electrodes; 131, 151, 231… Polysilicon electrodes; 132, 152, 2… 32…metal electrode, 161~165, 261, 263, 265…laminated body, 171, 172…barrier layer, 181, 281…liner layer, 182~184, 282~285…sidewall, 250, 250a, 250b…dummy electrode, CG, CGhv, CGvv, CS, CSHv, CSVv…contact, TR, TR1, TR1hv, TR2hv, TRhv, TR2vv, TRvv…transistor.

Claims

1. A semiconductor device, wherein, have: The first region, containing impurities of the first conductivity type, is disposed on the substrate; The second region, located within the first region, contains a higher concentration of impurities of the first conductivity type than the first region. A first structure is disposed on a substrate on one side of the second region in a first direction, having at least a first sidewall on the second region side, and having one or more gate electrodes, wherein the first direction is the direction along the substrate; A second structure, disposed on the substrate on the other side of the second region in the first direction, having at least a second sidewall on the second region side, including a barrier layer and not having a gate electrode; and The contact portion extends into the second region by passing through the first sidewall and the second sidewall that are opposite each other and sandwiching the second region, and is electrically connected to the second region.

2. The semiconductor device of claim 1, wherein, The first construct includes: The first gate electrode and the second gate electrode are disposed at a position above the first region that does not overlap with the second region; and A spacer layer is disposed on both sides of the first gate electrode and the second gate electrode in the first direction.

3. The semiconductor device as claimed in claim 1, wherein, The side of the contact portion contacts at least one of the first sidewall or the second sidewall on at least one side in the first direction.

4. The semiconductor device of claim 1, wherein, The central position between the first sidewall and the second sidewall is substantially the same as the central position of the second region in the first direction.

5. The semiconductor device of claim 1, wherein, It also has: The third structure, disposed in the first direction on the side opposite to the first structure when viewed from the second structure, includes one or more gate electrodes; as well as Other contact portions are located between the first structure and the third structure in the first direction.

6. A semiconductor device, wherein, have: The first region, containing impurities of the first conductivity type, is disposed on the substrate; The second region, located within the first region, contains a higher concentration of impurities of the first conductivity type than the first region. The gate electrode is disposed above the first region in a manner that does not overlap with the second region; A barrier layer is disposed at least above the second region; The first sidewall is disposed on both sides of the gate electrode in the first direction, separated by the first portion of the barrier layer, wherein the first direction is the direction along the substrate; The second sidewall is disposed on both sides of the second portion of the barrier layer in the first direction; and The first contact portion extends into the second region by passing through one of the first sidewalls and one of the second sidewalls, which are opposite each other and sandwich the second region, and is electrically connected to the second region. The gate electrode is not disposed between the second sidewalls.

7. The semiconductor device of claim 6, wherein, A silicide layer is provided on the surface of the second region, which is located between the barrier layers sandwiching the second region in the first direction. The lower end of the first contact portion is connected to the silicide layer.

8. The semiconductor device of claim 7, wherein, The central position of the second region in the first direction is substantially the same as the central position of the silicide layer.

9. The semiconductor device of claim 7, wherein, A voltage is applied to the first contact portion.

10. The semiconductor device of claim 6, wherein, It also has a second contact portion connected to the upper surface of the gate electrode.

11. The semiconductor device of claim 6, wherein, The gate electrode has: Polycrystalline silicon electrodes; and A metal electrode is disposed on the polycrystalline silicon electrode.

12. The semiconductor device of claim 6, wherein, The gate electrode has: Polycrystalline silicon electrodes; and A self-aligned silicide layer is disposed on the polycrystalline silicon electrode.

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