A graphics processor prefetch unit and method of prefetching instructions and vertices

Abstract

The application belongs to the technical field of graphics processing and provides a graphics processor prefetch unit and an instruction and vertex prefetch method. The graphics processor prefetch unit comprises an external storage interface module, a state machine control module, a first-level cache module, a second-level cache module and an output module. The instructions, vertices and indexes prefetched by the graphics processor are subjected to state machine control and two-level caching, and the three types of data are transmitted in time. Since the transmission lengths of the instructions and the vertices are different and the vertices are repeatedly used, the pointers of the instructions and the vertices are compared between two transmission sections, the data type of the next section is arbitrated, the transmission sequence of the instructions and the vertices is dynamically adjusted according to the prefetch and output states of different types of data, the empty or full state of the data of the instructions, the vertices and the indexes in the cache and the waiting time are reduced, the data transmission efficiency is optimized, and the data bandwidth of the graphics processor is improved.

Description

Technical Field

[0001] This invention belongs to the field of graphics processing technology, and particularly relates to a graphics processor prefetching unit and a method for prefetching instructions and vertices. Background Technology

[0002] In a graphics processing unit (GPU), instructions and vertices are the front-end data entry points for graphics processing. Instructions are generated by compiling the shading language program using a graphics compiler. Vertices are the basic units that make up primitives. After undergoing spatial transformations and lighting in the shader, vertices are fed into primitive assembly and processing to assemble primitives. After rasterization, primitives are used to generate fragments, where the number of pixels is far greater than the number of vertices. Vertex and fragment pixel data mainly include spatial coordinates, color values, texture coordinates, and normal vectors. Each attribute contains up to four components, and each component may be a single-precision floating-point type. Instruction and vertex data are stored in external memory before graphics processing.

[0003] In the graphics pipeline, the bandwidth requirements of fragment pixels are greater than those of instructions and vertices. Within the same graphics processor, the transmission rates of instructions, vertices, and fragment pixels should be matched as closely as possible to avoid wasting hardware resources and to ensure graphics processing performance.

[0004] In the graphics pipeline, the raw data of related instructions, vertices, and indices in external memory is transferred in small segments sequentially. A segment of instruction, vertex, and index is written to the cache in turn, and then read into the shader in sequence. When the data in the cache is empty or full, it can cause waiting for reading or writing data, resulting in low transfer efficiency. Summary of the Invention

[0005] In view of the above problems, the purpose of this invention is to provide a graphics processor prefetching unit and a method for prefetching instructions and vertices, aiming to solve the technical problem of low data transmission efficiency in existing graphics processors.

[0006] On one hand, the graphics processor prefetch unit includes:

[0007] The external memory interface module is used to send the external memory read address and transmission length calculated by the state machine control module when the cache write address is in the state state to the external memory controller, and to transmit the data returned by the external memory to the first-level cache module.

[0008] The state machine control module has a read state machine and a write state machine, which are used to control the read state and write state of the cache, respectively.

[0009] The first-level cache module is used to partition and store the instructions, vertex, and index data transmitted from the external storage interface module through the state machine control module, and read them out to the second-level cache module or the output module.

[0010] The second-level cache module, including the second-level vertex cache and the second-level index cache, is used to first write the index when the state machine control module arbitrates and selects to read vertex and index data from the first-level cache module, then mark the duplicate index numbers, and skip duplicate vertex attribute data when writing vertices.

[0011] The output module is used to format and integrate the instructions, indexes and vertex data read from the first-level cache module and the second-level cache module before outputting them to the unified rendering architecture shader.

[0012] On the other hand, the instruction and vertex prefetching methods in the graphics processor include writing data to the L1 cache and reading data from the L1 cache;

[0013] S11. When the state machine control module receives the graphics processing start command, the cache write state machine jumps from the idle state to the arbitration state.

[0014] S12. In arbitration mode, when the first-level cache is not full, the cache write state machine actively initiates an external storage read request to read a piece of data from the configured external storage address.

[0015] S13, The cache write state machine parses the configuration feature bits of the header data of the data segment;

[0016] S14. If the configuration feature bit is set to configuration, then enter the configuration state and configure the address and transmission length of the external storage instruction, vertex, and index.

[0017] S15. If the configuration feature bit is not configured, then jump to the address state according to the address of the external memory instruction, vertex, index and the current value of the register for the transfer length.

[0018] S16. In the address state, the cache write state machine enters the data state after receiving the response signal from the external storage interface module. Whenever it receives a piece of data from external storage, it writes the data to the corresponding area of ​​the first-level cache, decrements the count value by 1 from the transmission length, and ends the current cache write operation when the count value is 0. At the same time, it modifies the external storage address to the external storage address plus the transmission length.

[0019] The specific process of reading data from the first-level cache is as follows:

[0020] S21. When the Level 1 cache is not empty, the cache read state machine jumps from the idle state to the arbitration state.

[0021] S22. In arbitration mode, query the pointers corresponding to instructions and vertices in the first-level cache and compare their sizes.

[0022] S23. If the instruction pointer is less than the vertex pointer, the arbitration selects instruction data. When the output module is ready to receive, the instruction data is directly read from the first-level cache and transmitted to the output module. When the instruction count value decreases to 0, the arbitration selection is performed again.

[0023] S24. If the vertex pointer is greater than or equal to the instruction pointer, the arbitration selects vertex data and reads the index corresponding to the vertex data to be read from the first-level cache and writes it into the second-level index cache. When the index count value decreases to 0, the vertex data with the missing sequence number is read from the first-level cache and written to the second-level vertex cache until the vertex count value decreases to 0. Then the arbitration selection is performed again.

[0024] S25. When the secondary vertex buffer and secondary index buffer are full, data is read from the secondary buffer and transmitted to the output module when the output module is ready to receive data.

[0025] The beneficial effects of this invention are as follows: The graphics processor prefetch unit provided by this invention controls the prefetched instructions, vertices, and indices using a state machine and a two-level cache, and transmits these three types of data in a time-sharing manner. Due to the different transmission lengths of instructions and vertices and the reuse of vertices, the data type of the next read / write segment is arbitrated by comparing the pointers of instructions and vertices between two transmission segments. This realizes the dynamic adjustment of the transmission order of instructions and vertices according to the prefetch and output states of different types of data, reduces the situation of empty or full data in the cache of instructions, vertices, and indices, and the waiting time, optimizes the data transmission efficiency, and improves the prefetch data bandwidth of the graphics processor. Attached Figure Description

[0026] Figure 1 This is a structural diagram of the graphics processor prefetch unit provided in an embodiment of the present invention;

[0027] Figure 2 This is a flowchart of the prefetch unit level 1 cache write data provided in an embodiment of the present invention;

[0028] Figure 3 This is a flowchart of the data reading process of the prefetch unit's first-level cache provided in an embodiment of the present invention;

[0029] Figure 4 This is a cache data distribution diagram provided in an embodiment of the present invention;

[0030] Figure 5 This is an example diagram of data transmission provided in an embodiment of the present invention. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0032] To illustrate the technical solution described in this invention, specific embodiments are described below.

[0033] Figure 1 The structure of the graphics processor prefetch unit provided in the embodiment of the present invention is shown. For ease of explanation, only the parts related to the embodiment of the present invention are shown.

[0034] like Figure 1 As shown, the graphics processor prefetch unit provided in this embodiment includes:

[0035] The external memory interface module is used to send the external memory read address and transmission length calculated by the state machine control module when the cache write address is in the state state to the external memory controller, and to transmit the data returned by the external memory to the first-level cache module.

[0036] The state machine control module has a read state machine and a write state machine, which are used to control the read state and write state of the cache, respectively. The cache read state includes sub-states of idle, arbitration, hit judgment, address, and data, and the cache write state includes sub-states of idle, arbitration, configuration, address, and data.

[0037] The first-level cache module is used to partition and store the instructions, vertex, and index data transmitted from the external storage interface module through the state machine control module, and read them out to the second-level cache module or the output module.

[0038] The second-level cache module, including the second-level vertex cache and the second-level index cache, is used to first write the index when the state machine control module arbitrates and selects to read vertex and index data from the first-level cache module, then mark the duplicate index numbers, and skip duplicate vertex attribute data when writing vertices.

[0039] The output module is used to format and integrate the instructions, indexes and vertex data read from the first-level cache module and the second-level cache module before outputting them to the unified rendering architecture shader.

[0040] In this embodiment, the graphics processor prefetch unit controls the read and write operations of the cache through a state machine control module, and employs a two-level cache to transmit instruction, vertex, and index data in a time-sharing manner. Instruction and vertex prefetching in the graphics processor prefetch unit includes two processes: writing data to the first-level cache and reading data from the first-level cache.

[0041] Combination Figure 2 As shown, writing data to the first-level cache specifically includes the following steps:

[0042] S11. When the state machine control module receives the graphics processing start command, the cache write state machine jumps from the idle state to the arbitration state.

[0043] S12. In arbitration mode, when the first-level cache is not full, the cache write state machine actively initiates an external storage read request to read a piece of data from the configured external storage address.

[0044] S13, The cache write state machine parses the configuration feature bits of the header data of the data segment;

[0045] S14. If the configuration feature bit is set to configuration, then enter the configuration state and configure the address and transmission length of the external storage instruction, vertex, and index.

[0046] S15. If the configuration feature bit is not configured, then jump to the address state according to the address of the external memory instruction, vertex, index and the current value of the register for the transfer length.

[0047] S16. In the address state, the cache write state machine enters the data state after receiving the response signal from the external storage interface module. Whenever it receives a piece of data from external storage, it writes the data to the corresponding area of ​​the first-level cache, decrements the count value by 1 from the transmission length, and ends the current cache write operation when the count value is 0. At the same time, it modifies the external storage address to the external storage address plus the transmission length.

[0048] In this embodiment, during a cache write operation, when an instruction or vertex in the first-level cache completes a data transmission, the write state machine jumps to the data type with the smaller read / write pointer in the first-level cache to perform the next data transmission, reading data from external storage and writing it into the first-level cache.

[0049] Combination Figure 3 As shown, the specific process of reading data from the first-level cache is as follows:

[0050] S21. When the Level 1 cache is not empty, the cache read state machine jumps from the idle state to the arbitration state.

[0051] S22. In arbitration mode, query the pointers corresponding to instructions and vertices in the first-level cache and compare their sizes.

[0052] S23. If the instruction pointer is less than the vertex pointer, the arbitration selects instruction data. When the output module is ready to receive, the instruction data is directly read from the first-level cache and transmitted to the output module. When the instruction count value decreases to 0, the arbitration selection is performed again.

[0053] S24. If the vertex pointer is greater than or equal to the instruction pointer, the arbitration selects vertex data and reads the index corresponding to the vertex data to be read from the first-level cache and writes it into the second-level index cache. When the index count value decreases to 0, the vertex data with the missing sequence number is read from the first-level cache and written to the second-level vertex cache until the vertex count value decreases to 0. Then the arbitration selection is performed again.

[0054] S25. When the secondary vertex buffer and secondary index buffer are full, data is read from the secondary buffer and transmitted to the output module when the output module is ready to receive data.

[0055] Step S22 above compares the sizes of the instruction pointer and the vertex pointer. When writing and reading instructions and vertices from the L1 cache, the pointers are incremented and decremented by 1 respectively. The data type with the larger pointer value is selected to initiate a read cache request. If the pointer values ​​are the same, the default vertex and instruction priority order applies.

[0056] Steps S23 and S24 involve selecting the appropriate quantity type based on the pointer value. When arbitrarily selecting instruction data, if the output module is ready to receive it, it directly reads the data from the first-level cache and passes it to the output module. When arbitrarily selecting vertex data, the index is first read from the first-level cache and written to the second-level index cache. Then, the vertex data with missing sequence numbers read from the first-level cache is written to the second-level vertex cache. The specific process is executed based on the index count value and the vertex count value.

[0057] Both the index count and vertex count are configured based on the size of the L2 cache. When a write operation is performed to the L2 index cache, the count is decremented by 1; when a write operation is performed to the L2 vertex cache, the count is decremented by 1. When a vertex's sequence number is matched, the L1 cache read address skips that vertex, and the count is also decremented by 1. During cache read operations, when a vertex is read from the L1 cache, if the vertex's sequence number is matched, the L1 cache read address skips that vertex, and the corresponding vertex pointer in the L1 cache arbitration is also decremented by 1. During cache read operations, when both the L2 vertex cache and L2 index cache are full, data is read from the L2 cache and transmitted to the output module when the output module is ready to receive data.

[0058] like Figure 4 As shown, the first-level cache is configured into three partitions before rendering starts: instruction, index, and vertex. When reading or writing data in the first-level cache, the offset address is calculated at the corresponding base address according to the data type being transferred. The second-level cache only contains indexes and vertices, not instructions. When the first-level cache write data stream starts transferring, it is sorted according to the amount of raw data in external storage. Since repeated vertices are skipped during vertex transfer, a vertex has a maximum of 4 attribute data. The amount of data in the index is relatively small, which improves the reading speed of vertices and indices in the first-level cache. When the read / write state machine transitions after a data transfer is completed, the data type for the next segment of the first-level cache is dynamically selected based on the instructions in the first-level cache and the vertex read / write flag values.

[0059] Figure 5 An example of data transfer is shown, in which a certain amount of data is written to the L1 buffer in the order of instruction, index, vertex, and so on. When reading the data stream from the L1 buffer, the data stream is read in the order of instruction, index, vertex, index, vertex, index, vertex, instruction, based on the pointer size.

[0060] At the front end of the graphics pipeline, graphics instructions, vertex attributes, and indexes are stored in different areas of external memory. The graphics processor accesses external memory and shader cores at different frequencies and with varying latency and bandwidth limitations, thus requiring caching for asynchronous processing. A common approach is to sequentially transfer the raw data of related instructions, vertices, and indexes in small segments from external memory, while writing a segment of instruction, vertex, and index to the cache in turn, and then reading it into the shader. When the data in the cache is empty or full, it leads to waiting times for reading or writing, resulting in low transmission efficiency. This invention uses a two-level cache method to compare indexes and mark vertex indices, quickly eliminating the transmission of duplicate vertex attribute data. Simultaneously, it arbitrates the data type of the next segment of reading and writing by comparing instruction and vertex pointers during the read / write process, reducing the occurrence of empty or full data in the cache and the waiting time, thereby improving data transmission efficiency.

[0061] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for instruction and vertex prefetching in a graphics processor, characterized in that, The prefetching method includes writing data to the first-level cache and reading data from the first-level cache; The process of writing data to the first-level cache specifically includes the following steps: S11. When the state machine control module receives the graphics processing start command, the cache write state machine jumps from the idle state to the arbitration state. S12. In arbitration mode, when the first-level cache is not full, the cache write state machine actively initiates an external storage read request to read a piece of data from the configured external storage address. S13, The cache write state machine parses the configuration feature bits of the header data of the data segment; S14. If the configuration feature bit is set to configuration, then enter the configuration state and configure the address and transmission length of the external storage instruction, vertex, and index. S15. If the configuration feature bit is not configured, then jump to the address state according to the address of the external memory instruction, vertex, index and the current value of the register for the transfer length. S16. In the address state, the cache write state machine enters the data state after receiving the response signal from the external storage interface module. Whenever it receives a piece of data from external storage, it writes the data to the corresponding area of ​​the first-level cache, decrements the count value by 1 from the transmission length, and ends the current cache write operation when the count value is 0. At the same time, it modifies the external storage address to the external storage address plus the transmission length. The specific process of reading data from the first-level cache is as follows: S21. When the L1 cache is not empty, the cache read state machine jumps from the idle state to the arbitration state. S22. In arbitration mode, query the pointers corresponding to instructions and vertices in the first-level cache and compare their sizes. S23. If the instruction pointer is less than the vertex pointer, the arbitration selects instruction data. When the output module is ready to receive, the instruction data is directly read from the first-level cache and transmitted to the output module. When the instruction count value decreases to 0, the arbitration selection is performed again. S24. If the vertex pointer is greater than or equal to the instruction pointer, the arbitration selects vertex data and reads the index corresponding to the vertex data to be read from the first-level cache and writes it into the second-level index cache. When the index count value decreases to 0, the vertex data with the missing sequence number is read from the first-level cache and written to the second-level vertex cache until the vertex count value decreases to 0. Then the arbitration selection is performed again. S25. When the secondary vertex buffer and secondary index buffer are full, data is read from the secondary buffer and transmitted to the output module when the output module is ready to receive data.

2. The instruction and vertex prefetching method in a graphics processor as described in claim 1, characterized in that, In step S17, during a cache write operation, when an instruction or vertex in the first-level cache completes a data transfer, the write state machine jumps to the data type with the smaller first-level cache read / write pointer to perform the next data transfer, reading data from external storage and writing it into the first-level cache.

3. The instruction and vertex prefetching method in a graphics processor as described in claim 2, characterized in that, When instructions and vertices are written to the L1 cache, the pointer is incremented by 1; when they are read out, the pointer is decremented by 1. A read cache request is initiated based on the data type with the larger pointer value. If the pointer values ​​are the same, the default priority order applies.

4. The instruction and vertex prefetching method in a graphics processor as described in claim 3, characterized in that, Both the index count and vertex count are configured based on the size of the second-level cache. When a write operation is performed to the second-level index cache, the index count is reduced by 1.

5. The instruction and vertex prefetching method in a graphics processor as described in claim 4, characterized in that, When writing to the secondary vertex cache, the vertex count is decremented by 1. If the vertex sequence number is hit, the primary cache read address skips the vertex, and the vertex count is also decremented by 1.

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