A method of manufacturing a semiconductor device

Abstract

The application provides a preparation method of a semiconductor device, comprising the following steps: forming a top metal layer on a semiconductor layer; forming an insulating layer on the semiconductor layer to cover a first metal structure and a second metal structure, and the lowest part of the upper surface of the insulating layer is higher than the top surface of the top metal layer; planarizing the insulating layer; etching the insulating layer to form a first groove, the first groove is located above the second metal structure and the bottom surface is higher than the top surface of the second metal structure; etching the insulating layer to form a second groove and deepening the first groove until the bottom part exposes the second metal structure, and the second groove is arranged to be spaced apart from the first and second metal structures in the horizontal direction. The application increases the thickness of the insulating layer, simultaneously adds a planarization process, and opens the insulating layer above the second metal structure through step-by-step etching. In the process, the insulating layer above the first metal structure can be well protected, so that the probability of damage to the first metal structure is reduced, and the product yield is improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology and relates to a method for fabricating a semiconductor device. Background Technology

[0002] Semiconductor devices are fabricated layer by layer using planar processes. For logic devices, the first step is to define the active areas for transistors on a substrate. Then, N-type and P-type regions are created through ion implantation. Next, the gate is fabricated, followed by another round of ion implantation to complete the source and drain of each transistor. This part of the process, used to fabricate N-type and P-type field-effect transistors on the substrate, is known as the front-end of line (FEOL) process. In contrast, the back-end of line (BEOL) process is used to create several layers of conductive metal lines, with different layers connected by pillar-shaped metal structures.

[0003] In semiconductor manufacturing processes, top metal is an indispensable component. During wafer-level production, when removing the oxide layer from certain top metal structures, it is easy to damage the oxide layer on top metal structures of other special patterns that need to be protected. This can easily cause damage to the top metal structures of these special patterns, resulting in quality issues.

[0004] Therefore, how to improve the fabrication methods of semiconductor devices to increase product yield has become an important technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method for fabricating semiconductor devices to solve the problem that the existing fabrication methods are prone to damaging the top metal structure, resulting in a decrease in yield.

[0006] To achieve the above and other related objectives, this application provides a method for fabricating a semiconductor device, comprising the following steps:

[0007] A semiconductor layer is provided, and a top metal layer is formed on the semiconductor layer, the top metal layer including a first metal structure and a second metal structure spaced apart in a horizontal direction;

[0008] An insulating layer is formed on the semiconductor layer, the insulating layer covering the first metal structure and the second metal structure, and the lowest point of the upper surface of the insulating layer is higher than the top surface of the top metal layer;

[0009] The insulating layer is planarized to obtain an insulating plane that is higher than the top surface of the top metal layer;

[0010] The insulating layer is etched to form a first groove, the first groove being located above the second metal structure, and the bottom surface of the first groove being higher than the top surface of the second metal structure;

[0011] The insulating layer is etched to form a second groove, and the first groove is deepened until the bottom of the first groove exposes the second metal structure. The second groove is spaced apart from both the first metal structure and the second metal structure in the horizontal direction.

[0012] Optionally, the following steps are included:

[0013] A first mask layer is formed on the insulating plane, and the first mask layer is patterned to obtain a first opening, the first opening being located above the second metal structure;

[0014] The insulating layer is etched based on the first opening to obtain the first groove, wherein the bottom surface of the first groove is higher than the top surface of the second metal structure;

[0015] A second mask layer is formed on the insulating plane, and the second mask layer is patterned to obtain a second opening and a third opening spaced apart. The second opening is located above the second metal structure, and the insulating layer above the first metal structure is still covered by the second mask layer.

[0016] Based on the second opening and the third opening, the insulating layer is etched until the bottom of the first groove is exposed to reveal the second metal structure, and the second groove is obtained in the insulating layer in the region where the third opening is located.

[0017] Optionally, before forming the second mask layer on the insulating plane, the remaining first mask layer after forming the first groove is removed.

[0018] Optionally, the first mask layer includes a photoresist layer, and the second mask layer includes a photoresist layer.

[0019] Optionally, the third opening is located horizontally between the first metal structure and the second metal structure.

[0020] Optionally, after etching the insulating layer based on the second opening and the third opening until the bottom of the first groove exposes the second metal structure, a portion of the second mask layer remains on the insulating layer above the first metal structure.

[0021] Optionally, the width of the first metal structure is smaller than the width of the second metal structure.

[0022] Optionally, the first metal structure includes metal wires, and the second metal structure includes solder pads.

[0023] Optionally, the insulating layer may be made of silicon oxide.

[0024] Optionally, the method of etching the insulating layer to obtain the first groove includes at least one of dry etching and wet etching, and the method of etching the insulating layer until the bottom of the first groove exposes the second metal structure and obtains the second groove includes at least one of dry etching and wet etching.

[0025] As described above, the semiconductor device fabrication method of this application increases the thickness of the insulating layer, incorporates a planarization process, and uses step-by-step etching to open the insulating layer above the second metal structure. During this process, the insulating layer above the first metal structure is well protected, thereby reducing the probability of damage to the first metal structure and improving product yield. In the second etching step, in addition to the insulating layer above the second metal structure, the insulating layers in other desired areas can be etched simultaneously. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the structure to be etched provided in a method for fabricating a semiconductor device.

[0027] Figure 2 This diagram illustrates a method for fabricating a semiconductor device by forming a photoresist layer to cover an insulating layer.

[0028] Figure 3 This diagram illustrates a method for fabricating a semiconductor device, showing a photoresist layer patterned to obtain an opening in the photoresist layer that exposes an insulating layer above a second metal structure, and then etching the insulating layer based on the opening in the photoresist layer to expose the second metal structure.

[0029] Figure 4 The diagram shown is a process flow chart of the method for fabricating the semiconductor device of this application.

[0030] Figure 5 The diagram shows a method for fabricating a semiconductor device according to this application, in which a top metal layer is formed on the semiconductor layer and an insulating layer is formed on the semiconductor layer.

[0031] Figure 6 The diagram shown illustrates a method for fabricating a semiconductor device according to this application, in which the insulating layer is planarized to obtain an insulating plane.

[0032] Figure 7 The diagram shows a method for fabricating a semiconductor device according to this application, in which a first mask layer is formed on the insulating plane and patterned to obtain a first opening.

[0033] Figure 8 The diagram shown illustrates a method for fabricating a semiconductor device according to this application, based on etching the insulating layer through the first opening to obtain a first groove.

[0034] Figure 9 The diagram shows a method for fabricating a semiconductor device according to this application, in which a second mask layer is formed on the insulating plane and patterned to obtain a second opening and a third opening spaced apart.

[0035] Figure 10 The diagram shows a method for fabricating a semiconductor device according to this application, in which the insulating layer is etched until the bottom of the first groove is exposed to reveal the second metal structure, and a second groove is obtained in the insulating layer in the region where the third opening is located.

[0036] Component designation explanation Detailed Implementation

[0037] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application.

[0038] Please see Figures 1 to 10 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0039] Please see Figures 1 to 3 A method for fabricating a semiconductor device includes the following steps:

[0040] (1) such as Figure 1 As shown, a structure to be etched is provided, including a semiconductor layer 101, a first metal structure 102, a second metal structure 103 and an insulating layer 104, wherein the width of the first metal structure 102 is much smaller than the width of the second metal structure 103, the portion of the insulating layer 104 located on the second metal structure 103 is relatively flat, while the portion located on the first metal structure 102 has a protruding tip.

[0041] (2) such as Figure 2 As shown, a photoresist layer 105 is formed to cover the insulating layer 104.

[0042] (3) such as Figure 3As shown, the photoresist layer 105 is patterned to obtain a photoresist layer opening that exposes the insulating layer above the second metal structure 103, and then the insulating layer 104 is etched based on the photoresist layer opening to expose the second metal structure 103.

[0043] In the aforementioned semiconductor device fabrication method, due to the special pattern of the first metal structure 102 (e.g., a single metal line) and the thin photoresist layer covering the first metal structure 102, the insulating layer above the first metal structure 102 is easily exposed and damaged, which in turn easily causes damage to the first metal structure 102 and leads to quality problems. Therefore, this application improves the semiconductor process steps to solve the above problems.

[0044] Please see Figure 4 The diagram shows a process flow chart of the semiconductor device fabrication method of this application, including the following steps:

[0045] S1: A semiconductor layer is provided, and a top metal layer is formed on the semiconductor layer, the top metal layer including a first metal structure and a second metal structure spaced apart in the horizontal direction;

[0046] S2: An insulating layer is formed on the semiconductor layer, the insulating layer covering the first metal structure and the second metal structure, and the lowest point of the upper surface of the insulating layer is higher than the top surface of the top metal layer;

[0047] S3: Planarize the insulating layer to obtain an insulating plane that is higher than the top surface of the top metal layer;

[0048] S4: Etch the insulating layer to form a first groove, the first groove being located above the second metal structure, and the bottom surface of the first groove being higher than the top surface of the second metal structure;

[0049] S5: Etch the insulating layer to form a second groove, and deepen the first groove until the bottom of the first groove exposes the second metal structure. The second groove is spaced apart from both the first metal structure and the second metal structure in the horizontal direction.

[0050] Please refer to the following first. Figure 5 The steps S1 and S2 are performed as follows: a semiconductor layer 201 is provided, a top metal layer is formed on the semiconductor layer, the top metal layer includes a first metal structure 202 and a second metal structure 203 spaced apart in the horizontal direction, and an insulating layer 204 is formed on the semiconductor layer 201, the insulating layer 204 covers the first metal structure 202 and the second metal structure 203, and the lowest point of the upper surface of the insulating layer 204 is higher than the top surface of the top metal layer.

[0051] As an example, transistor structures, conductive interconnect structures, and other necessary structures may be pre-fabricated in the semiconductor layer 201. The material of the top metal layer includes, but is not limited to, copper or aluminum.

[0052] As an example, the first metal structure 202 and the second metal structure 203 have different patterns. In this embodiment, the width of the first metal structure 202 is smaller than the width of the second metal structure 203.

[0053] As an example, the first metal structure 202 includes a metal wire, and the second metal structure 203 includes a solder pad. In this embodiment, the first metal structure 202 is a single metal wire adjacent to the second metal structure 203.

[0054] As an example, the insulating layer 204 is formed using chemical vapor deposition, physical vapor deposition, or other suitable methods, and the material of the insulating layer 204 includes, but is not limited to, silicon oxide.

[0055] Please see again Figure 6 Perform step S3: planarize the insulating layer 204 using chemical mechanical polishing (CMP) or other suitable methods to obtain an insulating plane M, the insulating plane M being higher than the top surface of the top metal layer.

[0056] Please see again Figure 7 and Figure 8 Step S4 is performed: the insulating layer 204 is etched to form a first groove 207, the first groove 207 is located above the second metal structure 203, and the bottom surface of the first groove 207 is higher than the top surface of the second metal structure 203.

[0057] As an example, such as Figure 7 As shown, a first mask layer 205 is first formed on the insulating plane M, and the first mask layer 205 is patterned to obtain a first opening 206, which is located above the second metal structure 203.

[0058] As an example, the first mask layer 205 includes a photoresist layer. The first mask layer 205 is patterned by photolithography processes such as exposure and development to obtain the first opening 206. The bottom surface of the first opening 206 exposes the insulating layer 204.

[0059] As an example, such as Figure 8 As shown, the insulating layer 204 is then etched based on the first opening 206 to obtain the first groove 207, the bottom surface of the first groove 207 being higher than the top surface of the second metal structure 203.

[0060] As an example, the method of etching the insulating layer 204 to obtain the first groove 207 includes at least one of dry etching and wet etching.

[0061] As an example, during the etching of the insulating layer 204 to obtain the first groove 207, the thickness of the first mask layer 205 is reduced, but it still covers the insulating layer above the first metal structure 202.

[0062] Please see again Figure 9 and Figure 10 Step S5 is performed: the insulating layer 204 is etched to form a second groove 211, and the first groove 207 is deepened until the bottom of the first groove 207 exposes the second metal structure 203. The second groove 211 is spaced apart from the first metal structure 202 and the second metal structure 203 in the horizontal direction.

[0063] As an example, such as Figure 9 As shown, a second mask layer 208 is first formed on the insulating plane M, and the second mask layer 208 is patterned to obtain a second opening 209 and a third opening 210 spaced apart. The second opening 209 is located above the second metal structure 203, and the insulating layer above the first metal structure 202 is still covered by the second mask layer 208.

[0064] As an example, before forming the second mask layer 208 on the insulating plane M, the remaining first mask layer 205 used to form the first groove 207 is removed.

[0065] As an example, the second mask layer 208 includes a photoresist layer. The second mask layer 208 is patterned by photolithography processes such as exposure and development to obtain the second opening 209 and the third opening 210. The bottom surfaces of the second opening 209 and the third opening 210 expose the insulating layer 204.

[0066] As an example, the third opening 210 is located in the horizontal direction between the first metal structure 202 and the second metal structure 203 or other desired etching areas.

[0067] As an example, such as Figure 10 As shown, the insulating layer 204 is then etched based on the second opening 209 and the third opening 210 until the bottom of the first groove 207 is exposed to reveal the second metal structure 203, and a second groove 211 is obtained in the insulating layer 204 in the region where the third opening 210 is located.

[0068] As an example, the method of etching the insulating layer 204 until the bottom of the first groove 207 is exposed to reveal the second metal structure 203 and obtain the second groove 211 includes at least one of dry etching and wet etching.

[0069] As an example, after etching the insulating layer 204 based on the second opening 209 and the third opening 210 until the bottom of the first groove 207 is exposed to reveal the second metal structure 203, a portion of the second mask layer 208 remains on the insulating layer 204 above the first metal structure 202. That is, the insulating layer 204 above the first metal structure 202 can be well protected, thereby reducing the probability of damage to the first metal structure 202.

[0070] In summary, the semiconductor device fabrication method of this application increases the thickness of the insulating layer, incorporates a planarization process, and uses step-by-step etching to open the insulating layer above the second metal structure. During this process, the insulating layer above the first metal structure is well protected, thereby reducing the probability of damage to the first metal structure and improving product yield. In the second etching step, in addition to the insulating layer above the second metal structure, the insulating layers in other desired areas can be etched simultaneously. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0071] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A semiconductor layer (201) is provided, and a top metal layer is formed on the semiconductor layer (201). The top metal layer includes a first metal structure (202) and a second metal structure (203) spaced apart in the horizontal direction. An insulating layer (204) is formed on the semiconductor layer (201), the insulating layer (204) covers the first metal structure (202) and the second metal structure (203), and the lowest point of the upper surface of the insulating layer (204) is higher than the top surface of the top metal layer; The insulating layer (204) is planarized to obtain an insulating plane (M) that is higher than the top surface of the top metal layer; The insulating layer (204) is etched to form a first groove (207), the first groove (207) being located above the second metal structure (203), and the bottom surface of the first groove (207) being higher than the top surface of the second metal structure (203); The insulating layer (204) is etched to form a second groove (211), and the first groove (207) is deepened until the bottom of the first groove (207) exposes the second metal structure (203). The second groove (211) is spaced apart from the first metal structure (202) and the second metal structure (203) in the horizontal direction. The formation of the first groove (207) and the second groove (211) includes the following steps: A first mask layer (205) is formed on the insulating plane (M), and the first mask layer (205) is patterned to obtain a first opening (206), the first opening (206) being located above the second metal structure (203); The insulating layer is etched based on the first opening (206) to obtain the first groove (207), the bottom surface of the first groove (207) being higher than the top surface of the second metal structure (203); A second mask layer (208) is formed on the insulating plane (M), and the second mask layer (208) is patterned to obtain a second opening (209) and a third opening (210) spaced apart. The second opening (209) is located above the second metal structure (203), and the insulating layer (204) above the first metal structure (202) is still covered by the second mask layer (208). Based on the second opening (209) and the third opening (210), the insulating layer (204) is etched until the bottom of the first groove (207) is exposed to reveal the second metal structure (203), and the second groove (211) is obtained in the insulating layer (204) in the area where the third opening (210) is located.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that: Before forming the second mask layer (208) on the insulating plane (M), the remaining first mask layer (205) after forming the first groove (207) is removed.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that: The first mask layer (205) includes a photoresist layer, and the second mask layer (208) includes a photoresist layer.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that: The third opening (210) is located horizontally between the first metal structure (202) and the second metal structure (203).

5. The method for fabricating a semiconductor device according to claim 1, characterized in that: After etching the insulating layer (204) based on the second opening (209) and the third opening (210) until the bottom of the first groove (207) exposes the second metal structure (203), a portion of the second mask layer (208) remains on the insulating layer (204) above the first metal structure (202).

6. The method for fabricating a semiconductor device according to claim 1, characterized in that: The width of the first metal structure (202) is smaller than the width of the second metal structure (203).

7. The method for fabricating a semiconductor device according to claim 1, characterized in that: The first metal structure (202) includes metal wires, and the second metal structure (203) includes solder pads.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that: The insulating layer (204) is made of silicon oxide.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that: The method of etching the insulating layer (204) to obtain the first groove (207) includes at least one of dry etching and wet etching. The method of etching the insulating layer (204) until the bottom of the first groove (207) exposes the second metal structure (203) and obtains the second groove (211) includes at least one of dry etching and wet etching.

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