Array substrate and manufacturing method thereof

Abstract

The application discloses an array substrate, which comprises a substrate, a first conductive layer, a first insulating layer and a second conductive layer which are sequentially stacked. The first conductive layer comprises a source electrode, a gate electrode, a drain electrode and a first capacitor plate which is spaced apart from the source electrode. The second conductive layer comprises an active layer and a second capacitor plate which is spaced apart from the active layer. One side of the active layer is connected to the drain electrode, and the other side of the active layer is connected to the source electrode, so as to form a thin film transistor. The active layer overlaps the gate electrode, so that the gate electrode can be reused as a light shielding layer. The first capacitor plate and the second capacitor plate overlap to form a capacitor. The application also provides a manufacturing method of the array substrate. The array substrate and the manufacturing method thereof simplify the film layer structure, thereby reducing the film layer thickness of the array substrate, and meanwhile, the number of manufacturing masks can be reduced, and the process is simplified.

Description

Technical Field

[0001] This application belongs to the field of display technology, specifically relating to array substrates and their fabrication methods. Background Technology

[0002] Current active-matrix organic light-emitting diode (EMD) panels employ a top-gate structure for their thin-film transistors (TFTs). The fabrication process for the array substrate used to form this TFT structure is complex, typically involving seven or more photomasks, and the substrate itself is quite thick. Therefore, to simplify the structure and fabrication process of the array substrate, a new array substrate and its fabrication method are needed, which can reduce the substrate thickness and the number of photomasks required. Summary of the Invention

[0003] The purpose of this application is to provide an array substrate and a method for manufacturing the same, which can reduce the thickness of the array substrate, reduce the number of photomasks to be fabricated, simplify the process steps, and solve the problems of complex array substrate structure and process.

[0004] To address the aforementioned technical problems, this application provides an array substrate, comprising:

[0005] Substrate;

[0006] A first conductive layer is disposed on the substrate; the first conductive layer includes a source electrode, a gate electrode, and a drain electrode disposed at intervals.

[0007] A first insulating layer is disposed covering the first conductive layer;

[0008] A second conductive layer is disposed on the first insulating layer; the second conductive layer includes an active layer, which overlaps with the gate, and the gate is multiplexed as a light-shielding layer; one side of the active layer is connected to the drain, and the other side of the active layer is connected to the source, thereby forming a thin-film transistor;

[0009] The first conductive layer further includes a first capacitor plate spaced apart from the source electrode, and the second conductive layer further includes a second capacitor plate spaced apart from the active layer. The first capacitor plate and the second capacitor plate are overlapped to form a capacitor.

[0010] In some embodiments, a first via and a second via are formed on the first insulating layer. The first via exposes the drain electrode, and the second via exposes the source electrode. The active layer is connected to the drain electrode through the first via, and the active layer is connected to the source electrode through the second via.

[0011] In some embodiments, the array substrate further includes:

[0012] A second insulating layer is provided, which covers the second conductive layer; the second insulating layer has a third via, which exposes the active layer.

[0013] A third conductive layer is disposed on the second insulating layer, and the third conductive layer includes an anode; the anode is connected to the active layer through the third via.

[0014] A pixel definition layer is disposed on the third conductive layer, and an opening is formed on the pixel definition layer to expose the anode.

[0015] In some embodiments, the first conductive layer further includes a first trace. The third conductive layer further includes a second trace.

[0016] In some embodiments, the first conductive layer further includes a first trace.

[0017] The array substrate further includes a second trace. The second trace includes a first sublayer and a second sublayer stacked sequentially. The first sublayer is formed by the second conductive layer.

[0018] The array substrate further includes a fourth conductive layer. The fourth conductive layer is disposed on the second conductive layer. The second sublayer is formed by the fourth conductive layer.

[0019] In some embodiments, the second insulating layer includes a passivation layer and a planarization layer sequentially stacked on the second conductive layer. The third via penetrates the planarization layer and the passivation layer, exposing the active layer.

[0020] This application also provides a method for manufacturing an array substrate, comprising the following steps:

[0021] Provide a substrate;

[0022] A first conductive layer is formed on the substrate;

[0023] The first conductive layer is patterned using a first photomask to form spaced source, drain, gate and first capacitor plate;

[0024] A first insulating layer is formed on the first conductive layer;

[0025] A second conductive layer is formed on the first insulating layer;

[0026] A second photomask is used to pattern the second conductive layer to form an active layer and a second capacitor plate spaced apart from the active layer; the second capacitor plate and the first capacitor plate are overlapped to form a capacitor; the active layer is overlapped with the gate, and the gate is multiplexed as a light-shielding layer; one side of the active layer is connected to the drain, and the other side of the active layer is connected to the source, forming a thin-film transistor.

[0027] In some embodiments, after the step of patterning the second conductive layer with a second photomask to form an active layer and a second capacitor plate spaced apart from the active layer, the method further includes the following step:

[0028] A second insulating layer is formed on the second conductive layer;

[0029] A third conductive layer is formed on the second insulating layer;

[0030] A pixel definition layer is formed on the third conductive layer;

[0031] A third photomask is used to pattern the third conductive layer and the pixel definition layer to form an anode, which is connected to the active layer.

[0032] In some embodiments, the first conductive layer is patterned using the first photomask, and a first trace is also formed.

[0033] The third conductive layer is patterned using a third photomask, and a second trace is also formed.

[0034] In some embodiments, the first conductive layer is patterned using the first photomask, and a first trace is also formed.

[0035] After the step of forming the second conductive layer on the first insulating layer, the method further includes the following step:

[0036] A fourth conductive layer is formed on the second conductive layer;

[0037] The fourth conductive layer and the second conductive layer are patterned using a second photomask to form the active layer, the second capacitor plate, and the second trace; the second trace includes a first sub-layer formed on the second conductive layer and a second sub-layer formed on the fourth conductive layer, which are stacked together.

[0038] The array substrate provided in this application includes a substrate, a first conductive layer, a first insulating layer, and a second conductive layer stacked sequentially. The first conductive layer includes a source electrode, a gate electrode, a drain electrode, and a first capacitor electrode spaced apart from the source electrode. The second conductive layer includes an active layer and a second capacitor electrode spaced apart from the active layer. One side of the active layer is connected to the drain electrode, and the other side of the active layer is connected to the source electrode to form a thin-film transistor. The active layer overlaps with the gate electrode so that the gate electrode can be reused as a light-shielding layer. The first capacitor electrode and the second capacitor electrode overlap to form a capacitor. This application also provides a method for fabricating the array substrate described above.

[0039] The array substrate and its fabrication method provided in this application simplify the film structure and avoid the separation of electrodes into different layers, thereby reducing the film thickness of the array substrate, because the source, drain, gate, and first capacitor plate are arranged in the same layer, and the active layer and second capacitor plate are arranged in the same layer. Furthermore, since the active layer and gate are overlapped, the gate is reused as a light-shielding layer, saving film layers. Moreover, the source, drain, gate, and first capacitor plate are formed using the same first photomask, and the active layer and second capacitor plate are formed using the same second photomask, avoiding the complex steps of using multiple photomasks, reducing the number of photomasks required, and simplifying the process. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of the structure of an array substrate provided in an embodiment of this application;

[0042] Figure 2 This is a flowchart of a method for fabricating an array substrate according to an embodiment of this application;

[0043] Figure 3 yes Figure 2 A structural diagram of steps S1 to S6;

[0044] Figure 4 yes Figure 2 A structural diagram of steps S7 to S10;

[0045] Figure 5 This is a schematic diagram of the structure of an array substrate provided in another embodiment of this application;

[0046] Figure 6 This is a flowchart of a method for fabricating an array substrate according to another embodiment of this application;

[0047] Figure 7 yes Figure 2 A structural diagram of steps S1' to S6';

[0048] Figure 8 yes Figure 2 A schematic diagram of the structure of steps S7' to S10'.

[0049] Reference numerals: Array substrate 10; Substrate 11; First conductive layer 12; Source 12a; Gate 12b; Drain 12c; First capacitor plate 12d; First insulating layer 13; First via K1; Second via K2; Second conductive layer 14; Active layer 14a; Second capacitor plate 14b; Thin film transistor (TFT); Capacitor C; Second insulating layer 15; Passivation layer 15a; Planarization layer 15b; Third via K3; Third conductive layer 16; Anode 16a; Pixel definition layer 17; Opening K4; First trace L1; Second trace L2; First sublayer L2a; Second sublayer L2b; Fourth conductive layer 18. Detailed Implementation

[0050] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0051] It should be noted that, in the description of this application, the orientations or positional relationships indicated by terms such as "upper," "lower," "front," "back," "left," "right," "inner," and "outer" are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0052] Please refer to Figure 1 An embodiment of this application provides an array substrate 10 comprising a substrate 11, a first conductive layer 12, a first insulating layer 13, and a second conductive layer 14, which are sequentially stacked. Specifically, the first conductive layer 12 is disposed on the substrate 11. The first insulating layer 13 covers the first conductive layer 12. The second conductive layer 14 is disposed on the first insulating layer 13.

[0053] The first conductive layer 12 includes a source 12a, a gate 12b, a drain 12c, and a first capacitor plate 12d spaced apart from the source 12a. The second conductive layer 14 includes an active layer 14a and a second capacitor plate 14b spaced apart from the active layer 14a. One side of the active layer 14a is connected to the drain 12c, and the other side of the active layer 14a is connected to the source 12a, thus forming a thin-film transistor (TFT). The active layer 14a overlaps with the gate 12b so that the gate 12b can be reused as a light-shielding layer. The first capacitor plate 12d and the second capacitor plate 14b overlap to form a capacitor C.

[0054] The array substrate 10 provided in this application embodiment simplifies the film structure and avoids the separation of electrodes into different layers, thereby reducing the film thickness of the array substrate 10. Furthermore, since the active layer 14a and the gate 12b are arranged in a co-layer configuration, and the active layer 14a and the second capacitor plate 14b are also co-layered, the active layer 14a and the second capacitor plate 14b are saved. Additionally, because the active layer 14a and the gate 12b overlap, the gate 12b is reused as a light-shielding layer, saving film layers and avoiding the need for a separate light-shielding layer that would occupy space on the array substrate 10.

[0055] In this embodiment, a first via K1 and a second via K2 are formed on the first insulating layer 13. The first via K1 exposes the drain 12c, and the second via K2 exposes the source 12a. The active layer 14a is connected to the drain 12c through the first via K1, and the active layer 14a is connected to the source 12a through the second via K2.

[0056] Understandably, vias connect the drain 12c to one side of the active layer 14a and the source 12a to the other side of the active layer 14a. A single process forms the first via K1 and the second via K2 on the first insulating layer 13 to achieve the connection between the source 12a and the active layer 14a, and between the drain 12c and the active layer 14a, which is a simple process.

[0057] In this embodiment, the array substrate 10 further includes a second insulating layer 15, a third conductive layer 16, and a pixel definition layer 17, which are sequentially stacked. Specifically, the second insulating layer 15 covers the second conductive layer 14. The third conductive layer 16 is disposed on the second insulating layer 15. The pixel definition layer 17 is disposed on the third conductive layer 16.

[0058] The second insulating layer 15 has a third via K3. The third conductive layer 16 includes an anode 16a. The third via K3 exposes the active layer 14a, allowing the anode 16a to be connected to the active layer 14a through the third via K3. The pixel definition layer 17 has an opening K4 that exposes the anode 16a.

[0059] Understandably, the second insulating layer 15 has a third via K3 exposing the active layer 14a, allowing the anode 16a to be connected to the active layer 14a through the third via K3. The pixel definition layer 17 has an opening K4 so that light emitted from the anode 16a can exit through the opening K4.

[0060] In this embodiment, the first conductive layer 12 further includes a first trace L1. The third conductive layer 16 further includes a second trace L2.

[0061] Understandably, since the first conductive layer 12 includes the first trace L1, the source 12a, drain 12c, gate 12b, first capacitor plate 12d, and the first trace L1 are all disposed in the same layer, further saving the film space occupied by separately disposing of the first trace L1. Furthermore, the source 12a, drain 12c, gate 12b, first capacitor plate 12d, and the first trace L1 can be formed using the same photomask, simplifying the process and saving photomask space. Similarly, since the third conductive layer 16 includes the second trace L2, the anode 16a and the second trace L2 are all disposed in the same layer, saving the film space occupied by separately disposing of the second trace L2. Furthermore, the anode 16a and the second trace L2 can be formed using the same photomask, simplifying the process and saving photomask space.

[0062] In this embodiment, the second insulating layer 15 includes a passivation layer 15a and a planarization layer 15b sequentially stacked on the second conductive layer 14. The third via K3 penetrates the planarization layer 15b and the passivation layer 15a, exposing the active layer 14a.

[0063] Understandably, the passivation layer 15a is disposed on the second conductive layer 14, covering the second conductive layer 14. This protects the surface of the second conductive layer 14 from oxidation. The planarization layer 15b is disposed to planarize the film layer. The third via K3 penetrates the planarization layer 15b and the passivation layer 15a, and a single photomask can be used to create an opening in both the planarization layer 15b and the passivation layer 15a, saving process steps.

[0064] Please refer to Figure 2 , Figure 2 This is a flowchart of a method for fabricating an array substrate 10 according to an embodiment of this application.

[0065] Figure. Accordingly, one embodiment of this application also provides a method for fabricating an array substrate 10, comprising the following five steps:

[0066] Step S1, provide a substrate 11.

[0067] Step S2: A first conductive layer 12 is formed on the substrate 11.

[0068] Step S3: Pattern the first conductive layer 12 using a first photomask to form spaced source electrodes.

[0069] 12a, drain 12c, gate 12b and first capacitor plate 12d.

[0070] Step S4: A first insulating layer 13 is formed on the first conductive layer 12.

[0071] Step S5: A second conductive layer 14 is formed on the first insulating layer 13.

[0072] Step S6: A second photomask is used to pattern the second conductive layer 14, forming an active layer 14a and a second capacitor plate 14b spaced apart from the active layer 14a. The second capacitor plate 14b and the first capacitor...

[0073] Electrode plates 12d are stacked to form a capacitor. One side of the active layer 14a is connected to the drain 12c, and the other side of the active layer 14a5 is connected to the source 12a, forming a thin-film transistor (TFT). The active layer 14a is stacked with the gate 12b, and the gate 12b can be reused as a light-shielding layer.

[0074] An embodiment of this application provides a method for fabricating an array substrate 10, wherein the source 12a, drain 12c, gate 12b, and first capacitor plate 12d are formed using the same first photomask, and the active layer 14a and the second capacitor...

[0075] The electrode 14b is formed using the same second photomask, which avoids the complicated steps of using multiple photomasks, reduces the number of photomasks to be made, and simplifies the process.

[0076] The fabrication method of the array substrate 10 in this embodiment will be described below.

[0077] Please refer to Figure 3 Step S1, provide a substrate 11.

[0078] Optionally, the substrate 11 can be a rigid substrate 11 or a flexible substrate 11. The material of the substrate 11 includes one of glass, sapphire, polyimide or silicon dioxide.

[0079] 5. Proceed to step S2.

[0080] Step S2: A first conductive layer 12 is formed on the substrate 11.

[0081] Specifically, a conductive material is deposited on the substrate 11 to form a first conductive layer 12.

[0082] Optionally, the material of the first conductive layer 12 may be selected from aluminum (Al), molybdenum (Mo), titanium (Ti), or copper (Cu), or the first conductive layer 12 may be formed using an alloy composed of the aforementioned metallic elements. It is understood that conductive layers made using the aforementioned metallic elements and their alloys have low resistivity and excellent conductivity.

[0083] Proceed to step S3.

[0084] Step S3: A first photomask is used to pattern the first conductive layer 12 to form spaced source 12a, drain 12c, gate 12b and first capacitor plate 12d.

[0085] Specifically, a first photomask is used to shield the first conductive layer 12, and then the first conductive layer 12 is exposed to form a preliminary pattern. Then, an etchant is used to etch the preliminary pattern to form the final spaced source 12a, drain 12c, gate 12b and first capacitor plate 12d.

[0086] Understandably, using a first photomask to pattern the source 12a, drain 12c, gate 12b and first capacitor plate 12d in one step greatly simplifies the process and saves photomasks.

[0087] Optionally, the source 12a, drain 12c, and gate 12b can have a single-layer structure or a stacked structure of two or more layers.

[0088] In this embodiment, the first photomask is a half-tone mask (HT).

[0089] By using a halftone photomask and adjusting the exposure rate, patterns for at least two target objects can be created. Compared to a photomask that can only form one pattern, a halftone photomask simplifies the patterning process and avoids the need for multiple photomask layers to pattern the first conductive layer 12.

[0090] In this embodiment, a first photomask is used to pattern the first conductive layer 12, and a first trace L1 is also formed.

[0091] Understandably, while the first photomask is used to pattern the source 12a, drain 12c, gate 12b and the first capacitor plate 12d, the first trace L1 is also formed, which further simplifies the process and saves photomasks.

[0092] Proceed to step S4.

[0093] Step S4: A first insulating layer 13 is formed on the first conductive layer 12.

[0094] Specifically, an insulating material is deposited on the first conductive layer 12 to form the first insulating layer 13.

[0095] Optionally, the material of the first insulating layer 13 may include at least one of silicon nitride, silicon oxide, silicon oxynitride, or titanium oxide.

[0096] Proceed to step S5.

[0097] Step S5: A second conductive layer 14 is formed on the first insulating layer 13.

[0098] Specifically, a conductive material is deposited on the first insulating layer 13 to form the second conductive layer 14.

[0099] Optionally, the second conductive layer 14 can be formed of an oxide semiconductor. Specifically, the oxide semiconductor can be one of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), or indium gallium oxide (IGO), but this application is not limited thereto.

[0100] In this embodiment, the second conductive layer 14 is formed of indium gallium zinc oxide. It is understood that the second conductive layer 14, made of an oxide semiconductor material, has high carrier mobility, resulting in high efficiency for the thin-film transistor (TFT) formed using it as the active layer 14a.

[0101] Proceed to step S6.

[0102] In step S6, a second photomask is used to pattern the second conductive layer 14 to form an active layer 14a and a second capacitor plate 14b spaced apart from the active layer 14a. The second capacitor plate 14b and the first capacitor plate 12d are overlapped to form a capacitor C. One side of the active layer 14a is connected to the drain 12c, and the other side of the active layer 14a is connected to the source 12a, forming a thin-film transistor (TFT). The active layer 14a is overlapped with the gate 12b, and the gate 12b can be reused as a light-shielding layer.

[0103] Specifically, a second photomask is used to shield the second conductive layer 14, followed by exposure treatment of the second conductive layer 14 to form a preliminary pattern. Then, an etching solution is used to etch the preliminary pattern to form an active layer 14a and a second capacitor plate 14b spaced apart from the active layer 14a. The formed second capacitor plate 14b and the first capacitor plate 12d are overlapped to form a capacitor C. The formed active layer 14a and the gate 12b are overlapped so that the gate 12b can be reused as a light-shielding layer.

[0104] Understandably, using a second photomask to pattern the active layer 14a and the second capacitor plate 14b in a single step simplifies the process and saves on photomasks. Furthermore, the active layer 14a and the second capacitor plate 14b are disposed on the same layer, simplifying the film structure and thus reducing the film thickness of the array substrate 10. Also, since the active layer 14a overlaps with the gate 12b, the gate 12b is reused as a light-shielding layer, saving on film layers and avoiding the need for a separate light-shielding layer that would occupy space on the array substrate 10.

[0105] In this embodiment, the second photomask is a half-tone mask (HT), for the same reason as the first photomask.

[0106] Please refer to Figure 4 Optionally, the fabrication method of the array substrate 10 in this embodiment further includes steps S7, S8, S9, and S10. Steps S7 to S10 follow step S6 in sequence.

[0107] Step S7: A second insulating layer 15 is formed on the second conductive layer 14.

[0108] Step S8: A third conductive layer 16 is formed on the second insulating layer 15.

[0109] Step S9: A pixel definition layer 17 is formed on the third conductive layer 16.

[0110] In step S10, a third photomask is used to pattern the third conductive layer 16 and the pixel definition layer 17 to form an anode 16a, which is connected to the active layer 14a.

[0111] Continue to complete the fabrication of the array substrate 10, and proceed from step S6 to step S7.

[0112] Step S7: A second insulating layer 15 is formed on the second conductive layer 14.

[0113] Specifically, an insulating material is deposited on the second conductive layer 14 to form the second insulating layer 15.

[0114] Optionally, step S7 may include the following steps:

[0115] Step S71: Deposit passivation layer material on the second conductive layer 14 to form passivation layer 15a.

[0116] Optionally, the material of the passivation layer 15a may include at least one of silicon nitride, silicon oxide, silicon oxynitride, or titanium oxide.

[0117] Step S72: Deposit planarization material on passivation layer 15a to form planarization layer 15b.

[0118] Optionally, the material of the planarization layer 15b can be epoxy resin, polyimide, polyvinyl alcohol, etc.

[0119] In step S73, the planarization layer 15b and the passivation layer 15a are patterned to form a third via K3, exposing the active layer 14a.

[0120] Then proceed to step S8.

[0121] Step S8: A third conductive layer 16 is formed on the second insulating layer 15.

[0122] Specifically, a conductive material is deposited on the second insulating layer 15 to form the third conductive layer 16.

[0123] Optionally, the third conductive layer 16 can be made of indium tin oxide (ITO) or other metallic materials such as silver (Ag) or aluminum (Al), and this application does not limit this.

[0124] Then proceed to step S9.

[0125] Step S9: A pixel definition layer 17 is formed on the third conductive layer 16.

[0126] Specifically, an organic material is coated or an inorganic material is deposited on the third conductive layer 16 to form the pixel definition layer 17.

[0127] Optionally, the material of the pixel definition layer 17 can be either inorganic or organic. Organic materials include polyimide, acrylic resin, etc., while inorganic materials include silicon carbide, silicon oxide, silicon nitride, etc.

[0128] Then proceed to step S10.

[0129] In step S10, a third photomask is used to pattern the third conductive layer 16 and the pixel definition layer 17 to form an anode 16a, which is connected to the active layer 14a.

[0130] Specifically, a third photomask is used to shield the third conductive layer 16 and the pixel definition layer 17. Then, the third conductive layer 16 and the pixel definition layer 17 are exposed to form a preliminary pattern. Next, an etching solution is used to etch the preliminary pattern, causing the third conductive layer 16 to form an anode 16a and the pixel definition layer 17 to form an opening K4, exposing the anode 16a. Since a third via K3 is formed on the second insulating layer 15, the anode 16a is connected to the active layer 14a through the third via K3.

[0131] Understandably, using a third photomask to pattern the opening K4 of the anode 16a and the pixel definition layer 17 at one time greatly simplifies the process and saves photomasks.

[0132] In this embodiment, the third photomask is a half-tone mask (HT), for the same reason as the first photomask.

[0133] In this embodiment, a third photomask is used to pattern the third conductive layer 16, and a second trace L2 is also formed.

[0134] Understandably, when the pattern of the anode 16a and the pixel definition layer 17 is formed in one step using a third photomask, the second trace L2 is also formed. The pixel definition layer 17 covers the second trace L2. This further simplifies the process flow, saves photomasks, and avoids the additional steps of depositing the film layer of the second trace L2 and etching to form the pattern of the second trace L2.

[0135] This completes the fabrication of the array substrate 10 provided in one embodiment of this application.

[0136] Please see Figure 5 Another embodiment of this application also provides an array substrate 10, which differs from the above embodiment in that the position of the second trace L2 is different.

[0137] In the above embodiments, the third conductive layer 16 further includes a second trace L2.

[0138] In this embodiment, the array substrate 10 includes a fourth conductive layer 18 disposed on the second conductive layer 14. The first conductive layer 12 also includes a first trace L1. The array substrate 10 also includes a second trace L2. The second trace L2 includes a first sublayer L2a and a second sublayer L2b stacked sequentially. The first sublayer L2a is formed by the second conductive layer 14. The second sublayer L2b is formed by the fourth conductive layer 18.

[0139] Optionally, the material of the fourth conductive layer 18 may be selected from aluminum (Al), molybdenum (Mo), titanium (Ti) or copper (Cu), or the fourth conductive layer 18 may be formed using an alloy composed of the aforementioned metal elements.

[0140] It should be noted that the conductive layer made using the aforementioned metallic elements and their alloys has low resistivity and excellent conductivity. The second trace L2 includes a second sub-layer L2b formed by the fourth conductive layer 18, which can reduce impedance and improve conductivity.

[0141] Optionally, the width of the second sublayer L2b is equal to the width of the first sublayer L2a, or the width of the second sublayer L2b is less than the width of the first sublayer L2a. This avoids undercutting between the second sublayer L2b and the first sublayer L2a, which could result in uneven or incomplete coverage of subsequent film layers.

[0142] Understandably, in this embodiment, the second trace L2 is formed by the second conductive layer 14, rather than by the third conductive layer 16. Since the third conductive layer 16 also includes an anode 16a, if the second trace L2 were formed by the third conductive layer 16, it would affect the opening K4 area of ​​the anode 16a, thereby affecting the opening K4 ratio of the light-emitting device. Forming the second trace L2 by the second conductive layer 14 avoids occupying the third conductive layer 16 used to form the anode 16a, thus improving the opening K4 ratio of the light-emitting device.

[0143] Please refer to Figure 6 Correspondingly, another embodiment of this application also provides a method for manufacturing an array substrate 10. The difference between this embodiment and the method for manufacturing an array substrate 10 provided in the above embodiment is that the manufacturing steps of the second trace L2 are different.

[0144] Specifically, in this embodiment, step S1' proceeds sequentially to steps S2', S3', S4' and S5', and after step S5', it proceeds to step S51'.

[0145] Please refer to Figure 7 and Figure 8 In this embodiment, step S51' involves forming a fourth conductive layer 18 on the second conductive layer 14.

[0146] Specifically, a conductive material is deposited on the second conductive layer 14 to form the fourth conductive layer 18.

[0147] Optionally, the material of the fourth conductive layer 18 may be selected from aluminum (Al), molybdenum (Mo), titanium (Ti) or copper (Cu), or the fourth conductive layer 18 may be formed using an alloy composed of the aforementioned metal elements.

[0148] Understandably, conductive layers made using the aforementioned metallic elements and their alloys have low resistivity and excellent conductivity. The second trace L2 includes a second sub-layer L2b formed by the fourth conductive layer 18, which can reduce impedance and improve conductivity.

[0149] Then step S51' proceeds to step S6'.

[0150] In step S6', a second photomask is used to pattern the fourth conductive layer 18 and the second conductive layer 14 to form an active layer 14a, a second capacitor plate 14b, and a second trace L2. The second trace L2 includes a first sub-layer L2a formed on the second conductive layer 14 and a second sub-layer L2b formed on the fourth conductive layer 18, which are stacked together. The second capacitor plate 14b and the first capacitor plate 12d are overlapped to form a capacitor C. One side of the active layer 14a is connected to the drain 12c, and the other side of the active layer 14a is connected to the source 12a, forming a thin-film transistor (TFT). The active layer 14a is overlapped with the gate 12b, and the gate 12b can be reused as a light-shielding layer.

[0151] Specifically, a second photomask is used to shield the fourth conductive layer 18 and the second conductive layer 14. The fourth conductive layer 18 and the second conductive layer 14 are then exposed to form a preliminary pattern. An etchant is then used to etch the preliminary pattern to form an active layer 14a, a second capacitor plate 14b, and a second trace L2. The formed second capacitor plate 14b and the first capacitor plate 12d are overlapped to form a capacitor C. The formed active layer 14a and the gate 12b are overlapped so that the gate 12b can be reused as a light-shielding layer. The second trace L2 includes a first sub-layer L2a formed on the second conductive layer 14 and a second sub-layer L2b formed on the fourth conductive layer 18, which are stacked together.

[0152] Understandably, using a second photomask to pattern the active layer 14a, the second capacitor plate 14b, and the second trace L2 in one step can simplify the process and save on photomasks.

[0153] Then step S6' proceeds sequentially to steps S7', S8', S9', and S10'.

[0154] In step S10', a third photomask is used to pattern the third conductive layer 16 and the pixel definition layer 17 to form an anode 16a, which is connected to the active layer 14a.

[0155] Specifically, a third photomask is used to shield the third conductive layer 16 and the pixel definition layer 17. Then, the third conductive layer 16 and the pixel definition layer 17 are exposed to form a preliminary pattern. Next, an etching solution is used to etch the preliminary pattern, causing the third conductive layer 16 to form an anode 16a and the pixel definition layer 17 to form an opening K4, exposing the anode 16a. Since a third via K3 is formed on the second insulating layer 15, the anode 16a is connected to the active layer 14a through the third via K3.

[0156] Understandably, using a third photomask to pattern the anode 16a and the opening K4 of the pixel definition layer 17 in one step greatly simplifies the process and saves photomasks. Compared with the above embodiment, in this embodiment, the second trace L2 is formed by the second conductive layer 14 instead of the third conductive layer 16. Forming the second trace L2 by the second conductive layer 14 avoids occupying the third conductive layer 16 used to form the anode 16a, thus improving the opening K4 ratio of the light-emitting device.

[0157] The other steps are the same as in the above embodiments.

[0158] The above provides a detailed description of an array substrate and its fabrication method provided in this application.

[0159] The array substrate provided in this application includes a substrate, a first conductive layer, a first insulating layer, and a second conductive layer stacked sequentially. The first conductive layer includes a source electrode, a gate electrode, a drain electrode, and a first capacitor electrode spaced apart from the source electrode. The second conductive layer includes an active layer and a second capacitor electrode spaced apart from the active layer. One side of the active layer is connected to the drain electrode, and the other side of the active layer is connected to the source electrode to form a thin-film transistor. The active layer overlaps with the gate electrode so that the gate electrode can be reused as a light-shielding layer. The first capacitor electrode and the second capacitor electrode overlap to form a capacitor. This application also provides a method for fabricating the array substrate described above.

[0160] The array substrate and its fabrication method provided in this application simplify the film structure and avoid the separation of electrodes into different layers, thereby reducing the film thickness of the array substrate, because the source, drain, gate, and first capacitor plate are arranged in the same layer, and the active layer and second capacitor plate are arranged in the same layer. Furthermore, since the active layer and gate are overlapped, the gate is reused as a light-shielding layer, saving film layers. Moreover, the source, drain, gate, and first capacitor plate are formed using the same first photomask, and the active layer and second capacitor plate are formed using the same second photomask, avoiding the complex steps of using multiple photomasks, reducing the number of photomasks required, and simplifying the process.

[0161] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. An array substrate, characterized in that, include Substrate; A first conductive layer is disposed on the substrate; the first conductive layer includes a source electrode, a gate electrode, and a drain electrode disposed at intervals, and the first conductive layer also includes a first trace. A first insulating layer is disposed covering the first conductive layer; A second conductive layer is disposed on the first insulating layer; the second conductive layer includes an active layer, which overlaps with the gate, and the gate is multiplexed as a light-shielding layer; one side of the active layer is connected to the drain, and the other side of the active layer is connected to the source, thereby forming a thin-film transistor; The first conductive layer further includes a first capacitor plate spaced apart from the source electrode, and the second conductive layer further includes a second capacitor plate spaced apart from the active layer. The first capacitor plate and the second capacitor plate are overlapped to form a capacitor. The second capacitor plate and the active layer are formed by a single patterning process. The second capacitor plate and the active layer are disposed in the same layer and are made of the same material. A second insulating layer is provided, which covers the second conductive layer; the second insulating layer has a third via, which exposes the active layer. A third conductive layer is disposed on the second insulating layer, and the third conductive layer includes an anode; the anode is connected to the active layer through the third via; the anode is in direct contact with the active layer. The array substrate further includes a second trace, which includes a first sub-layer and a second sub-layer stacked sequentially; the first sub-layer is formed by the second conductive layer. The array substrate further includes a fourth conductive layer, which is disposed on the second conductive layer. The second sublayer is formed by the fourth conductive layer. The material of the fourth conductive layer is selected from aluminum, molybdenum, titanium, or copper, or an alloy thereof. The width of the second sub-layer is equal to the width of the first sub-layer, or the width of the second sub-layer is less than the width of the first sub-layer.

2. The array substrate according to claim 1, characterized in that, The first insulating layer has a first via and a second via; the first via exposes the drain electrode, the second via exposes the source electrode, the active layer is connected to the drain electrode through the first via, and the active layer is connected to the source electrode through the second via.

3. The array substrate according to claim 1, characterized in that, The array substrate also includes A pixel definition layer is disposed on the third conductive layer, and an opening is formed on the pixel definition layer to expose the anode.

4. The array substrate according to claim 1, characterized in that, The second insulating layer includes a passivation layer and a planarization layer stacked sequentially on the second conductive layer. The third via penetrates the planarization layer and the passivation layer, exposing the active layer.

5. A method for fabricating an array substrate, characterized in that, Includes the following steps: Provide a substrate; A first conductive layer is formed on the substrate; The first conductive layer is patterned using a first photomask to form spaced source, drain, gate, first trace and first capacitor plate; A first insulating layer is formed on the first conductive layer; A second conductive layer is formed on the first insulating layer; A fourth conductive layer is formed on the second conductive layer; A second photomask is used to pattern the fourth conductive layer and the second conductive layer to form a second trace, an active layer, and a second capacitor plate spaced apart from the active layer. The second capacitor plate and the first capacitor plate are overlapped to form a capacitor. The active layer is overlapped with the gate, and the gate is multiplexed as a light-shielding layer. One side of the active layer is connected to the drain, and the other side of the active layer is connected to the source, forming a thin-film transistor. The second trace includes a first sub-layer formed on the second conductive layer and a second sub-layer formed on the fourth conductive layer, wherein the material of the fourth conductive layer is selected from aluminum, molybdenum, titanium, or copper, or an alloy thereof. The width of the second sub-layer is equal to the width of the first sub-layer, or the width of the second sub-layer is less than the width of the first sub-layer. A second insulating layer is formed on the second conductive layer; a third via is formed in the second insulating layer, and the third via exposes the active layer; A third conductive layer is formed on the second insulating layer; the third conductive layer includes an anode; the anode is connected to the active layer through the third via; The anode is in direct contact with the active layer.

6. The method for fabricating an array substrate according to claim 5, characterized in that, After the step of forming the third conductive layer on the second insulating layer, the method further includes the following steps: A pixel definition layer is formed on the third conductive layer; A third photomask is used to pattern the third conductive layer and the pixel definition layer to form the anode, which is connected to the active layer.

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