Semiconductor structure, memory device, and method of fabricating a semiconductor structure

Abstract

The application provides a semiconductor structure, a storage device and a semiconductor structure preparation method. The semiconductor structure comprises: a substrate, the substrate comprising an active region and a channel, and the channel being located on the surface of the active region; an insulation structure comprising isolation structures located on both sides of the active region and a gate insulation layer located on the surface of the channel, the isolation structures being connected with the gate insulation layer; a gate located on the surface of the insulation structure, the gate extending along the first direction; and a drift region formed between the channel and the isolation structure and located on the surface of the active region, so as to adjust the voltage resistance of the semiconductor structure. The technical scheme has the advantages that by adding the drift region with the same doping type as the channel on both sides of the channel, the doping concentration of the edge region of the channel is increased, the edge of the side channel is prevented from being opened in advance, the voltage resistance performance of the device is increased, and the problem of electric leakage is solved.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a semiconductor structure, a storage device, and a method for fabricating the semiconductor structure. Background Technology

[0002] High-voltage power integrated circuits often utilize the high analog accuracy of bipolar transistors (Bipolar transistors), the high integration density of complementary metal-oxide-semiconductor (CMOS), and the high power or voltage characteristics of double-diffused MOSFETs (DMOS) to monolithically integrate Bipolar analog circuits, CMOS logic circuits, CMOS analog circuits, and DMOS high-voltage power devices (BCD process). Lateral high-voltage devices, because their drain, gate, and source are all on the chip surface, are easily integrated with low-voltage signal circuits through internal interconnections and are widely used in high-voltage power integrated circuits. The BCD process not only combines the advantages of high transconductance and strong load drive capability of bipolar devices with the high integration density and low power consumption of CMOS, but also integrates high-speed switching DMOS power devices. Because DMOS simultaneously possesses high speed and high voltage withstand characteristics, power management chips manufactured using the BCD process can operate at high voltages and high frequencies, making it an ideal process for manufacturing high-performance switching power supply chips. Monolithic integrated chips manufactured using the BCD process can also improve system performance, save on circuit packaging costs, and have better reliability.

[0003] Please see Figures 1-2 ,in, Figure 1 This is a schematic diagram of a semiconductor structure according to an embodiment of the BCD process. Figure 2 For along Figure 1 A cross-sectional view along the AA' direction. (See attached image.) Figures 1-2 As shown, the semiconductor structure includes a substrate 10, an active region 11, a channel 12, a gate 13, and an insulating structure 14. The active region 11 is located within the substrate 10, and the channel 12 is located on the surface of the active region 11. The insulating structure 14 further includes an isolation structure 141 and a gate insulating layer 142, and the active region 11 and the trap ion-implanted active region 12 are encapsulated within the insulating structure 14. The gate 13 is located on the surface of the insulating structure 14 and forms a cross with the active region 11 and the channel 12. Figure 2As shown, due to inherent process limitations, at the junction of the isolation structure 141 and the gate insulating layer 142, the ends of the isolation structure 141 (indicated by arrow 19) are generally thinner than the central region. This, coupled with polysilicon deposition pits, causes the channel to turn on prematurely, effectively creating a parasitic low-threshold voltage field-effect transistor (MOS transistor). In N-type MOS transistors, the P-type well elements are typically B / BF2, which diffuse into the adjacent isolation structure 141 due to concentration differences, further increasing the likelihood of premature channel edge turn-on and leakage.

[0004] Therefore, improving the leakage current at both ends of the channel in the BCD process is a problem that needs to be solved. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to improve the leakage current problem at both ends of the channel in the BCD process, and to provide a semiconductor structure, a memory device, and a method for fabricating the semiconductor structure.

[0006] To address the aforementioned problems, the present invention provides a semiconductor structure comprising: a substrate, the substrate including an active region and a channel, wherein the channel is located on the surface of the active region; an insulating structure including isolation structures located on both sides of the active region and a gate insulating layer located on the surface of the channel, wherein the isolation structures are connected to the gate insulating layer; a gate located on the surface of the insulating structure and extending along a first direction; and further comprising a drift region formed between the channel and the isolation structure and located on the surface of the active region to adjust the withstand voltage of the semiconductor structure.

[0007] In some embodiments, the doping type of the drift region is the same as the doping type of the channel.

[0008] In some embodiments, the width of the drift region on the surface of the active region is 0.05 μm to 1 μm.

[0009] In some embodiments, the active region extends along a second direction; wherein the first direction is perpendicular to or forms an angle with the second direction.

[0010] In some embodiments, the semiconductor structure further includes a source and a drain located at both ends of the substrate along a second direction; wherein the first direction is perpendicular to or forms an angle with the second direction.

[0011] To address the aforementioned problems, the present invention provides a storage device comprising the semiconductor structure described herein.

[0012] To address the aforementioned problems, the present invention provides a method for fabricating a semiconductor structure, comprising the following steps: providing an initial substrate; forming an isolation structure within the initial substrate to define an initial active region; forming drift regions at both ends of the initial active region; forming a channel within the initial active region, wherein the drift regions are located between the channel and the isolation structure; forming a gate insulating layer on the surface of the channel, wherein the gate insulating layer is connected to the isolation structure to form an insulating structure; and forming a gate electrode on the surface of the insulating structure.

[0013] In some embodiments, the step of forming drift regions at both ends of the initial active region further includes: performing type-1 ion doping at both ends of the initial active region to form the drift regions.

[0014] In some embodiments, the step of forming a channel in the initial active region further includes: performing type-1 ion doping in the initial active region to form the channel.

[0015] In some embodiments, the method further includes a step of performing type II ion doping on both sides of the channel along the second direction to form a source and a drain.

[0016] The above technical solution increases the doping concentration in the channel edge region by adding drift regions with the same doping type as the channel on both sides, thereby preventing premature turn-on at the channel edge, increasing the device's withstand voltage performance, and solving the leakage problem.

[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 The diagram shown is a schematic representation of a semiconductor structure in the BCD process.

[0020] Figure 2 The following is along Figure 1 Cross-sectional view along the AA' direction.

[0021] Figure 3The diagram shown is a schematic diagram of an embodiment of the semiconductor structure described in this invention.

[0022] Figure 4 The following is along Figure 3 Cross-sectional view along the BB' direction.

[0023] Figure 5 The diagram shown is an architectural schematic of an embodiment of the storage device described in this invention.

[0024] Figure 6 The diagram shown is a flowchart of one embodiment of the semiconductor structure fabrication method of the present invention.

[0025] Figures 7A to 7D The diagram shown is a process flow chart of an embodiment of the semiconductor structure fabrication method of the present invention. Detailed Implementation

[0026] The technical solutions in the embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] Please see Figures 3-4 ,in, Figure 3 The diagram shown is a schematic representation of an embodiment of the semiconductor structure described in this invention. Figure 4 The following is along Figure 3 A cross-sectional view along the BB' direction. (See attached image.) Figures 3-4 As shown, the semiconductor structure includes a substrate 30, an insulating structure 31, a gate 32, and a drift region 34. The substrate 30 includes an active region 301 and a channel 302, with the channel 302 located on the surface of the active region 301. The insulating structure 31 includes isolation structures 311 located on both sides of the active region 301 and a gate insulating layer 312 located on the surface of the channel 302, with the isolation structures 311 and the gate insulating layer 312 in contact. The gate 32 is located on the surface of the insulating structure 31. The drift region 34 is formed between the channel 302 and the isolation structure 311 to adjust the breakdown voltage of the semiconductor structure.

[0028] In some embodiments, the doping type of the drift region 34 is the same as that of the channel 302. As one embodiment, the active region 301 may be N-type doped, and the drift region 34 and the channel 302 may be P-type doped. In other embodiments, the active region 301 may also be P-type doped, and the drift region 34 and the channel 302 may also be N-type doped.

[0029] The above technical solution increases the doping concentration of the edge region of the channel 302 by adding the drift region 34 with the same doping type as the channel 302 at both ends of the channel 302, thereby preventing premature turn-on at the edge of the channel 302, increasing the withstand voltage performance of the device, and solving the leakage problem.

[0030] In some embodiments, the width W1 of the drift region 34 on the surface of the active region 301 is 0.05 μm to 1 μm. By providing the drift region 34 with a width W1 of 0.05 μm to 1 μm at both ends of the channel 302 along the first direction D1, the doping concentration within this range can be increased, thereby mitigating the phenomenon of premature turn-on of the semiconductor structure.

[0031] In this embodiment, the gate 32 extends along the first direction D1, the active region 301 extends along the second direction D2, and the first direction D1 is perpendicular to the second direction D2. In other embodiments, the first direction D1 and the second direction D2 may also form an angle.

[0032] In some embodiments, the semiconductor structure further includes a source (not shown) and a drain (not shown), located at opposite ends of the substrate 30 along the second direction D2. Specifically, the source and drain are located in the active region 301 of the substrate 30, and their doping types differ from those of the channel 302. As one embodiment, the source and drain may be N-type doped, and the channel 302 may be P-type doped. In other embodiments, the source and drain may also be P-type doped, and the channel 302 may be N-type doped.

[0033] Based on the same inventive concept, the present invention also provides a storage device.

[0034] Please see Figure 5 This is a schematic diagram of the architecture of an embodiment of the storage device described in this invention. The storage device 100 in this embodiment includes: a semiconductor structure 101; wherein, the semiconductor structure 101 adopts the architecture of this invention. Figures 3-4 The semiconductor structure shown is described in detail above and will not be repeated here.

[0035] In some embodiments, the storage device 100 may be a dynamic random access memory (DRAM), a double data rate (DDR) synchronous dynamic random access memory (SDRAM), a low power double data rate 4 (LPDDR4) SDRAM, or a Rambus dynamic random access memory (RDRAM).

[0036] The above technical solution increases the doping concentration in the channel edge region by adding drift regions with the same doping type as the channel on both sides, thereby preventing premature turn-on at the channel edge, increasing the device's withstand voltage performance, and solving the leakage problem.

[0037] Figure 6 The diagram shows a flowchart of an embodiment of the semiconductor structure fabrication method of the present invention, including the following steps: Step S61, providing an initial substrate; Step S62, forming an isolation structure within the initial substrate to define an initial active region; Step S63, forming drift regions at both ends of the initial active region; Step S64, forming a channel within the initial active region, wherein the drift region is located between the channel and the isolation structure; Step S65, forming a gate insulating layer on the surface of the channel, wherein the gate insulating layer is connected to the isolation structure to form an insulating structure; Step S66, forming a gate electrode on the surface of the insulating structure.

[0038] Figures 7A to 7D The diagram shown is a process flow chart of an embodiment of the semiconductor structure fabrication method of the present invention.

[0039] Please see Figure 7A And in step S61, an initial substrate 70 is provided. In an embodiment, the initial substrate 70 is single-crystal silicon. As an embodiment, the doping type of the initial substrate 70 can be N-type. In other embodiments, the doping type of the initial substrate 70 can also be P-type.

[0040] Please see Figure 7B And in step S62, an isolation structure 311 is formed within the initial substrate 70 to define an initial active region 71. The material of the isolation structure 311 may be silicon nitride, silicon oxycarbide, or silicon oxide. In some embodiments, the method for forming the isolation structure 311 includes, but is not limited to, thermal oxidation of an insulating material, chemical vapor deposition, plasma chemical vapor deposition, or atomic layer deposition performed after etching within the etched groove. The initial substrate 70 defined by the isolation structure 311 serves as the initial active region 71.

[0041] Please see Figure 7CAnd in step S63, drift regions 34 are formed at both ends of the initial active region 71, partially overlapping with the initial active region 71. In some embodiments, the step of forming drift regions 34 on both sides of the initial active region 71 further includes the following step: performing first-type ion doping at both ends of the initial active region 71 to form the drift regions 34. Specifically, a first mask may be formed in the portion corresponding to the initial active region 71, and the initial substrate 70 may be ion-doped using the first mask as a shield, thereby forming drift regions 34 at both ends of the initial active region 71 and on the side of the isolation structure 311 away from the initial active region 71. In this embodiment, the first-type ion doping is P-type ion doping.

[0042] Please see Figure 7D And step S64, in the initial active region 71 (shown in...) Figure 7C A channel 302 is formed within the initial active region 71 (shown in the diagram). The drift region 34 is located between the channel 302 and the isolation structure 311. Specifically, in the initial active region 71 (shown in the diagram), a channel 302 is formed within the initial active region 71 (shown in the diagram). Figure 7C The channel 302 is formed by partial well region doping within the channel, and the undoped region serves as the active region 301.

[0043] In some embodiments, the initial active region 71 (shown in...) Figure 7C The step of forming channel 302 within the initial active region 71 (shown in the diagram) further includes the following steps: Figure 7C The channel 302 is formed by performing type I ion doping within the channel 302. In this embodiment, the type I ion doping is P-type ion doping. By adding drift regions 34 with the same doping type as the channel 302 at both ends of the channel 302, the doping concentration at the edge region of the channel 302 is increased, preventing premature turn-on at the edge of the channel 302, thereby increasing the device's withstand voltage performance and solving the leakage problem.

[0044] In some embodiments, the width W1 of the drift region 34 on the surface of the active region 301 is 0.05 μm to 1 μm. By providing the drift region 34 with a width W1 of 0.05 μm to 1 μm at both ends of the channel 302 along the first direction D1, the doping concentration within this range can be increased, thereby mitigating the phenomenon of premature turn-on of the semiconductor structure.

[0045] Please see Figure 4In steps S65 and S66, a gate insulating layer 312 is formed on the surface of the channel, and the gate insulating layer 312 is connected to the isolation structure 311 to form an insulating structure 31; a gate is formed on the surface of the insulating structure 31. The gate insulating layer 312 may be a silicon nitride layer, a silicon carbide layer, or a silicon oxide layer. In some embodiments, the method for forming the gate insulating layer 312 includes, but is not limited to, thermal oxidation, chemical vapor deposition, plasma chemical vapor deposition, and atomic layer deposition. In some embodiments, polysilicon is deposited on the surface of the insulating structure 31 to form a gate 32. In some embodiments, the gate 32 extends along the first direction D1, the active region 301 extends along the second direction D2, and the first direction D1 is perpendicular to the second direction D2. In other embodiments, the first direction D1 and the second direction D2 may also form an angle.

[0046] After completing the above steps, you will get the following: Figure 4 The semiconductor structure shown.

[0047] In some embodiments, the method further includes a step of performing second-type ion doping on both sides of the active region to form a source and a drain (not shown). In this embodiment, the second-type ion doping is N-type ion doping.

[0048] The above technical solution increases the doping concentration of the edge region of the channel 302 by adding the drift region 34 with the same doping type as the channel 302 at both ends of the channel 302, thereby preventing premature turn-on at the edge of the channel 302, increasing the withstand voltage performance of the device, and solving the leakage problem.

[0049] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0050] Generally, terms can be understood at least partially from their usage in context. For example, the term "one or more," as used herein, depends at least partially on the context and can be used to describe any feature, structure, or characteristic in a singular sense, or in a plural sense, to describe a combination of features, structures, or characteristics. Similarly, terms such as "a," "a," or "the" can also be understood, at least partially on the context, to express either a singular or a plural usage. Furthermore, the term "based on" can be understood not necessarily to express an exclusive set of factors, but rather, alternatively, also at least partially on the context, to allow for the presence of other factors that are not necessarily explicitly described.

[0051] It should be noted that the terms "comprising" and "having," and their variations, used in this invention document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context. It should be understood that such data used interchangeably where appropriate. Furthermore, embodiments and features within embodiments of this invention can be combined with each other unless otherwise specified. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar or identical parts between embodiments can be referred to interchangeably.

[0052] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A semiconductor structure, comprising: A substrate, the substrate including an active region and a channel, wherein the channel is located on the surface of the active region; An insulating structure includes isolation structures located on both sides of the active region and a gate insulating layer located on the surface of the channel, wherein the isolation structures are in contact with the gate insulating layer; A gate is located on the surface of the insulating structure, and the gate extends along a first direction; The source and drain are located at opposite ends of the active region of the substrate along a second direction, wherein the first direction is perpendicular to the second direction. The invention is characterized by further including a drift region disposed on both sides of the channel along a first direction, perpendicular to the channel current direction between the source and drain, and located between the channel and the isolation structure, and on the surface of the active region. The doping type of the drift region is the same as that of the channel, thereby increasing the doping concentration of the edge region of the channel along the channel current direction between the source and drain, preventing premature turn-on at the edge of the channel, adjusting the withstand voltage of the semiconductor structure, and solving the leakage problem.

2. The semiconductor structure according to claim 1, characterized in that, The width of the drift region on the surface of the active region is 0.05 μm to 1 μm.

3. A storage device, characterized in that, Includes the semiconductor structure described in any one of claims 1 to 2.

4. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: Provide an initial substrate; An isolation structure is formed within the initial substrate to define the initial active region; A drift region is formed at both ends of the initial active region. The drift region is disposed at both ends of the channel along a first direction, perpendicular to the channel current direction between the subsequently formed source and drain. A channel is formed within the initial active region, and the drift region is located between the channel and the isolation structure. The doping type of the drift region is the same as that of the channel. The doping concentration of the edge region of the channel along the channel current direction between the source and drain is increased to prevent premature turn-on at the edge of the channel, thereby adjusting the breakdown voltage of the semiconductor structure and solving the leakage problem. A gate insulating layer is formed on the surface of the channel, and the gate insulating layer is connected to the isolation structure to form an insulating structure; A gate is formed on the surface of the insulating structure, the gate extends along a first direction, and the active region extends along a second direction, the first direction being perpendicular to the second direction; Type II ion doping is performed on both sides of the channel along the second direction to form the source and drain.

5. The method according to claim 4, characterized in that, The step of forming drift regions at both ends of the initial active region further includes: performing type-1 ion doping at both ends of the initial active region to form the drift regions.

6. The method according to claim 4, characterized in that, The step of forming a channel in the initial active region further includes: performing type-1 ion doping in the initial active region to form the channel.

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