A charge pump circuit that improves dynamic current mismatch

Abstract

The present application belongs to the technical field of integrated circuits, and relates to a phase-locked frequency source in a wireless communication system, and specifically provides a charge pump circuit for improving dynamic current mismatch, which is used to improve the dynamic current mismatch problem of the charge pump circuit, so as to realize the low-stray performance of the phase-locked frequency source. The present application comprises: a charge pump main circuit and a control signal generation circuit, which provides a short-time discharge path for the discharge intermediate stage current mirror branch when the discharge switch is opened, shortens the opening time of the discharge, and improves the mismatch of the discharge and charge start-up time; when the charge switch and the discharge switch are closed, a short-time low-impedance path is provided for the gate end of the NMOS tube and the PMOS tube connected to the output end to discharge or charge, so as to accelerate the closing speed of the charge and discharge; in summary, the present application improves the dynamic current mismatch problem through the fast charge and discharge path, improves the linearity of the charge pump circuit, and realizes the low-stray performance of the phase-locked loop.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology and relates to phase-locked frequency sources in wireless communication systems. Specifically, it provides a charge pump circuit for improving dynamic current mismatch in phase-locked frequency sources. Background Technology

[0002] Phase-locked loop (PLL) frequency sources are widely used in wireless communication systems due to their frequency uniformity and phase alignment capabilities, including long-distance signal modulation and demodulation, and providing stable high-frequency clock signals. As the core module of the digital-to-analog conversion in a PLL, the dynamic current mismatch in the charge pump circuit generates periodic voltage ripple, thus deteriorating the PLL's output spurious performance. However, with the increasing demands of communication systems, the output spurious requirements of the PLL used to provide clock signals are becoming increasingly stringent, and the design of low-spurious PLLs is receiving more attention. Therefore, to achieve low-spurious performance in a PLL, it is necessary to improve the dynamic current mismatch of the charge pump circuit to meet higher performance requirements. Summary of the Invention

[0003] The purpose of this invention is to provide a charge pump circuit that improves dynamic current mismatch, thereby improving the dynamic current mismatch problem of the charge pump circuit and achieving low spurious performance of the phase-locked loop frequency source. This invention improves the dynamic current mismatch problem through a fast charge and discharge path, improves the linearity of the charge pump circuit, and achieves low spurious performance of the phase-locked loop.

[0004] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0005] A charge pump circuit for improving dynamic current mismatch includes: a charge pump main circuit and a control signal generation circuit; wherein the charge pump main circuit and the control signal generation circuit are connected through a discharge switch signal DN terminal, a discharge switch complementary signal DN terminal, a charge switch signal UP terminal, a charge switch complementary signal UP terminal, a discharge start acceleration signal DNP terminal, a discharge start acceleration complementary signal DNP terminal, a discharge turn-off acceleration signal DNC terminal, and a charge turn-off acceleration signal UPC terminal.

[0006] Furthermore, the main circuit of the charge pump includes: NMOS transistors MN1-MN10, PMOS transistors MP1-MP7, current source I1, capacitors C1-C3, and transmission gate TG1; wherein:

[0007] One end of current source I1 is connected to VDD, and the other end is connected to the gate and drain of NMOS transistor MN1. The gates of NMOS transistors MN1, MN2, and MN3 are connected, and the source terminals of NMOS transistors MN1, MN2, and MN3 are connected and then connected to GND.

[0008] The source terminals of NMOS transistors MN4 and MN5 are connected to the drain terminal of NMOS transistor MN2. The gate terminal of NMOS transistor MN4 is connected to the DN terminal and the drain terminal is connected to the drain terminal of PMOS transistor MP1. The gate terminal of NMOS transistor MN5 is connected to the DN terminal and the drain terminal is connected to the drain terminal of PMOS transistor MP2. Capacitor C2 is connected across the drain terminal of NMOS transistor MN2 and GND.

[0009] The source terminals of NMOS transistors MN6 and MN7 are connected to the drain terminal of NMOS transistor MN3. The gate terminal of NMOS transistor MN6 is connected to the UP terminal and the drain terminal is connected to the drain terminal of PMOS transistor MP5. The gate terminal of NMOS transistor MN7 is connected to the UP terminal and the drain terminal is connected to the drain terminal of PMOS transistor MP6. Capacitor C3 is connected across the drain terminal of NMOS transistor MN3 and GND.

[0010] The gate and drain of PMOS transistor MP1 are connected, and its source is connected to VDD. The gate and drain of PMOS transistor MP2 are connected, and its source is connected to VDD. The gate of PMOS transistor MP3 is connected to the gate of PMOS transistor MP2 and leads to node VP1. The source of PMOS transistor MP3 is connected to VDD. The drain of PMOS transistor MP3 is connected to the drain and gate of NMOS transistor MN8. The source of NMOS transistor MN8 is connected to GND. The gate of NMOS transistor MN9 is connected to the gate of NMOS transistor MN8 and leads to node VN1. The source of NMOS transistor MN9 is connected to GND, and its drain is connected to the OUT terminal. The drain of NMOS transistor MN10 is connected to node VN1, its source is connected to GND, and its gate is connected to the DNC terminal.

[0011] Capacitor C1 is connected across the drain of PMOS transistor MP1 and GND. The two output terminals of transmission gate TG1 are connected to the drain of PMOS transistor MP1 and node VP1, respectively. The control terminal of transmission gate TG1 is connected to the DNP terminal and the DNP terminal, respectively.

[0012] The gate and drain of PMOS transistor MP5 are connected, and the source is connected to VDD. The gate and drain of PMOS transistor MP6 are connected, and the source is connected to VDD. The gate of PMOS transistor MP4 is connected to the gate of PMOS transistor MP5 and leads out to node VP2. The source of PMOS transistor MP4 is connected to VDD, and the drain is connected to OUT. PMOS transistors MP5 and MP4 form a charging output current mirror. The drain of PMOS transistor MP7 is connected to node VP2, the source is connected to GND, and the gate is connected to UPC.

[0013] Furthermore, the control signal generation circuit includes: inverters INV1 to INV3, buffers B1 to B3, NOR gate NOR1, NAND gate NAND1, OR gate OR1, and capacitor C4; wherein:

[0014] The inputs of inverter INV1, buffer B1, buffer B2, one input of NOR1, and one input of NAND1 are all connected to the DN terminal. The output of inverter INV1 is connected to the DN terminal. The output of buffer B1 is connected to the other input of NOR1. The output of NOR1 is connected to the DNC terminal. The output of buffer B2 is connected to the other input of NAND1. The output of NAND1 and the input of inverter INV1 are all connected to the DNP terminal. The output of inverter INV2 is connected to the DNP terminal.

[0015] The inputs of inverter INV3, buffer B3, and one input of OR gate OR1 are all connected to the UP terminal. The output of inverter INV3 is connected to the UP terminal. The output of buffer B3 is connected to the other input of OR gate OR1. The output of OR gate OR1 is connected to the UPC terminal. Capacitor C4 is connected across the UP terminal and GND.

[0016] Based on the above technical solution, the beneficial effects of the present invention are as follows:

[0017] This invention provides a charge pump circuit that improves dynamic current mismatch. It uses identical NMOS transistors as the charging and discharging switches for the charge pump, avoiding current mismatch caused by differences in switching devices during charging and discharging. Furthermore, it employs a transmission gate connected to the drain terminals of two complementary discharge switches. When the transmission gate is on, an additional discharge path is formed, increasing the discharge speed of the corresponding voltage node in the discharge branch and shortening the time difference between the on-time of the charge pump circuit during charging and discharging, thus reducing overall dynamic mismatch. Simultaneously, a switching transistor structure connecting the gate terminal of the output current source transistor to the VDD / GND terminal is used at the output current source transistor. When the output current source transistor is off, the introduced switch transistor briefly conducts, forming a low-impedance path. This allows the gate voltage of the corresponding current source transistor to quickly rise to the VDD potential or fall to the GND potential, improving the turn-off speed during charging and discharging, and further improving the dynamic mismatch between charging and discharging currents. Ultimately, this invention has the advantages of low dynamic current mismatch and suitability for phase-locked frequency sources with low spurious performance. Attached Figure Description

[0018] Figure 1 This is a circuit diagram of the main circuit of the charge pump in the charge pump circuit for improving dynamic current mismatch in this invention.

[0019] Figure 2 This is a circuit diagram of the control signal generation circuit in the charge pump circuit for improving dynamic current mismatch in this invention.

[0020] Figure 3 This is a simulation comparison diagram of the discharge current under transient conditions in the charge pump circuit of this invention embodiment.

[0021] Figure 4 This is a simulation comparison diagram of the output mismatch current of the charge pump circuit under transient conditions in an embodiment of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and beneficial effects of this invention clearer and more understandable, the invention will be further described in detail below with reference to the embodiments and examples.

[0023] This embodiment provides a charge pump circuit for improving dynamic current mismatch, including: a charge pump main circuit and a control signal generation circuit; wherein, the charge pump main circuit and the control signal generation circuit are connected through a discharge switch signal DN terminal, a discharge switch complementary signal DN terminal, a charge switch signal UP terminal, a charge switch complementary signal UP terminal, a discharge start acceleration signal DNP terminal, a discharge start acceleration complementary signal DNP terminal, a discharge turn-off acceleration signal DNC terminal, and a charge turn-off acceleration signal UPC terminal.

[0024] Furthermore, the charge pump main circuit is as follows: Figure 1 As shown, it includes: NMOS transistors MN1-MN10, PMOS transistors MP1-MP7, current source I1, capacitors C1-C3, and transmission gate TG1; wherein:

[0025] One end of current source I1 is connected to VDD, and the other end is connected to the gate and drain of NMOS transistor MN1. The gates of NMOS transistors MN1, MN2, and MN3 are connected, and the source terminals of NMOS transistors MN1, MN2, and MN3 are connected and connected to GND. Current source I1 and NMOS transistors MN1, MN2, and MN3 constitute a basic current mirror.

[0026] The source terminals of NMOS transistors MN4 and MN5 are connected to the drain terminal of NMOS transistor MN2. The gate terminal of NMOS transistor MN4 is connected to the DN terminal and the drain terminal is connected to the drain terminal of PMOS transistor MP1. The gate terminal of NMOS transistor MN5 is connected to the DN terminal and the drain terminal is connected to the drain terminal of PMOS transistor MP2. Capacitor C2 is connected across the drain terminal of NMOS transistor MN2 and GND. NMOS transistors MN4 and MN5 and capacitor C2 form a discharge current control structure, which keeps NMOS transistor MN2 in the on state and keeps the drain terminal voltage of MN2 constant.

[0027] The sources of NMOS transistors MN6 and MN7 are connected and then connected to the drain of NMOS transistor MN3. The gate of NMOS transistor MN6 is connected to the UP terminal and the drain of NMOS transistor MP5. The gate of NMOS transistor MN7 is connected to the UP terminal and the drain of NMOS transistor MP6. Capacitor C3 is connected across the drain of NMOS transistor MN3 and GND. NMOS transistors MN6 and MN7 and capacitor C3 form a charging current control structure, which keeps NMOS transistor MN3 in the ON state and keeps the drain voltage of MN3 constant.

[0028] The gate and drain of PMOS transistor MP1 are connected, and its source is connected to VDD. The gate and drain of PMOS transistor MP2 are connected, and its source is connected to VDD. The gate of PMOS transistor MP3 is connected to the gate of PMOS transistor MP2, and a node VP1 is formed. The source of PMOS transistor MP3 is connected to VDD. The drain of PMOS transistor MP3 is connected to the drain and gate of NMOS transistor MN8. The source of NMOS transistor MN8 is connected to GND. The gate of NMOS transistor MN9 is connected to the gate of NMOS transistor MN8, and a node VN1 is formed. The source of NMOS transistor MN9 is connected to GND and the drain is connected to OUT. PMOS transistors MP2 and MP3 form a discharge intermediate current mirror, and NMOS transistors MN8 and MN9 form a discharge output current mirror. The drain of NMOS transistor MN10 is connected to node VN1, the source is connected to GND, and the gate is connected to DNC. When DNC provides a high-level pulse signal, NMOS transistor MN10 conducts for a short period of time, forming a low-impedance discharge path, which causes the voltage of node VN1 to drop rapidly to the GND potential, thus improving the discharge turn-off speed.

[0029] Capacitor C1 is connected between the drain of PMOS transistor MP1 and GND. The two outputs of transmission gate TG1 are connected to the drain of PMOS transistor MP1 and node VP1, respectively. The control terminal of transmission gate TG1 is connected to the DNP terminal and the DNP terminal, respectively. The control signals of the DNP terminal and the DNP terminal are complementary signals. When the DNP terminal signal is high and the DNP terminal signal is low, transmission gate TG1 is turned on, forming an additional discharge path and increasing the discharge speed of node VP1.

[0030] The gate and drain of PMOS transistor MP5 are connected, and its source is connected to VDD. The gate and drain of PMOS transistor MP6 are connected, and its source is connected to VDD. The gate of PMOS transistor MP4 is connected to the gate of PMOS transistor MP5 and leads to node VP2. The source of PMOS transistor MP4 is connected to VDD, and its drain is connected to OUT. PMOS transistors MP5 and MP4 form a charging output current mirror. The drain of PMOS transistor MP7 is connected to node VP2, its source is connected to GND, and its gate is connected to UPC. When UPC provides a low-level pulse signal, PMOS transistor MP7 conducts for a short period of time, forming a low-impedance charging path, which causes the voltage at node VP1 to rise rapidly to the VDD potential, improving the charging turn-off speed.

[0031] Furthermore, the control signal generation circuit is as follows: Figure 2 As shown, it includes: inverters INV1 to INV3, buffers B1 to B3, NOR gate NOR1, NAND gate NAND1, and OR gate OR1, and capacitor C4; wherein:

[0032] The inputs of inverter INV1, buffer B1, buffer B2, one input of NOR1, and one input of NAND1 are all connected to the DN terminal. The output of inverter INV1 is connected to the DN terminal. The output of buffer B1 is connected to the other input of NOR1, and the output of NOR1 is connected to the DNC terminal. The output of buffer B2 is connected to the other input of NAND1, and the output of NAND1 and the input of inverter INV1 are connected to the DNP terminal. The output of inverter INV2 is connected to the DNP terminal. Therefore, the polarity of the signals at the DN and DNP terminals is opposite. When the signal at the DN terminal changes from low to high, the DNP terminal outputs a short low-level pulse, and the DNP terminal outputs a short high-level pulse. Figure 1 The transmission gate TG1 described above is open for a period of time; when the signal at the DN terminal changes from high level to low level, the DNC terminal outputs a short high-level pulse, making... Figure 1 The NMOS transistor MN10 described above is turned on for a period of time;

[0033] The inputs of inverter INV3, buffer B3, and one input of OR gate OR1 are all connected to the UP terminal. The output of inverter INV3 is connected to the UP terminal. The output of buffer B3 is connected to the other input of OR gate OR1. The output of OR gate OR1 is connected to the UPC terminal. When the signal at the UP terminal changes from high to low, the UPC terminal outputs a short low-level pulse, causing... Figure 1The PMOS transistor MP7 is turned on for a period of time; capacitor C4 is connected between the UP terminal and GND, so that the load capacitance of the UP terminal is the same as the load capacitance of the DN terminal.

[0034] This embodiment controls the opening and closing timing of the rapid charge / discharge path in the main circuit of the charge pump by controlling the signal generated by the control signal circuit, thereby improving dynamic current mismatch; such as Figure 3 The figure shown is a simulation comparison of the charge pump discharge current under transient conditions. Figure 3 It can be seen that, through the technical solution proposed in this embodiment, the discharge current is improved in both the turn-on speed and the turn-off speed; for example Figure 4 The figure shown is a simulation comparison of the charge pump output mismatch current under transient conditions. Figure 4 It can be seen that the dynamic mismatch of the charge pump is improved through the technical solution proposed in this embodiment.

[0035] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All disclosed features, or steps in all methods or processes, may be combined in any way except for mutually exclusive features and / or steps.

Claims

1. A charge pump circuit for improving dynamic current mismatch, comprising: The charge pump main circuit and the control signal generation circuit are connected via a discharge switch signal DN terminal and a discharge switch complementary signal. Terminal, charging switch signal UP terminal, charging switch complementary signal Terminal, discharge start acceleration signal DNP terminal, discharge start acceleration complementary signal The discharge shutdown acceleration signal DNC terminal and the charging shutdown acceleration signal UPC terminal are connected. The charge pump main circuit includes: NMOS transistors MN1~MN10, PMOS transistors MP1~MP7, current source I1, capacitors C1~C3, and transmission gate TG1; wherein: One end of current source I1 is connected to VDD, and the other end is connected to the gate and drain of NMOS transistor MN1. The gates of NMOS transistors MN1, MN2, and MN3 are connected, and the source terminals of NMOS transistors MN1, MN2, and MN3 are connected and then connected to GND. The source terminals of NMOS transistors MN4 and MN5 are connected to the drain terminal of NMOS transistor MN2, and the gate terminal of NMOS transistor MN4 is connected to... The gate of NMOS transistor MN5 is connected to the DN terminal, and the drain of NMOS transistor MN5 is connected to the drain of PMOS transistor MP2. Capacitor C2 is connected across the drain of NMOS transistor MN2 and GND. The source terminals of NMOS transistors MN6 and MN7 are connected to the drain terminal of NMOS transistor MN3. The gate terminal of NMOS transistor MN6 is connected to the UP terminal, and its drain terminal is connected to the drain terminal of PMOS transistor MP5. The gate terminal of NMOS transistor MN7 is connected to... The drain terminal is connected to the drain terminal of PMOS transistor MP6, and capacitor C3 is connected across the drain terminal of NMOS transistor MN3 and GND. The gate and drain of PMOS transistor MP1 are connected, and its source is connected to VDD. The gate and drain of PMOS transistor MP2 are connected, and its source is connected to VDD. The gate of PMOS transistor MP3 is connected to the gate of PMOS transistor MP2 and leads to node VP1. The source of PMOS transistor MP3 is connected to VDD. The drain of PMOS transistor MP3 is connected to the drain and gate of NMOS transistor MN8. The source of NMOS transistor MN8 is connected to GND. The gate of NMOS transistor MN9 is connected to the gate of NMOS transistor MN8 and leads to node VN1. The source of NMOS transistor MN9 is connected to GND, and its drain is connected to the OUT terminal. The drain of NMOS transistor MN10 is connected to node VN1, its source is connected to GND, and its gate is connected to the DNC terminal. Capacitor C1 is connected across the drain of PMOS transistor MP1 and GND. The two outputs of transmission gate TG1 are connected to the drain of PMOS transistor MP1 and node VP1, respectively. The control terminal of transmission gate TG1 is connected to the DNP terminal, End connected; The gate and drain of PMOS transistor MP5 are connected, and the source is connected to VDD. The gate and drain of PMOS transistor MP6 are connected, and the source is connected to VDD. The gate of PMOS transistor MP4 is connected to the gate of PMOS transistor MP5 and leads out to node VP2. The source of PMOS transistor MP4 is connected to VDD, and the drain is connected to OUT. PMOS transistors MP5 and MP4 form a charging output current mirror. The drain of PMOS transistor MP7 is connected to node VP2, the source is connected to VDD, and the gate is connected to UPC. The control signal generation circuit includes: inverters INV1~INV3, buffers B1~B3, NOR gate NOR1, NAND gate NAND1, OR gate OR1, and capacitor C4; wherein: The inputs of inverter INV1, buffer B1, buffer B2, one input of NOR gate NOR1, and one input of NAND gate NAND1 are all connected to the DN terminal. The output of inverter INV1 is connected to... The output of buffer B1 is connected to the other input of NOR gate NOR1, and the output of NOR gate NOR1 is connected to the DNC terminal. The output of buffer B2 is connected to the other input of NAND gate NAND1, and the output of NAND gate NAND1 and the input of inverter INV2 are connected together to... The output terminal of inverter INV2 is connected to the DNP terminal; The inputs of inverter INV3, buffer B3, and one input of OR gate OR1 are all connected to the UP terminal. The output of inverter INV3 is connected to... The output of buffer B3 is connected to the other input of OR gate OR1, and the output of OR gate OR1 is connected to the UPC terminal. Capacitor C4 is connected across the UP terminal and GND.

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