Radio frequency power amplifier and method for making a doherty power amplifier

Abstract

A radio frequency power amplifier and a method for making a Doherty power amplifier are disclosed. The radio frequency power amplifier includes at least one transistor, a harmonic cancellation circuit, and an impedance inverter. One end of the harmonic cancellation circuit is directly connected to the drain of the transistor and acts as part of the harmonic matching network of the transistor at the frequency of the second and / or third harmonic of the fundamental frequency. The impedance inverter is used to perform impedance inversion operation on the static or modulated impedance at the fundamental frequency without the influence of the harmonic cancellation circuit.

Description

Technical Field

[0001] This invention relates to a radio frequency circuit design and manufacturing method thereof, particularly a radio frequency power amplifier and a method for manufacturing a Doherty power amplifier (such as a forward or reverse Doherty power amplifier) ​​and related improvements thereof. Background Technology

[0002] In upcoming 5G MIMO applications, the demand for high-efficiency power amplifiers is constantly increasing. Furthermore, high bandwidth is an indispensable requirement for high-speed data transmission in microwave communication applications for 5G and other standards. Traditional switching Doherty power amplifiers can employ harmonic load cancellation architectures (e.g., Class F, Class F...). -1 (e.g., class) are widely used to provide better back-off efficiency, but they are severely limited in terms of bandwidth by the requirement to use narrow-band quarter-wavelength transmission lines.

[0003] To address the aforementioned bandwidth limitation problem, numerous solutions have been proposed. However, no feasible solution has yet been found that simultaneously achieves high efficiency while integrating a harmonic cancellation architecture. Therefore, Doherty power amplifiers currently used in the industry typically require a trade-off between high efficiency and high bandwidth due to the need for parasitic compensation techniques. As previously explained, due to the difficulty and complexity of harmonic network design, even if some device parasitic effects can be used to provide better bandwidth, they cannot simultaneously be used to cancel harmonics for a high-efficiency design. Similarly, if device parasitic effects are used in harmonic load cancellation design to provide better efficiency, these parasitic effects will cause bandwidth limitations. Furthermore, because such designs require additional quarter-wavelength transmission lines and offset lines, this configuration further reduces bandwidth and results in a large circuit size, hindering miniaturization and integration.

[0004] Therefore, in existing Doherty power amplifiers that use a switching power amplifier architecture as the harmonic matching network, only high efficiency can be achieved, but with low bandwidth (narrow bandwidth design) and complex circuit design resulting in a large size. Such a design is not suitable for applications in monolithic microwave integrated circuits (MMICs), hybrid ICs, or other types of distributed RF circuits. Summary of the Invention

[0005] The embodiments of the present invention solve the problem of excessively narrow bandwidth of RF power amplifiers by using an impedance inverter network to replace the basic matching network, while also eliminating the parasitic effects of load harmonics.

[0006] Embodiments of the present invention also achieve the effect of effectively miniaturizing the circuit design of the switching radio frequency amplifier.

[0007] The embodiments of the present invention further address key problems currently faced by Doherty power amplifiers used in industry, such as the trade-off between bandwidth and efficiency. The embodiments of the present invention also resolve the trade-off between efficiency and size minimization, enabling power amplifiers designed according to embodiments of the present invention to not only provide high back-off efficiency but also simultaneously achieve minimization of size and high bandwidth.

[0008] The embodiments of the present invention also solve the problems of excessive design complexity and excessive size encountered when designing a switching Doherty power amplifier that can control the second and third harmonics.

[0009] This invention proposes a radio frequency (RF) power amplifier adapted to operate at a base frequency and electrically connected to a load, the RF power amplifier including at least one transistor and a hybrid matching circuit. The hybrid matching circuit is electrically connected between the drain of the at least one transistor and the load, wherein the hybrid matching circuit includes: a first circuit having a first terminal electrically connected to the drain of the at least one transistor and a second terminal electrically connected to the load; and a second circuit electrically connected between the drain of the at least one transistor and an RF ground terminal, wherein the first circuit and an output parasitic element of the at least one transistor operate as an impedance inverter of the RF power amplifier at the base frequency, and the second circuit provides a high impedance path relative to the RF ground terminal at the base frequency, and wherein the second circuit provides an impedance relative to the RF ground terminal at the frequency of a first target harmonic of the base frequency, such that the impedance observed from the intrinsic plane of the at least one transistor is either a high impedance or a low impedance, to eliminate the first target harmonic. The second circuit can be used to provide an impedance relative to the radio frequency ground terminal at the frequency of a second target harmonic of the fundamental frequency, such that the impedance observed from the intrinsic plane of the at least one transistor is either a high impedance or a low impedance, in order to eliminate the second target harmonic.

[0010] Wherein, when the at least one transistor is a single transistor, the harmonic matching network of the single transistor is formed based on at least one output parasitic element of the single transistor, the first circuit and the second circuit; and when the at least one transistor is a plurality of transistors, the harmonic matching network of one of the plurality of transistors is formed based on at least one output parasitic element of one of the plurality of transistors, the first circuit and the second circuit.

[0011] Wherein, the frequency of the first target harmonic is the second harmonic frequency of the fundamental frequency, and the frequency of the second target harmonic is the third harmonic frequency of the fundamental frequency.

[0012] Wherein, at the second harmonic frequency of the fundamental frequency, the impedance observed from the intrinsic plane of the at least one transistor is the low impedance; and at the third harmonic frequency of the fundamental frequency, the impedance observed from the intrinsic plane of the at least one transistor is the low impedance.

[0013] The first circuit includes:

[0014] A transmission circuit is electrically connected between the first end and the second end;

[0015] A first reactive element, electrically connected between one of the first terminal and the second terminal and the radio frequency ground terminal; and

[0016] A second reactive element is electrically connected between the other of the first and second terminals and the radio frequency ground terminal.

[0017] The transmission circuit includes at least one of an inductor and a transmission line.

[0018] The second circuit includes a capacitive element and two inductive elements, wherein the capacitive element is connected in parallel with one of the two inductive elements, and the capacitive element is connected in series with the other of the two inductive elements.

[0019] The capacitive element and the inductive element include:

[0020] A first capacitive element;

[0021] A first inductive element, connected in series with the first capacitive element, and situated between the drain of the at least one transistor and the radio frequency ground terminal; and

[0022] A second inductive element, one end of which is electrically connected to the drain of the at least one transistor and the first terminal, and the other end of which is electrically connected to the radio frequency ground terminal.

[0023] The dimensions of the first capacitive element and the first inductive element are designed to provide a low-impedance path to the radio frequency ground terminal at the frequency of the first target harmonic of the fundamental frequency.

[0024] The second inductive element is sized such that, at the base frequency, the first capacitive element, the first inductive element, and the second inductive element are equivalent to an open circuit relative to the radio frequency ground terminal.

[0025] Wherein, the first capacitive element is implemented as a capacitor, and the first and second inductive elements are each implemented as a part or integral of at least one of an inductor and a transmission line, and the dimensions of the capacitor, the inductor, and the transmission line conform to the following formula:

[0026]

[0027]

[0028] Z 21 tan(θ 21 )=ω0L 21 ;

[0029] Z 22 tan(θ 22 )=ω0L 22 ;

[0030] Z 21 'tan(θ) 21 ′)+ω0L 21 ′=ω0L 21 ;

[0031] Z 22 'tan(θ) 22 ′)+ω0L 22 ′=ω0L 21 ;

[0032] Where C 21 Let L be the capacitance value of the capacitor. 21 L is the inductance value of the inductor used to implement the first inductive element. 22 Z is the inductance value of the inductor used to implement the second inductive element. 21 To implement an inductance value of L 21 The characteristic impedance of the transmission line of the first inductive element, Z 22 To implement an inductance value of L 22 The characteristic impedance of the transmission line of the second inductive element, ω o Let θ be the fundamental frequency, n be the harmonic order index, and θ be the harmonic frequency. 21 To implement an inductance value of L 21 The electrical angle θ of the transmission line of the first inductive element. 22 To implement an inductance value of L 22 The electrical angle of the transmission line of the second inductive element, Z 21 ′ and θ 21 ′ is used to match inductor L 21 To implement an inductance value of L 21 The characteristic impedance and electrical angle of the transmission line of the first inductive element, and Z22 ′ and θ 22 ′ is used to match inductor L 22 To implement the inductance value L 22 The characteristic impedance and electrical angle of the transmission line of the second inductive element.

[0033] The impedance inverter includes at least one of the following architectures: an n-stage low-pass lumped quarter-wavelength converter, a quarter-wavelength stub transmission line, a quasi-lumped n-order low-pass filter, a quasi-lumped n-order low-pass quarter-wavelength converter, a quasi-lumped low-pass Chabyshev converter, a quasi-lumped low-pass Chabyshev quarter-wavelength converter, a quasi-lumped low-pass quarter-wavelength step impedance converter, and a quasi-lumped low-pass quarter-wavelength step impedance quarter-wavelength converter.

[0034] The capacitive element and the inductive element include:

[0035] A first inductive element; and

[0036] An inductive-capacitive resonant circuit is connected in series with the first inductive element and electrically connected between the drain of the at least one transistor and the radio frequency ground terminal, wherein:

[0037] The inductor-capacitor resonant circuit includes a second inductive element and a first capacitive element connected in parallel.

[0038] The first and second inductive elements are used to provide at least one of a second harmonic high impedance, a second harmonic low impedance, and a third harmonic low impedance on the intrinsic plane of the transistor connecting the second circuit.

[0039] The second inductive element and the first capacitive element are used to provide a high-impedance path relative to the RF ground terminal at the fundamental frequency based on the following formula:

[0040]

[0041] Where LCH is the inductance of the second inductive element, CCH is the capacitance of the first capacitive element, and ω o This is the fundamental frequency.

[0042] This invention proposes a method for manufacturing a Doherty power amplifier, comprising the following steps: providing at least one main amplifier operating at a fundamental frequency; providing at least one peak amplifier connected in parallel with the at least one main amplifier and sharing a common load or a load; connecting a first hybrid matching circuit between the output of the at least one main amplifier and the output of the at least one peak amplifier, wherein connecting the first hybrid matching circuit includes: connecting a first circuit between the output of the at least one main amplifier and the output of the at least one peak amplifier, wherein the first circuit is part of an impedance inverter network of the first hybrid matching circuit of the Doherty power amplifier.

[0043] The circuit connecting the first hybrid matching circuit further includes:

[0044] A second circuit is connected between the output of the at least one main amplifier and an RF ground terminal;

[0045] A third circuit is connected between the output of the at least one peak amplifier and the radio frequency ground terminal;

[0046] The type and size of the components included in the first circuit are determined so as to form an impedance inverter network using an output parasitic element of one of the main amplifier and the peak amplifier at the base frequency;

[0047] The component dimensions included in the second and third circuits are determined so that the second and third circuits provide a high impedance relative to the RF ground at the base frequency, so that the function of the impedance inverter network is not affected; and

[0048] The component dimensions included in the second and third circuits are determined so that the impedances observed from the essential plane of the main amplifier and the peak amplifier are either a high impedance or a low impedance, thereby eliminating either the second or third harmonic of the fundamental frequency.

[0049] The connection to the first hybrid matching circuit further includes:

[0050] The component dimensions included in the second and third circuits are determined so that the impedances observed from the essential plane of the main amplifier and the peak amplifier are either a high impedance or a low impedance, thereby eliminating the other of the second and third harmonics of the fundamental frequency, by utilizing the impedances provided by at least the first, second, and third circuits.

[0051] The impedance inverter network of the first hybrid matching circuit includes at least one of the following architectures: an n-stage low-pass lumped quarter-wavelength converter, a quarter-wavelength stub transmission line, a quasi-lumped n-order low-pass filter, a quasi-lumped n-order low-pass quarter-wavelength converter, a quasi-lumped low-pass Chabyshev converter, a quasi-lumped low-pass Chabyshev quarter-wavelength converter, a quasi-lumped low-pass quarter-wavelength step impedance converter, and a quasi-lumped low-pass quarter-wavelength step impedance quarter-wavelength converter.

[0052] The method further includes providing at least two peak amplifiers, wherein providing at least one peak amplifier includes providing at least two peak amplifiers.

[0053] At least one additional hybrid matching circuit is connected between the outputs of the at least two peak amplifiers, such that any two of the at least two peak amplifiers are associated with the at least one hybrid matching circuit, wherein the first hybrid matching circuit and the additional hybrid matching circuit are electrically connected and share the common load, wherein connecting the at least one additional hybrid matching circuit includes:

[0054] A first circuit is connected between the output of the at least one main amplifier and the output of the at least two peak amplifiers, wherein the first circuit is part of an impedance inverter network of the at least one additional hybrid matching circuit of the Doherty power amplifier.

[0055] This invention proposes another method for manufacturing a Doherty power amplifier, comprising the following steps: providing at least one main amplifier operating at a fundamental frequency; providing at least one peak amplifier connected in parallel with the at least one main amplifier and sharing a common load or a load; connecting a first hybrid matching circuit between the output of the at least one main amplifier and the output of the at least one peak amplifier, wherein connecting the first hybrid matching circuit includes: connecting a first circuit between the output of the at least one main amplifier and the output of the at least one peak amplifier, wherein the first circuit is part of an impedance inverter network of the first hybrid matching circuit of the Doherty power amplifier; and using a second hybrid matching circuit or an additional impedance... An inverter network and a parasitic elimination shunt network are connected between the output of the at least one main amplifier and the output of the at least one peak amplifier, wherein the first hybrid matching circuit and the second hybrid matching circuit, or the first hybrid matching circuit, the at least one additional hybrid matching circuit and the parasitic elimination shunt network are connected together by the impedance inverter network and share the common load, wherein connecting the second hybrid matching circuit includes: connecting a first circuit between the output of the at least one main amplifier and the output of the at least one peak amplifier, wherein the first circuit of the second hybrid matching circuit is part of an impedance inverter network of the second hybrid matching circuit of the Doherty power amplifier.

[0056] The impedance inverter network connecting the first hybrid matching circuit and the second hybrid matching circuit includes at least one of the following architectures: a quarter-wavelength converter, an n-order high-pass quarter-wavelength converter, an n-order low-pass quarter-wavelength converter, an n-stage low-pass lumped quarter-wavelength converter, an n-stage high-pass lumped quarter-wavelength converter, a quarter-wavelength stub transmission line, a quasi-lumped n-order low-pass filter, a quasi-lumped n-order high-pass filter, a quasi-lumped n-order low-pass quarter-wavelength converter, a quasi-lumped low-pass Chaibeschoff converter, and so on. Lumped low-pass Chabyshev quarter-wavelength converter, quasi-lumped low-pass quarter-wavelength step impedance converter, quasi-lumped low-pass quarter-wavelength step impedance quarter-wavelength converter, quasi-lumped n-order high-pass quarter-wavelength converter, quasi-lumped high-pass Chabyshev converter, quasi-lumped high-pass Chabyshev quarter-wavelength converter, quasi-lumped high-pass quarter-wavelength step impedance converter, quasi-lumped high-pass quarter-wavelength step impedance quarter-wavelength converter, and combinations of low-pass and high-pass lumped or distributed quarter-wavelength converters.

[0057] The impedance inverter network of the second hybrid matching circuit includes at least one of the following architectures: an n-stage low-pass lumped quarter-wavelength converter, a quarter-wavelength stub transmission line, a quasi-lumped n-order low-pass filter, a quasi-lumped n-order low-pass quarter-wavelength converter, a quasi-lumped low-pass Chabyshev converter, a quasi-lumped low-pass Chabyshev quarter-wavelength converter, a quasi-lumped low-pass quarter-wavelength step impedance converter, and a quasi-lumped low-pass quarter-wavelength step impedance quarter-wavelength converter.

[0058] The method further includes providing at least two peak amplifiers, wherein providing at least one peak amplifier includes providing at least two peak amplifiers.

[0059] At least one additional hybrid matching circuit is connected between the outputs of the at least two peak amplifiers, such that any two of the at least two peak amplifiers are associated with a hybrid matching circuit, wherein the first hybrid matching circuit, the second hybrid matching circuit, and the at least one additional hybrid matching circuit are connected together by the impedance inverter network and share the common load, wherein connecting the at least one additional hybrid matching circuit includes:

[0060] A first circuit is connected between the outputs of the at least two peak amplifiers, wherein the first circuit is part of an impedance inverter network of the at least one additional hybrid matching circuit of the Doherty power amplifier.

[0061] This invention proposes a radio frequency (RF) power amplifier operating at a base frequency, the RF power amplifier being electrically connected to a load, and comprising: at least one transistor; a harmonic cancellation circuit, one end of which is directly connected to the drain of the at least one transistor, and the other end of which is electrically connected to an RF ground terminal, wherein the harmonic cancellation circuit is part of a harmonic matching network of the at least one transistor at one of the second harmonic frequency and the third harmonic frequency of the base frequency; and an impedance inverter having a first terminal electrically connected to the drain of the at least one transistor and a second terminal electrically connected to the load, the impedance inverter being used to perform impedance inversion of static impedance or impedance inversion of modulated impedance at the base frequency without affecting the harmonic cancellation circuit.

[0062] This invention designs a new Doherty power amplifier using a novel connection network called a "hybrid matching network," which can be integrated into any RF application in industrial applications. While the description of this invention focuses on the application of the hybrid matching network in the Doherty power amplifier, it can also be used in various switching or continuous amplifier architectures, such as Class F, Class F... -1 Class, J class, E class, continuous F class, continuous F -1 Amplifier architectures such as Class-J, Class-E, and Class-J consecutively. Attached Figure Description

[0063] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without any further effort.

[0064] Figure 1A Schematic diagram of a radio frequency power amplifier according to some embodiments of the present invention;

[0065] Figure 1B :according to Figure 1A Equivalent circuit diagrams of RF power amplifiers in some embodiments;

[0066] Figure 2A A schematic diagram of a radio frequency power amplifier having a power amplifier with multiple transistors according to some embodiments of the present invention;

[0067] Figure 2B :according to Figure 2A Equivalent circuit diagrams of RF power amplifiers in some embodiments;

[0068] Figures 3A to 3C :according to Figure 1B Circuit diagrams of radio frequency power amplifiers with hybrid matching networks in some embodiments;

[0069] Figure 4A and Figure 4B :according to Figure 2B Circuit diagrams of RF power amplifiers with fully hybrid matching networks in some embodiments;

[0070] Figure 4C and Figure 4D :according to Figure 2B Circuit diagrams of RF power amplifiers with single-sided hybrid matching networks in some embodiments;

[0071] Figure 5A A schematic diagram comparing the characteristics of a conventional Doherty power amplifier and a Doherty power amplifier with a hybrid matching network according to an embodiment of the present invention;

[0072] Figure 5B A schematic diagram comparing the characteristics of a forward Doherty power amplifier and a reverse Doherty power amplifier with a hybrid matching network according to an embodiment of the present invention;

[0073] Figure 6 A flowchart illustrating the steps of a method for manufacturing a Doherty power amplifier according to an embodiment of the present invention;

[0074] Figure 7 : A flowchart of another method for manufacturing a Doherty power amplifier according to an embodiment of the present invention;

[0075] Figures 8A to 8E : A schematic diagram of a Doherty power amplifier according to some embodiments of the present invention;

[0076] Figures 9A to 9E :according to Figures 8A to 8E Circuit diagrams of some embodiments of the Doherty power amplifier;

[0077] Figure 10A and Figure 10B : A schematic diagram of an N-channel Doherty power amplifier according to some embodiments of the present invention.

[0078] Explanation of reference numerals in the attached figures

[0079] 100,200,200',200”: RF power amplifier

[0080] 110,210_1,210_2: Amplifier

[0081] 120,220,220',220”: Hybrid matching circuit

[0082] 121,221,121_1,121_2: First circuit

[0083] 121a~121d, 221a~221d: Configuration of impedance inverters

[0084] 122,222,222_1,222_2: Second circuit

[0085] 122a~122j: Configuration of harmonic cancellation circuits

[0086] 123, 224, 225: Compensation circuits

[0087] 130,230_1,230_2: Input matching circuit

[0088] 223: Third Circuit

[0089] 226, 227: Parasitic Elimination Circuits

[0090] 240: Power Divider

[0091] 250, 250', 300, 300': Impedance inverter network

[0092] C1,C2,C 11 C 12 C 21 C CH :capacitance

[0093] C b DC blocking capacitor

[0094] C GD C GS C DS C GD1 C GS1 C DS1 C GD2 C GS2 C DS2 Parasitic capacitance

[0095] CS1: Current source

[0096] GND: Radio frequency ground terminal

[0097] ITP: Essential Plane

[0098] L0,L 11 ,L 12 ,L 21 ,L 22 ,L 22 ',L CH :inductance

[0099] L par ,L par1 ,L par2 Parasitic inductance

[0100] PAE_n, PAE_o, PAE_DPA, PAE_IDPA: Efficiency curves

[0101] Pout_n, Pout_o, Pout_DPA, Pout_IDPA: Output power curves

[0102] RFin: Radio frequency input signal

[0103] R OPT Ro m ,R Op Output impedance

[0104] RFout: Radio frequency output signal

[0105] S110~S130, S210~S240: Steps in manufacturing a Doherty power amplifier; TC: Transmission circuit.

[0106] Td, Td1, Td2: Drain

[0107] TL0,TL 21 ,TL 21 ',TL 22 ',TL CH Transmission line

[0108] TR1, TR2, TR1-Main, TR2-Peak: Transistor

[0109] X i ,X j ,X CF Reactor components

[0110] Z L Z LOAD Z Lm Z Lp :load. Detailed Implementation

[0111] This invention proposes a novel radio frequency amplifier and a method for manufacturing Doherty power amplifiers (including, for example, forward and reverse Doherty power amplifiers). To make the above-mentioned objects, features, and advantages of this invention more apparent and understandable, specific embodiments of the invention are described in detail below with reference to the accompanying drawings. The following descriptions of various embodiments of the invention are for illustrative purposes only and do not represent all embodiments of the invention or limit the invention to specific embodiments. It should also be noted that, in order to clearly illustrate the various inventive features of the invention, multiple embodiments are described below. However, this does not mean that each embodiment can only be implemented individually. Those skilled in the art can design feasible implementation examples by combining them together according to their needs, or replace substituted components / modules in different embodiments according to design requirements. In other words, the implementation methods taught by this invention are not limited to the solutions described in the following embodiments, but also include substitutions and arrangements between various embodiments / components / modules where feasible, which are described here first.

[0112] For clarity, the accompanying drawings and illustrations in this invention are generally not drawn to scale and are not intended to correspond to actual relative dimensions. Furthermore, the same element numbers may be used to represent the same, corresponding, or similar elements, and are not limited to representing only the same elements.

[0113] The terminology used in this invention is for describing specific embodiments only and is not intended to limit the invention. Furthermore, the use of the quantifiers "a" or "an" for elements and components throughout this invention is for convenience and to provide the general meaning of the scope of the invention; it should be interpreted in this invention as including one or at least one, and a single concept also includes plural cases, unless it clearly indicates otherwise. In addition, the term "and / or" includes any combination of the listed items and may also be expressed as " / ".

[0114] The terms "first," "second," and "third," etc., used in the specification and accompanying drawings of this invention are used to distinguish different objects, areas, levels, or steps, and are not used to describe a specific order (unless expressly required by the claims). Therefore, the first component / element / circuit described in the specification paragraphs may be the second component / element / circuit described in the claims. Furthermore, in certain specific examples, even if the specification does not use terms such as "first" or "second," it may still be described using related terms such as "first" or "second" as described in the claims.

[0115] The term "comprising" and any variations thereof are intended in this specification to cover the presence of the features, regions, integers, steps, operations, and elements indicated by the inclusion without exclusive exclusion, but do not exclude the presence of additional features, regions, integers, steps, operations, and elements.

[0116] The terms "connection" or "coupling" used in this invention do not imply that there can be no space between the objects. That is, the connection or coupling between two objects can mean that the two objects are directly connected / coupled to each other, or connected / coupled to each other through other objects. Conversely, if objects are described as "directly connected" or "directly coupled," it means that there are no space between the two objects. Terms such as "electrically connected," "electrically coupled," and other similar terms describing connection relationships (e.g., "located between" versus "directly located between," "adjacent" versus "directly adjacent," and so on) should be interpreted in a similar manner as described above.

[0117] The term "electrical connection" between objects refers to the ability of electronic signals to be transmitted from one object to another, at least under certain circumstances. Therefore, a physical connection between a passive conductive element (e.g., traces, solder pads, internal wiring, etc.) and a passive insulating element (e.g., film on a printed circuit board, electrically insulating adhesive connecting two devices, electrically insulating filler, or injection molding layer, etc.) is not considered an electrical connection between the two elements.

[0118] The terms “network” and “circuit” used in this article are interchangeable. The term “circuit” is more often used to describe the connection and arrangement between components from the perspective of physical and electronic connections, while the term “network” is more often used to describe the equivalent architecture between input and output ports.

[0119] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art. It should be noted that terms used herein, such as those broadly defined in dictionaries, should be interpreted in their ordinary sense and consistent with their context. Unless otherwise specified, the terms used herein should not be interpreted narrowly in an overly idealized or formal manner.

[0120] The embodiments of the present invention can be described using functional blocks, units, and / or modules in conjunction with accompanying drawings. Those skilled in the art will understand that the functional blocks, units, and / or modules can be physically implemented using electronic circuits fabricated using semiconductor technology or other technologies, such as logic circuits, discrete components, analog circuits, hardware circuits, memory elements, and wiring connections. Each functional block, unit, and / or module can be composed of two or more physically separable discrete modules. Furthermore, in different embodiments, the functional blocks, units, and / or modules can also be physically combined to form a more complex functional block, unit, and / or module.

[0121] Figure 1A This is a schematic diagram of a radio frequency power amplifier according to some embodiments of the present invention. Please refer to... Figure 1A The RF power amplifier 100 can be a switching RF power amplifier designed to operate at a base frequency, such as from 0.3 GHz to 3000 GHz. The RF power amplifier 100 can be configured to electrically connect to a load Z. LOAD To drive the load Z by providing an amplified radio frequency signal LOAD In some embodiments, the baseband may be a frequency used in MIMO applications of 4G or 5G, or any other frequency used in other applications (e.g., X-band, Ka-band, Ku-band, etc.), and the present invention is not limited thereto.

[0122] The radio frequency power amplifier 100 includes a transistor-based amplifier 110 and a hybrid integrated matching circuit 120, wherein the amplifier 110 includes a transistor TR1. The transistor TR1 is biased to amplify the radio frequency input signal RFin received from its gate and outputs the amplified signal via its drain. In this embodiment, Figure 1A The amplifier 110 illustrated is a single-stage amplifier, so the gate of transistor TR1 can be considered as the input terminal of amplifier 110, and the drain of transistor 110 can be considered as the output terminal of amplifier 110, but the present invention is not limited thereto. In some embodiments, amplifier 110 may also be a multi-stage amplifier containing two or more transistors, and such architectures will be further described in subsequent embodiments of the present invention.

[0123] The hybrid matching circuit 120 is electrically connected between the drain of transistor TR1 and the load Z. LOAD Between, and used to convert the output impedance of transistor TR1 to the load Z at the fundamental frequency and harmonic frequency. LOAD Matching impedance, wherein the harmonic frequency is, for example, the second harmonic frequency and / or the third harmonic frequency.

[0124] Please refer to further details. Figure 1A and Figure 1B ,in Figure 1B According to Figure 1A Equivalent circuit diagrams of RF power amplifiers in some embodiments are shown below. In this embodiment, transistor TR1 is depicted as an equivalent model including current source CS1 and multiple parasitic elements located between electrodes, such as parasitic capacitance C. GD C GS and C DS and parasitic inductance L par .

[0125] The hybrid matching circuit 120 includes a first circuit 121 and a second circuit 122. The first circuit 121 has a first terminal electrically connected to the drain of transistor TR1 and an electrical terminal connected to the load Z. LOAD The second terminal. The second circuit 122 is electrically connected between the drain of transistor TR1 and the radio frequency ground terminal GND.

[0126] The first circuit 121 and the output parasitic element C DS and L par Operating as an impedance inverter of the RF power amplifier 100, it provides an impedance inverter network at the base frequency; at the same time, the second circuit 122 provides a high impedance path relative to the RF ground terminal GND at the base frequency.

[0127] The second circuit 122 is used to provide an impedance relative to the RF ground terminal GND, such that at the frequency of the first target harmonic of the fundamental frequency, the output impedance R- observed from the intrinsic plane ITP of the transistor TR1 is... O The impedance is either high or low to eliminate the first target harmonic. In this embodiment, the frequency of the first target harmonic can be the second harmonic frequency, the third harmonic frequency, or other harmonic frequencies; the present invention is not limited thereto.

[0128] Specifically, the hybrid matching circuit 120 utilizes the first circuit 121 in conjunction with the parasitic element C of transistor TR1. DS and L par At the fundamental frequency, an impedance inverter network is formed; and since the second circuit 122 provides a high impedance relative to the RF ground terminal GND, the second circuit 122 can be considered an open circuit or electrically isolated from the RF power amplifier 100. The hybrid matching circuit 120 also utilizes the parasitic element C of the transistor TR1 at the frequency of the first target harmonic. DS and L par The first circuit 121 and the second circuit 122 form a harmonic matching network.

[0129] In other words, the parasitic element C of the first circuit 121 and the transistor TR1 DS and L parAs part of the impedance inverter network and harmonic matching network, the second circuit 122 is primarily used as a harmonic cancellation circuit and becomes part of the harmonic matching network at the target harmonic frequency. In other words, the impedance inverter network and the harmonic matching network share the parasitic element C. DS and L par As part of the first circuit 121, and individual circuits within the hybrid matching circuit 120, neither the first circuit 121 nor the second circuit 122 can independently form an impedance inverter network or a harmonic matching network. This is due to the output parasitic capacitance C. DS Output parasitic inductance L par The first circuit 121 and the second circuit 122 are combined into an impedance inverter network and a harmonic matching network at different frequencies. Therefore, the impedance inverter network and the harmonic matching network can be regarded as being hybrid integrated together.

[0130] From another perspective, a hybrid matching circuit can refer to an output matching network that uses the output parasitic capacitance and inductance of a transistor to perform impedance inversion while simultaneously suppressing first-order or second-order harmonic loads (such as second- and third-order harmonic loads). This configuration creates a hybrid architecture that integrates the transistor parasitic elements, impedance inversion network, and harmonic matching network, thereby enabling the miniaturization of the RF power amplifier 100.

[0131] Furthermore, because the second circuit 122 is equivalent to an open circuit at the base frequency, the impedance inverter network remains unaffected. In other words, at the base frequency, the output impedance R... O In essence, it is unrelated to the impedance provided by the second circuit 122 relative to the radio frequency ground terminal GND.

[0132] In some embodiments, the second circuit 122 can also be used to provide an impedance relative to the RF ground terminal GND, such that the output impedance R O The impedance is high or low at the frequency of the second target harmonic to eliminate the second target harmonic. Similarly, the frequency of the second target harmonic can be the second harmonic frequency, the third harmonic frequency, or other order harmonic frequencies, and the present invention is not limited thereto.

[0133] More specifically, the second circuit 122 can be designed to modulate resonant loads at multiple different resonant frequencies (or eliminate harmonic effects) to achieve a high-efficiency switching power amplifier architecture, such as a Class F amplifier. -1 Class-A, Class-J, Class-S amplifiers, etc. For example, the second circuit 122 can be designed to make the output impedance R... OThe transistor TR1 operates with high impedance at the second harmonic frequency and low impedance at the third harmonic frequency, thereby enabling it to operate in Class F mode. In other examples, the second circuit 122 can also be designed to make the output impedance R... O It exhibits high impedance at the second harmonic frequency, but simultaneously does not modulate the third harmonic, thereby allowing transistor TR1 to operate at F. -1 Class pattern.

[0134] In some embodiments, the impedance inverter network provided by the hybrid matching circuit 120 can be any low-pass impedance inverter with at least one shunt reactance. For example, by selecting an appropriate first circuit 121 architecture, the impedance inverter network can be an n-stage low-pass lumped quarter-wavelength converter. th Stage lumped quarterwave transformer), low pass stub transmission line (low pass n) th Stage-reduced lengthquarter wave transmission line), quasi-lumped nth-order low-pass filter (quasi-lumped n) th orderlow pass filter), quasi-lumped nth-order low-pass quarter-wavelength converter th Quasi-lumped low-pass Chebyshev transformer, quasi-lumped low-pass Chebyshev quarter-wave transformer, quasi-lumped low-pass quarter-wave stepped impedance transformer, or quasi-lumped low-pass quarter-wave stepped impedance quarter-wave transformer.

[0135] It should be noted that due to the parasitic capacitance C DS / parasitic inductance L parUsed as part of an impedance inverter network, the impedance inverter network does not need to be physically and completely presented on the circuit board. In other words, the absence of a visually perceptible impedance inverter circuit / network in the hardware configuration of an RF power amplifier does not mean that the RF power amplifier does not fall within the scope of the claims of this invention. As long as the elements in the claims are present in the equivalent circuit of the RF power amplifier, the RF power amplifier still falls within the scope covered by the claims of this invention.

[0136] In some embodiments, the second circuit 122 may be configured to be adjacent to and directly connected to the drain of the transistor TR1, that is, at least one element in the second circuit 122 is physically located closest to the drain of the transistor TR1 and directly connected to the drain compared to other elements in the hybrid matching circuit 120.

[0137] In some embodiments, the RF power amplifier 100 further includes an input matching circuit 130. The input matching circuit 130 is electrically connected to the input terminal of the amplifier 110 and is used to transmit the RF input signal RFin received from the power supply to the input terminal of the amplifier 110. From another perspective, the input matching circuit 130 is electrically connected to the gate of the transistor TR1 and transmits the RF input signal RFin to the gate of the transistor TR1.

[0138] In some embodiments, the RF power amplifier 100 further includes a DC rejection capacitor C. b The DC blocking capacitor C b Electrically connected to hybrid matching circuit 120 and load Z LOAD And to prevent DC signals from being input to the load Z LOAD .

[0139] In some embodiments, the hybrid matching circuit 120 further includes a compensation circuit 123. The compensation circuit 123 is electrically connected between the first circuit 121 and the second circuit 122, and is used to compensate the harmonic matching network.

[0140] In some embodiments, the compensation circuit 123 may be implemented using an inductor-capacitor resonator (or LC resonator). The LC resonator is used to resonate at the fundamental frequency and correct for offset harmonic loads. The compensation circuit 123 can be used in any RF power amplifier with a first-order or second-order harmonic cancellation configuration.

[0141] In some embodiments, the hybrid matching circuit 120 can be used with III-V semiconductors (e.g., gallium arsenide (GaAs), indium phosphide (InP), or gallium nitride (GaN)), silicon semiconductors, silicon on insulator (SOI), complementary metal-oxide semiconductors (CMOS), silicon-germanium semiconductors (SiGe), and other types of semiconductor process technologies to fabricate corresponding radio frequency integrated circuits (RFICs), radio frequency hybrid integrated circuits (RF Hybrid ICs), or radio frequency discrete applications.

[0142] In some embodiments, the transistor TR1 can be implemented using a semiconductor material with a relatively large fundamental impedance in its intrinsic plane. For example, gallium nitride.

[0143] In some embodiments, some of the passive components included in the hybrid matching circuit 120 can be fabricated using a monolithic microwave integrated circuit (MMIC), while other passive components can be implemented using a discrete substrate, such as a PCB or a laminate.

[0144] In some embodiments, the hybrid matching circuit 120 can also be used in purely discrete RF switched power amplifiers and Doherty power amplifiers.

[0145] Implementation examples of RF power amplifiers with multiple transistors, for example Figure 2A and Figure 2B As shown, where Figure 2A This is a schematic diagram of an RF power amplifier having a power amplifier with multiple transistors according to some embodiments of the present invention, and Figure 2B According to Figure 2A Equivalent circuit diagrams of RF power amplifiers in some embodiments.

[0146] Please refer to Figure 2A The radio frequency power amplifier 200 includes a transistor-based two-stage amplifier (amplifier 210_1 and amplifier 210_2) and a hybrid matching circuit 220. Amplifier 210_1 and amplifier 210_2 are similar to... Figure 1A and Figure 1B The amplifier 110 described in the embodiment includes a first transistor TR1 and a second transistor TR2. The second transistor TR2 and the first transistor TR1 are connected in parallel through a hybrid matching circuit 220, wherein the load Z LOAD It is shared by the first transistor TR1 and the second transistor TR2. From the perspective of the hybrid matching circuit 220, one end of the hybrid matching circuit 220 is electrically connected to the first transistor TR1, and the other end of the hybrid matching circuit 220 is simultaneously electrically connected to the second transistor TR2 and the load Z. LOADFrom the perspective of the equivalent circuit, the first transistor TR1 and the second transistor TR2 can be considered as sharing a common load Z. L The common load Z L It can have a load Z LOAD Different impedances. Under this load Z LOAD This refers to a static load, typically, for example, 50 ohms. In the subsequent descriptions of embodiments herein, the load Z... LOAD and common load Z L All will be represented as "load".

[0147] In some embodiments, the RF power amplifier 200 may be a Doherty power amplifier (hereinafter referred to as "Doherty power amplifier 200"), wherein amplifier 210_1 can be considered as the main amplifier of the Doherty power amplifier 200 (hereinafter referred to as "main amplifier 210_1"), and amplifier 210_2 can be considered as the peak amplifier of the Doherty power amplifier 200 (hereinafter referred to as "peak amplifier 210_2"). From the perspective of the transistor hierarchy, the first transistor TR1 can be considered as the main transistor (hereinafter referred to as "main transistor TR1"), and the second transistor TR2 can be considered as the peak transistor (hereinafter referred to as "peak transistor TR2"). To clearly illustrate the connection relationships between components, the following embodiments will be described from the perspective of transistors. Those skilled in the art can understand the relative relationships between transistors and amplifiers based on the description of the following embodiments.

[0148] Hybrid matching circuit 220 is used to switch the output impedance R of main transistor TR1 and peak transistor TR2. Om and output impedance R Op To match the modulated load Z at the fundamental frequency and resonant frequency respectively. Lm and load Z Lp The impedance. Here, the output impedance of the main transistor TR1 refers to the impedance from the intrinsic plane ITP of the main transistor TR1. m The observed impedance, and the output impedance R of the peak transistor TR2. Op This refers to the intrinsic plane ITP of the peak transistor TR2. p The observed impedance. Furthermore, the hybrid matching circuit 220 is also used to phase shift the output signal of transistor TR1, for example, by approximately 90 degrees. It should be noted that those skilled in the art will understand that the 90-degree phase shift does not mean that the phase change needs to be precisely 90 degrees; in reality, a slight lead or lag is possible.

[0149] The Doherty power amplifier 200 may also include input matching circuits 230_1 and 230_2, a power divider 240, and an impedance inverter network 250. Input matching circuits 230_1 and 230_2 are connected to the gates of the main transistor TR1 and the peak transistor TR2, respectively. The function and operation of input matching circuits 230_1 and 230_2 are similar to those described above. Figure 1A The input matching circuit described in the embodiment will not be repeated here.

[0150] It should be noted that the input matching circuits 230_1 and 230_2 can also be used to provide a phase shift of about 90 degrees between the input signals S1 and S2 to compensate for the phase shift caused by the hybrid matching circuit 220 between the output signals of transistors TR1 and TR2, but the present invention is not limited thereto.

[0151] Power divider 240 is electrically connected to the input terminals of input matching circuits 230_1 and 230_2, and is used to convert the RF input signal RFin into two signals S1 and S2 with a phase difference to compensate for the phase shift caused by the hybrid matching circuit 220. For example, signal S2 may have a phase lag of approximately 90 degrees behind signal S1, and signal S1 may have the same phase as the input RF signal RFin. In some embodiments, power divider 240 may be a 90-degree hybrid divider, a Wilkinson power splitter, or a simple direct-input power divider, etc., but the invention is not limited thereto.

[0152] In some embodiments, the power divider 240 may be implemented using either average input power distribution or non-average input power distribution. Non-average input power distribution can be achieved by transferring more energy to the peak transistor TR2 during load modulation and less energy to the peak transistor TR2 when it is open or unloaded. This non-average input power distribution can be used when the main transistor TR1 and the peak transistor TR2 are designed as a symmetrical Doherty power amplifier. Conversely, average input power distribution can be used when the main transistor TR1 and the peak transistor TR2 are designed with significantly different dimensions (generally, the peak transistor TR2 can be twice the size of the main transistor TR1) and when used in an asymmetrical Doherty power amplifier, but the invention is not limited thereto.

[0153] One end of the impedance inverter network 250 is electrically connected to the peak transistor TR2 and the hybrid matching circuit 220, and the other end of the impedance inverter network 250 is electrically connected to the load Z. LOAD The impedance inverter network 250 is used to convert the load Z LOAD(Generally 50 ohms) converted to load Z L The load Z L The impedance is half the basic impedance of the main transistor TR1. In some embodiments, the impedance inverter network 250 may be, for example, a simple inductor-capacitor network or a distributed quarter-wavelength transmission line, or a lumped or stub type with a characteristic impedance of A quarter-wavelength transmission line.

[0154] Please refer to again Figure 2A and Figure 2B The main transistor TR1 and the peak transistor TR2 have similar characteristics. Figure 1B The equivalent circuit model of transistor TR1 is shown. The main transistor TR1 includes a current source CS1 and a parasitic capacitance C. GD1 Parasitic capacitance C GS1 and parasitic capacitance C DS1 and parasitic inductance L par1 The peak transistor TR2 includes a current source CS2 and a parasitic capacitance C. GD2 Parasitic capacitance C GS2 and parasitic capacitance C DS2 and parasitic inductance L par2 In addition, load Z L It can be considered as a common load of the main transistor TR1 and the peak transistor TR2.

[0155] In this embodiment, the hybrid matching circuit 220, depending on its selected architecture, may include a first circuit 221, at least one second circuit 222, and a third circuit 223. Specifically, the hybrid matching circuit 220 can also be divided into a fully hybrid architecture and a single-sided hybrid architecture. A fully hybrid matching circuit 220 means that the parasitic elements of both the main transistor TR1 and the peak transistor TR2 are used as part of the impedance inverter network; related details will follow. Figure 4A and Figure 4B The specific details are described in the embodiments. The single-sided hybrid matching circuit 220 refers to a circuit in which only one of the parasitic elements of the main transistor TR1 and the peak transistor TR2 is available as part of the impedance inverter network, while the parasitic element of the other of the main transistor TR1 and the peak transistor TR2 that is not used as the impedance inverter network is canceled out by other circuits. The relevant details will be described in detail in other embodiments.

[0156] If a fully hybrid architecture is adopted, the fully hybrid matching circuit 220 includes a first circuit 221, a second circuit 222, and a third circuit 223. The first terminal of the first circuit 221 is electrically connected to the drain of the main transistor TR1, and the second terminal of the first circuit 221 is electrically connected to the drain of the peak transistor TR2 and the load Z. LThe first and second terminals of the first circuit 221 are respectively connected to the second circuit 222 and the third circuit 223. The second circuit 222 is electrically connected between the drain of the main transistor TR1 and the RF ground terminal GND. The third circuit 223 is electrically connected between the drain of the peak transistor TR2 and the RF ground terminal GND.

[0157] First circuit 221, output parasitic elements CDS1 and L of main transistor TR1 par1 And the output parasitic elements CDS2 and L of the peak transistor TR2 par2 Operating as an impedance inverter for the Doherty power amplifier, it provides an impedance inverter network at the base frequency; while the second circuit 222 and the third circuit 223 provide high impedance paths relative to the RF ground terminal GND at the base frequency.

[0158] The second circuit 222 provides an impedance relative to the RF ground terminal GND, so that the output impedance R of the main transistor TR1 is reduced. Om The first target harmonic is at a high or low impedance at the frequency of the fundamental frequency, thereby eliminating the first target harmonic.

[0159] The third circuit 223 is similar to the second circuit 222, providing an impedance relative to the RF ground terminal GND to reduce the output impedance R of the peak transistor TR2. Op The first target harmonic is at a high or low impedance at the frequency of the fundamental frequency, thereby eliminating the first target harmonic.

[0160] Furthermore, in some embodiments, the second circuit 222 and the third circuit 223 may also provide an impedance relative to the RF ground terminal GND, so that the output impedance R Om and R Op The second target harmonic is at a high or low impedance at the frequency of the fundamental frequency, thereby eliminating the second target harmonic.

[0161] Specifically, the fully hybrid matching circuit 220 utilizes the first circuit 121 in conjunction with the parasitic element C of the main transistor TR1. DS1 and L par1 And the parasitic element C of peak transistor TR2 DS2 and L par2 An impedance inverter network is formed at the base frequency, and the second circuit 222 and the third circuit 223 are presented as high impedance relative to the RF ground terminal GND, so they can be regarded as open circuits and electrically isolated from the RF power amplifier 200.

[0162] The fully hybrid matching circuit 220 can also utilize the parasitic element C of the main transistor TR1. DS1 and L par1 Parasitic element C of peak transistor TR2 DS2 and Lpar2 The second circuit 222 and the third circuit 223 form a harmonic matching network at the frequency of the first target harmonic. In other words, the harmonic matching network of the main transistor TR1 can be formed by at least the parasitic element C of the main transistor TR1. DS1 / L par1 The circuit is formed by one of the first circuit 221, the second circuit 222, and the third circuit 223; and the harmonic matching network of the peak transistor TR2 can be formed by at least the parasitic element C of the peak transistor TR2. DS2 and L par2 It is formed by one of the first circuit 221, the second circuit 222, and the third circuit 223.

[0163] Compared to Figure 1A and Figure 1B The hybrid matching circuit 120 shown, and the fully hybrid matching circuit 220 of this embodiment, further utilize parasitic elements from an additional transistor (i.e., peak transistor TR2) as part of the impedance inverter network at the fundamental frequency, and as part of the harmonic matching network at one or more harmonic frequencies.

[0164] In some embodiments, the second circuit 222 and the third circuit 223 include the same circuit architecture.

[0165] If a single-sided hybrid architecture is adopted, the single-sided hybrid matching circuit 220 may include a first circuit 221, a second circuit 222, and a third circuit 223, and also includes one of a parasitic elimination circuit 226 and a parasitic elimination circuit 227. Similar parts of the single-sided hybrid matching circuit 220 can be referred to the above-described embodiment of the fully hybrid matching circuit 220, and will not be repeated here.

[0166] In an embodiment employing a single-sided hybrid architecture, the second circuit 222 is electrically connected between the drain of one of the main transistor TR1 and the peak transistor TR2 and the RF ground terminal GND. The third circuit 223 is electrically connected between the drain of the other of the main transistor TR1 and the peak transistor TR2 and the RF ground terminal GND. Parasitic cancellation circuits 226 / 227 are electrically connected to the drain of either the main transistor TR1 or the peak transistor TR2.

[0167] For example, if the parasitic element of the main transistor TR1 is used as part of the impedance inverter network, then the parasitic cancellation circuit 227 will be employed and electrically connected between the drain of the peak transistor TR2 and the RF ground terminal GND. Therefore, the architecture and size of the first circuit 221 can be designed to match the parasitic capacitance C of the main transistor TR1. DS1 and parasitic inductance L par1 To form an impedance inverter network. Due to the parasitic capacitance C DS2 and parasitic inductance L par2It can be equivalently canceled out by the parasitic elimination circuit 227, therefore the parasitic capacitance C DS2 and parasitic inductance L par2 This can be equivalent to being omitted / eliminated from the impedance inverter network. The impedance inverter network in this example can be considered as... Figure 1A and Figure 1B Impedance inverter network of the embodiment.

[0168] In other implementation examples, if the parasitic elements of the peak transistor TR2 are used as part of the impedance inverter network, then the parasitic cancellation circuit 226 is employed and electrically connected between the drain of the peak transistor TR1 and the RF ground terminal GND. Therefore, the architecture and dimensions of the first circuit 221 can be designed to match the parasitic capacitance C of the peak transistor TR2. DS2 and parasitic inductance L par2 To form an impedance inverter network. Due to the parasitic capacitance C DS1 and parasitic inductance L par1 This can be equivalently canceled out by the parasitic elimination circuit 226, therefore the parasitic capacitance C DS1 and parasitic inductance L par1 This can be considered as something that is omitted or eliminated from the impedance inverter network.

[0169] In an embodiment of the single-sided hybrid matching circuit 220, in addition to the parasitic elements of the main transistor TR1 / peak transistor TR2, the first circuit 221, the second circuit 222, and the parasitic elimination circuits 226 / 227 are also part of the harmonic matching network.

[0170] It should be noted that, Figure 2B The second circuit 222 and the third circuit 223 shown in the embodiment are exemplified by being electrically connected to the main transistor TR1 and the peak transistor TR2, respectively, but the present invention is not limited thereto. In other embodiments, the second circuit 222 may also be electrically connected to the drain of the peak transistor TR2, and the third circuit 223 may be connected to the drain of the main transistor TR1. In still other embodiments, one of the second circuit 222 and the third circuit 223 may be omitted, such that the harmonic matching network is configured only for one of the main transistor TR1 and the peak transistor TR2.

[0171] In some embodiments, the hybrid matching circuit 220 further includes compensation circuits 224 / 225. For example... Figure 2B As shown, compensation circuit 224 is electrically connected between the first terminal of the first circuit 221 and the second circuit 222, and compensation circuit 225 is electrically connected between the second terminal of the first circuit 221 and the third circuit 223. The functions and operation of compensation circuits 224 / 225 are as described above. Figure 1B As described in the examples, they will not be repeated here.

[0172] In summary, the hybrid matching circuits 120 / 220 utilize the parasitic effects of transistors to design an impedance inverter network while simultaneously providing multi-order harmonic cancellation (e.g., second-order and third-order harmonic cancellation), thereby achieving load modulation over a wide bandwidth. This enables high-efficiency switching or continuous-mode amplifier architectures, such as Class F, F... -1 Class-A, Class-J, and other amplifier architectures can be applied to main amplifiers or peak amplifiers. Furthermore, due to the load Z... L The impedance is set to half the base impedance of transistor TR1, which helps the fully hybrid matching network described in this invention to eliminate the need for an additional base matching network (which would typically limit bandwidth). The fully hybrid matching network architecture described in this embodiment also helps to achieve the miniaturization of the overall design of the output matching terminal of the Doherty power amplifier.

[0173] Therefore, the RF power amplifier 100 / 200 of this invention simultaneously provides high bandwidth and high efficiency, thus solving the bandwidth limitation problem caused by the parasitic capacitance and inductance of components in traditional Doherty power amplifiers. Furthermore, compared to designs using complex and bulky harmonic matching networks, the RF power amplifier 100 / 200 of this invention also achieves high efficiency using a miniaturized harmonic matching network. Moreover, by designing the impedance inverter network using the output parasitic capacitance and inductance of transistors, the basic matching network or offset line configuration is omitted, thus solving the bandwidth limitation problem.

[0174] Furthermore, by configuring the second / third circuit, which serves as a harmonic cancellation circuit, closest to the drain of the main transistor / peak transistor and directly connecting it to the drain, the output characteristics can be further improved.

[0175] Furthermore, the size of the overall amplifier architecture can be significantly reduced by employing embodiments of the present invention. The present invention is not limited to using a single-stage main transistor TR1 and peak transistor TR2; multiple cascaded main amplifiers and peak amplifiers can also be combined to achieve high-gain applications, and related embodiments will be described further below. Moreover, the hybrid matching network is not limited to the design illustrated in the embodiments of the present invention; any feasible hybrid matching network architecture can be used as long as it satisfies the main concept of the present invention, namely, using the parasitic effects of transistors to simultaneously achieve load modulation and at least first-order harmonic cancellation.

[0176] It should be noted that the harmonic matching network provided by the hybrid matching circuits 120 / 220 is not limited to the components described above. The actual harmonic matching network may include other unmentioned components. For example, load Z... Lm and load ZLp It can also be considered as part of the harmonic matching network of the main amplifier and the peak amplifier, but due to the load Z Lm and Z Lp Weak coupling, load Z Lm and Z Lp The importance of harmonic matching networks is relatively low.

[0177] Because the hybrid matching network of this invention features a compact structure and small size, it can be easily integrated into applications such as radio frequency multiple-input multiple-output (MIMO). In other embodiments of this invention, the passive components of the harmonic matching network can be matched internally, making the harmonic matching network an equivalent open circuit at the fundamental frequency, thereby achieving the effect of compact overall circuit design and easy integration.

[0178] In the Doherty power amplifier interconnect design of this invention, the fully hybrid matching circuit can include three different types, while the single-sided hybrid matching circuit can include four different types. The choice of type depends on the device's output parasitic capacitance C. DS Is it higher or lower than the equivalent parallel capacitance C of the low-pass π-type lumped or stub quarter-wavelength transmission line used as an impedance inverter network? O Or C OT .

[0179] Since the first circuit 121 / 221 primarily dominates the composition of the impedance inverter network at the fundamental frequency, it will be described as an impedance inverter 121 / 221 in the following description to clearly describe its main function. Similarly, since the second circuit 122 / 222 and the third circuit 223 primarily function as harmonic cancellation networks at the target harmonic frequency, they will be described as harmonic cancellation circuits in the following description. In other words, it should be noted that the terms "first circuit" and "impedance inverter" are interchangeable herein, as are "second / third circuit" and "harmonic cancellation circuit." However, this does not mean that the first circuit / impedance inverter is provided alone as an impedance inverter network. As previously stated, the first circuit is part of the impedance inverter network and the harmonic matching network.

[0180] Figures 3A to 3C According to Figure 1B Circuit diagrams of RF power amplifiers with hybrid matching networks in some embodiments are shown.

[0181] Please refer to Figure 3A ,in Figure 3AA schematic diagram of the impedance inverter 121 and harmonic cancellation circuit 122 is shown. The impedance inverter 121 includes a transmission circuit TC and two reactive elements X. i and X j The transmission circuit TC is electrically connected between the first terminal T1 and the second terminal T2. Reactant element X i Electrically connected between terminal T1 and RF ground GND. Reactant element X j It is electrically connected between the second terminal T2 and the RF ground terminal GND. This is based on the device's parasitic capacitance C. DS The relationship between the parallel capacitance value of the impedance inverter network used and the reactance element X i and X j It can be a capacitive element or an inductive element.

[0182] The harmonic cancellation circuit 122 includes a capacitive element and two inductive elements, wherein the capacitive element is connected in parallel with one of the two inductive elements and in series with the other of the two inductive elements.

[0183] In some embodiments, depending on the type of impedance inverter network used, the transmission circuit TC may include at least one of an inductor and a transmission line.

[0184] In some embodiments, at least one of the capacitive element and the two inductive elements may be configured to be directly connected to the drain of the transistor TR1.

[0185] In some embodiments, one of the capacitive element and the two inductive elements is configured in the circuit layout to be closest to the drain of transistor TR1.

[0186] Next, please refer to Figure 3B ,in Figure 3B Draw Figure 3A Several different implementation examples of the impedance inverter 121 in the embodiments.

[0187] Based on factors affecting the output parasitic capacitance of transistor TR1, such as its manufacturing process, materials, and dimensions, the impedance inverter 121 can be implemented using different architectures, such as impedance inverters 121a to 121d. Each architecture includes a corresponding impedance inverter network IIN, and each impedance inverter network IIN is matched with the output parasitic capacitance C of transistor TR1. DS What is formed.

[0188] In this embodiment, the impedance inverters 121a to 121d are exemplified as single-stage low-pass π-type quarter-wavelength converters / filters, wherein the transmission circuit TC is implemented through an inductor L0 or a transmission line TL0, and is electrically connected to the reactive element X at the second terminal T2. j With capacitor C12 To implement. Based on the output parasitic capacitance C DS Is it greater than the capacitance C of a single-stage low-pass π-type quarter-wavelength converter / filter? 12 The capacitance value is electrically connected to the reactive element X at the first terminal T1. i However, with capacitor C 11 (See impedance inverters 121a and 121c) or inductor L 11 (See impedance inverters 121b and 121d) for implementation. More specifically, a single-stage low-pass lumped π-type quarter-wavelength converter / filter can be implemented using two parallel capacitors C. O and a series inductor L O Composed of two capacitors C, a single-stage low-pass stub π-type quarter-wavelength converter / filter can be formed by two capacitors C. OT It consists of a series transmission line TL0.

[0189] To make the impedance inverter network IIN equal to a single-stage low-pass lumped or stubbed π-type quarter-wavelength transmission line with a 90-degree phase delay, the inductor L0 or transmission line TL0 can be sized based on the following formula:

[0190]

[0191]

[0192] θ O =cos -1 (ω0*C OT *R OPT );

[0193] R in the formula OP Represents the fundamental impedance, ω o C represents the fundamental frequency. OT Z0 represents the capacitance value of the parallel capacitance of a single-stage low-pass stub π-type quarter-wavelength transmission line, Z0 represents the characteristic impedance of the transmission line TL0, and θ0 represents the electrical angle of the transmission line TL0.

[0194] Capacitor C 12 The dimensions can be designed to have a capacitance value C O The capacitance value C O It is calculated based on the fundamental impedance of transistor TR1 and conforms to the following formula: Similarly, capacitor C 12 The dimensions can also be designed to have a capacitance value C OT The capacitance value C OT It is calculated based on the fundamental impedance of transistor TR1, and is consistent with the aforementioned C. O The calculation formulas are different.

[0195] When the output parasitic capacitance C DS The capacitance value is less than the capacitance C. 12 When the capacitance value is [value], the reactance element X i It can be selected with capacitor C 11 To achieve this, so that C 11 and C DS The equivalent capacitance C of both eq It can be equal to the capacitance C 12 The capacitance value. Therefore, in order to meet the above requirements, the capacitance C... 11 The dimensions can be designed to conform to the following formula:

[0196] C 11 =C 12 -C DS ;

[0197] Where C in the formula 11 Indicates the first capacitor C 11 The capacitance value.

[0198] When the output parasitic capacitance C DS The capacitance value is greater than the capacitance C. 12 When the capacitance value is [value], the reactance element X i It can be selected with inductance L 11 To achieve this, so that L 11 and C DS The equivalent capacitance C of both eq It can be equal to the capacitance C 12 The capacitance value.

[0199]

[0200] Where L 11 Indicates the first inductance L 11 The inductance value.

[0201] In short, a dual-port impedance inverter network is used in the design of the hybrid matching circuit 220, which includes at least one parallel capacitor (e.g., C) located on the side closest to the transistor. 11 ) or parallel inductors (e.g., L) 11 The parallel capacitor or inductor is connected in series with the transmission circuit TC. The parallel capacitor / inductor is used to absorb the parasitic capacitance and inductance of the transistor. Four typical configurations are illustrated. In configuration 121a, the two terminals T1 and T2 are respectively connected to the parallel capacitor C. 11 and C 12 In configuration 121b, only terminal T2 is connected to the parallel capacitor C. 12 The connection terminal T1 is connected to a parallel inductor (e.g., L). 11Configuration 121c is similar to 121a, and configuration 121d is similar to 121b, the difference being that the inductor L0 shown in configurations 121a / 121b is replaced by a transmission line TL0 in configurations 121c / 121d, and the capacitance value C shown in configurations 121a / 121b is... O In the configuration of 121c / 121d, the capacitor value C will be used. OT replace.

[0202] In some embodiments, the impedance inverter network IIN can be implemented using a quarter-wavelength transmission line, the equivalent circuit architecture of which is equivalent to... Figure 3B The single-stage low-pass π-type filter shown. The dimensions of the quarter-wavelength transmission line can be designed according to the following formula:

[0203]

[0204] Z in the formula T The characteristic impedance of a quarter-wavelength transmission line, and Z LOAD This represents the impedance of the load.

[0205] It should be noted that, although Figure 3A and Figure 3B The embodiment illustrates a single-stage low-pass π-type quarter-wavelength filter as an example, but the invention is not limited thereto. For example, the impedance inverter network can be an n-stage low-pass lumped quarter-wavelength converter, a quarter-wavelength stub transmission line, a quasi-lumped nth-order low-pass filter, a quasi-lumped nth-order low-pass quarter-wavelength converter, a quasi-lumped low-pass Chabyshev converter, a quasi-lumped low-pass Chabyshev quarter-wavelength converter, a quasi-lumped low-pass quarter-wavelength step impedance converter, and a quasi-lumped low-pass quarter-wavelength step impedance quarter-wavelength converter, etc., as long as the impedance inverter network uses a low-pass network with a parallel capacitor architecture to absorb device parasitic effects, and the transmission circuit TC is as follows... Figure 3B If the structures shown are located in the middle, they all fall within the scope of the architecture covered by this invention.

[0206] Please refer to again Figure 3C ,in Figure 3C Several different embodiments of the harmonic cancellation circuit 122 are illustrated.

[0207] The harmonic cancellation circuit 122 can be selectively implemented as harmonic cancellation circuits 122a to 122j, wherein harmonic cancellation circuits 122a to 122f can be used to provide low impedance at the second harmonic frequency and high impedance at the third harmonic frequency, and harmonic cancellation circuits 122g to 122j can be used to provide high impedance at the second harmonic frequency, low impedance at the second harmonic frequency, or low impedance at the third harmonic frequency.

[0208] For harmonic cancellation circuits 122a to 122f, the harmonic cancellation circuit includes a first capacitive element (e.g., capacitor C). 21 ), the first inductive element (e.g., inductor L) 21 or transmission line TL 21 ) and a second inductive element (e.g., inductor L) 22 or transmission line TL 22 The first inductive element is connected in series with the first capacitive element and is located between the drain Td of transistor TR1 and the RF ground terminal GND. One end of the second inductive element is electrically connected to the drain Td of transistor TR1 and the first terminal T1, and the other end of the second inductive element is electrically connected to the RF ground terminal GND.

[0209] The dimensions of the first capacitive element and the first inductive element are designed to provide a low-impedance path to the radio frequency ground (GND) at the frequency of the first target harmonic of the fundamental frequency. The dimensions of the second inductive element are designed such that the first capacitive element, the first inductive element, and the second inductive element can be equivalent to an open circuit relative to the radio frequency ground (GND) at the fundamental frequency.

[0210] Specifically, in the harmonic cancellation circuit 122a, the capacitive element can utilize capacitor C. 21 To achieve this, the first inductive element can utilize inductance L 21 This is achieved, and the second inductive element can utilize inductance L. 22 This is achieved through a harmonic cancellation network, which includes a parallel inductor-capacitor network, wherein the parallel inductor-capacitor network consists of series-connected inductors L... 21 and capacitor C 21 Composed of.

[0211] Capacitor C 21 and inductor L 21 and L 22 The dimensions can be designed according to the following formula:

[0212]

[0213]

[0214] Where C in the formula 21 Indicates capacitance C 21 The capacitance value, L 21 Inductance L 21 The inductance value, L 22 Indicating inductance L 22 The inductance value, and n represents the harmonic order.

[0215] By adopting the above settings, capacitor C 21 and inductor L 21The series circuit provides impedance to the first terminal T1, which can be bypassed by the inductor L at the fundamental frequency. 22 The harmonic cancellation circuit 122a is thus offset, making it an open circuit relative to the RF ground terminal GND. Therefore, at the fundamental frequency, the harmonic cancellation circuit 122a does not affect the function of the impedance inverter network.

[0216] Capacitor C 21 and inductor L 21 The series circuit also establishes a low-impedance path at the second harmonic frequency, making the equivalent circuit observed from the intrinsic plane of transistor TR1 a short circuit, i.e., the output impedance R of transistor TR1. O For low impedance. The above formula can be simplified to the second harmonic frequency as follows:

[0217]

[0218] L 22 =3L 21 .

[0219] Inductor L 21 The inductance value can be calculated using the design boundary condition equations for a Class F amplifier, such that the capacitance C... 21 and inductor L 21 and L 22 An impedance relative to the RF ground terminal GND can be provided so that the equivalent circuit observed from the intrinsic plane of transistor TR1 at the third harmonic frequency can be considered an open circuit, i.e., the output impedance R of transistor TR1. O It has high impedance at the third harmonic frequency. Therefore, the operating modes of the Class F amplifier, namely second harmonic short-circuit and third harmonic open-circuit operation, can be implemented.

[0220] Harmonic cancellation circuits 122b to 122d are similar to harmonic cancellation circuit 122a, with the main difference being the inductor L in harmonic cancellation circuit 122a. 21 / L 22 In other embodiments, it will be used as a transmission line TL 21 / TL 22 Instead, the transmission line TL 21 / TL 22 It can be regarded as related to inductance L 21 / L 22 Equivalent. In other words, the parallel inductor L 21 The characteristic impedance Z can be used 21 and electrical angle θ 21 Parallel transmission line TL 21 To replace, and parallel inductor L 22 The characteristic impedance Z can be used 22 and electrical angle θ 22 Parallel transmission line TL22 To replace it. Other related parts can be referred to the relevant description of the above embodiment of harmonic cancellation circuit 122a, and will not be repeated here.

[0221] Specifically, in the harmonic cancellation circuit 122b, the first inductive element can utilize the transmission line TL. 21 To implement, in which the transmission line TL 21 The dimensions can be designed based on the following formula:

[0222] Z 21 tan(θ 21 )=ω0L 21 ;

[0223] Z in the formula 21 Represents transmission line TL 21 The characteristic impedance, and θ 21 Represents transmission line TL 21 The electrical angle.

[0224] In the harmonic cancellation circuit 122c, the second inductive element can utilize the transmission line TL. 22 To implement, in which the transmission line TL 22 The dimensions can be designed based on the following formula:

[0225] Z 22 tan(θ 22 )=ω0L 22 ;

[0226] Z in the formula 22 Represents transmission line TL 22 The characteristic impedance, and θ 22 Represents transmission line TL 22 The electrical angle.

[0227] In the harmonic cancellation circuit 122d, the first inductive element and the second inductive element can be respectively connected via transmission line TL. 21 and TL 22 To implement. Regarding transmission lines TL 21 and TL 22 The design criteria can be referred to the above description, and will not be repeated here.

[0228] Harmonic cancellation circuit 122e is similar to harmonic cancellation circuit 122a, the difference being that the first inductive element in harmonic cancellation circuit 122e is an inductor L. 21 'and transmission line TL 21 To implement this using a combination of ', where inductor L 21 'and transmission line TL 21 The equivalent impedance of ' is equal to the inductance L that is replaced. 21 The impedance. Therefore, the inductance L21 'and transmission line TL 21 The dimensions of ' can be designed according to the following formula:

[0229] Z 21 'tan(θ) 21 ′)+ω0L 21 ′=ω0L 21 ;

[0230] Z in the formula 21 'Represents transmission line TL 21 'characteristic impedance, θ 21 ′ represents transmission line TL 21 ' electrical angle, and L 21 'Represents inductance L 21 The inductance value of '.

[0231] The harmonic cancellation circuit 122f is similar to the harmonic cancellation circuit 122e, the difference being that the second inductive element in the harmonic cancellation circuit 122f is an inductor L. 22 'and transmission line TL 22 To implement this using a combination of ', where inductor L 22 'and transmission line TL 22 The equivalent impedance of ' is equal to the inductance L that is replaced. 22 The impedance. Therefore, the inductance L 22 'and transmission line TL 22 The dimensions of ' can be designed according to the following formula:

[0232] Z 22 'tan(θ) 22 ′)+ω0L 22 ′=ω0L 22 ;

[0233] Z in the formula 22 'Represents transmission line TL 22 'characteristic impedance, θ 22 ′ represents transmission line TL 22 ' electrical angle, and L 22 'Represents inductance L 22 The inductance value of '.

[0234] For harmonic cancellation circuits 122g to 122j, the harmonic cancellation circuit includes a first inductive element (e.g., inductor L). 21 or transmission line TL 21 ) and inductor-capacitor resonant circuits (e.g., capacitor C) CH Paired with inductor L CH / Transmission Line TL CHThe inductor-capacitor resonant circuit (hereinafter referred to as the LC resonant circuit) is connected in series with the first inductive element and is located between the drain Td of transistor TR1 and the radio frequency ground GND. The LC resonant circuit includes a second inductive element (e.g., inductor L) connected in parallel. CH / Transmission Line TL CH ) and the first capacitive element (e.g., capacitor C) CH ).

[0235] The first and second inductive elements are used to provide a second harmonic high impedance, a second harmonic low impedance, or a third harmonic low impedance on the intrinsic plane of transistor TR1.

[0236] In other words, the inductance value of the first inductive element is configured to present the high impedance required to eliminate the second harmonic on the intrinsic plane of the transistor connected to the harmonic cancellation network.

[0237] Specifically, in the harmonic cancellation circuit 122g, the first inductive element can utilize inductance L 21 To implement this, the second inductive element can utilize inductance L. CH To implement this, and the first capacitive element can utilize capacitor C. CH To implement.

[0238] In this embodiment, the inductor L CH and capacitor C CH An LC resonant circuit is formed and resonates at the fundamental frequency, causing the entire harmonic cancellation network to present a high impedance relative to the RF ground terminal GND at the fundamental frequency, thus not affecting the function of the impedance inverter network. To enable the harmonic cancellation network to present a high impedance, the inductor L... CH and capacitor C CH The dimensions can be designed according to the following formula:

[0239]

[0240] L in the formula CH Represents inductance L CH The inductance value, and C CH Represents capacitor C CH The capacitance value.

[0241] The impedance elimination circuits 122h to 122j are similar to the aforementioned impedance elimination circuit 122g, except that the inductor L shown in the impedance elimination circuit 122g is... 21 / L CH In other embodiments, it will be used as a transmission line TL 21 / TL CH Replacement, in which transmission line TL 21 / TL CH It can be equivalent to an inductor L 21 / L22 .

[0242] In some embodiments, the capacitor elements included in the impedance inverter 121 and the harmonic cancellation circuit 122 may be implemented using static capacitors or variable capacitors, but the invention is not limited thereto.

[0243] Figure 4A and Figure 4B According to Figure 2B Circuit diagrams of RF power amplifiers with fully hybrid matching networks in some embodiments.

[0244] Please refer to Figure 4A ,in Figure 4A The diagram illustrates the impedance inverter 221, harmonic cancellation circuit 222, and harmonic cancellation circuit 223 within the fully hybrid matching circuit 220. The impedance inverter 221 includes a transmission circuit TC and two reactive elements X. i and X j One end of the transmission circuit TC is electrically connected to the drain Td1 of the main transistor TR1 via a first terminal T1, and the other end of the transmission circuit TC is electrically connected to the drain Td2 of the peak transistor TR2 via a second terminal T2. In other words, the transmission circuit TC is electrically connected between the first terminal T1 and the second terminal T2, and is also located between the main transistor TR1 and the peak transistor TR2. Reactant element X i Electrically connected between terminal T1 and RF ground GND. Reactant element X j Electrically connected between the second terminal T2 and the radio frequency ground terminal GND.

[0245] Harmonic cancellation circuit 222 and harmonic cancellation circuit 223 each include a capacitive element and two inductive elements, wherein the capacitive element is connected in parallel with one of the two inductive elements and in series with the other of the two inductive elements.

[0246] In some embodiments, one of the capacitive element and one of the two inductive elements in harmonic cancellation circuit 222 may be configured to be directly connected to the drain of transistor TR1. Similarly, one of the capacitive element and one of the two inductive elements in harmonic cancellation circuit 223 may be configured to be directly connected to the drain of transistor TR2.

[0247] In some embodiments, one of the capacitive element and one of the two inductive elements in the harmonic cancellation circuit 222 may be configured in the circuit layout to be closest to the drain Td1 of the transistor TR1. Similarly, one of the capacitive element and one of the two inductive elements in the harmonic cancellation circuit 223 may be configured in the circuit layout to be closest to the drain Td2 of the transistor TR2.

[0248] Please refer to again Figure 4B ,in Figure 4B for Figure 4A Several different implementation examples of the impedance inverter 221 shown in the embodiments.

[0249] Based on factors affecting the output parasitic capacitance of transistors TR1 and TR2, such as their manufacturing process, materials, and dimensions, the impedance inverter 121 can be implemented using different architectures, such as impedance inverters 221a to 221d. Each architecture includes a corresponding impedance inverter network IIN, and each impedance inverter network IIN is matched with the output parasitic capacitance C of transistors TR1 and TR2. DS1 and parasitic capacitance C DS2 What is formed.

[0250] In this embodiment, impedance inverters 221a to 221d are exemplified as single-stage low-pass π-type quarter-wavelength converters / filters, wherein in this example, the transmission circuit TC can be via... Figure 3B The implementation is carried out using the type described in the embodiments.

[0251] Based on the output parasitic capacitance C DS1 Is it greater than the capacitance value of capacitor C1 (which may be C)? O Or C OT The reactive element X is electrically connected to the first terminal T1. i Capacitor C can be used 11 (See impedance inverters 221a and 221c) or inductor L 11 (See impedance inverters 221b and 221d) for implementation. Similarly, based on the output parasitic capacitance C DS2 Is it greater than the capacitance value of capacitor C2 (which may be C)? O Or C OT The reactive element X is electrically connected to the second terminal T2. j Capacitor C can be used 12 (See impedance inverters 221b and 221a) or inductor L 12 (See impedance inverters 221d and 221c) to implement this.

[0252] The design basis for this embodiment and the foregoing Figure 3B The embodiment is similar, wherein capacitor C 11 and C 12 The dimensions can be designed according to the following formula:

[0253] C 11 =C1-C DS1 ;

[0254] C 12 =C2-C DS2 ;

[0255] The definition of each element in the formula can be referred to the definition in the aforementioned embodiment, and here C1 can be equal to C2.

[0256] In addition, inductor L 11 and L 12 The dimensions can be designed according to the following formula:

[0257]

[0258]

[0259] In short, the impedance inverter 221 also includes a parallel capacitor (e.g., C) at the end near the connecting transistors TR1 / TR2. 11 / C 12 ) and parallel inductors (e.g., L) 11 / L 12 At least one of the following, and it is also connected in series with the transmission circuit TC. The parallel capacitor / inductor is used to absorb the parasitic capacitance and inductance of the transistor. Four typical configurations are shown in the figure. In configuration 121a, the two connection terminals T1 and T2 are respectively connected to the parallel capacitor C. 11 and C 12 In configuration 221b, only terminal T2 is connected to the parallel capacitor C. 12 The connection terminal T1 is connected to the parallel inductor L. 11 In configuration 221c, only terminal T1 is connected to the parallel capacitor C. 11 The connection terminal T2 is connected to the parallel inductor L. 12 In configuration 221d, the two connection terminals T1 and T2 are respectively connected to parallel inductors L. 11 and L 12 It should be noted that the inductors (e.g., L11 / L12) used here are merely for describing an embodiment of the impedance inverter 221 architecture, but the invention is not limited thereto. The inductors can utilize the aforementioned... Figure 3B The transmission line described in the embodiment is used instead.

[0260] In some embodiments, the impedance inverter network IIN can be implemented using a quarter-wavelength transmission line. At the fundamental frequency, the load Z L The impedance can be selected to be half of the fundamental impedance observed in the intrinsic plane of the transistor TR1, while the size of the quarter-wavelength transmission line can be set to have a characteristic impedance equal to the fundamental impedance.

[0261] The design guidelines for harmonic cancellation circuits 222 and 223 can be found in the above description. Figure 3C The description of the embodiments will not be repeated here.

[0262] For the Doherty power amplifier (e.g., RF power amplifier 200) in the embodiments of the present invention, neither the main transistor TR1 nor the peak transistor TR2 needs to use a basic matching network, which enables miniaturized circuit design and solves the bandwidth limitation problem caused by the complex basic matching network used for the main transistor TR1 and the peak transistor TR2.

[0263] The fully hybrid matching network utilizes the output parasitic capacitance and output parasitic inductance of both the main transistor and the peak transistor to design the impedance inverter load modulation network, and simultaneously provides harmonic load cancellation, such as second harmonic cancellation and third harmonic cancellation. The parasitic capacitance may include the drain-to-source capacitance C. DS The Miller capacitance is located between the drain and source. Therefore, switching or continuous-state amplifier architectures, such as Class F, F... -1 Class-A, Class-J, and other amplifier architectures can be applied to the main amplifier or peak amplifier of a switching power amplifier.

[0264] All the embodiments described above provide a particular fully hybrid matching circuit 220 that not only provides load modulation functionality but also enables switching power amplifiers using the fully hybrid matching circuit 220 to achieve very high efficiency over a wide bandwidth. Because no additional base matching network or offset line is required, the fully hybrid matching network allows for a compact circuit layout and facilitates circuit miniaturization, a characteristic crucial for radio frequency integrated circuits (RFICs).

[0265] Figure 4C and Figure 4D It is based on Figure 2B Circuit diagrams of RF power amplifiers with single-sided hybrid matching networks in some embodiments.

[0266] The single-sided hybrid matching network uses either a master transistor or a peak transistor, but not both, and the output parasitic capacitance (drain-source capacitance C) is... DS The Miller capacitance between the drain and source of the component and the output parasitic inductance (series drain inductance L) par ) serves as an impedance inverter load modulation network and provides harmonic load cancellation (e.g., Class F, F) for the main and / or peaking elements of a switching power amplifier, such as the second and third harmonics. -1 Class, J class or continuous F class, continuous F -1 Class, continuous J class).

[0267] Please refer to Figure 4CThe Doherty power amplifier 200' includes the main transistor TR1, the peak transistor TR2, and the single-sided hybrid matching circuit 220', wherein the single-sided hybrid matching circuit 220' includes the impedance inverter 221, the harmonic cancellation circuit 222, and the parasitic cancellation circuit 227.

[0268] This embodiment is similar to Figure 4A The illustrated embodiment is shown, therefore similar parts will not be described again. It is similar to... Figure 4A The difference lies only in the parasitic element C of the main transistor. DS1 and L par1 It is used to design the impedance inverter network, and the parasitic elimination circuit is introduced to eliminate the output parasitic effect on the peak side.

[0269] Specifically, the impedance inverter network only uses the parasitic element C output by the main transistor. DS1 and L par1 and reactive element X i X j And the series transmission circuit TC. Based on the parasitic capacitance C of the main element. DS1 The relationship between the equivalent capacitance value used in low-impedance inverter networks and the reactive element X i It can be a capacitive element or an inductive element.

[0270] Parasitic elimination circuit 227 is connected between the drain of the peak transistor TR2 and the radio frequency ground terminal GND, and is used to eliminate parasitic element C. DS2 and L par2 The effect of the drain electrode of the peak transistor TR2, wherein the parasitic elimination circuit 227 is an inductive element.

[0271] For example, parasitic elimination circuit 227 includes a reactive element X CF The drain electrode is connected to the peak transistor TR2 to eliminate parasitic elements C of the peak transistor. DS2 and L par2 Effects of the fundamental frequency.

[0272] Because the output parasitics of the peak transistor TR2 has been X CF To eliminate the parasitic impedance of an inverter network using only one main transistor output, it can be considered as... Figure 3B The impedance inverter network in the two circuits is the same, and the capacitor C is the same. 12 It has a capacitance value that is independent of peak transistor output parasitism.

[0273] In this embodiment, if the peak transistor is Figure 3C If the harmonic cancellation network eliminates the parasitic cancellation circuit 227, then it can be used as part of the harmonic matching network of the peak transistor TR2.

[0274] Please refer to Figure 4D The Doherty power amplifier 200” includes the main transistor TR1, the peak transistor TR2, and the single-sided hybrid matching circuit 220”, wherein the single-sided hybrid matching circuit 220” includes the impedance inverter 221, the harmonic cancellation circuit 223, and the parasitic cancellation circuit 226.

[0275] This embodiment is similar to Figure 4C The illustrated embodiment is shown, therefore similar parts will not be described again. It is similar to... Figure 4C The difference lies in the peak transistor parasitic element C DS2 and L par2 It was used to design the impedance inverter network, and the parasitic elimination circuit was modified to eliminate the parasitic effects on the main output.

[0276] Specifically, the impedance inverter network only uses the peak transistor output parasitic element C. DS2 and L par2 and reactive element X i X j And the series transmission circuit TC. Based on the parasitic capacitance C of the peak element. DS2 The relationship between the equivalent capacitance value used in low-impedance inverter networks and the reactive element X j It can be a capacitive element or an inductive element.

[0277] Parasitic elimination circuit 226 is connected between the drain of the main transistor TR1 and the radio frequency ground terminal GND, and is used to eliminate parasitic element C. DS1 and L par1 The effect of the drain electrode of the main transistor TR1, wherein the parasitic elimination circuit 226 is an inductive element.

[0278] Because the output parasitics of the main transistor TR1 has been X CF To eliminate the parasitic impedance of an inverter network using only a single peak transistor output, it can be considered as... Figure 3B The impedance inverter network is the same, only the definitions of terminals T1 and T2 are interchanged.

[0279] In this embodiment, if the main transistor is Figure 3C If the harmonic cancellation network eliminates the harmonics, then the parasitic cancellation circuit 226 can be used as part of the harmonic matching network of the main transistor TR1.

[0280] Figure 5A This diagram illustrates a comparison of the characteristics of a conventional Doherty power amplifier and a Doherty power amplifier with a hybrid matching network according to an embodiment of the present invention. Figure 5BThis is a schematic diagram comparing the characteristics of a forward and reverse Doherty power amplifier with a hybrid matching network according to an embodiment of the present invention.

[0281] Please refer to Figure 5A ,in Figure 5A The illustration adopts the method of the present invention. Figure 2A The Doherty power amplifier using the hybrid matching network in this embodiment and the conventional Doherty power amplifier both exemplify a Class F harmonic cancellation architecture with second and third harmonic load cancellation. This embodiment simulates a large signal with 6dB power backoff, and the results clearly show that the Doherty power amplifier of this embodiment exhibits a significant improvement in bandwidth compared to the conventional power amplifier. Furthermore, the peak power of the Doherty power amplifier of this embodiment remains approximately the same as that of the conventional Doherty power amplifier. The characteristic improvements shown in the above simulation results can also be observed in the simulation results of other embodiments of this invention.

[0282] Although the output power (approximately 33.4 dBm) exhibited by the Doherty power amplifier of this embodiment and the conventional Doherty power amplifier at an operating frequency of 5.8 GHz demonstrates a high 6 dB power back-off power conversion efficiency (approximately 66–68%), the circuit of this embodiment provides 18–20% fractional bandwidth (FBW) compared to the conventional circuit which only provides 7–8%. The simulation results used in this study employ gallium nitride (GaN) process components as examples to simulate the characteristic improvements of this embodiment. However, similar characteristic improvements can be achieved in group III-V semiconductors (e.g., gallium arsenide (GaAs), indium phosphide (InP), or gallium nitride (GaN)), silicon semiconductors, complementary metal-oxide-semiconductor (CMOS), silicon-on-insulator (SOI), silicon-germanium (SiGe), and other semiconductor process technologies used in monolithic microwave integrated circuits, hybrid ICs, or other types of distributed radio frequency circuit applications. The efficiency curve PAE_n of the Doherty power amplifier with 6dB power back-off in this embodiment of the invention and the efficiency curve PAE_o of the conventional Doherty power amplifier with 6dB power back-off show significant differences under frequency sweep results. Furthermore, the output power Pout_n of the Doherty power amplifier with 6dB power back-off in this embodiment of the invention and the output power curve Pout_o of the conventional Doherty power amplifier with 6dB power back-off also show significant differences.

[0283] Furthermore, corresponding to the input power back-off, this embodiment of the invention also provides perfect 6dB output power back-off for load modulation, with a maximum power added efficiency (PAE) of 68.343%. The output power is 38.933dBm at peak, and 32.881dBm after a 6dB back-off from peak. The power gain is 7.31dB at peak, and 9.294dB after a 6dB back-off from peak.

[0284] The intrinsic drain voltage of the main transistor reaches a peak of 55.618V (almost twice the drain bias of a Class F design) and is almost square-wave shaped; while the intrinsic drain current of the main transistor reaches a peak of 0.24A and is almost sine-wave shaped under the 6dB back-off operation of the Doherty power amplifier. A comparison of the main transistor's dynamic load line and DC load line shows that the traditional Class F load line is biased at 28V in Class AB mode. When the peak drain current of the peak transistor reaches 0.038A, the peak transistor is about to turn on, and the dynamic load line will transition to a rising state in Class C mode biased at 28V.

[0285] The peak intrinsic drain voltage of the main transistor is 57.87V (almost twice the drain bias of a Class F design) and is almost square-wave shaped; while the peak intrinsic drain current is 0.55A and is half-sine-wave shaped. During peak power operation, the Doherty power amplifier exhibits some harmonics due to gain compression. The dynamic load line of the main transistor corresponding to the DC load line shows that the Doherty power amplifier operates at 28V bias in Class AB mode during peak operation. The peak transistor's intrinsic drain voltage has a peak value of 63.032V (almost twice the drain bias of a Class F design) and is almost square-wave shaped; while the peak transistor's intrinsic drain current reaches 0.5A and is half-sine-wave shaped. During peak power operation, the Doherty power amplifier exhibits some harmonics due to gain compression. The comparison between the peak transistor dynamic load line and the DC load line shows that the traditional Class F load line is biased at 28V in Class C mode.

[0286] Please refer to Figure 5B ,in Figure 5B The illustration adopts the method of the present invention. Figure 2A The embodiment of the forward Doherty power amplifier 200 with a single-sided hybrid matching network and as described in the present invention Figure 9AA comparative schematic diagram of the characteristics of the inverted Doherty power amplifier with a single-sided hybrid matching network in the embodiment is shown, both employing harmonic load cancellation using second and third harmonic loads (in this case, Class F harmonic cancellation). The 6dB power back-off of their large-signal simulation results clearly demonstrate that both the forward and inverted Doherty power amplifiers of this embodiment offer approximately a 20% improvement in bandwidth. However, at the operating frequency, the efficiency curve PAE_IDPA of the inverted Doherty power amplifier with 6dB power back-off is approximately 68.5%, while the efficiency curve PAE_DPA of the forward Doherty power amplifier with 6dB power back-off is approximately 66.5%. This slight increase in efficiency is due to the low leakage current from the main amplifier to the peak amplifier during the back-off operation of the inverted Doherty power amplifier. The Pout_IDPA of the inverted Doherty power amplifier and the Pout_DPA of the forward Doherty power amplifier exhibit similar 3dB fractional bandwidth. It is worth noting that these results may vary with appropriate component design and should not be taken as general conclusions in comparisons between inverted and forward Doherty power amplifiers using the hybrid matching circuit of the present invention.

[0287] Figure 6 This is a flowchart illustrating the steps of a method for manufacturing a Doherty power amplifier according to an embodiment of the present invention.

[0288] Please refer to Figure 6 The method for manufacturing a Doherty power amplifier can be used to manufacture the Doherty power amplifier described in the above embodiments of the present invention. The method includes the following steps: providing at least one main amplifier operating at a base frequency (step S110); providing at least one peak amplifier connected in parallel with the at least one main amplifier and sharing a common load or a load (step S120); and connecting a first hybrid matching circuit between the output of the at least one main amplifier and the output of the at least one peak amplifier (step S130).

[0289] In connecting the first hybrid matching circuit (step S130), a first circuit may be connected between the output of the at least one main amplifier and the output of the at least one peak amplifier. This first circuit is part of an impedance inverter network of the first hybrid matching circuit of the Doherty power amplifier.

[0290] Specifically, in connecting the first hybrid matching circuit (step S130), the following steps can be performed: connecting a second circuit between the output of the at least one main amplifier and an RF ground terminal; connecting a third circuit between the output of the at least one peak amplifier and the RF ground terminal; determining the component type and size included in the first circuit to construct an impedance inverter network using an output parasitic element of one of the main amplifiers and the peak amplifier at the fundamental frequency; and determining the component size included in the second circuit and the third circuit to utilize the impedance provided by at least the first circuit, the second circuit, and the third circuit so that the impedance observed from the intrinsic plane of the main amplifier and the peak amplifier is one of a high impedance and a low impedance, thereby eliminating at least one of the second and third harmonics of the fundamental frequency.

[0291] Furthermore, in providing at least one peak amplifier (step S120), at least two peak amplifiers can be provided. The method may further include connecting at least one additional hybrid matching circuit between the outputs of the at least two peak amplifiers, such that any two of the at least two peak amplifiers are associated with the at least one hybrid matching circuit, wherein the first hybrid matching circuit and the first additional hybrid matching circuit are electrically connected and share the common load. The step of connecting at least one additional hybrid matching circuit includes connecting a first circuit between the output of the at least one main amplifier and the outputs of the at least two peak amplifiers, wherein the first circuit is part of an impedance inverter network of the at least one additional hybrid matching circuit of the Doherty power amplifier. Therefore, this method can also be used to manufacture, for example... Figure 10A The diagram shows an N-channel Doherty power amplifier.

[0292] Please refer to Figure 7The method for manufacturing a Doherty power amplifier can be used to manufacture the Doherty power amplifier described in the above embodiments of the present invention, particularly the inverted Doherty power amplifier described in the above embodiments of the present invention. The method includes the following steps: providing at least one main amplifier operating at a fundamental frequency (step S210); providing at least one peak amplifier connected in parallel with the at least one main amplifier and sharing a common load or a load (step S220); connecting a first hybrid matching circuit between the output of the at least one main amplifier and the output of the at least one peak amplifier (step S230); and connecting a second hybrid matching circuit or an additional impedance inverter network and a parasitic cancellation circuit between the output of the at least one main amplifier and the output of the at least one peak amplifier (step S240). In this method, the first hybrid matching circuit and the second hybrid matching circuit, or the first hybrid matching circuit, the at least one additional hybrid matching circuit, and the parasitic cancellation circuit, are connected together by the impedance inverter network and share the common load.

[0293] In this method, the first hybrid matching circuit and the second hybrid matching circuit are connected together via an impedance inverter network and share the common load. The impedance inverter network prevents signal leakage between the two transistors when one of the transistors is turned off. The impedance inverter network can be at least one of the following architectures: a quarter-wavelength converter, an n-order high-pass quarter-wavelength converter, an n-order low-pass quarter-wavelength converter, an n-stage low-pass lumped quarter-wavelength converter, an n-stage high-pass lumped quarter-wavelength converter, a quarter-wavelength stub transmission line, a quasi-lumped n-order low-pass filter, a quasi-lumped n-order high-pass filter, a quasi-lumped n-order low-pass quarter-wavelength converter, a quasi-lumped low-pass Chabyshev converter, a quasi-lumped low-pass Chabyshev quarter-wavelength converter, a quasi-lumped low-pass quarter-wavelength step impedance converter, a quasi-lumped low-pass quarter-wavelength step impedance quarter-wavelength converter, a quasi-lumped n-order high-pass quarter-wavelength converter, a quasi-lumped high-pass Chabyshev converter, a quasi-lumped high-pass Chabyshev quarter-wavelength converter, a quasi-lumped high-pass quarter-wavelength step impedance converter, a quasi-lumped high-pass quarter-wavelength step impedance quarter-wavelength converter, and a combination of low-pass and high-pass lumped or distributed quarter-wavelength converters.

[0294] In connecting the first hybrid matching circuit (step S230), a first circuit can be connected between the output of the at least one main amplifier and the output of the at least one peak amplifier. This first circuit serves as part of an impedance inverter network of the first hybrid matching circuit of the Doherty power amplifier. In connecting a second hybrid matching circuit (step S240), a first circuit can also be connected between the output of the at least one main amplifier and the output of the at least one peak amplifier. This first circuit of the second hybrid matching circuit serves as part of an impedance inverter network of the second hybrid matching circuit of the Doherty power amplifier.

[0295] according to Figure 7 The method shown can manufacture Figures 8A to 8E The Doherty power amplifier (i.e., the inverted Doherty power amplifier). Details of the impedance inverter network 300 have been described previously, therefore... Figure 7 The details will not be elaborated further. When the hybrid matching circuit is not used in at least one of the main amplifier or the peak amplifier, the additional impedance inverter network 300' can be used as the output matching for at least one of the main amplifier or the peak amplifier. The architecture for designing the additional impedance inverter network 300' is similar to that of the impedance inverter network 300, and therefore will not be elaborated further. Furthermore, if the additional impedance inverter network utilizes component parasitics, it will become as follows: Figure 8D and Figure 8E This is a part of the hybrid matching circuit shown. Figures 9A to 9E Display respectively Figures 8A to 8E The detailed components are similar to those of the components with similar numbers in the previous embodiments, which provide similar functions and will not be described in detail here.

[0296] Furthermore, in providing at least one peak amplifier (step S220), at least two peak amplifiers can be provided. The method may further include connecting at least one additional hybrid matching circuit between the outputs of the at least two peak amplifiers, such that any two of the at least two peak amplifiers are associated with a hybrid matching circuit, wherein the first hybrid matching circuit, the second hybrid matching circuit, and the at least one additional hybrid matching circuit are connected together by the impedance inverter network and share the common load. The step of connecting at least one additional hybrid matching circuit includes connecting a first circuit between the outputs of the at least two peak amplifiers, wherein the first circuit is part of an impedance inverter network of the at least one additional hybrid matching circuit of the Doherty power amplifier. Therefore, this method can also be used to manufacture... Figure 10B The diagram shows an N-channel Doherty power amplifier.

[0297] In both methods described above, connecting the at least one additional hybrid matching circuit includes connecting a second circuit between the outputs of the at least two peak amplifiers. The second circuit is used to provide an impedance relative to an RF ground at a fundamental frequency to eliminate at least one of a second target harmonic and a third target harmonic of the fundamental frequency.

[0298] Although the present invention has been disclosed using the above preferred embodiments, it is not intended to limit the present invention. Any modifications and alterations made by those skilled in the art to the above embodiments without departing from the spirit and scope of the present invention shall still fall within the technical scope protected by the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A radio frequency power amplifier, characterized in that, Suitable for operation at the base frequency and for electrical connection to a load, the radio frequency power amplifier includes: At least one transistor, wherein each transistor has an input terminal and an output terminal; and At least one hybrid matching circuit is electrically connected between the output terminal of one of the at least one transistors and the load, wherein the at least one hybrid matching circuit includes: A first circuit, wherein a first terminal is electrically connected to the output terminal of the corresponding transistor, and a second terminal is electrically connected to the load; and A second circuit is electrically connected between the output terminal of the corresponding transistor and a radio frequency ground terminal. The first circuit and an output parasitic element of the corresponding transistor together function as an impedance inverter of the RF power amplifier at the base frequency to provide an impedance inverter network. The output parasitic element includes at least one of an output parasitic capacitance and an output parasitic inductance of the corresponding transistor. The second circuit provides a high-impedance path relative to the RF ground at the base frequency, effectively acting as an open circuit relative to the RF ground, so that the function of the impedance inverter network is unaffected by the second circuit. The second circuit is configured to provide an impedance relative to the radio frequency ground terminal at the frequency of a first target harmonic of the fundamental frequency, such that the impedance observed from the intrinsic plane of the corresponding transistor is either a high impedance or a low impedance, in order to eliminate the first target harmonic. The high impedance refers to an impedance that is large relative to the fundamental impedance observed from the intrinsic plane of the corresponding transistor at the fundamental frequency, and is equivalent to an open circuit; the low impedance refers to an impedance that is small relative to the fundamental impedance, and is equivalent to a short circuit. The corresponding transistor is a transistor electrically connected to the second circuit.

2. The radio frequency power amplifier as described in claim 1, characterized in that, The second circuit is further configured to provide an impedance relative to the radio frequency ground terminal at the frequency of a second target harmonic of the fundamental frequency, such that the impedance observed from the intrinsic plane of the corresponding transistor is the other of the high impedance and the low impedance, in order to eliminate the second target harmonic.

3. The radio frequency power amplifier as described in claim 2, characterized in that, The harmonic matching network of the corresponding transistor is formed at least based on the output parasitic element of the corresponding transistor, the first circuit, and the second circuit; and when the at least one transistor is a plurality of transistors, any two of the plurality of transistors are associated with one of the at least one hybrid matching circuit.

4. The radio frequency power amplifier as described in claim 2, characterized in that, The frequency of the first target harmonic is the second harmonic frequency of the fundamental frequency, and the frequency of the second target harmonic is the third harmonic frequency of the fundamental frequency.

5. The radio frequency power amplifier as described in claim 4, characterized in that, At the second harmonic frequency of the fundamental frequency, the impedance observed from the intrinsic plane of the corresponding transistor is the low impedance; and at the third harmonic frequency of the fundamental frequency, the impedance observed from the intrinsic plane of the corresponding transistor is the high impedance.

6. The radio frequency power amplifier as described in claim 1, characterized in that, The first circuit includes: A transmission circuit is electrically connected between the first end and the second end; A first reactive element, electrically connected between one of the first terminal and the second terminal and the radio frequency ground terminal; and A second reactive element is electrically connected between the other of the first and second terminals and the radio frequency ground terminal.

7. The radio frequency power amplifier as described in claim 6, characterized in that, The transmission circuit includes at least one of an inductor and a transmission line.

8. The radio frequency power amplifier as described in claim 1, characterized in that, The second circuit includes a capacitive element and two inductive elements, wherein the capacitive element is connected in parallel with one of the two inductive elements, and the capacitive element is connected in series with the other of the two inductive elements.

9. The radio frequency power amplifier as described in claim 8, characterized in that, The capacitive element and the inductive element include: A first capacitive element; A first inductive element, connected in series with the first capacitive element, and located between the output terminal of the corresponding transistor and the radio frequency ground terminal; and A second inductive element, one end of which is electrically connected to the output terminal of the corresponding transistor and the first terminal, and the other end of which is electrically connected to the radio frequency ground terminal.

10. The radio frequency power amplifier as described in claim 9, characterized in that, The dimensions of the first capacitive element and the first inductive element are designed to provide a low-impedance path to the radio frequency ground at the frequency of the first target harmonic of the fundamental frequency.

11. The radio frequency power amplifier as claimed in claim 10, characterized in that, The second inductive element is sized such that, at the base frequency, the first capacitive element, the first inductive element, and the second inductive element are equivalent to an open circuit relative to the RF ground terminal.

12. The radio frequency power amplifier as described in claim 11, characterized in that, The first capacitive element is implemented as a capacitor, and the first and second inductive elements are each implemented as a part or integral of at least one of an inductor and a transmission line. The dimensions of the capacitor, the inductor, and the transmission line conform to the following formula: ； ； ； ； ； ； Where C 21 Let L be the capacitance value of the capacitor. 21 L is the inductance value of the inductor used to implement the first inductive element. 22 Z is the inductance value of the inductor used to implement the second inductive element. 21 To implement an inductance value of L 21 The characteristic impedance of the transmission line of the first inductive element, Z 22 To implement an inductance value of L 22 The characteristic impedance of the transmission line of the second inductive element, The fundamental frequency is n, and the harmonic order is n. To implement an inductance value of L 21 The electrical angle of the transmission line of the first inductive element, To implement an inductance value of L 22 The electrical angle of the transmission line of the second inductive element, and For use with inductor L 21 To implement an inductance value of L 21 The characteristic impedance and electrical angle of the transmission line of the first inductive element, and and For use with inductor L 22 To implement the inductance value L 22 The characteristic impedance and electrical angle of the transmission line of the second inductive element.

13. The radio frequency power amplifier as described in claim 1, characterized in that, The impedance inverter includes at least one of the following architectures: an n-stage low-pass lumped quarter-wavelength converter, a quarter-wavelength stub transmission line, a quasi-lumped n-order low-pass filter, a quasi-lumped n-order low-pass quarter-wavelength converter, a quasi-lumped low-pass Chabyshev converter, a quasi-lumped low-pass Chabyshev quarter-wavelength converter, a quasi-lumped low-pass quarter-wavelength step impedance converter, and a quasi-lumped low-pass quarter-wavelength step impedance quarter-wavelength converter.

14. The radio frequency power amplifier as described in claim 8, characterized in that, The capacitive element and the inductive element include: A first inductive element; and An inductor-capacitor resonant circuit is connected in series with the first inductor element and electrically connected between the output terminal of the corresponding transistor and the radio frequency ground terminal, wherein: The inductor-capacitor resonant circuit includes a second inductive element and a first capacitive element connected in parallel. The first inductive element and the second inductive element are used to provide at least one of a second harmonic high impedance, a second harmonic low impedance, and a third harmonic low impedance in the intrinsic plane of the corresponding transistor. The second inductive element and the first capacitive element are used to provide a high-impedance path relative to the RF ground terminal at the fundamental frequency based on the following formula: ； Where L CH C is the inductance value of the second inductive element. CH The capacitance value of the first capacitive element, and This is the fundamental frequency.

15. A method for manufacturing a Doherty power amplifier, characterized in that, include: Provide at least one main amplifier operating at a base frequency; Provide at least one peak amplifier connected in parallel with the at least one main amplifier and sharing a common load or a load; A first hybrid matching circuit is connected between the output of the at least one main amplifier and the output of the at least one peak amplifier, wherein connecting the first hybrid matching circuit includes: A first circuit is connected between the output of the at least one main amplifier and the output of the at least one peak amplifier, and the type and size of the components included in the first circuit are determined, so that at the fundamental frequency, an output parasitic element of one of the main amplifiers and the peak amplifiers together with the first circuit constitutes an impedance inverter network, so that the first circuit is part of the impedance inverter network of the first hybrid matching circuit. A second circuit is connected between the output of the at least one main amplifier and an RF ground terminal; A third circuit is connected between the output of the at least one peak amplifier and the radio frequency ground terminal; The component sizes included in the second and third circuits are determined so that the second and third circuits provide a high impedance relative to the RF ground at the base frequency, which is equivalent to an open circuit relative to the RF ground, so that the function of the impedance inverter network is not affected. as well as The component dimensions included in the second and third circuits are determined so that, utilizing the impedances provided by at least the first, second, and third circuits, the impedance observed from the intrinsic plane of the main amplifier and the peak amplifier is either a high impedance or a low impedance, thereby eliminating either the second or third harmonic of the fundamental frequency. The high impedance refers to an impedance that is large relative to the fundamental impedance observed from the intrinsic plane at the fundamental frequency and is equivalent to an open circuit, while the low impedance refers to an impedance that is small relative to the fundamental impedance and is equivalent to a short circuit.

16. The method of manufacturing a Doherty power amplifier as described in claim 15, characterized in that, Connecting the first hybrid matching circuit further includes: The component dimensions included in the second and third circuits are determined so that the impedances observed from the essential plane of the main amplifier and the peak amplifier are either a high impedance or a low impedance, thereby eliminating the other of the second and third harmonics of the fundamental frequency, by utilizing the impedances provided by at least the first, second, and third circuits.

17. The method of manufacturing a Doherty power amplifier as described in claim 15, characterized in that, The impedance inverter network of the first hybrid matching circuit includes at least one of the following architectures: an n-stage low-pass lumped quarter-wavelength converter, a quarter-wavelength stub transmission line, a quasi-lumped n-order low-pass filter, a quasi-lumped n-order low-pass quarter-wavelength converter, a quasi-lumped low-pass Chabyshev converter, a quasi-lumped low-pass Chabyshev quarter-wavelength converter, a quasi-lumped low-pass quarter-wavelength step impedance converter, and a quasi-lumped low-pass quarter-wavelength step impedance quarter-wavelength converter.

18. The method of manufacturing a Doherty power amplifier as described in claim 15, characterized in that, Providing the at least one peak amplifier includes providing at least two peak amplifiers, and the method further includes: At least one additional hybrid matching circuit is connected between the outputs of the at least two peak amplifiers, such that any two of the at least two peak amplifiers are associated with the at least one hybrid matching circuit, wherein the first hybrid matching circuit and the at least one additional hybrid matching circuit are electrically connected and share the common load, wherein connecting the at least one additional hybrid matching circuit includes: A first circuit is connected between the output of the at least one main amplifier and the output of the at least two peak amplifiers, wherein the first circuit is part of an impedance inverter network of the at least one additional hybrid matching circuit of the Doherty power amplifier.

19. A method for manufacturing a Doherty power amplifier, characterized in that, include: Provide at least one main amplifier operating at a base frequency; Provide at least one peak amplifier connected in parallel with the at least one main amplifier and sharing a common load or a load; A first hybrid matching circuit is connected between the output of the at least one main amplifier and the output of the at least one peak amplifier, wherein connecting the first hybrid matching circuit includes: A first circuit is connected between the output of the at least one main amplifier and the output of the at least one peak amplifier, and the type and size of the components included in the first circuit are determined, so that at the fundamental frequency, an output parasitic element of one of the main amplifiers and the peak amplifiers together with the first circuit constitutes an impedance inverter network, so that the first circuit is part of the impedance inverter network of the first hybrid matching circuit. A harmonic cancellation circuit is connected between the output of one of the at least one main amplifier and the at least one peak amplifier and an RF ground terminal, and the component size included in the harmonic cancellation circuit is determined so that the harmonic cancellation circuit provides a high impedance relative to the RF ground terminal at the fundamental frequency, which is equivalent to an open circuit, so that the function of the impedance inverter network is not affected, and provides an impedance relative to the RF ground terminal at the frequency of a target harmonic of the fundamental frequency, so that the impedance observed from the intrinsic plane of the corresponding amplifier is one of a high impedance and a low impedance, so as to eliminate the target harmonic; A second hybrid matching circuit or an additional impedance inverter network and a parasitic cancellation circuit are connected between the output of the at least one main amplifier and the output of the at least one peak amplifier, wherein connecting the second hybrid matching circuit includes: A first circuit is connected between the output of the at least one main amplifier and the output of the at least one peak amplifier, and the types and sizes of the components included in the first circuit are determined. This allows an impedance inverter network to be formed at the fundamental frequency using an output parasitic element from one of the main amplifiers or the peak amplifier, together with the first circuit. Thus, the first circuit of the second hybrid matching circuit becomes part of the impedance inverter network of the second hybrid matching circuit. The first hybrid matching circuit and the second hybrid matching circuit, or the first hybrid matching circuit, the additional impedance inverter network, and the parasitic cancellation circuit, are connected together through an impedance inverter network and share the common load. The impedance inverter network is used to prevent signal leakage between the main amplifier and the peak amplifier when one of them is turned off. The high impedance refers to an impedance that is large relative to the fundamental impedance observed from the intrinsic plane at the fundamental frequency and is equivalent to an open circuit, while the low impedance refers to an impedance that is small relative to the fundamental impedance and is equivalent to a short circuit.

20. The method of manufacturing a Doherty power amplifier as described in claim 19, characterized in that, The impedance inverter network connecting the first hybrid matching circuit and the second hybrid matching circuit includes at least one of the following architectures: a quarter-wavelength converter, an n-order high-pass quarter-wavelength converter, an n-order low-pass quarter-wavelength converter, an n-stage low-pass lumped quarter-wavelength converter, an n-stage high-pass lumped quarter-wavelength converter, a quarter-wavelength stub transmission line, a quasi-lumped n-order low-pass filter, a quasi-lumped n-order high-pass filter, a quasi-lumped n-order low-pass quarter-wavelength converter, a quasi-lumped low-pass Chaibesher converter, and a quasi-lumped... Quasi-lumped low-pass Chabyshev quarter-wavelength converter, quasi-lumped low-pass quarter-wavelength step impedance converter, quasi-lumped low-pass quarter-wavelength step impedance quarter-wavelength converter, quasi-lumped n-order high-pass quarter-wavelength converter, quasi-lumped high-pass Chabyshev converter, quasi-lumped high-pass Chabyshev quarter-wavelength converter, quasi-lumped high-pass quarter-wavelength step impedance converter, quasi-lumped high-pass quarter-wavelength step impedance quarter-wavelength converter, and combinations of low-pass and high-pass lumped or distributed quarter-wavelength converters.

21. The method of manufacturing a Doherty power amplifier as described in claim 19, characterized in that, The impedance inverter network of the second hybrid matching circuit includes at least one of the following architectures: an n-stage low-pass lumped quarter-wavelength converter, a quarter-wavelength stub transmission line, a quasi-lumped n-order low-pass filter, a quasi-lumped n-order low-pass quarter-wavelength converter, a quasi-lumped low-pass Chabyshev converter, a quasi-lumped low-pass Chabyshev quarter-wavelength converter, a quasi-lumped low-pass quarter-wavelength step impedance converter, and a quasi-lumped low-pass quarter-wavelength step impedance quarter-wavelength converter.

22. The method of manufacturing a Doherty power amplifier as described in claim 19, characterized in that, Providing the at least one peak amplifier includes providing at least two peak amplifiers, and the method further includes: At least one additional hybrid matching circuit is connected between the outputs of the at least two peak amplifiers, such that any two of the at least two peak amplifiers are associated with a hybrid matching circuit, wherein the first hybrid matching circuit, the second hybrid matching circuit, and the at least one additional hybrid matching circuit are connected together by the impedance inverter network and share the common load, wherein connecting the at least one additional hybrid matching circuit includes: A first circuit is connected between the outputs of the at least two peak amplifiers, wherein the first circuit is part of an impedance inverter network of the at least one additional hybrid matching circuit of the Doherty power amplifier.

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