power-on reset circuit

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By using a current mirror circuit and a PMOS transistor in the power-on reset circuit, and utilizing the gate-source voltage of NMOS and PMOS as the switching voltage, the problems of high area and power consumption in the prior art are solved, achieving the effect of saving area and reducing power consumption.

CN115955226BActive Publication Date: 2026-07-31SHANGHAI HUAHONG GRACE SEMICON MFG CORP

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Patent Information

Authority / Receiving Office: CN · China
Patent Type: Patents(China)
Current Assignee / Owner: SHANGHAI HUAHONG GRACE SEMICON MFG CORP
Filing Date: 2022-11-30
Publication Date: 2026-07-31

AI Technical Summary

Technical Problem

Existing power-on reset circuits occupy a large chip area and consume a lot of power in integrated circuits.

Method used

By employing a current mirror circuit and a PMOS transistor, and using the gate-source voltage of the first NMOS transistor and the first PMOS transistor as the switching voltage, the number of resistors and transistors is reduced, and the current mirror circuit is used to achieve the switching of the reset signal.

Benefits of technology

It effectively saves space, reduces power consumption, and realizes the function of a reset signal.

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Abstract

This invention discloses a power-on reset circuit, comprising: a current mirror circuit and a first PMOS transistor. The current mirror circuit adjusts the current magnitude through the gate-drain voltage difference between a first NMOS transistor with its source grounded and a second NMOS transistor with its source grounded through a first resistor. The gate of the first NMOS transistor serves as a first node and is simultaneously connected to the gate of the first PMOS transistor; the source of the first PMOS transistor is connected to the power supply voltage, and its drain serves as a second node and is connected to a third current path; the gate-drain voltage of the first NMOS transistor is added to the gate-source voltage of the first PMOS transistor to form a switching voltage. When the power supply voltage is greater than the switching voltage, the initial reset signal is triggered. This invention reduces the number of resistors and transistors, thereby maximizing area savings and reducing power consumption.

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Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit, and more particularly to a power-on reset (POR) circuit. Background Technology

[0002] The power-on reset circuit generates a reset signal when the system is powered on, used for digital system reset and startup of various modules. It typically requires a large number of resistors to meet power consumption requirements, thus occupying a significant layout area.

[0003] like Figure 1 The diagram shows a schematic of an existing POR circuit. Resistors R101 and R102 divide the power supply voltage VDD and form a switching voltage (Vtrip) at node NET100. The switching voltage is input to the gate of NMOS transistor M101. The drain of NMOS transistor M101, i.e., node NET101, is connected to the power supply voltage VDD through resistor R103. The drain of NMOS transistor M101 also outputs a power-on reset signal to the input of inverter INV100. The output of inverter INV100 outputs an inverted reset signal RSTB.

[0004] Depend on Figure 1 As shown, the switching voltage of the existing circuit is obtained by dividing the power supply voltage VDD by resistors R101 and R102. In integrated circuits, resistors occupy a large chip area and also consume a lot of power. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a power-on reset circuit that can save area and reduce power consumption.

[0006] To solve the above-mentioned technical problems, the power-on reset circuit provided by the present invention includes: a current mirror circuit and a first PMOS transistor.

[0007] The current mirror circuit includes a first NMOS transistor, a second NMOS transistor, a first resistor, a first current path, and a second current path.

[0008] The gate and drain of the first NMOS transistor and the gate of the second NMOS transistor are all connected to the first node.

[0009] The source of the first NMOS transistor is grounded, and the voltage of the first node is the gate-source voltage of the first NMOS transistor.

[0010] The source of the second NMOS transistor is connected to the first terminal of the first resistor and the second terminal of the first resistor is grounded.

[0011] The first current path is connected between the power supply voltage and the first node; the second current path is connected between the power supply voltage and the drain of the second NMOS transistor.

[0012] The first current path and the second current path are mirror images of each other. The magnitude of the current in the second current path is the difference between the voltage of the first node and the gate-source voltage of the second NMOS transistor divided by the first resistor.

[0013] The gate of the first PMOS transistor is connected to the first node, and the source of the first PMOS transistor is connected to the power supply voltage.

[0014] The drain of the first PMOS transistor serves as the second node and is connected to the third current path. The on-state current of the first PMOS transistor is greater than the on-state current of the third current path.

[0015] The switching voltage is formed by the sum of the voltage of the first node and the gate-source voltage of the first PMOS transistor. When the power supply voltage is less than the switching voltage, the first PMOS transistor is turned off, the third current path is turned on, and the second node is grounded.

[0016] When the power supply voltage is greater than or equal to the switching voltage, the first PMOS transistor is turned on, and the on-current of the first PMOS transistor is greater than the on-current of the third current path, causing the voltage of the second node to rise to the power supply voltage. The voltage of the second node serves as the initial reset signal.

[0017] A further improvement is that it also includes a first inverter and a second inverter connected in series.

[0018] The initial reset signal is connected to the input terminal of the first inverter, the output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the second inverter outputs a reset signal. The first inverter and the second inverter shape the initial reset signal to form the reset signal.

[0019] A further improvement is that the first current path is composed of a second PMOS transistor, the source of which is connected to the power supply voltage, and the gate of which serves as the bias terminal of the first current path and is connected to the bias terminal of the second current path.

[0020] The drain of the second PMOS transistor is connected to the first node.

[0021] A further improvement is that the second current path is composed of a third PMOS transistor, the source of which is connected to the power supply voltage, and the gate of which serves as the bias terminal of the second current path and is connected to the bias terminal of the first current path.

[0022] The drain and gate of the third PMOS transistor are both connected to the drain of the second NMOS transistor.

[0023] A further improvement is that the third current path is composed of a third NMOS transistor, the source of which is grounded.

[0024] The gate of the third NMOS transistor is connected to the first node.

[0025] The drain of the third NMOS transistor is connected to the second node.

[0026] A further improvement is that the first inverter is a CMOS inverter, and the first inverter includes a fourth NMOS transistor and a fourth PMOS transistor.

[0027] The source of the fourth NMOS transistor is grounded, and the source of the fourth PMOS transistor is connected to the power supply voltage.

[0028] The gate of the fourth NMOS transistor and the gate of the fourth PMOS transistor are connected together and serve as the input terminal of the first inverter.

[0029] The drain of the fourth NMOS transistor and the drain of the fourth PMOS transistor are connected together and serve as the output terminal of the first inverter.

[0030] A further improvement is that the second inverter is a CMOS inverter, which includes a fifth NMOS transistor and a fifth PMOS transistor.

[0031] The source of the fifth NMOS transistor is grounded, and the source of the fifth PMOS transistor is connected to the power supply voltage.

[0032] The gate of the fifth NMOS transistor and the gate of the fifth PMOS transistor are connected together and serve as the input terminal of the second inverter.

[0033] The drain of the fifth NMOS transistor and the drain of the fifth PMOS transistor are connected together and serve as the output terminal of the second inverter.

[0034] A further improvement is that a fourth current path is connected between the source of the fifth PMOS transistor and the power supply voltage, and the fourth current path is a mirror image of the first current path.

[0035] A further improvement is that the fourth current path is composed of a sixth PMOS transistor, the source of which is connected to the power supply voltage, and the gate of which serves as the bias terminal of the fourth current path and is connected to the bias terminal of the second current path.

[0036] The drain of the sixth PMOS transistor is connected to the source of the fifth PMOS transistor.

[0037] A further improvement is that the first NMOS transistor is composed of a single NMOS transistor or is formed by multiple NMOS transistors connected in parallel.

[0038] A further improvement is that the switching voltage is adjusted by adjusting the width-to-length ratio or the number of the first NMOS transistors.

[0039] A further improvement is that the first PMOS transistor is composed of a single PMOS transistor or is formed by multiple PMOS transistors connected in parallel.

[0040] A further improvement is that the switching voltage is adjusted by adjusting the width-to-length ratio or the number of the first PMOS transistors.

[0041] A further improvement is that the power supply voltage is several V.

[0042] A further improvement is that the first resistor has a value of several hundred kΩ.

[0043] This invention does not require the use of multiple resistors to divide the voltage to achieve the switching of the reset signal. Instead, it uses the sum of the gate-source voltages of the first NMOS transistor and the first PMOS transistor as the switching voltage. The first NMOS transistor also serves as a component of the current mirror circuit. Therefore, this invention can reduce the number of resistors and transistors, thereby maximizing area savings and reducing power consumption. Attached Figure Description

[0044] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0045] Figure 1 This is an existing power-on reset circuit diagram;

[0046] Figure 2 This is a power-on reset circuit diagram according to an embodiment of the present invention;

[0047] Figure 3A This is a current simulation diagram of the current mirror circuit during power-on of the power-on reset circuit in an embodiment of the present invention;

[0048] Figure 3B This is a simulation diagram of the power-on reset signal of the power-on reset circuit in an embodiment of the present invention. Detailed Implementation

[0049] like Figure 2 The diagram shown is a power-on reset circuit diagram according to an embodiment of the present invention. The power-on reset circuit according to an embodiment of the present invention includes: a current mirror circuit 101 and a first PMOS transistor MP3.

[0050] The current mirror circuit 101 includes a first NMOS transistor MN1, a second NMOS transistor MN2, a first resistor R1, a first current path 102, and a second current path 103.

[0051] The gate and drain of the first NMOS transistor MN1 and the gate of the second NMOS transistor MN2 are all connected to the first node NBIAS.

[0052] The source of the first NMOS transistor MN1 is grounded to GNDA, and the voltage of the first node NBIAS is the gate-source voltage of the first NMOS transistor MN1.

[0053] The source of the second NMOS transistor MN2 is connected to the first terminal of the first resistor R1 and the second terminal of the first resistor R1 is grounded GNDA.

[0054] The first current path 102 is connected between the power supply voltage VDDA and the first node NBIAS; the second current path 103 is connected between the power supply voltage VDDA and the drain of the second NMOS transistor MN2.

[0055] The first current path 102 and the second current path 103 are mirror images of each other. The magnitude of the current in the second current path 103 is the difference between the voltage of the first node NBIAS and the gate-source voltage of the second NMOS transistor MN2 divided by the first resistor R1.

[0056] The gate of the first PMOS transistor MP3 is connected to the first node NBIAS, and the source of the first PMOS transistor MP3 is connected to the power supply voltage VDDA.

[0057] The drain of the first PMOS transistor MP3 serves as the second node DET and is connected to the third current path 104. The on-state current of the first PMOS transistor MP3 is greater than the on-state current of the third current path 104.

[0058] The switching voltage is formed by the sum of the voltage of the first node NBIAS and the gate-source voltage of the first PMOS transistor MP3. When the power supply voltage VDDA is less than the switching voltage, the first PMOS transistor MP3 is turned off, the third current path 104 is turned on, and the second node DET is grounded to GNDA.

[0059] When the power supply voltage VDDA is greater than or equal to the switching voltage, the first PMOS transistor MP3 is turned on. The on-current of the first PMOS transistor MP3 is greater than the on-current of the third current path 104, causing the voltage of the second node DET to rise to the power supply voltage VDDA. The voltage of the second node DET serves as the initial reset signal.

[0060] In this embodiment of the invention, a first inverter 105 and a second inverter 106 connected in series are also included.

[0061] The initial reset signal is connected to the input terminal of the first inverter 105, the output terminal of the first inverter 105 is connected to the input terminal of the second inverter 106, and the output terminal of the second inverter 106 outputs a reset signal RSTB. The first inverter 105 and the second inverter 106 shape the initial reset signal to form the reset signal RSTB.

[0062] In this embodiment of the invention, the first current path 102 is composed of a second PMOS transistor MP1. The source of the second PMOS transistor MP1 is connected to the power supply voltage VDDA, and the gate of the second PMOS transistor MP1 serves as the bias terminal of the first current path 102 and is connected to the bias terminal PBIAS of the second current path 103.

[0063] The drain of the second PMOS transistor MP1 is connected to the first node NBIAS.

[0064] The second current path 103 is composed of a third PMOS transistor MP2. The source of the third PMOS transistor MP2 is connected to the power supply voltage VDDA, and the gate of the third PMOS transistor MP2 serves as the bias terminal PBIAS of the second current path 103 and is connected to the bias terminal of the first current path 102.

[0065] The drain and gate of the third PMOS transistor MP2 are both connected to the drain of the second NMOS transistor MN2.

[0066] The third current path 104 is composed of a third NMOS transistor MN3, and the source of the third NMOS transistor MN3 is grounded to GNDA.

[0067] The gate of the third NMOS transistor MN3 is connected to the first node NBIAS.

[0068] The drain of the third NMOS transistor MN3 is connected to the second node DET.

[0069] In this embodiment of the invention, the first inverter 105 is a CMOS inverter, and the first inverter 105 includes a fourth NMOS transistor MN4 and a fourth PMOS transistor MP4.

[0070] The source of the fourth NMOS transistor MN4 is grounded to GNDA, and the source of the fourth PMOS transistor MP4 is connected to the power supply voltage VDDA.

[0071] The gate of the fourth NMOS transistor MN4 and the gate of the fourth PMOS transistor MP4 are connected together and serve as the input terminal of the first inverter 105.

[0072] The drains of the fourth NMOS transistor MN4 and the fourth PMOS transistor MP4 are connected together and serve as the output terminal of the first inverter 105. Figure 2 In this process, the signal RST output from the output terminal of the first inverter 105 is inverted with the final reset signal RSTB.

[0073] The second inverter 106 is a CMOS inverter, and the second inverter 106 includes a fifth NMOS transistor MN5 and a fifth PMOS transistor MP5.

[0074] The source of the fifth NMOS transistor MN5 is grounded to GNDA, and the source of the fifth PMOS transistor MP5 is connected to the power supply voltage VDDA.

[0075] The gate of the fifth NMOS transistor MN5 and the gate of the fifth PMOS transistor MP5 are connected together and serve as the input terminal of the second inverter 106.

[0076] The drain of the fifth NMOS transistor MN5 and the drain of the fifth PMOS transistor MP5 are connected together and serve as the output terminal of the second inverter 106.

[0077] In this embodiment of the invention, a fourth current path 107 is also connected between the source of the fifth PMOS transistor MP5 and the power supply voltage VDDA, and the fourth current path 107 and the first current path 102 are mirror images of each other.

[0078] The fourth current path 107 is composed of a sixth PMOS transistor MP6. The source of the sixth PMOS transistor MP6 is connected to the power supply voltage VDDA, and the gate of the sixth PMOS transistor MP6 serves as the bias terminal of the fourth current path 107 and is connected to the bias terminal PBIAS of the second current path 103.

[0079] The drain of the sixth PMOS transistor MP6 is connected to the source of the fifth PMOS transistor MP5.

[0080] In this embodiment of the invention, the first NMOS transistor MN1 is composed of a single NMOS transistor or formed by multiple NMOS transistors connected in parallel. The switching voltage is adjusted by regulating the width-to-length ratio or the number of the first NMOS transistor MN1.

[0081] Alternatively, the first PMOS transistor MP3 may consist of a single PMOS transistor or be formed by multiple PMOS transistors connected in parallel. The switching voltage can be adjusted by regulating the width-to-length ratio or the number of the first PMOS transistor MP3.

[0082] The power supply voltage VDDA is several V.

[0083] The first resistor R1 has a value of several hundred kΩ.

[0084] The present invention does not require the use of voltage division of multiple resistors to achieve the switching of the reset signal RSTB. Instead, it uses the sum of the gate-source voltages of the first NMOS transistor MN1 and the first PMOS transistor MP3 as the switching voltage. The first NMOS transistor MN1 also serves as a component of the current mirror circuit 101. Therefore, the present invention can reduce the number of resistors and transistors, thereby maximizing area savings and reducing power consumption.

[0085] like Figure 3A The figure shown is a current simulation diagram of the current mirror circuit 101 of the power-on reset circuit in an embodiment of the present invention; curve 201 represents the power supply voltage change curve over time, and curve 202 represents... Figure 1 Curve 202 shows the current curves along the paths of resistors R101 and R102 in the power-on reset circuit of this embodiment; curve 203 shows the current curve along the path of R1 in the current mirror circuit 101 when the power-on reset circuit is powered on. It can be seen that in curve 202, the current is about 50μA when the voltage is 2.5V and about 100μA when the voltage is 5V; while in curve 203, the current is about 1μA when the voltage is 2.5V and about 1μA when the voltage is 5V. Therefore, this embodiment of the invention can minimize power consumption.

[0086] like Figure 3B The figure shown is a simulation diagram of the power-on reset signal RSTB of the power-on reset circuit in an embodiment of the present invention; curve 201 represents the power supply voltage change curve over time, and curve 204 represents... Figure 1 The curves showing the changes in the reset signal of the existing power-on reset circuit are shown; curve 205 represents the curves showing the changes in the reset signal of the power-on reset circuit of the present invention. It can be seen that the reset signal of the power-on reset circuit of the present invention can also achieve the function of power-on reset.

[0087] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A power-on reset circuit, characterized by comprising: include: Current mirror circuit and first PMOS transistor; The current mirror circuit includes a first NMOS transistor, a second NMOS transistor, a first resistor, a first current path, and a second current path. The gate and drain of the first NMOS transistor and the gate of the second NMOS transistor are all connected to the first node; The source of the first NMOS transistor is grounded, and the voltage of the first node is the gate-source voltage of the first NMOS transistor. The source of the second NMOS transistor is connected to the first terminal of the first resistor and the second terminal of the first resistor is grounded; The first current path is connected between the power supply voltage and the first node; The second current path is connected between the power supply voltage and the drain of the second NMOS transistor; The first current path and the second current path are mirror images of each other. The magnitude of the current in the second current path is the difference between the voltage of the first node and the gate-source voltage of the second NMOS transistor divided by the first resistor. The gate of the first PMOS transistor is connected to the first node, and the source of the first PMOS transistor is connected to the power supply voltage. The drain of the first PMOS transistor serves as the second node and is connected to the third current path. The on-current of the first PMOS transistor is greater than the on-current of the third current path. The switching voltage is formed by the sum of the voltage of the first node and the gate-source voltage of the first PMOS transistor. When the power supply voltage is less than the switching voltage, the first PMOS transistor is turned off, the third current path is turned on, and the second node is grounded. When the power supply voltage is greater than or equal to the switching voltage, the first PMOS transistor is turned on, and the on-current of the first PMOS transistor is greater than the on-current of the third current path, causing the voltage of the second node to rise to the power supply voltage. The voltage of the second node serves as the initial reset signal.

2. The power-on reset circuit of claim 1, wherein, It also includes a first inverter and a second inverter connected in series; The initial reset signal is connected to the input terminal of the first inverter, the output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the second inverter outputs a reset signal. The first inverter and the second inverter shape the initial reset signal to form the reset signal.

3. The power-on reset circuit of claim 1, wherein: The first current path is composed of a second PMOS transistor, the source of which is connected to the power supply voltage, and the gate of which serves as the bias terminal of the first current path and is connected to the bias terminal of the second current path. The drain of the second PMOS transistor is connected to the first node.

4. The power-on reset circuit as described in claim 3, characterized in that: The second current path is composed of a third PMOS transistor, the source of which is connected to the power supply voltage, and the gate of which serves as the bias terminal of the second current path and is connected to the bias terminal of the first current path. The drain and gate of the third PMOS transistor are both connected to the drain of the second NMOS transistor.

5. The power-on reset circuit as described in claim 1, characterized in that: The third current path is composed of a third NMOS transistor, and the source of the third NMOS transistor is grounded; The gate of the third NMOS transistor is connected to the first node; The drain of the third NMOS transistor is connected to the second node.

6. The power-on reset circuit as described in claim 2, characterized in that: The first inverter is a CMOS inverter, and the first inverter includes a fourth NMOS transistor and a fourth PMOS transistor; The source of the fourth NMOS transistor is grounded, and the source of the fourth PMOS transistor is connected to the power supply voltage. The gate of the fourth NMOS transistor and the gate of the fourth PMOS transistor are connected together and serve as the input terminal of the first inverter. The drain of the fourth NMOS transistor and the drain of the fourth PMOS transistor are connected together and serve as the output terminal of the first inverter.

7. The power-on reset circuit as described in claim 6, characterized in that: The second inverter is a CMOS inverter, and the second inverter includes a fifth NMOS transistor and a fifth PMOS transistor; The source of the fifth NMOS transistor is grounded, and the source of the fifth PMOS transistor is connected to the power supply voltage. The gate of the fifth NMOS transistor and the gate of the fifth PMOS transistor are connected together and serve as the input terminal of the second inverter; The drain of the fifth NMOS transistor and the drain of the fifth PMOS transistor are connected together and serve as the output terminal of the second inverter.

8. The power-on reset circuit as described in claim 7, characterized in that: A fourth current path is also connected between the source of the fifth PMOS transistor and the power supply voltage, and the fourth current path is a mirror image of the first current path.

9. The power-on reset circuit as described in claim 8, characterized in that: The fourth current path is composed of a sixth PMOS transistor, the source of which is connected to the power supply voltage, and the gate of which serves as the bias terminal of the fourth current path and is connected to the bias terminal of the second current path. The drain of the sixth PMOS transistor is connected to the source of the fifth PMOS transistor.

10. The power-on reset circuit as described in claim 1, characterized in that: The first NMOS transistor is composed of one NMOS transistor or is formed by multiple NMOS transistors connected in parallel.

11. The power-on reset circuit as described in claim 10, characterized in that: The switching voltage is adjusted by adjusting the width-to-length ratio or the number of the first NMOS transistors.

12. The power-on reset circuit as described in claim 1 or 10, characterized in that: The first PMOS transistor is composed of a single PMOS transistor or is formed by multiple PMOS transistors connected in parallel.

13. The power-on reset circuit as described in claim 12, characterized in that: The switching voltage is adjusted by adjusting the width-to-length ratio or the number of the first PMOS transistors.

14. The power-on reset circuit as described in claim 1, characterized in that: The power supply voltage is several volts.

15. The power-on reset circuit as described in claim 1, characterized in that: The first resistor has a value of several hundred kΩ.