Successive approximation analog-to-digital conversion method and circuit based on charge stacking

Abstract

The application provides a successive approximation type analog-digital conversion method based on charge stacking, comprising: obtaining an analog current of a memory-computing integrated circuit; copying the analog current to a capacitor array of each digital-analog converter by a common-source common-gate current mirror to obtain sampling currents of N digital-analog converters; an SW1 switch is always in a closed state to control N highest bit capacitors to be stacked; an SW2 switch is closed to sample the sampling currents on the capacitor array to obtain N sampling voltages, and the sampling voltages of the N digital-analog converters are stacked as analog signals, wherein the sampling voltage of a first digital-analog converter is a weighted sum of the N sampling voltages; the SW2 switch is opened to sequentially quantize the capacitor array in the first digital-analog converter, wherein the highest bit capacitor does not participate in quantization, and each quantization result is input to a comparator for comparison to obtain a digital signal.

Description

Technical Field

[0001] This invention relates to analog-to-digital converters, and more particularly to a successive approximation analog-to-digital conversion method and circuit based on charge stacking. Background Technology

[0002] In recent years, Successive Approximation Register (SAR) analog-to-digital converters have received increasing attention due to their advantages such as low power consumption, small size, and simple structure. Because digital signals are easy to process, resistant to interference, and highly accurate, analog signals from nature are typically converted into digital signals for further processing. The analog-to-digital converter (ADC) is crucial as a bridge between analog and digital signals.

[0003] Currently, various ADC structures have been researched and developed both domestically and internationally over the years. Common ADC structures include pipelined, folded interpolation, flash, and successive approximation types. In in-memory computing circuits, ADCs are also needed to convert analog signals computed in the memory array into digital signals for transmission and communication. Currently, analog-to-digital converters (ADCs) used in traditional in-memory computing circuits require all ADCs to be activated, resulting in high power consumption. Furthermore, shift and accumulation circuits are required after the ADC conversion, leading to additional power consumption, area overhead, and latency. Summary of the Invention

[0004] To address the technical problems of traditional in-memory computing circuits requiring all analog-to-digital converters to be turned on and the need for shift and accumulation circuits after analog-to-digital conversion, this invention provides a successive approximation analog-to-digital conversion method and circuit based on charge stacking.

[0005] This invention provides a successive approximation analog-to-digital converter (ADC) method and circuit based on charge stacking, comprising: acquiring the analog current of an in-memory computing circuit; a common-source cascode current mirror replicating the analog current onto the capacitor array of each ADC to obtain the sampling current of N ADCs; SW1 switch always being closed, controlling the N most significant bit capacitors to stack; SW2 switch being closed, the sampling current being sampled on the capacitor array to obtain N sampling voltages, the sampling voltages of the N ADCs being stacked as analog signals, wherein the sampling voltage of the first ADC is the weighted sum of the N sampling voltages; SW2 switch being open, the capacitor array in the first ADC being sequentially quantized, wherein the most significant bit capacitor is not involved in the quantization, and the quantization result of each step being input to a comparator for comparison to obtain a digital signal.

[0006] According to an embodiment of the present invention, the method includes three stages: a current stabilization stage, in which an analog current is obtained, and sampling currents of multiple digital-to-analog converters are obtained based on the analog current, with switch SW1 in a closed state; a sampling stage, in which switch SW2 is closed, the SAM signal is closed, N sampling currents are converted into N sampling voltages, and the sampling voltages of the N digital-to-analog converters are stacked as analog signals, wherein the sampling voltage of the first digital-to-analog converter is the weighted sum of the sampling voltages of the N highest-order capacitors; and a quantization stage, in which switch SW2 is opened, and the capacitor array in the first digital-to-analog converter is quantized sequentially, wherein the highest-order capacitors do not participate in the quantization, and the SAR logic module controls the opening / closing of the capacitor array for each quantization, and inputs the quantization result of each quantization to a comparator for comparison, and the SAR logic module outputs a digital signal.

[0007] According to an embodiment of the present invention, during the quantization stage, the number of bits of the analog-to-digital converter is 8 bits, 10 bits, or 16 bits, and the number of quantizations is equal to the number of bits of the analog-to-digital converter minus 1.

[0008] According to an embodiment of the present invention, during the quantization stage, N-1 analog-to-digital converters, except for the first analog-to-digital converter, do not perform any operation.

[0009] According to another embodiment of the present invention, the method includes: N analog-to-digital converters (ADCs) connected in series, each ADC including: a common-source cascode current mirror for receiving analog signals; a digital-to-analog converter (DAC) including a capacitor array, the input terminal of the DAC being connected to the output terminal of the common-source cascode current mirror for sampling analog current onto the capacitor array; a comparator, the positive input terminal being connected to a reference voltage and the negative input terminal being connected to the output terminal of the DAC; a SAR logic module, the input terminal of the SAR logic module being connected to the output terminal of the comparator, and the output terminal of the SAR logic module being connected to the input terminal of the DAC and the clock signal of the comparator; and switches SW1 and SW2, both controlled by the SAR logic module to alternately close or open, wherein switch SW1 controls the N capacitor arrays to be connected in a preset connection mode, and switch SW2 is used to control the sampling and quantization processes of the N DACs. When switch SW2 is closed, analog signal sampling and stacking are performed; when switch SW2 is open, the capacitor array in the first DAC is quantized sequentially, wherein the most significant bit capacitor does not participate in quantization.

[0010] According to another embodiment of the present invention, the preset connection method includes: connecting the highest-order capacitors of each capacitor array in series from top to bottom, connecting the lower plate of the first highest-order capacitor of the digital-to-analog converter in series with the upper plate of the next highest-order capacitor of the digital-to-analog converter, until connecting the upper plate of the Nth highest-order capacitor of the digital-to-analog converter, and grounding the lower plate of the Nth highest-order capacitor of the digital-to-analog converter.

[0011] According to another embodiment of the present invention, the input terminal of the common-source cascode current mirror is further provided with a clamping transistor for controlling the input of the clamping voltage.

[0012] According to another embodiment of the present invention, the SAR logic module further includes a resistive variable memory for storing analog signals.

[0013] According to another embodiment of the present invention, the output terminal of the common source cascode current mirror is also connected to an RST reset signal for controlling the voltage reset on the capacitor array.

[0014] According to another embodiment of the present invention, the output terminal of the common source cascode current mirror is also connected to a SAM signal, which is used to control the conversion of the sampling current into a sampling voltage.

[0015] Compared with the prior art, the charge stacking-based successive approximation analog-to-digital converter circuit provided by the present invention has at least the following advantages:

[0016] In the stacked mode of the successive approximation analog-to-digital converter circuit based on charge stacking, all lower-level analog-to-digital converters except the first analog-to-digital converter do not need to work, saving the power consumption of the analog-to-digital converter circuit in the in-memory computing circuit. At the same time, the analog domain realizes shift accumulation, eliminating the need for digital shift accumulation circuits, thus saving the area / delay / power consumption of the subsequent shift accumulation circuit in the in-memory computing circuit. Attached Figure Description

[0017] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0018] Figure 1 This schematic diagram illustrates the structure of an in-memory computing circuit in the prior art.

[0019] Figure 2 A schematic diagram of a successive approximation analog-to-digital conversion method according to an embodiment of the present invention is shown.

[0020] Figure 3 A schematic diagram of a successive approximation analog-to-digital converter circuit according to an embodiment of the present invention is shown.

[0021] Figure 4 A schematic diagram illustrating the dual-mode structure of a successive approximation analog-to-digital converter circuit according to an embodiment of the present invention is shown; and

[0022] Figure 5 The diagram schematically illustrates the waveforms of a dual-mode successive approximation analog-to-digital converter circuit according to an embodiment of the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments and the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0025] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0026] Figure 1 The schematic diagram illustrates the structure of a prior art in-memory computing circuit.

[0027] Specifically, I TBL I is the analog current generated by the in-memory computing circuit. SAM V is the sampling current of the digital-to-analog converter. CLP The clamping voltage, V CM V is the reference voltage for the digital-to-analog converter. REF_H For the high reference voltage of the digital-to-analog converter, V REF_L Φ is the reference low voltage for the digital-to-analog converter (DAC), Φ is the DAC clock signal, SAM is the DAC sampling signal, RST is the DAC reset signal, SW1 & SW2 are switch signals, and C is the input voltage. MSB This is the most significant bit.

[0028] like Figure 1 As shown, a traditional in-memory computing circuit consists of a memory array, an input driver circuit, a gating circuit, an analog-to-digital converter (ADC), and a digital shift-accumulator circuit. The input driver circuit generates excitation based on the digital input signal, and the in-memory computing array generates the calculated analog signal. The ADC converts the analog signal into a digital signal, and then the digital shift-accumulator circuit accumulates the results generated by multiple or multi-cycle ADC circuits.

[0029] Figure 2 A schematic diagram of a successive approximation analog-to-digital conversion method according to an embodiment of the present invention is shown.

[0030] like Figure 2 As shown, this embodiment of the invention provides a successive approximation analog-to-digital conversion method based on charge stacking, including the following steps S210-S250:

[0031] S210, Obtain the analog current I of the in-memory computing circuit. TBL .

[0032] S220, the common-source cascode current mirror will simulate current I. TBL The sampled current I of each digital-to-analog converter (DAC) is copied onto its capacitor array, and the sampled current I of multiple DACs is obtained. SAM .

[0033] Switches S230 and SW1 are always closed, controlling the N highest-order capacitors to stack.

[0034] When switches S240 and SW2 are closed, the sampling current is sampled on the capacitor array, resulting in N sampled voltages. These N sampled voltages from the digital-to-analog converter (DAC) are then stacked as analog signals. The sampled voltage of the first DAC is represented by the N highest-order capacitors C. MSB The weighted sum of the sampled voltages.

[0035] Switches S250 and SW2 are open, sequentially quantizing the capacitor array in the first digital-to-analog converter (DAC), where the most significant bit capacitor C... MSB It does not participate in quantization, and each quantization result is input to a comparator for comparison to obtain a digital signal.

[0036] In one embodiment of the present invention, the method includes three stages: a current stabilization stage, a sampling stage, and a quantization stage.

[0037] For example, during the current stabilization phase, the simulated current I is obtained. TBL Based on analog current I TBL Obtain the sampling current I of multiple digital-to-analog converters (DACs) SAM The SAM signal is disconnected, and the SW1 switch is in the closed state.

[0038] During the sampling phase, SW2 switch is closed, the SAM signal is closed, and N sampled voltages are converted into N sampled voltages. The sampled voltages from the N digital-to-analog converters (DACs) are stacked as analog signals. The sampled voltage of the first DAC is the N most significant bit capacitors C. MSB The weighted sum of the sampled voltages.

[0039] During the quantization phase, switch SW2 is disconnected, and the capacitor array in the first digital-to-analog converter (DAC) is quantized sequentially. The most significant bit capacitor does not participate in the quantization. Each quantization is controlled by a signal generated by the SAR logic module, which controls the opening and closing of the capacitor array switch. The quantization result is then input to a comparator for comparison, and the SAR logic module outputs a digital signal.

[0040] For example, during the quantization stage, the analog-to-digital converter (ADC) has 8, 10, or 16 bits, and the number of quantizations equals the number of bits in the ADC minus 1. In this embodiment, for instance, the ADC has 8 bits, and the final quantization is performed 7 times, resulting in a 7-bit digital signal output.

[0041] For example, during the quantization phase, the N-1 analog-to-digital converters (ADCs) other than the first ADC do not operate. N can be, for example, 4, meaning there can be 4 ADCs, and only the first ADC operates while the other 3 ADCs do not perform quantization.

[0042] Figure 3 A schematic diagram of a successive approximation analog-to-digital converter circuit according to an embodiment of the present invention is shown.

[0043] like Figure 3 As shown, another embodiment of the present invention provides a successive approximation analog-to-digital converter circuit based on charge stacking, including N analog-to-digital converters (ADCs) connected in series, each ADC including:

[0044] A common-source, common-gate current mirror is used to receive analog signals.

[0045] A digital-to-analog converter (DAC), including a capacitor array, has its input connected to the output of a cascode current mirror to convert the analog current I... TBL Copy it onto the capacitor array for sampling.

[0046] The comparator's positive input is connected to the reference voltage V. CM The negative input terminal is connected to the output terminal of the digital-to-analog converter (DAC).

[0047] The SAR logic module has its input connected to the comparator's output, and its output connected to the input of the digital-to-analog converter (DAC) and the comparator's clock signal.

[0048] Switches SW1 and SW2 are both controlled by the SAR logic module signal to alternately close or open. Switch SW1 controls N capacitor arrays to be connected in a preset connection mode. Switch SW2 is used to control the sampling and quantization processes of N digital-to-analog converters (DACs). When switch SW2 is closed, analog signal sampling and stacking are performed. When switch SW2 is open, the capacitor array in the first DAC is quantized sequentially. The highest bit capacitor does not participate in the quantization.

[0049] For example, the preset connection method includes: connecting the highest-order capacitor C of each capacitor array... MSB The capacitor C of the most significant bit of the first digital-to-analog converter (DAC) is connected in series from top to bottom. MSB The lower plate is connected in series with the highest bit capacitor C of the next digital-to-analog converter (DAC). MSB The upper plate is connected up to the highest bit capacitor C of the Nth digital-to-analog converter (DAC). MSB The upper plate, the highest bit capacitor C of the Nth digital-to-analog converter (DAC). MSB The lower electrode plate is grounded.

[0050] For example, the input terminal of the cascode current mirror is further provided with a clamping transistor for controlling the clamping voltage V. CLP Input.

[0051] For example, the SAR logic module also includes a resistive variable memory for storing analog signals.

[0052] Specifically, resistive random access memory (RRAM) has shown great potential in terms of operating power consumption, integration density, and process compatibility. New types of non-volatile memories, represented by RRAM, exhibit low power consumption, low latency, high density, and high process compatibility. Based on RRAM, non-volatile in-memory computing technology can effectively reduce data movement between the processor and memory, as well as between memory levels, thereby significantly reducing the resulting power consumption and latency.

[0053] For example, the output of the cascode current mirror is also connected to an RST reset signal, which is used to control the voltage reset on the capacitor array.

[0054] For example, the output of the cascode current mirror is also connected to a SAM signal to control the sampling current I. SAM Converted to sampling voltage.

[0055] According to an embodiment of the present invention, it further includes: an RST reset signal for controlling the voltage reset on the capacitor array, wherein the transistor controlled by the RST reset signal is used to control the reset process.

[0056] In an embodiment of the present invention, a SAM signal is further included for controlling the sampling current I. SAMThis is converted into a sampling voltage, i.e., the transistor controlled by the SAM signal is used to control the sampling process.

[0057] Figure 4 A schematic diagram illustrating a dual-mode successive approximation analog-to-digital converter circuit according to an embodiment of the present invention is provided. Figure 5 The diagram schematically illustrates the waveforms of a dual-mode successive approximation analog-to-digital converter circuit according to an embodiment of the present invention.

[0058] To facilitate understanding, this invention provides a specific embodiment using an 8-bit 4-analog-to-digital converter (ADC) as an example to further illustrate the above solution.

[0059] Example 1

[0060] like Figure 4 and Figure 5 As shown, in normal mode, i.e., the mode of existing technology, the four analog-to-digital converters operate independently, and the SW2 switch is always closed. During the sampling phase, the analog current I of the four analog-to-digital converters is... TBI The signals are sampled onto their respective capacitor arrays and converted into 4 channels of 8-bit digital signals during the quantization stage.

[0061] In the embodiments of this invention, analog signals are superimposed, comprising three stages: current stabilization stage P0, sampling stage P1, and quantization stage P2 in stacking mode. In the current stabilization stage P0, the array input drive BL (bit line) is turned on. After the current stabilizes and the previous cycle of quantization is completed, the sampling stage P1 begins. The RST reset signal clears the voltage on all capacitors to zero. The SAM sampling signal controls the current-to-voltage conversion process. The highest bit capacitor C of the four digital-to-analog converters... MSB The four analog-to-digital converters are connected in series from top to bottom, with switch SW1 always closed. During the sampling phase, P1 and SW2 are closed, and the analog current I of the four converters is... TBL They are sampled onto their respective capacitor arrays, respectively, V SAM3 V SAM2 V SAM1 V SAM0 At this point, the sampling voltage of the first digital-to-analog converter is the weighted sum of the four sampling voltages, V. SAM3 =V SAM3 / 2+V SAM2 / 4+V SAM1 / 8+V SAM0 / 16, analog signal stacking is performed. During the quantization phase P2, switch SW2 is turned off, and the capacitor array in the first digital-to-analog converter is quantized sequentially. The most significant bit capacitor does not participate in the quantization. Specifically, the quantization phase P2 of one cycle can be performed simultaneously with the current stabilization phase P0 of the next cycle, operating in a pipelined manner. After the quantization phase P2 begins, the SAR logic module of each digital-to-analog converter performs one comparison and capacitor array switching. The second, third, and fourth digital-to-analog converters do not operate during the quantization process, resulting in a single 7-bit digital signal. Therefore, shift accumulation is achieved in the analog domain.

[0062] In the description of this invention, it should be understood that the terms "upper," "lower," "front," "rear," "left," and "right," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted where they may cause confusion in understanding the invention. Furthermore, the shape, size, and positional relationship of the components in the drawings do not reflect their actual size, scale, or actual positional relationship.

[0063] Similarly, to simplify the invention and aid in understanding one or more aspects of the invention, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof. The use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples" indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0064] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified. Furthermore, the word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. Unless otherwise stated, the expressions "about," "approximately," "substantially," and "around" indicate less than 10%, preferably less than 5%.

[0065] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A successive approximation analog-to-digital conversion method based on charge stacking, characterized in that, The method includes: a current stabilization phase, a sampling phase, and a quantization phase; The current stabilization phase is as follows: the analog current of the in-memory computing circuit is acquired, and the common-source cascode current mirror copies the analog current to the capacitor array of each digital-to-analog converter (DAC) to obtain the sampling current of N DACs; the sampling signal of the DAC is disconnected, and the SW1 switch is closed to control the N capacitor arrays to be connected in a preset connection mode, and to control the N highest-order capacitors to be stacked; wherein, the lower plate of the first DAC's highest-order capacitor is connected in series with the upper plate of the next DAC's highest-order capacitor, until the upper plate of the Nth DAC's highest-order capacitor is connected, and the lower plate of the Nth DAC's highest-order capacitor is grounded; When SW2 is closed, the sampling phase begins: the sampling current is sampled on the capacitor array to obtain N sampling voltages. The sampling voltages of the N digital-to-analog converters are stacked as analog signals. The sampling voltage of the first digital-to-analog converter is the binary weighted sum of the sampling voltages of the N highest-order capacitors. When SW2 is turned off, the quantization stage begins: the capacitor array in the first digital-to-analog converter is quantized sequentially, with the most significant bit capacitor not participating in the quantization. Each quantization is controlled by the SAR logic module to close / open the capacitor array, and the quantization result is input to the negative input of the comparator and compared with the reference voltage to obtain a digital signal.

2. The successive approximation analog-to-digital conversion method based on charge stacking according to claim 1, characterized in that, During the quantization stage, the analog-to-digital converter (ADC) has 8, 10, or 16 bits, and the number of quantization operations equals the number of bits in the ADC minus 1.

3. The successive approximation analog-to-digital conversion method based on charge stacking according to claim 2, characterized in that, During the quantization phase, all N-1 analog-to-digital converters except the first one are suspended.

4. A successive approximation analog-to-digital converter circuit based on charge stacking, comprising: N serially connected analog-to-digital converters, characterized in that each of the analog-to-digital converters comprises: A common-source, cascode current mirror is used to receive analog signals; A digital-to-analog converter, including a capacitor array, wherein the input terminal of the digital-to-analog converter is connected to the output terminal of a common-source cascode current mirror, for replicating an analog current onto the capacitor array for sampling; The comparator has its positive input connected to a reference voltage and its negative input connected to the output of the digital-to-analog converter. A SAR logic module, wherein the input terminal of the SAR logic module is connected to the output terminal of the comparator, and the output terminal of the SAR logic module is connected to the input terminal of the digital-to-analog converter and the clock signal of the comparator; Switches SW1 and SW2 are alternately closed or opened under the control of the SAR logic module. Switch SW1 is located between the highest-order capacitor plates in the N capacitor arrays and is used to control the N capacitor arrays to be connected in a preset connection mode. Switch SW2 is located between the highest-order capacitor and the second-highest-order capacitor and is used to control the sampling and quantization processes of the N digital-to-analog converters. When switch SW2 is closed, the sampling stage begins: the sampling current is sampled on the capacitor arrays to obtain N sampling voltages. The sampling voltages of the N digital-to-analog converters are stacked as analog signals. When switch SW2 is opened, the capacitor arrays in the first digital-to-analog converter are quantized sequentially. The highest-order capacitor does not participate in the quantization. The preset connection mode includes: the lower plate of the highest-order capacitor of the first digital-to-analog converter is connected in series with the upper plate of the next highest-order capacitor of the next digital-to-analog converter, until the upper plate of the highest-order capacitor of the Nth digital-to-analog converter is connected. The lower plate of the highest-order capacitor of the Nth digital-to-analog converter is grounded.

5. The successive approximation analog-to-digital converter circuit based on charge stacking according to claim 4, characterized in that, The input terminal of the common-source cascode current mirror is also equipped with a clamping transistor for controlling the input clamping voltage.

6. The successive approximation analog-to-digital converter circuit based on charge stacking according to claim 5, characterized in that, The SAR logic module also includes a resistive variable memory for storing analog signals.

7. The successive approximation analog-to-digital converter circuit based on charge stacking according to claim 6, characterized in that, The output of the common-source cascode current mirror is also connected to an RST reset signal, which is used to control the voltage reset on the capacitor array.

8. The successive approximation analog-to-digital converter circuit based on charge stacking according to claim 7, characterized in that, The output of the common-source cascode current mirror is also connected to a sampling signal from a digital-to-analog converter, which is used to control the conversion of the sampling current into a sampling voltage.

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