A multiplier

Abstract

The application relates to an electronic technology field, and relates to a multiplier used for reducing operation time and area of the multiplier. The multiplier is used for multiplying a first value and a second value, and comprises P pre-encoders, P encoder groups and a compressor. Each pre-encoder is used for pre-encoding at least two bit positions in the second value to output a selection signal group; each encoder group is used for encoding the first value and the selection signal group output by the pre-encoder corresponding to the encoder group to output a partial product term; the P encoder groups comprise a first encoder group, a first encoder in the first encoder group is used for encoding a first selection signal group, a lowest bit position in the first value and a first sign bit to obtain a first partial product and a first output sign bit, the first selection signal group is the selection signal group output by a first pre-encoder, and the first pre-encoder corresponds to the first encoder group; and the compressor is used for compressing the partial product terms to obtain a plurality of accumulated values.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and more particularly to a multiplier. Background Technology

[0002] With the continuous development and maturation of artificial intelligence (AI) technology, AI technology has been gradually popularized in communication devices such as servers and terminals. AI technology places high demands on the computing power of processors in communication devices, such as central processing units (CPU), neural network processing units (NPU), graphics processing units (GPU), or digital signal processors (DSP). As the core computing unit of the processor, the multiplier plays an increasingly important role.

[0003] Existing multiplier architectures are designed based on standard encoders and standard adders, such as... Figure 1 As shown, the specific design implementation can be summarized into three steps: (1) The multiplicand and multiplier are encoded using the Radix-4 Booth algorithm in the encoder to obtain multiple partial product terms; (2) The permutation array including these multiple partial product terms is compressed using a Wallace tree; (3) The two accumulated values ​​obtained from the compressed permutation array are summed to obtain the multiplication result. Among them, for multipliers with an odd multiplier bit width, the multiplier needs to be extended by 1 bit sign bit by the pre-encoder. Figure 1 In this equation, the multiplier is represented as a binary number Y[N-1:0] with a bit width of N bits, the multiplier is represented as a binary number X[2M:0] with a bit width of (2M+1) bits, the value of X[2M:0] after being extended by 1 bit sign bit is represented as X[2M+1:0], and the result of the multiplication operation is represented as Z[N+2M+1:0].

[0004] The decimal number val(X) corresponding to the binary number X[2M+1:0] can be expressed as formula (1), where X 2M+1 X 2M X, ..., X0 represent the values ​​of each digit (or weight) in X[2M+1:0]. The principle of this multiplier for pre-encoding the binary number X[2M+1:0] is as follows: each odd term in formula (1) is decomposed using formula (2); each decomposed odd term is substituted into formula (1) to obtain formula (3); X in formula (3) is... 2k-1 X 2k and X2k+1 As a set of precoded terms. Then, through, as... Figure 2 The encoder group shown above will precode the group of terms (i.e., X). 2k-1 X 2k and X 2k+1 The precoded selection signal group (i.e., SM and S2M) is multiplied by the values ​​at different digits in Y[N-1:0] to obtain the corresponding partial product PP[N-1:0]. Figure 2 In this context, PP0 represents the 0 digits (i.e., 2) in Y[N-1:0]. 0 The partial product of the above numerical values, S 2k This indicates the sign bit corresponding to the precoding term in this group.

[0005] val(X) = -X 2M+1 ·2 2M+1 +X 2M ·2 2M +…+X1·2 1 +X0·2 0 (1)

[0006] X i ·2 i =X i ·2 i+1 +(-2X i )·2 i-1 , where i is an odd number (2)

[0007]

[0008] The multiplier mentioned above typically includes multiple encoder groups. The output of these encoder groups, which includes a partial product array, has a relatively dispersed shape. When the array is compressed using a Wallace tree, the Wallace tree will have a larger number of compression layers, resulting in a longer operation time and a larger area for the multiplier. Summary of the Invention

[0009] This application provides a multiplier to reduce the operation time and area of ​​the multiplier. To achieve the above objective, this application adopts the following technical solution:

[0010] In a first aspect, a multiplier is provided for multiplying an N-bit first value with a W-bit second value, where N and W are integers greater than 1. The multiplier includes: P pre-encoders, P encoder groups, and a compressor, wherein the P pre-encoders and the P encoder groups correspond one-to-one, and P is an integer greater than 1. Each of the P pre-encoders is used to pre-encode at least two bits of the second value to output a selection signal group. Each of the P encoder groups is used to encode the first value and the selection signal group output by the pre-encoder corresponding to the encoder group to output a partial product term, which includes multiple partial products. The P encoder groups... The encoder outputs P partial product terms; wherein, the P encoder groups include a first encoder group, the first encoder group includes a first encoder, the first encoder is used to encode a first selection signal group, the least significant bit and the first sign bit in a first value, to obtain a first partial product and a first output sign bit, the first selection signal group is the selection signal group output by the first pre-encoder in the P pre-encoders, the first sign bit is one of the at least two bits used by the first encoder during encoding, the first pre-encoder corresponds to the first encoder group; the compressor is used to compress the P partial product terms to obtain multiple accumulated values, the sum of the multiple accumulated values ​​is the product of the first value and the second value.

[0011] In the above technical solution, the P encoder groups include a first encoder group, which includes a first encoder. The first encoder is used to encode the least significant bit and the first sign bit in the first selection signal group and the first value during the encoding process. It can realize the pre-addition of the partial product obtained by the least significant bit encoding and the first sign bit, so that the array of multiple partial product terms output by the P encoder groups is more concentrated or more regular, thereby reducing the number of compression layers included in the compressor, and thus reducing the area of ​​the multiplier and improving the operation speed of the multiplier.

[0012] In one possible implementation of the first aspect, the first selection signal group includes a first selection signal, and the first encoder includes a first NAND gate, a first NOT gate, and a first AND gate. The output of the first NAND gate is coupled to the input of the first NOT gate and the first input of the first AND gate. The two inputs of the first NAND gate are respectively used to receive the least significant bit and the first selection signal, the output of the first NOT gate is used to output a first partial product, the second input of the first AND gate is used to receive a first sign bit, and the output of the first AND gate is used to output a first output sign bit. In the above possible implementation, the provided first encoder is simple and effective, capable of pre-adding the partial product obtained by encoding the least significant bit in the first value to the first sign bit. This makes the array of multiple partial product terms output by the P encoder groups more concentrated or regular, thereby reducing the number of compression layers included in the compressor, and thus reducing the area of ​​the multiplier and increasing the operation speed of the multiplier.

[0013] In one possible implementation of the first aspect, the P encoder groups include (P-1) first encoder groups. Optionally, the first encoder group to the (P-1)th encoder group in the P encoder groups are all first encoder groups. In the above possible implementation, the partial products of the least significant bit in the first value encoded in different encoder groups can be pre-added with different first sign bits by the (P-1) first encoder groups, thereby making the array of multiple partial product terms output by the P encoder groups more concentrated or more regular, thus reducing the number of compression layers included in the compressor, and further reducing the area of ​​the multiplier and improving the operation speed of the multiplier.

[0014] In one possible implementation of the first aspect, the first encoder is further configured to: encode a first output sign bit and a second sign bit to obtain a second output sign bit, wherein the second sign bit is the sign bit used by the pre-encoder corresponding to the next encoder group of the first encoder group, and the number of bits in the second sign bit in the partial product term is the same as the number of bits in the second output sign bit. In the above possible implementation, the multiplier further encodes the first output sign bit and the second sign bit through the first encoder, and encodes the constant 1 and the second partial product through the second encoder, thereby further regularizing the arrangement array of multiple partial product terms output by the P encoder groups, thereby further reducing the number of compression layers included in the compressor, further reducing the area of ​​the multiplier and improving the operation speed of the multiplier.

[0015] In one possible implementation of the first aspect, the first encoder further includes an OR gate; the two inputs of the OR gate are respectively used to receive a first output sign bit and a second sign bit, and the output of the OR gate is used to output a second output sign bit, with the third output sign bit being equal to the second sign bit. Optionally, the (P-1)th encoder group in the P encoder groups is the first encoder group. In the above possible implementations, the provided first encoder is simple and effective, capable of encoding the first output sign bit and the second sign bit, thereby making the array of multiple partial product terms output by the P encoder groups more concentrated or regularized, thus reducing the number of compression layers included in the compressor, and consequently reducing the area of ​​the multiplier and increasing the operation speed of the multiplier.

[0016] In one possible implementation of the first aspect, at least one of the P encoder groups further includes a second encoder; the second encoder is used to encode a constant 1 and a second partial product to obtain a third partial product and a fourth partial product. The second partial product is the partial product corresponding to the sign extension bit or a bit of the first value in the partial product term output by the encoder group to which the second encoder belongs, the third partial product corresponds to the same bit as the second partial product, and the bit corresponding to the fourth partial product is higher than the bit corresponding to the third partial product and the difference is 1. In the above possible implementation, by encoding the constant 1 and the second partial product by the second encoder, the arrangement array of multiple partial product terms output by the P encoder groups is further regularized, thereby further reducing the number of compression layers included in the compressor, so as to further reduce the area of ​​the multiplier and improve the operation speed of the multiplier.

[0017] In one possible implementation of the first aspect, the second encoder includes a second NOT gate; the input of the second NOT gate is used to receive a second partial product, the output of the second NOT gate is used to output a third partial product, and the fourth partial product is equal to the second partial product. In the above possible implementation, by encoding the constant 1 and the second partial product through the second NOT gate, the array of permutations including multiple partial product terms output by the P encoder groups is further regularized.

[0018] In one possible implementation of the first aspect, W is an odd number. The above possible implementations can reduce the area of ​​multipliers with odd multiplier bit widths and improve the multiplier's operational speed.

[0019] In one possible implementation of the first aspect, the P encoder groups further include a second encoder group, which is different from the first encoder group.

[0020] In one possible implementation of the first aspect, the multiplier further includes a summing circuit for receiving the plurality of accumulated values ​​and summing the plurality of accumulated values ​​to obtain the product.

[0021] In a second aspect, a processor is provided that includes the multiplier provided by the first aspect or any possible implementation thereof.

[0022] Thirdly, a chip is provided, comprising the multiplier provided in the first aspect or any possible implementation thereof.

[0023] Fourthly, a communication device is provided, the communication device including a processor, the processor including the multiplier provided in the first aspect or any possible implementation of the first aspect.

[0024] It is understood that any of the processors, processors, or communication devices provided above include the multipliers described above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects of the multipliers described above, and will not be repeated here. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the architecture of a multiplier;

[0026] Figure 2 This is a schematic diagram of the structure of a set of encoders;

[0027] Figure 3 This is a schematic diagram of a 9-bit × 9-bit multiplier.

[0028] Figure 4 This is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0029] Figure 5 This is a schematic diagram of the structure of a multiplier provided in an embodiment of this application;

[0030] Figure 6 A schematic diagram of a pre-encoder provided in an embodiment of this application;

[0031] Figure 7 This is a schematic diagram of the structure of a first encoder group provided in an embodiment of this application;

[0032] Figure 8 This is a schematic diagram of the structure of a second encoder group provided in an embodiment of this application;

[0033] Figure 9 This is a schematic diagram of an array and compressor provided in an embodiment of this application;

[0034] Figure 10 This is a schematic diagram of another first encoder group provided in an embodiment of this application;

[0035] Figure 11A schematic diagram illustrating the addition of a constant 1 and a partial product, provided as an embodiment of this application;

[0036] Figure 12 This is a schematic diagram of the structure of another first encoder group provided in an embodiment of this application;

[0037] Figure 13 This is a schematic diagram of another first encoder group provided in an embodiment of this application;

[0038] Figure 14 A schematic diagram of another arrangement array and compressor provided in the embodiments of this application;

[0039] Figures 15A-15E This application provides a schematic diagram of the structure of different pre-encoders and encoder groups in a multiplier.

[0040] Figure 16 This is a schematic diagram of a compressor provided in an embodiment of this application. Detailed Implementation

[0041] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c can be single or multiple. Furthermore, embodiments of this application use terms such as "first" and "second" to distinguish objects with similar names, functions, or roles. Those skilled in the art will understand that "first" and "second" do not limit the quantity or order of execution. The term "coupling" is used to indicate electrical connection, including direct connection via wires or connectors or indirect connection via other devices. Therefore, "coupling" should be considered as a broad type of electronic communication connection.

[0042] Before introducing the embodiments of this application, we will first introduce and explain the relevant technologies of multipliers with odd multiplier bit widths in the prior art.

[0043] In current multipliers with odd-numbered multiplier widths, the multiplier needs to be extended by 1 bit using a pre-encoder. Then, multiple encoder groups encode the multiplicand and the extended multiplier to obtain multiple partial product terms. Finally, a Wallace tree (also known as a compressor) compresses this array of partial product terms. Specifically, the Wallace tree includes multiple compression layers. For multiple bits within the same compression layer, multiple standard adders are used for parallel compression. Every three bits are compressed by a standard adder, outputting a carry-out bit and a sum-out bit.

[0044] For example, the output array of multiple encoder groups in the current multiplier is arranged as follows: Figure 3 As shown in (a) above, the Wallace tree includes multiple compressed layers as follows: Figure 3 As shown in (b) above. If the multiplier is a 9-bit × 9-bit multiplier, the multiple compaction layers in the Wallace tree are as follows: Figure 3 As shown in (c) in the figure. Figure 3 In the diagram, B0 to B18 represent different digits (i.e., 2^36 digits). 0 Up to 2 18 In this permutation array, different points represent different types of partial products (e.g., PPi, constant 1, sign extension E, and the inversion of sign extension E). In the Wallace tree, rectangles with different numbers represent adders in different compression layers (e.g., compression layers 1 to 10), rectangles with the same number represent different adders in the same compression layer, and circles with different numbers represent the carry-out bits obtained from compression by adders in different compression layers. Figure 3 As shown in (c), the Wallace tree in the 9-bit × 9-bit multiplier includes 10 compression layers, which in turn include 37 adders. It should be noted that this bit can also be called a weight bit, which refers to the bit at different positions in binary, similar to the ones, tens, and hundreds digits in decimal.

[0045] Because the sign bit generated by each encoder group in the current multiplier (for example, ...) Figure 3In the permutation array shown in (a), the digits of multiple sign bits (S) are mapped to the digits corresponding to the partial product obtained by encoding the least significant bit of the multiplier, resulting in a relatively dispersed shape of the permutation array. Therefore, when compressing this permutation array using a Wallace tree, the Wallace tree will include a larger number of compression layers, leading to a longer multiplier operation time and a larger area. Based on this, this application provides a multiplier that encodes the partial product obtained by encoding the sign bit and the least significant bit during the encoding process, making the shape of the encoded permutation array more concentrated, thereby reducing the number of compression layers included in the Wallace tree used to compress the permutation array, and thus reducing the area of ​​the multiplier and increasing its operation speed. The multiplier provided in this application can be applied to communication devices; a detailed description of the communication device and the multiplier is provided below.

[0046] Figure 4 This is a schematic diagram of the structure of a communication device provided in an embodiment of this application. The communication device may be a terminal, a server, or a chip, chipset, circuit board, or module within the terminal or server. See also... Figure 4 The communication device may include a memory 201, a processor 202, a communication interface 203, and a bus 204. The memory 201, processor 202, and communication interface 203 are interconnected via the bus 204. The memory 201 can be used to store data, software programs, and modules, and mainly includes a program storage area and a data storage area. The program storage area can store the operating system, applications required for at least one function, etc., while the data storage area can store data created during the use of the device. The processor 202 is used to control and manage the operation of the communication device, such as by running or executing software programs and / or modules stored in the memory 201, and by calling data stored in the memory 201 to perform various functions of the device and process data. The communication interface 203 is used to support communication by the device.

[0047] The processor 202 includes, but is not limited to, a central processing unit (CPU), a network processing unit (NPU), a graphics processing unit (GPU), a digital signal processor (DSP), or a general-purpose processor. The processor 202 includes one or more multipliers, such as a multiplier array, which are devices that implement multiplication operations within the processor 202.

[0048] Bus 204 can be a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 4 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0049] To further describe the technical solution, Figure 5 This is a schematic diagram of a multiplier provided in an embodiment of this application. The multiplier can be used to multiply an N-bit first value Y[N-1:0] by a W-bit second value X[W-1:0], where M and W are integers greater than 1. See also... Figure 5 The multiplier includes: P pre-encoders 31, P encoder groups 32 and compressor 33, with the P pre-encoders 31 and P encoder groups 32 corresponding one-to-one, where P is an integer greater than 1.

[0050] Each of the P precoders 31 is used to precode at least two bits in the second value X[W-1:0] to output a selection signal group. The P precoders 31 output P selection signal groups.

[0051] The bit width of the second value X[W-1:0] can be either odd or even. The at least two bits can be either two adjacent bits or three adjacent bits. For example, if the P precoders 31 include two precoders and the second value is a 4-bit binary number X[3:0], then the first precoder can be used to encode bits 0-1 (i.e., X0 and X1) of X[3:0], and the second precoder can be used to encode bits 1-3 (i.e., X1, X2, and X3) of X[3:0].

[0052] Alternatively, the selection signal group may include a first selection signal SM, or a first selection signal SM and a second selection signal S2M. The first selection signal SM and the second selection signal S2M may be two different signals.

[0053] Optionally, the P precoders 31 may include different precoders. In one example, such as Figure 6 As shown in (a), the pre-encoder is used to output SM and S2M. The pre-encoder 31 includes an XOR gate 311, an XOR gate 312, and a NOR gate 313. The first input of the XOR gate 311 is used to receive X. k-1The second input of XOR gate 311 is coupled to the first input of XOR gate 312 and is used to receive X. k The second input of the XOR gate 313 is used to receive X. k+1 The outputs of XOR gate 311 and XOR gate 312 are coupled to the two inputs of NOR gate 313, respectively. The output of XOR gate 311 is used to output SM, and the output of NOR gate 313 is used to output S2M. In another example, such as Figure 6 As shown in (b), the precoder can be used to output SM. The precoder 31 includes an XOR gate 314, the first input of which is used to receive X. k The second input of the XOR gate 314 is used to receive X. k+1 The output of the XOR gate 314 is used to output SM. Figure 6 X in k-1 X k and X k+1 This represents adjacent bits in the second value, where k is a positive integer less than W.

[0054] Each of the P encoder groups 32 is used to encode a first value and a selection signal group output by the pre-encoder 31 corresponding to that encoder group 32, to output a partial product term, which includes multiple partial products. The P encoder groups 32 output P partial product terms.

[0055] The P encoder groups 32 include at least one first encoder group 32a, which can be any one or more of the P encoder groups 32. Optionally, Figure 5 The at least one first encoder group 32a includes (P-1) first encoder groups 32a, and the (P-1) first encoder groups 32a are the first to (P-1) encoder groups among the P encoder groups 32.

[0056] Specifically, for each of the at least one first encoder group 32a, the first encoder group 32a includes a first encoder 321. The first encoder 321 is used to: encode a first selection signal group, the least significant bit of a first value, and a first sign bit to obtain a first partial product PP0' and a first output sign bit, wherein the bit corresponding to the first output sign bit is greater than the bit corresponding to the first sign bit and the difference is 1. The first selection signal group is the selection signal group output by the first pre-encoder 31 among the P pre-encoders 31, and the first sign bit is one of at least two bits used by the first pre-encoder during encoding. The first pre-encoder corresponds to the first encoder group 32a. It should be noted that the first encoder group 32a may include multiple encoders, and the first encoder 321 may be the encoder among the multiple encoders used to encode the least significant bit of the first value. Other encoders among the multiple encoders besides the first encoder 321 can be implemented using existing technology, and this application embodiment does not impose specific limitations on this.

[0057] That is, the first encoder 321 can be used to implement during the encoding process. (PP0 represents the partial product obtained by encoding the least significant bit Y0 using existing techniques) (Indicates the inversion of PP0) and the first sign bit S 2k The summation produces a summation output bit (PP0') and a carry output bit (S) as the first sign bit. 2k '. Among them, PP0' and S 2k The sum of the results and PP0 and S 2k The results of the addition are equal, thus the use of the first encoder 321 ensures that the final product is correct. The specific principle is as follows: Figure 2 It can be seen that PP0 satisfies formula (4). This represents the XOR operation; add an S to both sides of the equation in formula (4). 2k Then we get formula (5); the right side of the equation in formula (5) is calculated according to formula (6); for the calculation result of formula (6), if If PP0' = PP0_in, then PP0 + S can be obtained. 2k =PP0'+S 2k In the formula, PP0_in represents... Figure 2 PP0 and S in 2k Bit values ​​before encoding S represents 2k The opposite phase.

[0058]

[0059]

[0060] In one embodiment, such as Figure 7 As shown, the first encoder 321 includes a NAND gate 3211, a NOT gate 3212, and an AND gate 3213. The output terminal of the NAND gate 3211 is coupled to the input terminal of the NOT gate 3212 and the first input terminal of the AND gate 3213. Specifically, the two input terminals of the NAND gate 3211 are used to receive the least significant bit Y0 and SM from the first selection signal group, respectively; the output terminal of the NOT gate 3212 is used to output the first partial product PP0'; and the second input terminal of the AND gate 3213 is used to receive the first sign bit S. 2k (k is an integer), the output of AND gate 3213 is used to output the first output sign bit S. 2k It should be noted that... Figure 7 The document also shows other encoders in the first encoder group 32 besides the first encoder 321. The structure of these other encoders is merely exemplary and does not constitute a limitation on the embodiments of this application.

[0061] Optionally, the P encoder groups 32 may further include one or more second encoder groups 32b, which are different from the first encoder group 32a and do not include the first encoder 321. The other encoder groups in the P encoder groups 32 besides the at least one first encoder group 32a can be second encoder groups 32b. The second encoder groups 32b can be implemented using existing technology, and this application embodiment does not impose specific limitations on this. Figure 5 The following description uses the Pth encoder group out of the P encoder groups 32 as an example to illustrate the second encoder group 32b. For instance, the second encoder group 32b includes multiple encoders, which may include encoders with different structures. For example, ... Figure 8 As shown, the second encoder group 32b may include two types of encoders. The first encoder includes an AND gate and an XOR gate, and the second encoder includes an AND gate and an XOR gate. Each second encoder group 32b is used to encode the first value Y[N-1:0], the corresponding pre-encoder output SM, and the sign bit S. 2k This yields a partial product term. Figure 8 The second encoder group 32b shown is merely exemplary and does not constitute a limitation on the embodiments of this application.

[0062] Compressor 33 is used to compress the P partial product terms to obtain multiple accumulated values. The sum of these multiple accumulated values ​​is the product of the first value Y[N-1:0] and the second value X[W-1:0].

[0063] The compressor 33 may include Q compression layers, where Q is a positive integer. When Q equals 1, the compressor 33 includes a first compression layer, which compresses each bit in the array of partial product terms sequentially from low to high bit order to obtain a first compression array. Each row in the first compression array is an accumulated value. Each row in the array of partial products includes a partial product term, and each column includes multiple bits corresponding to the same bit in the multiple partial product terms. A partial product term includes multiple partial products corresponding to the output of an encoder group. When Q is an integer greater than 1, the compressor 33 includes: a first compression layer to a Qth compression layer; the first compression layer is used to compress each bit in the arrangement array of multiple partial products in order from low bit to high bit to obtain a first compression array; the jth compression layer is used to compress each bit in the (j-1)th compression array in order from low bit to high bit to obtain a jth compression array, where the value of j ranges from 2 to W, and the Qth compression array may include two or more rows, each row corresponding to an accumulated value, so that the Qth compression array includes multiple accumulated values.

[0064] Specifically, each compression layer compresses three bits of each digit, without compressing the carry-out bit and the current sum bit obtained from the compression layer. For example, for every three bits of each digit, each adder in the compression layer (using a standard adder as an example) performs the following compression: if all three bits are 0, the carry-out bit is 0 and the current sum-out bit is 0; if all three bits are 1, the carry-out bit is 1 and the current sum-out bit is 1; if one bit is 1 and the other two are 0, the carry-out bit is 0 and the current sum-out bit is 1; if two bits are 1 and the other bit is 0, the carry-out bit is 1 and the current sum-out bit is 1.

[0065] It should be noted that the carry-out output bit refers to the output bit of the next digit after the current compressed number, while the current summation output bit refers to the output bit after the current compressed number is compressed. For example, suppose the current compressed number is 2. 5 The next digit after the current compressed number is 2. 6 Compression 2 5 If all three corresponding bits are 1, then the compressed result is 2. 5 The above corresponds to generating a current summation output bit with a bit set to 1, 2 6 This corresponds to generating a carry-out bit with a value of 1.

[0066] For ease of understanding, taking N = 2M + 1, where the first to (P-1)th encoder groups in the P encoder groups 32 are all the first encoder group 32a as an example, the permutation array corresponding to the multiple partial product terms output by the P encoder groups 32 is as follows: Figure 9 As shown in (a) above. Compare Figure 9 (a) and Figure 3 From (a) we can see that, Figure 9 (a) shows the multiple output sign bits (i.e., S). 0’ To S 2M’ The digits of S are mapped onto the digits corresponding to the partial product obtained by encoding the second lowest bit of the multiplier. 0’ To S 2M’ respectively with Figure 3 In (a) shown, the multiple sign bits S are shifted forward by one position compared to each other. This makes the shape of the arrangement array more concentrated or more regular. Accordingly, Figure 9 (b) shows the multiple compression layers included in the compressor 33 used to compress the array and the adder in each compression layer. If the multiplier is a 9-bit × 9-bit multiplier, such as... Figure 9 As shown in (c), the compressor 33 includes 7 compression layers, which together include 34 adders. Therefore, compared with the prior art, the multiplier provided in this application reduces the number of compression layers and the total number of adders included in the compressor 33, thereby reducing the area of ​​the multiplier and increasing the operation speed of the multiplier. Figure 9 In the diagram, B0 to B18 represent different digits (i.e., 2^36 digits). 0 Up to 2 18 In this permutation array, different points represent different types of partial products (e.g., PPi, PP0', constant 1, sign extension bit E, and the inversion of sign extension bit E). In compressor 33, rectangles with different numbers represent adders in different compression layers (e.g., the first to the seventh compression layers), rectangles with the same number represent different adders in the same compression layer, and circles with different numbers represent carry-out bits obtained by compressing adders in different compression layers.

[0067] Optionally, the multiplier further includes an adder circuit 34, configured to receive the plurality of accumulated values ​​and sum the plurality of accumulated values ​​to obtain the product of the first value Y[N-1:0] and the second value X[W-1:0]. For example, the plurality of accumulated values ​​are two accumulated values, and the adder circuit 34 is an adder configured to receive these two accumulated values ​​and sum the two accumulated values ​​to obtain the product of the first value Y[N-1:0] and the second value X[W-1:0].

[0068] Furthermore, the first encoder 321 is also used to: encode a first output sign bit and a second sign bit to obtain a second output sign bit. The second sign bit is the sign bit output by the pre-encoder corresponding to the next encoder group in the first encoder group 31a to which the first encoder 321 belongs. The number of bits in the corresponding partial product term of the second sign bit is the same as the number of bits corresponding to the second output sign bit, and the number of bits corresponding to the first output sign bit is the same as the number of bits corresponding to the second output sign bit. Optionally, the (P-1)th encoder group 32 in the P encoder groups 32 may include the first encoder 321 described above.

[0069] In one embodiment, combined with Figure 7 ,like Figure 10 As shown, when W is odd and W = 2M + 1, and the first encoder 321 is the (P-1)th encoder group 32, the first encoder 321 further includes an OR gate 3214. The two input terminals of the OR gate 3214 are respectively used to receive the first output sign bit S. (2M-2) ' and the second sign bit S 2M The output of OR gate 3214 is used to output the second output sign bit S. (2M-2) ", second sign bit S 2M The digits in the corresponding partial product term and the second output sign bit S (2M-2) "The corresponding digits are the same, the second output sign bit S" (2M-2) "and the first output sign bit S (2M-2) The corresponding digits are the same. X 2M-1 X 2M-2 and X 2M-3 This represents at least two bits pre-encoded by the pre-encoder 31 corresponding to the (P-1)th encoder group 32.

[0070] That is, taking k=M as an example, the first encoder 321 is also used to convert the second sign bit S during the encoding process. 2M and the first output sign bit S (2M-2) 'Split into the second output sign bit S' (2M-2) The specific analysis is as follows: When S (2M-2) When '=1, then X 2M-1 =1, when X 2M-1 When X = 1, regardless of X 2M S exists whether the value is 1 or 0. 2M =0, therefore S (2M-2) 'with S 2M They are not both 1. Therefore, S 2M ×2 2M Split into two S 2M ×2 2M-1 Because of S (2M-2) 'with S 2M Since they are not both 1, S can be converted to 1 using OR gate 3214.(2M-2) 'and split to obtain an S 2M Merge into S (2M-2) ", to split the other S 2M As another output sign bit, it is output to the second output sign bit S. (2M-2) "Corresponding digits."

[0071] Furthermore, at least one of the P encoder groups 32 further includes a second encoder 322. The second encoder 322 is used to encode the constant 1 and the second partial product to obtain a third partial product and a fourth partial product. The second partial product is the partial product corresponding to the sign extension bit or a bit of the first value in the partial product term output by the encoder group to which the second encoder 322 belongs after encoding. The third partial product corresponds to the same bit as the second partial product, and the bit corresponding to the fourth partial product is higher than the bit corresponding to the third partial product and the difference is 1.

[0072] That is to say, such as Figure 11 As shown, the second encoder 322 can be used to add the constant 1 and the second part product during the encoding process. The summation output bit generated after the addition is the third part product, the carry output bit is the fourth part product, the third part product is the inversion of the second part product, and the fourth part product is equal to the second part product. Figure 11 The second part product is denoted as PPk, and the third part product is denoted as... The fourth part product is denoted as PPk, and the corresponding digits of the second and third part products are represented as 2. k Represent the digits corresponding to the fourth partial product as 2. k+1 .

[0073] In one embodiment, the second encoder 322 includes a NOT gate 3221. The input of the NOT gate 3221 is used to receive the second partial product, and the output of the NOT gate 3221 is used to output the third partial product. The fourth partial product is equal to the second partial product. Optionally, the second encoder 322 also includes other gate circuits. The structure of the second encoder 322 will be different when the second partial product is a sign extension bit or a partial product corresponding to a bit of the first value after encoding.

[0074] In one example, such as Figure 12 As shown, the second part of the product is the sign extension bit E. 2k The second encoder 322 further includes a first AND gate 3222, a second AND gate 3223, an OR gate 3224, and an XOR NOT gate 3225. The first input terminals of the first AND gate 3222 and the second AND gate 3223 are both used to receive the last bit Y in the first value Y[N-1:0]. N-1The second input of the first AND gate 3222 is used to receive the first selection signal SM, and the second input of the second AND gate 3223 is used to receive the second selection signal S2M. The outputs of the first AND gate 3222 and the second AND gate 3223 are respectively coupled to the two inputs of the OR gate 3224. The output of the OR gate 3224 is coupled to the first input of the XOR gate 3225. The second input of the XOR gate 3225 is used to receive the sign bit S. 2k The output of the XOR gate 3225 is coupled to the input of the NOT gate 3221. The output of the XOR gate 3225 is used to output the fourth partial product E. 2k The output of NOT gate 3221 is used to output the third part of the product.

[0075] In another example, such as Figure 13 As shown, the second partial product is the last bit Y in the first value Y[N-1:0]. N-1 The encoded partial product PP(M-1) is further represented by the second encoder 322, which includes a first AND gate 3226, a second AND gate 3227, an OR gate 3228, and an XOR gate 3229. The two inputs of the first AND gate 3226 are used to receive the last bit Y in the first value Y[N-1:0]. N-1 The first selection signal SM and the two inputs of the second AND gate 3227 are used to receive the second-to-last bit Y in the first value Y[N-1:0]. N-2 The second selection signal S2M, the outputs of the first AND gate 3226 and the second AND gate 3227 are respectively coupled to the two inputs of the OR gate 3228, the output of the OR gate 3228 is coupled to the first input of the XOR gate 3229, and the second input of the XOR gate 3229 is used to receive the sign bit S. 2k The output of XOR gate 3229 is coupled to the input of NOT gate 3221. The output of XOR gate 3229 is used to output the fourth partial product PP(M-1), and the output of NOT gate 3221 is used to output the third partial product.

[0076] For example, in combination Figure 9 In (a), when the P encoder groups 32 use Figures 10-12 In the described scheme, the permutation array corresponding to the multiple partial product terms output by the P encoder groups 32 is as follows: Figure 14 As shown in (a) above, it is about to Figure 9 S is shown in (a) (2M-2) 'and S 2M Replace with Figure 14 S is shown in (a) (2M-2) "and S 2M ,Will Figure 9The constant 1 in output (a) is added in advance during the encoding process. Correspondingly, the compressor 33 used to compress this array includes multiple compression layers with the structure as follows: Figure 14 As shown in (b) of the diagram. Figure 14 In this permutation array, different points represent different types of partial products (e.g., PPi, PP0', constant 1, sign extension E, and the inversion of sign extension E). Sign bit S 2M and the output sign bit S 2k 'and S (2M-2) In compressor 33, rectangles with different numbers represent adders in different compression layers (e.g., the first compression layer to the seventh compression layer), rectangles with the same number represent different adders in the same compression layer, and circles with different numbers represent carry-out bits obtained by compressing adders in different compression layers.

[0077] For ease of understanding, taking a 9-bit × 9-bit (i.e., Y[8:0] × X[8:0]) multiplier provided in this embodiment as an example, the number of the P pre-encoders 31 and the P encoder groups 32 are both equal to 5, and the compressor 33 includes 3 compression layers. The 5 pre-encoders 31, the 5 encoder groups 32, and the compressor 33 will be described in detail below. Figure 15A As shown, the first pre-encoder 31 is used to pre-encode 0, X0, and X1 to output SM0 and S2M0; the first encoder group 32 is used to encode Y0 to Y8, SM0, and S2M0, as well as the sign bit S0, in the first numerical value Y[8:0] to output the first partial product term (including PP0-0 to PP8-0, E0-0, ...). S0'). For example Figure 15B As shown, the second pre-encoder 31 is used to pre-encode X1, X2, and X3 to output SM2 and S2M2; the second encoder group 32 is used to encode Y0 to Y8, SM2, and S2M2, as well as the sign bit S2, in the first numerical value Y[8:0] to output the first partial product terms (including PP0-2 to PP8-2, ...). E0-2, S2'). For example... Figure 15C As shown, the third pre-encoder 31 is used to pre-encode X3, X4, and X5 to output SM4 and S2M4; the third encoder group 32 is used to encode Y0 to Y8, SM4, and S2M4, as well as the sign bit S4, in the first numerical value Y[8:0] to output the first partial product term (including PP0-4 ​​to PP8-4, E0-4, and S4'). Figure 15DAs shown, the fourth pre-encoder 31 is used to pre-encode X5, X6, and X7 to output SM6 and S2M6; the fourth encoder group 32 is used to encode Y0 to Y8, SM6, and S2M6, as well as the sign bits S6 and S8, in the first numerical value Y[8:0] to output the first partial product terms (including PP0-6 to PP8-6, E0-6, and S6”). Figure 15E As shown, the fifth pre-encoder 31 is used to pre-encode X7 and X8 to output SM8; the fifth encoder group 32 is used to encode Y0 to Y8, SM8, and the sign bit S8 in the first numerical value Y[8:0] to output the first partial product term (including PP0-8 to PP8-8, E0-8, and S8). It should be noted that... Figures 15A to 15E The structures of the pre-encoders and encoder groups shown are merely exemplary. For a structural description of each pre-encoder and each encoder group, please refer to the relevant description above. The embodiments of this application will not be repeated here.

[0078] like Figure 16 As shown, the compressor 33 includes three compression layers. The first compression layer includes 13 adders, the second compression layer includes 9 adders, and the third compression layer includes 7 adders, thus the three compression layers together include 29 adders. Figure 16 and Figure 3 Compared to the prior art compressor shown in (c), the number of compression layers is reduced by 7 and the total number of adders used is reduced by 8, thereby greatly reducing the number of compression layers and the total number of adders included in the compressor 33, and thus reducing the area of ​​the multiplier and increasing the operation speed of the multiplier. Figure 16 In the diagram, B0 to B18 represent different digits (i.e., 2^36 digits). 0 Up to 2 18 In this permutation array, different points represent different types of partial products (see details...). Figure 14 (as described), in compressor 33, rectangles with different numbers represent adders in different compression layers (e.g., the first to the third compression layers), rectangles with the same number represent different adders in the same compression layer, and circles with different numbers represent carry-out bits obtained by compressing adders in different compression layers.

[0079] In the multiplier provided in this embodiment, the P encoder groups include a first encoder group, which in turn includes a first encoder. The first encoder encodes the least significant bit and the first sign bit in the first selection signal group and the first numerical value during the encoding process. This allows for the pre-addition of the partial product obtained from the least significant bit encoding with the first sign bit, thereby making the array of multiple partial product terms output by the P encoder groups more concentrated or regularized. This reduces the number of compression layers in the compressor, thus reducing the area of ​​the multiplier and increasing its operation speed. Furthermore, the multiplier also encodes the first output sign bit and the second sign bit through the first encoder, and the constant 1 and the second partial product through the second encoder, further regularizing the array of multiple partial product terms output by the P encoder groups. This further reduces the number of compression layers in the compressor, further reducing the area of ​​the multiplier and increasing its operation speed.

[0080] In another embodiment of this application, a processor is also provided, the processor including a multiplier; wherein the multiplier is any of the multipliers provided above.

[0081] In another embodiment of this application, a chip is also provided, the chip including a multiplier; wherein the multiplier is any of the multipliers provided above.

[0082] In another embodiment of this application, a communication device is also provided, the structure of which can be as follows: Figure 4 As shown, the communication device may include a memory 201, a processor 202, a communication interface 203, and a bus 204. The processor 202 may include any of the multipliers described above.

[0083] It should be noted that the descriptions of the multiplier in the above text can be applied to the multipliers included in the processor, the chip, and the communication device, and will not be repeated here in the embodiments of this application.

[0084] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A multiplier, characterized in that, The multiplier is used to multiply an N-bit first value by a W-bit second value, where N and W are integers greater than 1. The multiplier includes P pre-encoders, P encoder groups, and a compressor. The P pre-encoders and the P encoder groups correspond one-to-one, and P is an integer greater than 1. Each of the P precoders is used to precode at least two bits in the second value to output a selection signal group; Each of the P encoder groups is used to encode the first value and the selection signal group output by the pre-encoder corresponding to the encoder group to output a partial product term, the partial product term including multiple partial products; the encoders of the P encoder groups output P partial product terms respectively. Wherein, the P encoder groups include a first encoder group, the first encoder group includes a first encoder, the first encoder is used to encode a first selection signal group, the least bit of the first value and a first sign bit to obtain a first partial product and a first output sign bit, the bit corresponding to the first output sign bit is greater than the bit corresponding to the first sign bit and the difference is 1, the first selection signal group is the selection signal group output by the first pre-encoder in the P pre-encoders, the first sign bit is one of the at least two bits used by the first encoder during encoding, and the first pre-encoder corresponds to the first encoder group; The compressor is used to compress the P partial product terms to obtain multiple accumulated values, the sum of which is the product of the first value and the second value.

2. The multiplier according to claim 1, characterized in that, The first selection signal group includes a first selection signal, and the first encoder includes: a first NAND gate, a first NOT gate, and a first AND gate, wherein the output terminal of the first NAND gate is coupled to the input terminal of the first NOT gate and the first input terminal of the first AND gate; Wherein, the two input terminals of the first NAND gate are used to receive the least bit and the first selection signal, respectively; the output terminal of the first NOT gate is used to output the first partial product; the second input terminal of the first AND gate is used to receive the first sign bit; and the output terminal of the first AND gate is used to output the first output sign bit.

3. The multiplier according to claim 1, characterized in that, The P encoder groups include (P-1) of the first encoder groups.

4. The multiplier according to any one of claims 1-3, characterized in that, The first encoder is also used for: The first output sign bit and the second sign bit are encoded to obtain the second output sign bit, which is the sign bit used by the pre-encoder corresponding to the next encoder group of the first encoder group. The number of bits in the second sign bit in the partial product term is the same as the number of bits in the second output sign bit.

5. The multiplier according to claim 4, characterized in that, The first encoder further includes: an OR gate; The two inputs of the OR gate are used to receive the first output sign bit and the second sign bit, respectively, and the output of the OR gate is used to output the second output sign bit.

6. The multiplier according to claim 4, characterized in that, The (P-1)th encoder group among the P encoder groups is the first encoder group.

7. The multiplier according to any one of claims 1-3, characterized in that, At least one of the P encoder groups further includes a second encoder; The second encoder is used to encode a constant 1 and a second partial product to obtain a third partial product and a fourth partial product. The second partial product is the partial product corresponding to the sign extension bit or a bit of the first value in the partial product term output by the encoder group to which the second encoder belongs. The third partial product corresponds to the same number bit as the second partial product, and the number bit corresponding to the fourth partial product is higher than the number bit corresponding to the third partial product and the difference is 1.

8. The multiplier according to claim 7, characterized in that, The second encoder includes a second NOT gate; The input of the second NOT gate is used to receive the second partial product, the output of the second NOT gate is used to output the third partial product, and the fourth partial product is equal to the second partial product.

9. The multiplier according to any one of claims 1-3, characterized in that, The number W is odd.

10. The multiplier according to any one of claims 1-3, characterized in that, The P encoder groups also include a second encoder group, which is different from the first encoder group.

11. The multiplier according to any one of claims 1-3, characterized in that, The multiplier also includes: A summing circuit is used to receive the plurality of accumulated values ​​and sum the plurality of accumulated values ​​to obtain the product.

12. A processor, characterized in that, The processor includes a multiplier as described in any one of claims 1-11.

13. A communication device, characterized in that, The communication device includes a multiplier as described in any one of claims 1-11.

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