Vector register file cache system based on risc-v instruction set

Abstract

The application provides a vector register stack cache system based on a RISC-V instruction set, and relates to the field of register stacks; the system comprises an instruction scheduling unit, an execution unit, a cache register, a vector register stack and a loading unit; the instruction scheduling unit is used for sending a cache instruction to the execution unit, the execution unit receives the cache instruction, and the cache register and the vector register stack are controlled to perform actions; the instruction scheduling unit is also used for sending a loading instruction corresponding to the cache instruction to the loading unit, and transmitting loading content corresponding to the loading instruction into the vector register stack; in this way, internal conflicts of the cache register, the vector register stack, the execution unit and the like can be reduced, performance is improved, and the recording cache unit connected with the cache register is used to realize the following: when a conflict occurs, the loading content that causes the conflict is cached, and the content that causes the conflict is revised, such as being renamed, so that the situation of difficult-to-avoid access conflicts is solved.

Description

Technical Field

[0001] This invention relates to the field of register files, and more specifically, to a vector register file caching system based on the RISC-V instruction set. Background Technology

[0002] RISC-V is an open-source instruction set architecture based on the principles of reduced instruction set computing. It boasts a complete toolchain, allowing anyone to design, manufacture, and sell RISC-V chips and software, offering immense potential for development. As society evolves, the industry's demands for processor performance are increasing, leading to the emergence of vector instructions. Vector instructions perform single-instruction multiple-data processing, trading area for time. Currently, almost all instruction set architectures support vector instructions, and the vector register file is the core component for implementing them. A robust vector register file system is crucial in the design of vector processors. Vector register files typically employ a multi-bank structure, upon which different processing structures are designed to improve processor performance.

[0003] The shortcomings of existing technology:

[0004] 1. The vector-dependent data path used in the RISC-V instruction set architecture is not optimized for all types of full vector register file data processing instructions. The use of expand, slide, narrow, etc. requires optimization of the data path design, which will involve a lot of repetitive work.

[0005] 2. One set of code corresponds to one set of hardware design, resulting in poor portability;

[0006] 3. Access conflicts are unavoidable when operating a VRF bank;

[0007] 4. Vector processors frequently access the VRF when performing memory-related and computation-related operations, which increases the probability of access conflicts. Summary of the Invention

[0008] The purpose of this invention is to provide a vector register file cache system based on the RISC-V instruction set to solve the problems existing in the background art.

[0009] The embodiments of the present invention are implemented as follows:

[0010] This application provides a vector register file cache system based on the RISC-V instruction set, including an instruction scheduling unit, an execution unit, a cache register, a vector register file, and a loading unit connected in sequence, and also includes a queue unit connected to the execution unit, the cache register, and the vector register file respectively;

[0011] The instruction scheduling unit is used to send cached instructions to the execution unit;

[0012] The execution unit is used to receive cache instructions and control the cache registers and vector register files to perform actions corresponding to the cache instructions;

[0013] The instruction scheduling unit is also used to send loading instructions corresponding to cached instructions to the loading unit;

[0014] The loading unit is used to receive loading instructions and pass the loading content corresponding to the loading instructions into the vector register file;

[0015] The queue unit is used to receive the loaded content sent by the vector register file and send the loaded content to the execution unit;

[0016] The execution unit is also used to perform calculations on the loaded content, obtain the calculation results, and transfer the calculation results to the cache register.

[0017] The beneficial effects of this invention are: by using a cache register to transfer loaded content between the execution unit and the vector register file, the cache register receives requests or results from the execution unit and can forward these received results to the queue unit and the execution unit so that the cache register can use the data of the received results when executing cached instructions, and delays writing the results back to the vector register file; thereby solving the problem of frequent access to the vector register file and amplified access conflict probability when the vector processor performs memory-related operations or computation-related operations.

[0018] Based on the above technical solution, the present invention can be further improved as follows.

[0019] Furthermore, the system also includes an expansion interface, which is connected to the cache register;

[0020] An extension interface is used to connect external devices that participate in the computation of loading content.

[0021] The beneficial effects of adopting the above-mentioned further solution are: the set extension interface puts the instruction processing outside the LANE, and realizes cross-LANE operation while modular design; thus solving the problem that the vector-dependent data path used for the RISC-V instruction set architecture has not been optimized for all types of full vector register file data processing instructions, and that using expand, slide, narrow, etc. requires optimizing the data path design for them, which would involve a lot of repetitive work.

[0022] Furthermore, the system also includes a storage unit connected to a cache register;

[0023] The storage unit is used to store the loaded content and the corresponding calculation results.

[0024] The beneficial effect of adopting the above-mentioned further solution is that it enables the storage of the loaded content and the corresponding calculation results.

[0025] Furthermore, the system also includes a recording cache unit, which is connected to a cache register;

[0026] A recording cache unit is used to receive the loaded content that has an access conflict sent by the cache register, revise the loaded content, and transmit the revised loaded content to the cache register.

[0027] The beneficial effect of adopting the above-mentioned further solution is that, through the record cache unit connected to the cache register, when an access conflict occurs, the cache register transfers the conflicting object to the record cache unit, the record cache unit caches the conflicting loaded content, and renames or otherwise modifies the conflicting content. After the modification, the loaded content that will not cause an access conflict is transferred back to the cache register, thereby resolving the situation where there is an unavoidable access conflict.

[0028] Furthermore, the aforementioned loading unit is connected to the vector register file via a loading data path, which is used to transfer the loading content corresponding to the loading instruction in the loading unit into the vector register file.

[0029] The beneficial effect of adopting the above-mentioned further scheme is that it enables the loading content corresponding to the loading instruction in the loading unit to be transferred into the vector register file.

[0030] Furthermore, the aforementioned vector register file and queue unit are connected via a read data path. Specifically, the vector register file is used to transfer the loaded content into the queue unit via the read data path.

[0031] The beneficial effect of adopting the above-mentioned further solution is that it enables the loaded content to be passed into the queue unit.

[0032] Furthermore, the cache register and the queue unit are connected via a first data bypass. The cache register is also used to transfer loaded content that cannot be calculated or cannot yield calculation results into the queue unit via the first data bypass.

[0033] The beneficial effect of adopting the above-mentioned further solution is that it enables the loading content that cannot be calculated or cannot obtain calculation results to be passed into the queue unit.

[0034] Furthermore, the aforementioned cache register is connected to the execution unit via a second data bypass and a write-back data path. The write-back data path is used to enable the execution unit to control the cache register to perform actions corresponding to cached instructions. The cache register is also used to transfer loaded content that cannot be calculated or cannot yield calculation results into the execution unit via the second data bypass.

[0035] The beneficial effects of adopting the above-mentioned further scheme are: to enable the execution unit to control the cache register to perform actions corresponding to the cache instructions, and to pass the loaded content that cannot be operated or cannot obtain the operation result into the execution unit through the second data bypass.

[0036] Furthermore, the aforementioned cache register and vector register file are connected via a write data path. Specifically, the cache register is used to transmit cached instructions to the vector register file via the write data path, thereby controlling the vector register file to perform actions corresponding to the cached instructions.

[0037] The beneficial effect of adopting the above-mentioned further scheme is that it enables the control vector register file to perform actions corresponding to cached instructions.

[0038] Furthermore, the aforementioned cache register and storage unit are connected via a storage data path. Specifically, the storage unit is used to store the loaded content and the corresponding calculation results through the storage data path.

[0039] The beneficial effect of adopting the above-mentioned further solution is that it enables the storage of loaded content and the corresponding calculation results through a data storage path. Attached Figure Description

[0040] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a system block diagram of the caching system in an embodiment of the present invention;

[0042] Figure 2 This is a schematic diagram of the connection of the ring component in an embodiment of the present invention. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0044] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0045] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0046] Example

[0047] This embodiment provides a vector register file cache system based on the RISC-V instruction set, including an instruction scheduling unit, an execution unit, a cache register, a vector register file, and a loading unit connected in sequence, and also includes a queue unit connected to the execution unit, the cache register, and the vector register file respectively;

[0048] The instruction scheduling unit is used to send cached instructions to the execution unit;

[0049] The execution unit is used to receive cache instructions and control the cache registers and vector register files to perform actions corresponding to the cache instructions;

[0050] Optionally, the cache register and the vector register file are connected via a write data path. Specifically, the cache register is used to transfer cached instructions to the vector register file via the write data path, thereby controlling the vector register file to perform actions corresponding to the cached instructions.

[0051] Specifically, the loaded content is transferred between the execution unit and the vector register file via a cache register; see [link to relevant documentation]. Figure 1The cache register receives requests or results from the execution unit (vector operation unit or floating-point vector function unit, etc.), and can forward these received results to the queue unit and the execution unit so that the data of the received results can be used when the cache register executes cached instructions, and the results are written back to the vector register file with delay. This solves the problem of frequent access to the vector register file when the vector processor performs memory-related operations or operation-related operations, which amplifies the probability of access conflicts.

[0052] Optionally, the cache register and the execution unit are connected via a second data bypass and a write-back data path. The write-back data path is used to enable the execution unit to control the cache register to perform actions corresponding to cached instructions. The cache register is also used to pass loaded content that cannot be calculated or cannot yield calculation results into the execution unit via the second data bypass.

[0053] The instruction scheduling unit is also used to send loading instructions corresponding to cached instructions to the loading unit;

[0054] The loading unit is used to receive loading instructions and pass the loading content corresponding to the loading instructions into the vector register file;

[0055] Optionally, the aforementioned loading unit is connected to the vector register file via a loading data path, which is used to transfer the loading content corresponding to the loading instruction in the loading unit into the vector register file.

[0056] The queue unit is used to receive the loaded content sent by the vector register file and send the loaded content to the execution unit;

[0057] The vector register file consists of multiple parallel single read / write ports. Based on the priority of the loaded content in the execution unit's operation queue unit, the arbitrated loaded content enters the operand queue of the corresponding execution unit in the queue unit through the read data path. The data width of the loaded content read out by the queue unit each time is the actual element width of the vector.

[0058] Optionally, the vector register file and the queue unit are connected via a read data path. Specifically, the vector register file is used to transfer the loaded content into the queue unit via the read data path.

[0059] Optionally, the cache register and the queue unit are connected via a first data bypass. The cache register is also used to transfer loaded content that cannot be calculated or cannot yield calculation results into the queue unit via the first data bypass.

[0060] The execution unit is also used to perform calculations on the loaded content, obtain the calculation results, and transfer the calculation results to the cache register.

[0061] Optionally, the system further includes a recording cache unit, which is connected to a cache register;

[0062] A recording cache unit is used to receive the loaded content that has an access conflict sent by the cache register, revise the loaded content, and transmit the revised loaded content to the cache register.

[0063] In order to reduce internal conflicts in cache registers, vector register files, and execution units, and improve performance, a record cache unit connected to the cache register is used.

[0064] Furthermore, based on the above-mentioned recording cache unit configuration, when an access conflict occurs, the cache register transfers the conflicting object to the recording cache unit. The recording cache unit caches the conflicting loaded content and renames or modifies the conflicting content. After modification, the loaded content that will not cause an access conflict is transferred back to the cache register, thereby resolving the situation where there is an unavoidable access conflict.

[0065] Optionally, the system may also include a storage unit connected to a cache register;

[0066] The storage unit is used to store the loaded content and the corresponding calculation results. The cache register is connected to the storage unit via a storage data path. Specifically, the storage unit stores the loaded content and the corresponding calculation results through this storage data path.

[0067] Optionally, the cache register and the storage unit are connected via a storage data path. The storage unit is specifically used to store the loaded content and the corresponding calculation results via the storage data path.

[0068] The data storage purpose is achieved through the aforementioned data loading path, data reading path, first data bypass, data writing back path, second data bypass, data writing path, and data storage path. The specific steps are as follows:

[0069] S1. The instruction scheduling unit sends the cached instructions to be executed to the execution unit;

[0070] S2. The execution unit requests the loaded content for the computation from the cache register and vector register file;

[0071] S3. When a conflict occurs between executing a cache instruction and accessing the vector register file, the cache register will delay the access and record the corresponding loaded content in the record cache unit; or when executing the corresponding cache instruction across LANE, the loaded content will be sent to the node on the outer ring of the LANE through the extended interface.

[0072] S4. The queue unit obtains the loaded content from the vector register file and sends the loaded content to the corresponding execution unit;

[0073] S5. If the execution unit has not completed the operation on the loaded content, it shall use the first data bypass of the cache register or the second data bypass of the vector register file cache, and re-enter the execution unit with the next loaded content to be operated on, as given by the vector register file, to participate in the operation.

[0074] S6. If the execution unit completes the operation on the loaded content, it sends the loaded content and the corresponding operation result to the cache register and the vector register file. The cache register then transfers the data to the record cache unit and simultaneously sends it to the storage unit. The loaded content with lower priority and the corresponding operation result are sent to the vector register file. The storage mode of this storage unit is little-endian mode, in which the loaded content of the least significant byte is stored first, and the loaded content with lower priority is the loaded content of the most significant byte.

[0075] Optionally, the above system can achieve the following steps when executing cache instructions and loading content:

[0076] ST1: The execution unit sends an interaction request to the cache register, that is, the execution unit controls the cache register's operation through the received cache instructions;

[0077] ST2-1: Cross-LANE operation: The cache register requests data from the vector register file and sends it to the extension interface. The extension interface connects to the nodes of the LANE outer ring to send and receive the loaded content and write it back to the vector register file.

[0078] ST2-2: Execution of cache instruction end operation: The calculation result of the loaded content is directly given to the storage unit outside the lane, and the storage unit caches the data to complete subsequent storage instructions, etc.

[0079] ST2-3: Execution of cached instructions not completed: If the queue unit requests to load content, the first data bypass is activated, and the loaded content is written from the cache register to the corresponding position in the queue unit; if the queue unit does not request to load content, the second data bypass is activated, and the loaded content from the cache register and vector register file to the queue unit is transferred to the execution unit for processing.

[0080] ST3: Execute ST2-2;

[0081] ST4: The storage unit executes a storage instruction to write the loaded content and the corresponding calculation results back to memory.

[0082] Optionally, the system also includes an expansion interface connected to a cache register;

[0083] An extension interface is used to connect external devices that participate in the computation of loading content.

[0084] Since the aforementioned multiple paths are based on vector data parallelism and utilize multiple LANEs (LANE is an ATM technology used to transmit traditional LAN frames over ATM networks, a service provided by edge switches or access routers) to perform data operations, but some "cross-LANE" operations exist in the vector extension instructions of the RISC-V instruction set (i.e., operations involving external devices loading content), the extension interface was designed to handle this type of instruction outside the LANE. This modular design achieves cross-LANE operations simultaneously. This solves the problem that the vector-related data paths used in the RISC-V instruction set architecture do not optimize for all types of full-vector register file data processing instructions. If expand, slide, narrow, etc., require optimization of the data path design, it would involve repetitive work.

[0085] The cross-LANE operation is divided into an interface within the LANE and specific processing components outside the LANE. This modular design reduces the workload in subsequent iterations and solves the problem of poor portability caused by a single codebase corresponding to a single hardware design. If the computation of the loaded content requires cross-LANE operations, it is connected to a ring component outside the LANE through an extension interface to participate in the computation of the loaded content. This participation in the computation of the loaded content by connecting to a ring component outside the LANE through an extension interface is implemented in the following way:

[0086] See Figure 2In the ring component structure diagram, it can include a as extension interface 0 in LANE0, b as extension interface 1 in LANE1, c as extension interface 2 in LANE2, and d as extension interface 3 in LANE3; e as ring node 0, f as ring node 1, g as ring node 2, and h as ring node 3. When the instruction scheduling unit issues a cached instruction, the vector register files in LANE0-LANE3 will exchange data between LANEs to complete the cached instruction. The extension interface of LANE0 is connected to ring node 0 and ring node 3 respectively. The LANE0 extension interface and the modular ring nodes 0 and 3 can be quickly debugged and iterated during each design change. When the design needs to add a LANE, the adjustment to the entire design will not be significant. Distributing the cross-LANE operation to multiple nodes also reduces the design load.

[0087] When the execution unit performs vector operations on the loaded content, see [link to relevant documentation]. Figure 1 and Figure 2 The instruction scheduling unit sends cached instructions to each outer LANE structure for processing parallel vector data. In the execution unit, cached instructions request the necessary data from the vector register file via the cache register register for subsequent operations. The vector register file sends the loaded content through the read data path to the queue unit, which has a certain cache depth. The queue unit then transmits the loaded content to the execution unit in a cached manner, thus hiding some latency when access conflicts occur in the vector register file. After the execution unit completes the operation on the loaded content, it transmits the result to the cache register through the write-back data path. After completing the operation on the currently loaded content, the cache register transmits the corresponding loaded content and operation result through the storage data path. The data is input to the storage unit and written back to its own memory. If the execution unit has not completed the operation on the loaded content and needs to perform the same operation on the result of the operation and the data subsequently read from the vector register file, the cache register retransmits the subsequent loaded content to the execution unit for operation through the second data bypass. If the operation on the loaded content is not completed and the result of the operation needs to be performed on the subsequent loaded content read from the vector register file, or if an access conflict occurs in the vector register file, the cache register transmits the incomplete loaded content and the subsequent loaded content read from the vector register file to the queue unit through the first data bypass, and the queue unit then transmits them to the execution unit for operation.

[0088] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A vector register file cache system based on the RISC-V instruction set, characterized in that, It includes an instruction scheduling unit, an execution unit, a cache register, a vector register file, and a loading unit connected in sequence, and also includes a queue unit connected to the execution unit, the cache register, and the vector register file respectively; The instruction scheduling unit is used to send cached instructions to the execution unit; The execution unit is configured to receive the cache instruction and control the cache register and vector register file to perform actions corresponding to the cache instruction; The instruction scheduling unit is also used to send a loading instruction corresponding to the cached instruction to the loading unit; The loading unit is used to receive the loading instruction and pass the loading content corresponding to the loading instruction into the vector register file; The queue unit is used to receive the loaded content sent by the vector register file and send the loaded content to the execution unit; The execution unit is also used to perform calculations on the loaded content, obtain calculation results, and transmit the calculation results to the cache register; The system also includes an expansion interface, which is connected to the cache register; The extended interface is used to connect external devices that participate in the computation of the loaded content; The system also includes a storage unit connected to the cache register; The storage unit is used to store the loaded content and the corresponding calculation results; The system also includes a recording cache unit, which is connected to the cache register; The recording cache unit is used to receive the loaded content that has encountered an access conflict sent by the cache register, revise the loaded content, and transmit the revised loaded content to the cache register.

2. The vector register file cache system based on the RISC-V instruction set according to claim 1, characterized in that, The loading unit is connected to the vector register file via a loading data path, which is used to transfer the loading content corresponding to the loading instruction in the loading unit into the vector register file.

3. The vector register file cache system based on the RISC-V instruction set according to claim 1, characterized in that, The vector register file is connected to the queue unit via a read data path. Specifically, the vector register file is used to transmit the loaded content into the queue unit through the read data path.

4. The vector register file cache system based on the RISC-V instruction set according to claim 1, characterized in that, The cache register is connected to the queue unit via a first data bypass. The cache register is also used to pass loaded content that cannot be calculated or cannot yield calculation results into the queue unit via the first data bypass.

5. The vector register file cache system based on the RISC-V instruction set according to claim 1, characterized in that, The cache register and the execution unit are connected via a second data bypass and a write-back data path. The write-back data path is used to enable the execution unit to control the cache register to perform actions corresponding to the cached instructions. The cache register is also used to pass loaded content that cannot be calculated or cannot obtain calculation results into the execution unit through the second data bypass.

6. The vector register file cache system based on the RISC-V instruction set according to claim 1, characterized in that, The cache register and the vector register file are connected via a write data path. Specifically, the cache register is used to transmit the cached instructions to the vector register file through the write data path, thereby controlling the vector register file to perform actions corresponding to the cached instructions.

7. The vector register file cache system based on the RISC-V instruction set according to claim 3, characterized in that, The cache register and the storage unit are connected via a storage data path. The storage unit is specifically used to store the loaded content and the corresponding calculation results through the storage data path.

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