Methods for detecting external interrupt exceptions in a microcontroller and microcontrollers

Abstract

This application provides a method and a microcontroller for detecting external interrupt anomalies in a microcontroller. In this embodiment, when an external interrupt occurs based on a flag bit I / O port of the microcontroller, the states of other flag bit I / O ports of the microcontroller are obtained; if the states of other flag bit I / O ports are those that cause the microcontroller to generate an external interrupt, then an external interrupt anomaly is determined. This method detects external interrupt faults, improves debugging efficiency, and helps debugging personnel quickly locate faults.

Description

Technical Field

[0001] This invention relates to the field of control, specifically a method for detecting external interrupt anomalies in a microcontroller and a microcontroller. Background Technology

[0002] In laser systems, to ensure the power supply system operates at its optimal state, it needs to be automatically calibrated periodically. The automatic calibration system mainly includes a data acquisition and storage module and a data analysis and parameter adjustment module. The data acquisition and storage module uses two microcontrollers; to improve communication anti-interference capabilities, the microcontrollers employ parallel communication via I / O ports to transmit data.

[0003] During the debugging phase, hardware faults such as short circuits between pins can cause the data acquisition and storage modules to malfunction. Currently, there is a lack of detection mechanisms for such external interrupt crosstalk faults, making troubleshooting difficult and impacting debugging efficiency. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the shortcomings of the existing technology and provide a method and microcontroller for detecting external interrupt abnormalities of a microcontroller, so as to detect external interrupt crosstalk faults and improve debugging efficiency.

[0005] To achieve the above-mentioned technical objectives, on the one hand, the present invention provides a method for detecting external interrupt abnormalities of a microcontroller, characterized in that the microcontroller includes multiple flag bit I / O ports, which can be used to cause the microcontroller to generate external interrupts. The method includes: when an external interrupt is generated based on the flag bit I / O port of the microcontroller, obtaining the status of other flag bit I / O ports of the microcontroller; when the status of the other flag bit I / O ports is a state that causes the microcontroller to generate external interrupts, then determining that the microcontroller has an external interrupt abnormality.

[0006] In addition, the method also includes: when the state of the other flag bit I / O ports is a state where the microcontroller does not generate an external interrupt, then execute the corresponding preset instruction for the event corresponding to the external interrupt; clear the external interrupt flag.

[0007] Specifically, the microcontroller also includes a data bit I / O port. The method further includes: receiving data sent by other microcontrollers through the data bit I / O port; receiving trigger pulses sent by the other microcontrollers through the flag bit I / O port; when the rising edge of the trigger pulse arrives, the level of the flag bit I / O port is high, thereby causing the microcontroller to generate an external interrupt.

[0008] Specifically, the flag bit I / O port is connected to the trigger pulse I / O port of other microcontrollers; the data bit I / O port is connected to the data transmission I / O port of other microcontrollers.

[0009] Specifically, obtaining the status of other flag bit I / O ports of the microcontroller includes: reading the level status of other flag bit I / O ports of the microcontroller through an interrupt function.

[0010] Specifically, determining that the microcontroller's external interrupt is abnormal when the state of the other flag bit I / O ports is such that the microcontroller generates an external interrupt includes: determining that the microcontroller's external interrupt is scrambled when the level state of the other flag bit I / O ports is high.

[0011] In addition, the method also includes: upon determining that the microcontroller's external interrupt string is disordered, sending information indicating the external interrupt string disorder to the host computer, so that the host computer can receive the information and display it, allowing the corresponding debugging personnel to perform debugging.

[0012] Specifically, the execution of the corresponding preset instruction for the event corresponding to the external interrupt includes: executing the instruction to read the data received by the corresponding data bit IO, and reading the data received by the corresponding data bit IO.

[0013] Specifically, in the case of no external interruption, all of the multiple flag I / O ports are in a low-level state; in the case of no external interruption, the multiple flag I / O ports receive different trigger pulses according to a preset order.

[0014] On the other hand, the present invention provides a device for detecting external interrupt abnormalities of a microcontroller. The microcontroller includes multiple flag bit I / O ports, which can be used to cause the microcontroller to generate an external interrupt. The device includes: an acquisition module, used to acquire the status of other flag bit I / O ports of the microcontroller when an external interrupt is generated based on the flag bit I / O ports of the microcontroller; and a determination module, used to determine that the microcontroller has an external interrupt abnormality when the status of the other flag bit I / O ports is a state that causes the microcontroller to generate an external interrupt.

[0015] On the other hand, the present invention provides a microcontroller including a processor, a memory, and multiple flag bit I / O ports. The flag bit I / O ports can be used to enable the microcontroller to generate external interrupts. The memory is used to store programs in the microcontroller. The processor executes the programs in the memory to: obtain the status of other flag bit I / O ports of the microcontroller when an external interrupt is generated based on the flag bit I / O ports; and determine that an external interrupt is abnormal when the status of the other flag bit I / O ports is the status of generating an external interrupt.

[0016] In this embodiment, when an external interrupt is generated based on the microcontroller's flag I / O port, the status of other flag I / O ports of the microcontroller is obtained; if the status of other flag I / O ports is such that the microcontroller generates an external interrupt, then the external interrupt of the microcontroller is determined to be abnormal. This detects external interrupt faults, improves debugging efficiency, and helps debugging personnel quickly locate faults. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating a method for detecting external interrupt exceptions of a microcontroller according to an embodiment of this application.

[0019] Figure 2 This is a schematic diagram of microcontroller communication according to an embodiment of this application;

[0020] Figure 3 This is a schematic diagram of the timing of microcontroller communication in an embodiment of this application;

[0021] Figure 4 This is a schematic diagram illustrating the detection of external interrupt anomalies in a microcontroller according to an embodiment of this application.

[0022] Figure 5 This is a schematic diagram illustrating the detection of external interrupt anomalies in a microcontroller according to an embodiment of this application.

[0023] Figure 6 This is a schematic diagram illustrating the detection and reporting of external interrupt anomalies of a microcontroller according to an embodiment of this application;

[0024] Figure 7 This is a schematic diagram of the framework of a device for detecting external interrupts of a microcontroller according to an embodiment of this application. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] like Figure 1As shown, this application provides a method for detecting external interrupt exceptions in a microcontroller. The microcontroller includes multiple flag bit I / O ports, which can be used to generate external interrupts. The microcontroller may also include other data bit I / O ports for data transmission. The method 100 includes:

[0027] 101: When an external interrupt is generated by the microcontroller's flag bit I / O port, obtain the status of other flag bit I / O ports of the microcontroller;

[0028] 102: When the status of other flag bits of the I / O port is such that the microcontroller generates an external interrupt, then the microcontroller is determined to be in an external interrupt abnormality.

[0029] It should be noted that the execution subject of this method 100 can be a device with computing capabilities, such as a microcontroller. This application embodiment has been verified in the STM32 series microcontrollers. Using this application embodiment, hardware short-circuit faults between adjacent interrupt pins IOA (i.e., flag bit I / O port) and IOB (i.e., flag bit I / O port) can be quickly located.

[0030] The following is a detailed explanation of the above steps:

[0031] 101: When an external interrupt is generated by the microcontroller's flag bit I / O port, obtain the status of other flag bit I / O ports of the microcontroller.

[0032] External interrupts refer to an internal mechanism in which a microcontroller handles external events in real time. When an external event occurs, the microcontroller's interrupt system forces the CPU (Central Processing Unit) to suspend the currently executing program and handle the interrupt event. After the interrupt is handled, the microcontroller returns to the interrupted program and continues execution.

[0033] For example, since a microcontroller has multiple flag I / O ports, such as flag IOA and flag IOB, when an external interrupt occurs based on flag IOA, the microcontroller can obtain the state of flag IOB, such as its voltage level.

[0034] The process of determining when an external interrupt has occurred may include: receiving a trigger pulse from another microcontroller via a flag I / O port; when the rising edge of the trigger pulse arrives, the flag I / O port goes high, thus triggering an external interrupt in the microcontroller. In addition, the microcontroller also includes a data I / O port to receive data from other microcontrollers.

[0035] For example, continuing from the previous text, such as Figure 2As shown, "Microcontroller 1" 201 and "Microcontroller 2" 202 communicate. "Microcontroller 1" 201 sends data to the data I / O port of "Microcontroller 2" 202 through its data I / O port 1. Simultaneously, "Microcontroller 1" 201 sends a trigger pulse to the flag I / O port of "Microcontroller 2" 202 through its flag I / O port 1. When the rising edge of the trigger pulse arrives, the flag I / O port of "Microcontroller 2" 202 goes high, triggering an external interrupt.

[0036] It should be noted that in the microcontroller passively receiving data, both flag bits IOA and IOB of "Microcontroller 2" 202 are low in the idle state. When "Microcontroller 1" 201 sends data to "Microcontroller 2" 202, it uses multiplexed data I / O ports, distinguished by IOA and IOB. Before sending data M, "Microcontroller 1" 201 sends a trigger pulse to "Microcontroller 2" 202 through IOA. Before sending data N, "Microcontroller 1" 201 sends a trigger pulse to "Microcontroller 2" 202 through IOB. By multiplexing the data I / O ports, the microcontroller's I / O ports are saved.

[0037] As mentioned above, the flag bit I / O port is connected to the trigger pulse I / O port of other microcontrollers; the data bit I / O port is connected to the data transmission I / O port of other microcontrollers.

[0038] As can be seen from the preceding text, such as Figure 2 As shown, the flag bit IOA port of "microcontroller 2" 202 is connected to the trigger pulse I / O port of "microcontroller 1" 201, that is, the flag bit IOA port of "microcontroller 1" 201. Correspondingly, the data bit I / O1 port of "microcontroller 2" 202 is connected to the data bit I / O1 port of "microcontroller 1" 201.

[0039] It should be noted that, to improve the anti-interference capability of communication, "Microcontroller 1" and "Microcontroller 2" use parallel communication via I / O ports to transmit data. According to the communication protocol, the I / O ports are functionally divided into flag bit I / O ports and data bit I / O ports. The data bit I / O ports are multiplexed, and multiple flag bit I / O ports sequentially switch their level states to achieve the transmission of various data types. To respond promptly to data transmission commands from "Microcontroller 1," "Microcontroller 2" uses an external interrupt to respond to changes in the flag bit I / O port levels.

[0040] In multiple flag I / O ports, when no external interrupt occurs, all flag I / O ports are in a low-level state; when no external interrupt occurs, the multiple flag I / O ports receive different trigger pulses according to a preset order.

[0041] As mentioned earlier, in the absence of an external interrupt, all flag I / O ports are in a low-level state. This will not be elaborated further. Furthermore, in the absence of an external interrupt, the microcontroller receiving data can arrange different flag I / O ports to receive different trigger pulses according to the time sequence. For example, for "Microcontroller 2," after initialization, its flag IOA port can receive the trigger pulse first, then the flag IOB port receives the next trigger pulse, and then the flag IOA port again, and so on in a cycle. This will not be elaborated further. It should be understood that a microcontroller can have more than two flag I / O ports.

[0042] Among them, such as Figure 3 As shown, at the initial time t0, both the IOA and IOB flags of "Microcontroller 2" are at a low level. At time t1, trigger pulse a301 arrives, causing a rising edge interrupt on flag IOA, which is in a high-level state (303). At this time, flag IOB remains low. At time t2, flag IOA returns to a low level. At time t3, trigger pulse b302 arrives, causing a rising edge interrupt on flag IOB, which is in a high-level state (304). At this time, flag IOA remains low. At time t4, flag IOB returns to a low level. This completes one working cycle.

[0043] Specifically, obtaining the status of other flag bits of the microcontroller's I / O ports includes: reading the level status of other flag bits of the microcontroller's I / O ports through interrupt functions.

[0044] For example, continuing from the previous text, in "Microcontroller 2", an interrupt function IOA_Fun() is set for the external interrupt of the IOA flag port, and an interrupt function IOB_Fun() is set for the external interrupt of the IOB flag port. When the external interrupt of the IOA flag port occurs, the program in the microcontroller jumps to the interrupt function IOA_Fun(), where the level state of the IOB flag port is read.

[0045] Among them, such as Figure 4As shown, in "Microcontroller 2", during software initialization, step 401 is executed: the external interrupt crosstalk fault code variable is initialized to 0. Then, step 402 is executed: IOA (i.e., the flag IOA port) is configured as an external interrupt and the interrupt is enabled. When the external interrupt of the flag IOA port occurs, step 403 is executed: a valid trigger pulse is detected on IOA, triggering the IOA external interrupt. The program in the microcontroller jumps to the interrupt function IOA_Fun(), i.e., step 404 is executed: entering the IOA_Fun() function. In IOA_Fun(), the level state of the flag IOB port is read, i.e., step 405 is executed: reading the level state of IOB in IOA_Fun().

[0046] Additionally, such as Figure 5 As shown, step 501, IOA_Fun(), is executed here, followed by step 502, which reads the IOB's level state.

[0047] It should be noted that for "Microcontroller 2", the operation of other flag bit I / O ports is similar to the above, such as the flag bit IOB port, which will not be described in detail here.

[0048] 102: When the status of other flag bits of the I / O port is such that the microcontroller generates an external interrupt, then the microcontroller is determined to be in an external interrupt abnormality.

[0049] For example, continuing from the previous text, "Microcontroller 2" determines whether the level of the IOB flag is low, that is, it executes step 406: determine whether the level of IOB is low. If the level of the IOB flag is not low at this time, that is, it is high, then it is determined that there is crosstalk between IOB and IOA external interrupt, that is, an abnormality.

[0050] Specifically, when the state of other flag bit I / O ports is such that the microcontroller generates an external interrupt, the microcontroller is determined to have an external interrupt error. This includes: when the level of other flag bit I / O ports is high, the microcontroller's external interrupt is determined to be scrambled.

[0051] For example, continuing from the previous text, such as Figure 5 As shown, "Microcontroller 2" executes step 503: Is IOB at a low level? If not, that is, at a high level, then there is an error. Execute step 504: Assign the amplitude to the external interrupt crosstalk fault code variable, and then return the external interrupt crosstalk fault code.

[0052] In addition, the method 100 also includes: when the state of other flag bit I / O ports is that the microcontroller does not generate an external interrupt, then execute the corresponding preset instruction for the event corresponding to the external interrupt; clear the external interrupt flag.

[0053] For example, continuing from the previous text, such as Figure 4As shown, if the IOB level is low at this time, the predefined instruction to read the corresponding data bit of the I / O port is executed, i.e., the preset instruction. The corresponding data read result is then returned, i.e., step 407 is executed: based on the judgment result, the corresponding instruction is executed. Then, the interrupt flag is cleared.

[0054] Among them, such as Figure 5 As shown, when IOB is low, the microcontroller executes step 505: read the data bit I / O data. Then it executes step 506: clear the IOA interrupt flag and returns the result (i.e., returns the result of reading the data). Thus, the interrupt function ends, that is, step 507: IOA_Fun() ends.

[0055] Specifically, for the event corresponding to the external interrupt, execute the corresponding preset instructions, including: execute the instruction to read the data received by the corresponding data bit IO, and read the data received by the corresponding data bit IO.

[0056] As explained earlier, it will not be repeated here. Only the following should be noted: As mentioned earlier, when "Microcontroller 1" sends a trigger pulse, its data I / O port also sends data to the data I / O port of "Microcontroller 2," so the data transmitted through that port is read.

[0057] It should also be noted that the exception detection for other flag I / O ports in "Microcontroller 2" is similar to that described above. For example, when an external interrupt occurs on flag IOB, the program in "Microcontroller 2" jumps to the interrupt function IOB_Fun(). In IOB_Fun(), the level of flag IOA is read. If the level of flag IOA is not low, it is determined that there is external interrupt crosstalk between flag IOA and flag IOB, and an external interrupt crosstalk fault code is returned. If the level of flag IOA is low, a predefined instruction is executed. Further details are omitted.

[0058] When an anomaly is detected, an alarm needs to be triggered. Specifically, the method 100 also includes: upon determining that the microcontroller's external interrupt string is corrupted, sending information indicating the external interrupt string corruption to the host computer, so that the host computer can receive and display the information, allowing the corresponding debugging personnel to perform debugging.

[0059] For example, continuing from the previous text, such as Figure 6As shown, in the main function Main() of "Microcontroller 2", step 601 is executed: Main() begins, initialization is performed, i.e., step 602: the external interrupt crosstalk fault code variable is initialized to 0. Step 603: IOA is configured as an external interrupt and the IOA external interrupt is enabled. That is, the external interrupt function is enabled. Step 604: IOB is configured as an external interrupt and the IOB external interrupt is enabled. That is, the external interrupt function is enabled. In the main function Main(), it is determined whether the loop condition is met, i.e., step 605: while(expression is true). If the loop condition is met, i.e., if true, the value of the external interrupt crosstalk fault code is read and sent to the host computer, i.e., step 606: the value of the external interrupt crosstalk fault code is read and sent to the host computer. It is then displayed on the host computer to help the debugging personnel understand the current operating status of the system. The main function Main() is exited until the loop condition while is no longer met. That is, step 607: Main() ends.

[0060] This application embodiment utilizes the fixed timing relationship of this type of external interrupt and adds crosstalk detection in the interrupt function, which can quickly locate faults and improve debugging efficiency.

[0061] This application also provides a device for detecting external interrupt exceptions in a microcontroller, applied in a microcontroller. The microcontroller includes multiple flag I / O ports, which can be used to generate external interrupts. For example... Figure 7 As shown, the device 700 includes:

[0062] The acquisition module 701 is used to acquire the status of other flag bit I / O ports of the microcontroller when an external interrupt is generated by the flag bit I / O port of the microcontroller.

[0063] The determination module 702 is used to determine that the microcontroller is in an external interrupt state when the state of other flag bit I / O ports is such that the microcontroller generates an external interrupt.

[0064] In addition, the device 700 also includes: an execution module, used to execute a preset instruction for the event corresponding to the external interrupt when the state of other flag bit I / O ports is a state that does not cause the microcontroller to generate an external interrupt; and a clearing module, used to clear the external interrupt flag.

[0065] In addition, the microcontroller also includes a data bit I / O port. The device 700 also includes: a receiving module, used to receive data sent by other microcontrollers through the data bit I / O port; and to receive trigger pulses sent by other microcontrollers through the flag bit I / O port. When the rising edge of the trigger pulse arrives, the level of the flag bit I / O port is high, thereby causing the microcontroller to generate an external interrupt.

[0066] The flag bit I / O port is connected to the trigger pulse I / O port of other microcontrollers; the data bit I / O port is connected to the data transmission I / O port of other microcontrollers.

[0067] Specifically, the acquisition module 701 is used to read the level status of other flag bit I / O ports of the microcontroller through an interrupt function.

[0068] Specifically, module 702 is used to determine if the microcontroller's external interrupt is scrambled when the level of other flag bit I / O ports is high.

[0069] In addition, the device 700 also includes a sending module, which is used to send information indicating external interrupt scrambling to the host computer after determining that the microcontroller has external interrupt scrambling, so that the host computer can display the information after receiving it and enable the corresponding debugging personnel to perform debugging.

[0070] Specifically, the execution module is used to execute instructions to read the data received by the corresponding data bit IO.

[0071] Among them, in the case of no external interrupt, the state of multiple flag bit I / O ports is low; in the case of no external interrupt, multiple flag bit I / O ports receive different trigger pulses according to a preset order.

[0072] Since the specific implementation of this device 700 is described in the previous text, it will not be repeated here.

[0073] This application also provides a microcontroller, including a processor, a memory, and multiple flag bit I / O ports, which can be used to enable the microcontroller to generate external interrupts.

[0074] The memory is used to store the program in the microcontroller;

[0075] The processor executes programs in memory for the purpose of:

[0076] When an external interrupt is generated based on the flag bit I / O port, obtain the status of other flag bit I / O ports of the microcontroller;

[0077] If the status of the other flag I / O ports is that an external interrupt has been generated, then an external interrupt exception is determined.

[0078] This will not be elaborated upon further here; for any content that has not been covered in detail, please refer to the content mentioned above.

[0079] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process may be rearranged without departing from the scope of this disclosure. The appended method claims provide elements of various steps in an exemplary order and are not intended to limit the scope to the specific order or hierarchy described.

[0080] To make the description of this disclosure more detailed and complete, illustrative descriptions of the embodiments and specific examples of the present invention have been provided above; however, this is not the only form of implementing or utilizing the specific examples of the present invention. The embodiments cover the features of multiple specific examples and the method steps and their order for constructing and operating these specific examples. However, other specific examples may also be used to achieve the same or equivalent functions and order of steps.

[0081] In the detailed description above, various features are combined together in a single embodiment to simplify this disclosure. This approach to disclosure should not be construed as reflecting an intention that embodiments of the claimed subject matter require more features than are explicitly stated in each claim. Rather, as reflected in the appended claims, the invention is presented with fewer features than all of the features in a single disclosed embodiment. Therefore, the appended claims are hereby explicitly incorporated into the detailed description, with each claim representing a separate preferred embodiment of the invention.

[0082] The disclosed embodiments have been described above to enable any person skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments without departing from the spirit and scope of this disclosure. Therefore, this disclosure is not limited to the embodiments given herein, but is consistent with the broadest scope of the principles and novel features disclosed in this application.

[0083] The foregoing description includes examples of one or more embodiments. It is certainly impossible to describe all possible combinations of components or methods in order to describe the above embodiments, but those skilled in the art will recognize that further combinations and arrangements of the various embodiments are possible. Therefore, the embodiments described herein are intended to cover all such changes, modifications, and variations that fall within the scope of the appended claims. Furthermore, the term "comprising" as used in the specification or claims is interpreted in a manner similar to the term "including," as interpreted when used as a conjunction in the claims. Additionally, the use of any term "or" in the specification of the claims is intended to mean "non-exclusive or."

[0084] Those skilled in the art will also understand that the various illustrative logical blocks, units, and steps listed in the embodiments of the present invention can be implemented by electronic hardware, computer software, or a combination of both. To clearly demonstrate the interchangeability of hardware and software, the functions of the various illustrative components, units, and steps described above have been generally described. Whether such functionality is implemented through hardware or software depends on the specific application and the overall system design requirements. Those skilled in the art can implement the described functions using various methods for each specific application, but such implementation should not be construed as exceeding the scope of protection of the embodiments of the present invention.

[0085] The various illustrative logic blocks or units described in the embodiments of this invention can be implemented or operate the described functions using a general-purpose processor, digital signal processor, application-specific integrated circuit (ASIC), field-programmable gate array or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. The general-purpose processor can be a microprocessor; alternatively, it can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented using a combination of computing devices, such as a digital signal processor and a microprocessor, multiple microprocessors, one or more microprocessors combined with a digital signal processor core, or any other similar configuration.

[0086] The steps of the methods or algorithms described in the embodiments of this invention can be directly embedded in hardware, a software module executed by a processor, or a combination of both. The software module can be stored in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium in the art. Exemplarily, the storage medium can be connected to the processor so that the processor can read information from and write information to the storage medium. Optionally, the storage medium can also be integrated into the processor. The processor and storage medium can be housed in an ASIC, which can be housed in a user terminal. Optionally, the processor and storage medium can also be housed in different components of the user terminal.

[0087] In one or more exemplary designs, the functions described in the embodiments of the present invention can be implemented in hardware, software, firmware, or any combination of these three. If implemented in software, these functions can be stored on a computer-readable medium or transmitted on a computer-readable medium in the form of one or more instructions or code. Computer-readable media include computer storage media and communication media that facilitate the transfer of computer programs from one place to another. Storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. For example, such computer-readable media can include, but is not limited to, RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store program code in the form of instructions or data structures and other forms that can be read by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Furthermore, any connection can be suitably defined as a computer-readable medium, for example, if the software is transmitted from a website, server or other remote resource via a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wirelessly, such as infrared, wireless and microwave, it is also included in the defined computer-readable medium. The disks and discs mentioned include compressed disks, laser discs, optical discs, DVDs, floppy disks, and Blu-ray discs. Disks typically copy data magnetically, while disks typically copy data optically using lasers. Combinations of the above can also be contained in computer-readable media.

[0088] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for detecting external interrupt exceptions in a microcontroller, characterized in that, The method is applied to parallel communication between two microcontrollers; each microcontroller includes two flag I / O ports, namely flag IOA and flag IOB, which can be used to generate external interrupts. The method includes: In the initial state, both flag bits of the second microcontroller's I / O ports are at a low level. In the absence of an external interrupt, the second microcontroller's IOA flag port first receives the trigger pulse sent by the first microcontroller, then the second microcontroller's IOB flag port receives the next trigger pulse, and then the second microcontroller's IOA flag port receives the next trigger pulse, and so on; and at most one flag I / O port is in the trigger state, i.e., high level state, at any given time. When an external interrupt is generated based on the flag bit IOA port of the second microcontroller, obtain the status of the flag bit IOB port of the second microcontroller; When the level of the flag bit IOB port is high, it is determined that the external interrupt of the second microcontroller is scrambled.

2. The method according to claim 1, characterized in that, The method further includes: When the flag bit of the I / O port is in a state where the microcontroller does not generate an external interrupt, the corresponding preset instruction is executed for the event corresponding to the external interrupt. Clear the external interrupt flag.

3. The method according to claim 1, characterized in that, The microcontroller also includes a data bit I / O port, and the method further includes: The microcontroller receives data sent from other microcontrollers via the data bit I / O port.

4. The method according to claim 3, characterized in that, The flag bit I / O port is connected to the I / O port of other microcontrollers for trigger pulses; The data bit I / O port is connected to the I / O ports of other microcontrollers for sending data.

5. The method according to claim 1, characterized in that, Obtain the status of the microcontroller's flag bit I / O port, including: The interrupt function reads the level state of the microcontroller's flag bit I / O port.

6. The method according to claim 1, characterized in that, The method further includes: Once it is determined that the microcontroller's external interrupt string is scrambled, a message indicating the scrambled external interrupt string is sent to the host computer. After receiving the message, the host computer displays it, allowing the corresponding debugging personnel to perform debugging.

7. The method according to claim 2, characterized in that, The execution of the corresponding preset instruction for the event corresponding to the external interrupt includes: Execute the instruction to read the data received by the corresponding data bit IO, and read the data received by the corresponding data bit IO.

8. A microcontroller, characterized in that, The microcontroller communicates in parallel with another microcontroller. The microcontroller includes a processor, a memory, and two flag bit I / O ports, namely flag bit IOA and flag bit IOB. The flag bit I / O ports can be used to enable the microcontroller to generate external interrupts. The memory is used to store the program in the microcontroller; The processor executes a program in memory for: In the initial state, both flag bits of the second microcontroller's I / O ports are at a low level. In the absence of an external interrupt, the second microcontroller's IOA flag port first receives the trigger pulse sent by the first microcontroller, then the second microcontroller's IOB flag port receives the next trigger pulse, and then the second microcontroller's IOA flag port receives the next trigger pulse, and so on; and at most one flag I / O port is in the trigger state, i.e., high level state, at any given time. When an external interrupt is generated based on the flag bit IOA port of the second microcontroller, obtain the status of the flag bit IOB port of the second microcontroller; When the level of the flag bit IOB port is high, it is determined that the external interrupt of the second microcontroller is scrambled.

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