A genetic algorithm-based method for establishing time optimization and a system thereof

Abstract

The application discloses a genetic algorithm-based establishment time optimization method and system, and relates to the technical field of digital circuits.In the system, a static timing analysis tool performs timing analysis on a circuit netlist to obtain a timing report; a fitness function calculator judges the timing quality of the current circuit netlist; a violation path extractor extracts violation paths; a clock end buf extractor selects registers on the violation paths and registers located at the front and back ends of the violation paths and obtains the number of buffers at the clock ends of the registers, i.e., obtains a current chromosome; a clock end buf scheme adjuster evolves and optimizes the current chromosome based on a genetic algorithm to optimize the number of buffers at the clock ends of the registers; and the method uses the idea of timing repair with useful bias to propose a method for optimizing the number of buffers at the clock ends of the registers based on a genetic algorithm, which optimizes the establishment time timing without affecting the data path transmission and without affecting the hold time timing.

Description

Technical Field

[0001] This invention relates to the field of digital circuit technology, and in particular to a method and system for optimizing setup time based on a genetic algorithm. Background Technology

[0002] Digital chip design is divided into two stages: front-end logic design and back-end physical design. These correspond to the chip's functional design and layout design processes, which transform requirements into code, code into a circuit netlist, and the circuit netlist into a circuit layout, ultimately delivering the chip to the chip manufacturer for tape-out.

[0003] In chip front-end design, using RTL code-level design methods results in zero circuit latency. However, in actual circuits, circuit components exhibit latency, and excessively slow signal propagation can lead to system crashes. Back-end physical design addresses timing issues by replacing circuit units or modifying clock path buffers to adjust signal transmission times to meet register sampling setup times, ensuring normal system operation without affecting the circuit architecture.

[0004] As integrated circuit design scales up and performance requirements increase, chip timing convergence becomes increasingly difficult. For digital systems, setup time and hold time are fundamental to digital circuit timing; failure to meet setup time requirements will negatively impact chip performance. Therefore, the analysis and optimization of setup time are crucial throughout the entire digital chip design process. As the placement and routing phases progress, the timing information output in timing reports becomes increasingly precise, revealing several setup time violation paths.

[0005] Figure 1 In chip design, the netlist concept diagram obtained by synthesis software from RTL code under the same clock domain mainly consists of clock source signals, CL combinational logic circuits, and REG register sections. Figure 1 The marked part represents the branch where a register setup time timing violation problem occurs.

[0006] There are various ways to fix timing problems that exist during chip physical design, such as trying to replace cells on the data path, or using a useful offset to insert a buffer on the clock path (e.g.) Figure 2 As shown in the diagram, we attempted to adjust the clock tree. However, due to the large design size and numerous timing paths, manually defining the number of buffers inserted into the clock path to fix setup time may lead to new setup time violations in the preceding and following stages of that path, resulting in low timing repair efficiency. Summary of the Invention

[0007] To overcome the shortcomings of the prior art, this invention provides a setup time optimization method based on a genetic algorithm. It utilizes the idea of ​​timing repair based on useful bias and proposes a method to optimize the number of buffers at the register clock end based on a genetic algorithm. This optimizes setup time timing without affecting data path transmission and without affecting hold time timing.

[0008] To achieve the above objectives, the present invention adopts the following technical solution, including:

[0009] A method for optimizing setup time based on genetic algorithms includes the following steps:

[0010] S1, Obtain the initial circuit netlist; Initialize the algorithm parameters in the genetic algorithm, including the number of evolution overflows GT, crossover probability Pc, and mutation probability Pm; Set the basic evolutionary direction of the chromosomes;

[0011] S2, perform timing analysis on the current circuit netlist to obtain the data arrival time, data demand time and setup time margin of each register in the current circuit netlist, and extract the path with a negative setup time margin, which is the violation path. The setup time margin = data demand time - data arrival time.

[0012] All violation paths are summed, and the timing quality of the current circuit netlist is determined based on the sum of the violation path sums. The larger the sum of the violation path sums, the better the timing, and vice versa. The violation path sum is the sum of the establishment time margins of all violation paths.

[0013] S3. Based on the timing analysis results of the current circuit netlist, select the registers on the violation path and the registers located before and after the violation path, and select a total of k registers as the genes of the chromosome. Use the number of buffers at the clock end of each register as the code of the gene. A set of genes and the corresponding code on the gene constitute a chromosome. Obtain the current chromosome based on the current circuit netlist.

[0014] S4, proceeding to the Gth evolution based on the current chromosome:

[0015] S41, Basic Chromosome Evolution: Based on the current chromosome and its basic evolutionary direction, the current chromosome is directly evolved to obtain several chromosomes after basic evolution;

[0016] S42, Crossover Evolution: Using several basic evolved chromosomes as mother chromosomes, perform several crossovers of the mother chromosomes according to the crossover probability to obtain several crossover-generated daughter chromosomes;

[0017] S43, Mutation and Evolution: Modify the gene positions on the child chromosomes generated by crossover according to the mutation probability to obtain mutated chromosomes;

[0018] S44, the basic evolved chromosomes, crossover-generated sub-chromosomes, and mutated chromosomes obtained in steps S41-S42 are all taken as the chromosomes obtained in the Gth evolution. The Gth evolution yields a total of N chromosomes.

[0019] Here, the number of buffers at the clock end of the i-th gene encoding on the j-th chromosome obtained in the G-th evolution is denoted as . i = 1, 2, ..., k; j = 1, 2, ..., N; G represents the number of iterations, i.e., the number of evolutions, G = 1, 2, ...;

[0020] S5, Selecting the best from the N chromosomes obtained in the Gth evolution:

[0021] The current circuit netlist is adjusted using each chromosome obtained from the Gth evolution. The number of buffers at the clock end of the corresponding register is adjusted according to the encoding of each gene on the chromosome. The timing analysis of the adjusted circuit netlist is performed to determine the timing quality of the adjusted circuit netlist. The chromosome with the best timing is selected as the optimal chromosome, and the circuit netlist is updated using the optimal chromosome.

[0022] S6. Perform timing analysis on the updated circuit netlist obtained in step S5 to determine whether there is a path in the updated circuit netlist with a negative setup time margin. If there is no path, it means that the algorithm condition is met, and the updated circuit netlist is output as the final optimization scheme for setup time.

[0023] If it exists, determine whether the current evolution count G is equal to the evolution overflow count GT. If it is equal, directly output the updated circuit netlist obtained in step S5 as the final optimized solution for the establishment time. If it is not equal, use the updated circuit netlist as the current circuit netlist, obtain the current chromosome based on the current circuit netlist, and then perform the next evolution based on the current chromosome. Jump to step S4 until the final optimized solution for the establishment time is obtained.

[0024] Preferably, it is assumed that the violation path in the current circuit netlist is: Register B → Register C; the registers on the violation path and the registers located before and after the violation path are selected as part of the gene fragments of the current chromosome, and the corresponding path is: Register A → Register B → Register C → Register D;

[0025] Among them, register B at the front end of the violation path and register A at the front end of the violation path are both front-level registers; register C at the back end of the violation path is the violation node register, and register D at the back end of the violation path is the rear-level register.

[0026] In step S1, the basic evolutionary direction of the chromosome is to reduce the number of clock buffers in the preceding registers and / or increase the number of clock buffers in the violation node registers and / or increase the number of clock buffers in the following registers.

[0027] Preferably, in step S41, the specific method of chromosome basic evolution is as follows: decrease the number of clock buffers in register A and / or register B by 1, and / or increase the number of clock buffers in register C by 1, and / or increase the number of clock buffers in register D by 1.

[0028] The following table shows the eight basic evolved chromosome segments:

[0029] Chromosome 1 segment 0 0 1 0 Chromosome 2 segment 0 0 1 1 Chromosome 3 segment 0 -1 0 0 Chromosome 4 segment -1 -1 0 0 Chromosome 5 segment 0 -1 1 0 Chromosome 6 segment 0 -1 1 1 Chromosome 7 fragment -1 -1 1 0 Chromosome 8 segment -1 -1 1 1

[0030] Here, -1 represents deleting a buffer, 1 represents adding a buffer, and 0 represents neither adding nor deleting a buffer.

[0031] Preferably, if there are consecutive violation paths in the current circuit netlist, assuming the consecutive violation paths are: register B → register C, register C → register D, then the registers on the consecutive violation paths and the registers located before and after the consecutive violation paths are selected to construct a partial gene fragment of the current chromosome. The corresponding path is: register A → register B → register C → register D → register E.

[0032] In the specific basic evolutionary process, the path is first divided into two branches according to the violation path: the branch of register A -> register B -> register C -> register D (i.e., the ABCD branch) and the branch of register B -> register C -> register D -> register E (i.e., the BCDE branch). Based on the basic evolutionary direction of the two branches, the encoding values ​​of registers A, B, and C are selected from the ABCD branch, and the encoding values ​​of registers D and E are selected from the BCDE branch, resulting in the eight basic evolved chromosome segments shown in Table 2 below:

[0033] Table 2 Chromosome fragments after basic evolution.

[0034]

[0035]

[0036] Here, -1 represents deleting a buffer, 1 represents adding a buffer, and 0 represents neither adding nor deleting a buffer.

[0037] Preferably, in step S42, the specific method of crossover evolution is as follows: two mother chromosomes are randomly selected for uniform crossover, and the average value of the encoding of the same gene locus on the two mother chromosomes is taken as the encoding of the corresponding gene locus of the crossover-generated daughter chromosome.

[0038] This invention also provides a system for optimizing setup time based on a genetic algorithm. The system includes: a circuit netlist, a static timing analysis tool, an automatic placement and routing tool, a fitness function calculator, a violation path extractor, a clock-end buf extractor, and a clock-end buf scheme adjuster.

[0039] The static timing analysis tool is used to perform timing analysis on the circuit netlist and obtain a timing report, which provides the data arrival time, data demand time, and setup time margin of each register in the current circuit netlist.

[0040] The fitness function calculator is used to calculate the sum of violation paths based on the timing report obtained from the static timing analysis tool, and to determine the timing quality of the current circuit netlist based on the sum of violation paths.

[0041] The violation path extractor is used to extract paths with negative establishment time margins, i.e., violation paths, based on the time series report obtained from the static time series analysis tool.

[0042] The clock-end buffer extractor is used to select registers on the violation path and registers located before and after the violation path based on the timing report obtained by the static timing analysis tool, and to obtain the number of buffers at the clock end of each register, that is, to obtain the current chromosome.

[0043] The clock-end buffer scheme adjuster optimizes the number of buffers at the clock end of each register by evolving and selecting the best chromosome based on a genetic algorithm.

[0044] The automatic placement and routing tool is used to update the circuit netlist based on the optimized number of buffers at the clock ends of each register.

[0045] Preferably, the static timing tool is Synopsys' Prime Time software; the automatic placement and routing tool is Synopsys' IC Compile software.

[0046] The advantages of this invention are:

[0047] (1) In view of the idea of ​​using useful deviation for timing repair, this invention proposes a method based on genetic algorithm to optimize the number of buffers at the register clock end, which optimizes the setup timing without affecting the data path transmission and without affecting the hold timing.

[0048] (2) A mathematical model is established by using a genetic algorithm to optimize the number of buffers at the clock end of the register to solve the problem of timing violations in the circuit. Multiple solutions are set according to the evolutionary idea and the optimal solution is found as an optimization scheme to use useful deviations to repair timing violations.

[0049] (3) By using a genetic algorithm to search for the optimal solution globally, under the objective constraint of the worst violation of the establishment time of all paths being non-negative, the optimal solution is found, which improves the efficiency of establishment time repair and greatly shortens the back-end design cycle.

[0050] (4) Use genetic algorithms to iterate and obtain optimized solutions instead of manual calculations, thereby accelerating chip development.

[0051] (5) By optimizing the chip setup time sequence, the chip's operating frequency is increased while ensuring chip functionality. Attached Figure Description

[0052] Figure 1 This is a conceptual diagram of a circuit netlist used in chip design.

[0053] Figure 2 This is a schematic diagram illustrating timing repair by inserting a buffer on the clock path using a useful offset.

[0054] Figure 3 This is a system architecture diagram for optimizing the setup time of digital chips according to the present invention.

[0055] Figure 4 This is a schematic diagram of the path corresponding to the chromosome.

[0056] Figure 5 This is a flowchart of a setup time optimization method based on genetic algorithms. Detailed Implementation

[0057] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0058] The physical design of digital chips involves a series of steps, including document preparation, layout planning, placement planning, clock tree synthesis, routing and dummy insertion, static timing analysis, timing repair, and verification. This culminates in the generation of a layout file for tape-out, transforming an abstract circuit into a concrete one. Each step utilizes EDA software to generate a circuit report, which designers then use to iteratively optimize the circuit in the backend workflow, ultimately completing the physical design.

[0059] During the clock tree synthesis stage of the back-end design, buffers are automatically inserted along the clock path of the circuit design to balance the clock delay of all clock inputs, so that the clock time from the clock source to the clock end of each register is the same, thus avoiding clock deviation.

[0060] After clock tree synthesis is completed, the structure of the circuit's clock input becomes more detailed, allowing for more accurate timing reports through static timing analysis. For setup time violation paths identified in the timing report, designers analyze each path individually. Based on register sampling principles, they fine-tune the number of register clock buffers for these violation paths to perform timing repair and resolve chip timing violations.

[0061] This invention primarily addresses the setup time optimization problem in timing repair. In the static timing analysis and timing repair stages after the placement and routing phase, software and algorithms are used to quickly and accurately obtain the optimal buffer optimization scheme for the clock tree.

[0062] Example 1

[0063] like Figure 3 As shown, the present invention provides a system for optimizing the setup time and timing of digital chips, including: a circuit netlist, a static timing analysis tool 1, an automatic placement and routing tool 2, a fitness function calculator 3, a violation path extractor 4, a clock-side buffer extractor 5, and a clock-side buffer scheme adjuster 6.

[0064] The circuit netlist is the circuit file to be optimized, which is obtained by the synthesis tool after logical synthesis of the design code.

[0065] The static timing tool 1 is Synopsys' PrimeTime software, used to perform static timing analysis on the circuit netlist, obtain the data arrival time, data demand time, and setup time margin of each register in the current circuit netlist, and generate a timing report. Paths with negative setup time margins are considered violation paths, where setup time margin = data demand time - data arrival time.

[0066] The fitness function calculator 3 is used to calculate the sum of violation paths based on the timing report obtained by the static timing analysis tool 1. The sum of violation paths is used to determine the timing quality of the current circuit netlist. The larger the sum of violation paths, the better the timing, and vice versa. The sum of violation paths is the sum of the establishment time margins of all violation paths.

[0067] The violation path extractor 4 is used to extract paths with negative establishment time margins, i.e., violation paths, based on the time series report obtained by the static time series analysis tool 1.

[0068] The clock-end buffer extractor 5 is used to select registers on the violation path and registers located before and after the violation path based on the timing report obtained by the static timing analysis tool 1, and to obtain the number of buffers at the clock end of each register.

[0069] The clock-end buffer scheme adjuster 6 optimizes the number of buffers at the clock end of each register by evolving and selecting the best chromosome based on a genetic algorithm.

[0070] The automatic placement and routing tool 2 is Synopsys' IC Compile software, used to update the circuit netlist based on the optimized number of buffers at the clock ends of each register.

[0071] Example 2

[0072] Depend on Figure 5 As shown, a method for optimizing setup time based on genetic algorithms includes the following steps:

[0073] S1, Obtain the initial circuit netlist; Initialize the algorithm parameters in the genetic algorithm, including the number of evolutionary overflows GT, crossover probability Pc, and mutation probability Pm; Set the basic evolutionary direction of the chromosomes.

[0074] S2, perform timing analysis on the current circuit netlist to obtain the data arrival time, data demand time and setup time margin of each register in the current circuit netlist, and extract the path with a negative setup time margin, which is the violation path. The setup time margin = data demand time - data arrival time.

[0075] All violation paths are summed, and the timing quality of the current circuit netlist is determined based on the sum of the violation paths. The larger the sum of the violation paths, the better the timing, and vice versa. The sum of the violation paths is the sum of the establishment time margins of all violation paths.

[0076] S3. Based on the timing analysis results of the current circuit netlist, select registers on the violation path and registers located before and after the violation path, and select a total of k registers as genes of the chromosome. Use the number of buffers at the clock end of each register as the gene code. A set of genes and the corresponding codes on the genes constitute a chromosome. Obtain the current chromosome based on the current circuit netlist.

[0077] S4, proceeding to the Gth evolution based on the current chromosome:

[0078] S41, Basic Chromosome Evolution: Based on the current chromosome and its basic evolutionary direction, the current chromosome is directly evolved to obtain several chromosomes after basic evolution.

[0079] S42, Crossover Evolution: Using several basic evolved chromosomes as mother chromosomes, perform several crossovers of the mother chromosomes according to the crossover probability to obtain several crossover-generated daughter chromosomes;

[0080] The specific method of crossover evolution is as follows: two mother chromosomes are randomly selected for uniform crossover, and the average value of the encoding of the same gene locus on the two mother chromosomes is taken as the encoding of the corresponding gene locus of the daughter chromosome generated by crossover.

[0081] S43, Mutation and Evolution: Modify the gene positions on the child chromosomes generated by crossover according to the mutation probability to obtain mutated chromosomes.

[0082] The encoding value of the gene bit is set to a range of 0-7, which means that the number of buffers at the register clock end is set to a range of 0-7.

[0083] S44, the basic evolved chromosomes, crossover-generated sub-chromosomes, and mutated chromosomes obtained in steps S41-S42 are all taken as the chromosomes obtained in the Gth evolution. The Gth evolution yields a total of N chromosomes.

[0084] Here, the number of buffers at the clock end of the i-th gene encoding on the j-th chromosome obtained in the G-th evolution is denoted as . i = 1, 2, ... k; j = 1, 2, ... N; G represents the number of iterations, i.e., the number of evolutions, G = 1, 2, ...

[0085] S5, Selecting the best from the N chromosomes obtained in the Gth evolution:

[0086] The current circuit netlist is adjusted using each chromosome obtained from the Gth evolution. The number of buffers at the clock end of the corresponding register is adjusted according to the encoding of each gene on the chromosome. Timing analysis is performed on the adjusted circuit netlist to determine the quality of the timing. The chromosome with the best timing is selected as the optimal chromosome, and the circuit netlist is updated using the optimal chromosome.

[0087] S6. Perform timing analysis on the updated circuit netlist obtained in step S5 to determine whether there is a path in the updated circuit netlist with a negative setup time margin. If there is no path, it means that the algorithm condition is met, and the updated circuit netlist is output as the final optimization scheme for setup time.

[0088] If it exists, determine whether the current evolution count G is equal to the evolution overflow count GT. If it is equal, directly output the updated circuit netlist obtained in step S5 as the final optimized solution for the establishment time. If it is not equal, use the updated circuit netlist as the current circuit netlist, obtain the current chromosome based on the current circuit netlist, and then perform the next evolution based on the current chromosome. Jump to step S4 until the final optimized solution for the establishment time is obtained.

[0089] In this invention, the basic approach to timing optimization is as follows: when a register setup time violation occurs, the basic repair idea is to ensure that the actual transmission time of the signal on the violation path is less than the expected transmission time, so that the signal arrives at the register input before use. This invention uses clock skew to increase the expected transmission time, implemented by reducing the number of buffers at the clock end of the preceding register and increasing the number of buffers at the clock end of the following register. Furthermore, adjusting the number of buffers at the clock end of the registers for timing repair not only optimizes the timing of the unit to be repaired but also affects the timing of preceding and following stages. Therefore, when generating the next generation solution (chromosome) using a genetic algorithm, this invention not only considers the two violation registers on the violation path but also selects the two registers with the most time constraints at the beginning and end of the violation path based on the timing report. For the number of buffers at the clock end of the four registers under this path, the basic evolutionary direction of the chromosome is: reducing the number of buffers at the clock end of the preceding register in the current chromosome's corresponding path (decrease by 1), and / or increasing the number of buffers at the clock end of the violation node register in the current chromosome's corresponding path (increase by 1), and / or increasing the number of buffers at the clock end of the following register in the current chromosome's corresponding path (increase by 1). In this context, the registers located at the front end of the violation path and the registers located at the front end of the violation path are both front-level registers; the registers located at the back end of the violation path are violation node registers, and the registers located at the back end of the violation path are rear-level registers.

[0090] For example, a circuit netlist has 100 registers and 10 sets of point-to-point violation paths. Eight of these are discontinuous path violations, and the other two are continuous path violations. A chromosome is composed of registers from these 10 sets of violation paths. Based on eight basic evolutionary directions, eight basic evolved chromosomes are generated. For the first basic evolutionary direction, which is to add a buffer at the node, in this scenario, a buffer is inserted at the violation node of each of the 10 sets of violation paths. On continuous violation paths, if there is a conflict in the number of insertions, the nearest insertion is used (the insertion scheme for a single branch may be repeated, but this is not a problem, as there are other violation paths).

[0091] like Figure 4As shown, due to the excessive logic depth between register B and register C on a branch, a setup time violation occurs in the path register B -> register C. The registers on the violation path and the registers located before and after the violation path are selected as part of the genes of the current chromosome. The corresponding path is: register A -> register B -> register C -> register D.

[0092] In this path, register B at the front end and register A at the front end of the violation path are both front-level registers; register C at the back end of the violation path is the violation node register, and register D at the back end of the violation path is the rear-level register.

[0093] Based on the fundamental evolutionary direction of chromosomes, by decreasing the number of clock buffers in register A and / or register B by 1, and / or increasing the number of clock buffers in register C by 1, and / or increasing the number of clock buffers in register D by 1, we obtain the eight fundamentally evolved chromosome segments shown in Table 1 below:

[0094] Table 1 Chromosome fragments after basic evolution.

[0095] Chromosome 1 segment 0 0 1 0 Chromosome 2 segment 0 0 1 1 Chromosome 3 segment 0 -1 0 0 Chromosome 4 segment -1 -1 0 0 Chromosome 5 segment 0 -1 1 0 Chromosome 6 segment 0 -1 1 1 Chromosome 7 fragment -1 -1 1 0 Chromosome 8 segment -1 -1 1 1

[0096] Here, -1 represents deleting a buffer, 1 represents adding a buffer, and 0 represents neither adding nor deleting a buffer.

[0097] Subsequently, using the eight basic evolved chromosomes as parent chromosomes, crossover and mutation evolution are performed based on the crossover and mutation probabilities to obtain the remaining N-8 evolved chromosomes. In this embodiment, 8 ≤ N ≤ 20.

[0098] If there are branches with consecutive violation paths in the current netlist, assuming the consecutive violation branches are: register B → register C, register C → register D, then the violation node register and the registers before and after the violation path on this branch are selected as gene fragments for joint analysis. The corresponding path is: register A → register B → register C → register D → register E.

[0099] Registers A and B are the pre-stage registers, registers C and D are the violation node registers, and register E is the post-stage register.

[0100] In the specific basic evolutionary process, the path is first divided into two branches according to the violation path: the branch from register A to register B to register C to register D (i.e., the ABCD branch) and the branch from register B to register C to register D to register E (i.e., the BCDE branch). Based on the basic evolutionary direction of the two branches and according to the principle of proximity of the violation node, the encoding values ​​of the ABCD branch are selected for registers A, B, and C, and the encoding values ​​of the BCDE branch are selected for registers D and E, resulting in the eight chromosome segments after basic evolution as shown in Table 2 below:

[0101] Table 2 Chromosome fragments after basic evolution.

[0102]

[0103]

[0104] The genetic algorithm in this invention can also be replaced by the particle swarm optimization algorithm.

[0105] The above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for optimizing setup time based on genetic algorithms, characterized in that, Includes the following steps: S1, Obtain the initial circuit netlist; Initialize the algorithm parameters in the genetic algorithm, including the number of evolution overflows. GT Crossover probability Pc Probability of mutation Pm ;Set the basic evolutionary direction of chromosomes; In step S1, the basic evolutionary direction of chromosomes is: to reduce the number of clock buffers in the preceding registers and / or to increase the number of clock buffers in the violation node registers and / or to increase the number of clock buffers in the following registers. S2, perform timing analysis on the current circuit netlist to obtain the data arrival time, data demand time and setup time margin of each register in the current circuit netlist, and extract the path with a negative setup time margin, which is the violation path. The setup time margin = data demand time - data arrival time. All violation paths are summed, and the timing quality of the current circuit netlist is determined based on the sum of the violation path sums. The larger the sum of the violation path sums, the better the timing, and vice versa. The violation path sum is the sum of the establishment time margins of all violation paths. S3, based on the timing analysis results of the current circuit netlist, select registers on the violation path and registers located before and after the violation path, for a total of... k Each register is used as a gene of a chromosome, and the number of buffers at the clock end of each register is used as the gene's code; a set of genes and their corresponding codes constitute a chromosome, and the current chromosome is obtained based on the current circuit netlist. S4, based on the current chromosome, proceed to the next... G Sub-evolution: S41, Basic Chromosome Evolution: Based on the current chromosome and its basic evolutionary direction, the current chromosome is directly evolved to obtain several chromosomes after basic evolution; S42, Crossover Evolution: Using several basic evolved chromosomes as mother chromosomes, perform several crossovers of the mother chromosomes according to the crossover probability to obtain several crossover-generated daughter chromosomes; S43, Mutation and Evolution: Modify the gene positions on the child chromosomes generated by crossover according to the mutation probability to obtain mutated chromosomes; S44, the basic evolved chromosomes, crossover-generated daughter chromosomes, and mutated chromosomes obtained in steps S41-S42 are all taken as the first... G Chromosomes obtained through the second evolution, the first G The secondary evolution yielded the following results: N One chromosome; Among them, the first G The second evolution yielded the first j The first chromosome i The gene encoding the first gene is the... i The number of buffers at the clock end of each register is denoted as , ; ; G This indicates the number of iterations, or the number of evolutions. ; S5, for the first G Obtained through secondary evolution Selecting the best chromosomes: Using the first G Each chromosome obtained from the secondary evolution adjusts the current circuit netlist. The number of buffers at the clock end of the corresponding register is adjusted according to the encoding of each gene on the chromosome. Timing analysis is performed on the adjusted circuit netlist to determine the quality of the timing. The chromosome with the best timing is selected as the optimal chromosome, and the optimal chromosome is used to update the circuit netlist. S6. Perform timing analysis on the updated circuit netlist obtained in step S5 to determine whether there is a path in the updated circuit netlist with a negative setup time margin. If there is no path, it means that the algorithm condition is met, and the updated circuit netlist is output as the final optimization scheme for setup time. If it exists, then determine the current evolution count. G Is it equal to the number of evolutionary overflows? GT If the values ​​are equal, the updated circuit netlist obtained in step S5 is directly output as the final optimization scheme for the setup time; if the values ​​are not equal, the updated circuit netlist is used as the current circuit netlist, the current chromosome is obtained based on the current circuit netlist, and then the next evolution is performed based on the current chromosome. The process jumps to step S4 until the final optimization scheme for the setup time is obtained. Assumption: The current circuit netlist contains a violation path: Register B → Register C; Select the registers on the violation path and the registers located before and after the violation path as part of the gene fragments of the current chromosome, the corresponding path is: Register A → Register B → Register C → Register D; In this context, register B at the front end of the violation path and register A at the front end of the violation path are both front-level registers; register C at the back end of the violation path is the violation node register, and register D at the back end of the violation path is the rear-level register.

2. The method for optimizing setup time based on genetic algorithm according to claim 1, characterized in that, In step S41, the specific method of basic chromosome evolution is as follows: decrease the number of clock buffers in register A and / or register B by 1, and / or increase the number of clock buffers in register C by 1, and / or increase the number of clock buffers in register D by 1. The following table shows the eight basic evolved chromosome segments: Table 1 Here, -1 represents deleting a buffer, 1 represents adding a buffer, and 0 represents neither adding nor deleting a buffer.

3. The method for optimizing setup time based on genetic algorithm according to claim 2, characterized in that, If there are consecutive violation paths in the current circuit netlist, assuming the consecutive violation paths are: register B → register C, register C → register D, then select the registers on the consecutive violation paths and the registers located before and after the consecutive violation paths to construct a partial gene fragment of the current chromosome. The corresponding path is: register A → register B → register C → register D → register E. In the specific basic evolutionary process, the path is first divided into two branches according to the violation path: the branch of register A -> register B -> register C -> register D (i.e., the ABCD branch) and the branch of register B -> register C -> register D -> register E (i.e., the BCDE branch). Based on the basic evolutionary direction of the two branches, the encoding values ​​of registers A, B, and C are selected from the ABCD branch, and the encoding values ​​of registers D and E are selected from the BCDE branch, resulting in the eight basic evolved chromosome segments shown in Table 2 below: Table 2 Here, -1 represents deleting a buffer, 1 represents adding a buffer, and 0 represents neither adding nor deleting a buffer.

4. The method for optimizing setup time based on genetic algorithm according to claim 1, characterized in that, In step S42, the specific method of crossover evolution is as follows: two mother chromosomes are randomly selected for uniform crossover, and the average value of the encoding of the same gene locus on the two mother chromosomes is taken as the encoding of the corresponding gene locus of the crossover-generated daughter chromosome.

5. A system applicable to the setup time optimization method based on genetic algorithm as described in claim 1, characterized in that, The system includes: circuit netlist, static timing analysis tool (1), automatic placement and routing tool (2), fitness function calculator (3), violation path extractor (4), clock-side buf extractor (5), and clock-side buf scheme adjuster (6). The static timing analysis tool (1) is used to perform timing analysis on the circuit netlist and obtain a timing report, that is, to obtain the data arrival time, data demand time and setup time margin of each register in the current circuit netlist; The fitness function calculator (3) is used to calculate the sum of violation paths based on the timing report obtained by the static timing analysis tool (1), and to determine the timing quality of the current circuit netlist based on the sum of violation paths. The violation path extractor (4) is used to extract the path with a negative establishment time margin, i.e. the violation path, based on the time series report obtained by the static time series analysis tool (1); The clock-end buf extractor (5) is used to select the registers on the violation path and the registers located before and after the violation path according to the timing report obtained by the static timing analysis tool (1), and obtain the number of buffers at the clock end of each register, that is, to obtain the current chromosome. The clock-end buffer scheme adjuster (6) optimizes the number of buffers at the clock end of each register by evolving and selecting the best chromosome based on a genetic algorithm. The automatic placement and routing tool (2) is used to update the circuit netlist based on the optimized number of buffers at the clock ends of each register.

6. The system for optimizing setup time based on a genetic algorithm according to claim 5, characterized in that, The static timing analysis tool (1) is Synopsys' Prime Time software; the automatic placement and routing tool (2) is Synopsys' IC Compile software.

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