LDMOS direct current modeling method for different voltage applications

Abstract

The application discloses an LDMOS direct current modeling method for different voltage applications, comprising the following steps: step S1, extracting relevant model parameters of device DC performance according to an existing SPICE model of different application voltage LDMOS; step S2, fitting parameters affecting the equivalent resistance of a drift region to form a mathematical fitting trend line of the corresponding parameters by using the relevant model parameters obtained in step S1; step S3, obtaining a mathematical relationship between the parameters affecting the equivalent resistance of the drift region and PA and PF of the device under different application voltages from the mathematical fitting trend line; and step S4, adding the obtained mathematical relationship to a SPICE model subcircuit to obtain a new DC model file of the LDMOS applicable to different voltages.

Description

Technical Field

[0001] This invention relates to an LDMOS DC modeling method, and more particularly to an LDMOS DC modeling method for different voltage applications. Background Technology

[0002] Figure 1a This is an existing LDMOS (Laterally Diffused Metal Oxide Semiconductor) structure, primarily used in radio frequency power amplification. 1 represents the field oxide region or shallow trench isolation region (STI). 1. Isolation; 2. N-type drift region (Ndrift), defined by a separate mask; 3. P-well; 4. Gate oxide; 5. Polysilicon gate, with the polysilicon field plate spanning the shallow channel isolation region (STI). The polysilicon lead-out electrode forms the gate of the LDMOS; 6. Drain N-type heavily doped region N+, whose lead-out electrode forms the drain D of the LDMOS; 7. Source N-type heavily doped region N+, whose lead-out electrode forms the source S of the LDMOS; 8. P-type heavily doped region P+, whose lead-out electrode forms the body B of the LDMOS; 9. P-type substrate (Psub); 10. N+ buried layer (NBL); 11. P-type epitaxial layer (Pepi), generally referring to the P-type region surrounded by an N-type isolation ring, typically connected to the lowest local potential.

[0003] like Figure 1b As shown, D, G, S, and B are the drain, gate, source, and body terminals of an LDMOS. To describe the impact of the drift region on device performance, the industry typically adds a resistor to the drain terminal of the LDMOS model for simulation, such as... Figure 1b As shown, R1 is the equivalent resistance of the drift region, and R2 is the equivalent resistance of the source. The existing DC model file for LDMOS is shown in the following code:

[0004]

[0005]

[0006] The above is an example of the Spice subcircuit description statement in the existing LDMOS DC model file. In this example, W is the device width, L is the device length, lc is the effective device length, 1_ndrift is the length of the N-type drift region (Ndrift), l_pepi is the length of the P-type epitaxial layer (Pepi), l_nbl is the length of the N+ type buried layer (NBL), w0 is the width parameter (all in meters); rds is the channel DC equivalent resistance, vv1 is the first voltage parameter, vv2 is the second voltage parameter, v(d, s) is the drain-source voltage, v(s1, s) is the source equivalent resistance voltage drop; count is the repeatability, nf is the cross exponent, m is the total number of reuses; dtemp is the device temperature, tc1x is the first-order temperature correction factor, tc2x is the second-order temperature correction factor, tfac is the temperature correction factor, tfacv1 is the first-order temperature exponent correction factor, tfacv2 is the second-order temperature exponent correction factor, tfacw is the width-dependent temperature correction factor, and pd is the perimeter of the drain diffusion region. diffusion (not including edge under gate), ad is the drain area, nrd is the number of blocks in the drain diffusion region, nrs is the number of blocks in the source diffusion region, snld80core indicates that this model file is applicable to LDMOS devices with a voltage of 80V.

[0007] Currently, the super-integrated silicon gate process BCD (Bipolar-CMOS-DMOS) platform typically develops LDMOS devices for various voltages, including 16V, 20V, 30V, 40V, 50V, 60V, 80V, 100V, and 120V, to meet customers' multi-voltage application needs. Facing multiple voltage applications, modeling requires adding corresponding testkey circuits. Multiple models need to be built based on device testing at different voltages; creating a separate model for each voltage is time-consuming and labor-intensive.

[0008] Despite offering a wide variety of LDMOS models applicable to different voltages, it is difficult to provide LDMOS models for the entire voltage range to meet the diverse needs of customers. For example, if a customer requires a 70V LDMOS, a model cannot be provided without the corresponding test key circuit. Summary of the Invention

[0009] To overcome the shortcomings of the existing technology, the purpose of this invention is to provide a DC modeling method for LDMOS with different voltage applications, so as to realize an LDMOS model that can be applied to different voltages.

[0010] To achieve the above and other objectives, this invention proposes a DC modeling method for LDMOS applications with different voltages, comprising the following steps:

[0011] Step S1: Extract relevant model parameters of the device's DC performance based on the existing SPICE models of LDMOS for different application voltages;

[0012] Step S2: Using the relevant model parameters extracted in step S1, fit the parameters that affect the equivalent resistance of the drift region to form a mathematical fitting trend line for the corresponding parameters.

[0013] Step S3: Obtain the mathematical relationship between the parameters affecting the equivalent resistance of the drift region of different application voltage devices and PA and PF from the mathematical fitting trend line, where PF is the overlapping area of ​​the gate polysilicon of the LDMOS, the shallow channel isolation region, and the N-type drift region, and PA is the overlapping area of ​​the shallow channel isolation region and the N-type drift region of the LDMOS.

[0014] Step S4: Add the obtained mathematical relationship to the SPICE model sub-circuit to obtain a new DC model file for LDMOS that can be applied to different voltages.

[0015] Optionally, the model parameters include threshold voltage (vth0), electron mobility (u0 / ua / ub), channel DC equivalent resistance (rds), and a first voltage parameter (vv1).

[0016] Optionally, the parameters affecting the equivalent resistance of the drift region include the channel DC equivalent resistance rds and the first voltage parameter vv1.

[0017] Optionally, in step S3, the following mathematical relationship between the DC equivalent resistance rds of different application voltage devices and PA and PF is obtained by mathematically fitting the trend line:

[0018] rds = 2.5E - 3*(pa + pf) + r0

[0019] Where r0 = 3E-3, pa is the length of PA, and pf is the length of PF, in units of um.

[0020] Optionally, in step S3, the mathematical relationship between the first voltage parameter vv1 of different application voltage devices and PA and PF is obtained by mathematically fitting the trend line.

[0021] vv1=-3.0E-2*(pa+pf)+v0

[0022] Where, v0 = 3E-1.

[0023] Optionally, in the mathematical relationship, different pa+pf correspond to different voltages.

[0024] Compared with existing technologies, the present invention provides a DC modeling method for LDMOS with different voltage applications. This method involves fitting parameters affecting the equivalent resistance of the drift region to form mathematical fitting trend lines for these parameters. From these trend lines, mathematical relationships are obtained between the parameters affecting the equivalent resistance of the drift region and PA and PF for devices with different application voltages. Finally, these mathematical relationships are added to the SPICE model sub-circuit to obtain a new DC model file for LDMOS applicable to different voltages, thus realizing an LDMOS model applicable to different voltages. Attached Figure Description

[0025] Figure 1a This is a schematic diagram of the existing LDMOS structure;

[0026] Figure 1b for Figure 1a The equivalent circuit structure diagram of LDMOS;

[0027] Figure 2 The diagram shown is a schematic diagram of the structure of an LDMOS device.

[0028] Figure 3 This is a flowchart of an LDMOS DC modeling method for different voltage applications according to the present invention;

[0029] Figure 4a This is a trend line graph showing the fitting relationship between rds and PF / PA lengths in this invention.

[0030] Figure 4b This is a trend line graph showing the fitting relationship between vv1 and the length of PF / PA in this invention.

[0031] Figure 5a , Figure 6a , Figure 7a The figures show a comparison of the Ids-Vgs curves of the 60V, 80V, and 100V LDMOS devices of the present invention and the prior art, respectively.

[0032] Figure 5b , Figure 6b , Figure 7b The figures show a comparison of the Ids-Vds curves of the 60V, 80V, and 100V LDMOS devices of the present invention and the prior art. Detailed Implementation

[0033] The following describes the embodiments of the present invention through specific examples and in conjunction with the accompanying drawings. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific examples, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0034] Figure 2 The diagram shown is a structural analysis of an LDMOS device. The area between the N-type drift region (Ndrift) 2 and the polysilicon (Poly) 5 field plate is divided into two parts: PF and PA. PF is the overlapping area of ​​the gate polysilicon (Poly) 5, the shallow channel isolation region (STI) 1, and the N-type drift region (Ndrift) 2. PA is the overlapping area of ​​the shallow channel isolation region (STI) 1 and the N-type drift region (Ndrift) 2.

[0035] Typically, for LDMOS with the same structure and process, different breakdown voltages are achieved by biasing PF and PA. Therefore, the equivalent resistance R1 of the drain (D, Drain) drift region can be equivalent to a variable resistance that varies with PF and PA. The parameters affecting the equivalent resistance R1 of the drift region are the channel DC equivalent resistance rds and the first voltage parameter vv1. Therefore, fitting these parameters can achieve the purpose of this invention.

[0036] Based on this, the present invention provides a DC modeling method for LDMOS for different voltage applications, such as... Figure 3 As shown, it includes the following steps:

[0037] Step S1: Extract relevant model parameters of the device's DC performance based on the SPICE models of existing LDMOS for different application voltages. The model parameters include, but are not limited to, threshold voltage vth0, electron mobility u0 / ua / ub, channel DC equivalent resistance rds, and first voltage parameter vv1.

[0038] Step S2: Using the relevant model parameters extracted in step S1, fit the parameters that affect the equivalent resistance of the drift region to form a mathematical fitting trend line for the corresponding parameters.

[0039] In this embodiment, the parameters affecting the equivalent resistance of the drift region include the channel DC equivalent resistance rds and the first voltage parameter vv1. Specifically, using the DC correlation model parameters extracted in step S1, the channel DC equivalent resistance rds and the first voltage parameter vv1 are fitted to form a mathematical fitting trend line for the channel DC equivalent resistance rds and the first voltage parameter vv1. The data for rds and vv1 with respect to PF+PA are shown in Table 1, and the fitting trend line is as follows: Figure 4a , Figure 4b As shown.

[0040] Table 1 rds / vv1 and PF+PA data table

[0041] 2.5 0.0093 0.22502 3.5 0.01175 0.19522 4.5 0.0143 0.165057

[0042] Step S3: Obtain the mathematical relationship between the DC equivalent resistance rds and the first voltage parameter vv1 of different application voltage devices and PA and PF from the mathematical fitting trend line, where PF is... Figure 2 The overlapping region of the gate polysilicon (Poly) 5, the shallow trench isolation region (STI) 1, and the N-type drift region (Ndrift) 2, PA is Figure 2 The overlapping area of ​​the shallow-medium channel isolation zone (STI) 1 and the N-type drift zone (Ndrift) 2. Figure 4a The mathematical relationship between rsd and PA and PF is shown next to the rds fitting trend line. Figure 4b The mathematical relationship between vv1 and PA and PF is shown next to the fitted trend line.

[0043] In this embodiment, the following mathematical relationships between the DC equivalent resistance rds and the first voltage parameter vv1 of different application voltage devices and PA and PF are obtained by mathematically fitting trend lines:

[0044] rds = 2.5E - 3*(pa + pf) + r0

[0045] vv1=-3.0E-2*(pa+pf)+v0

[0046] Where r0 = 3E-3, v0 = 3E-1; pa is the length of PA in μm, pf is the length of PF in μm, and different pa+pf correspond to different voltages.

[0047] Step S4: Add the obtained mathematical relationship to the SPICE model sub-circuit to obtain the DC model file of LDMOS. This embodiment of the invention uses an 80V LDMOS as a reference, but the reference is not limited to this; it can be 60V, 100V, or other voltage values.

[0048] In this embodiment, the obtained mathematical relation is added to the SPICE model sub-circuit, as shown in the following Spice model sub-circuit description statement:

[0049]

[0050] Figure 5a , Figure 6a , Figure 7a The graphs show a comparison of the Ids-Vgs curves of the 60V, 80V, and 100V LDMOS devices of the present invention and the prior art. Figure 5b , Figure 6b , Figure 7b The figures show a comparison of the Ids-Vds curves of the 60V, 80V, and 100V LDMOS devices of the present invention and the prior art, respectively. It can be seen that the model established by the method of the present invention matches the existing model well under different voltages.

[0051] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can make modifications and changes to the above embodiments without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the claims.

Claims

1. A DC modeling method for LDMOS applications with different voltages, comprising the following steps: Step S1: Extract relevant model parameters of the device's DC performance based on the existing SPICE models of LDMOS for different application voltages. The model parameters include threshold voltage vth0, electron mobility u0 / ua / ub, channel DC equivalent resistance rds, and first voltage parameter vv1. Step S2: Using the relevant model parameters extracted in step S1, fit the parameters that affect the equivalent resistance of the drift region to form a mathematical fitting trend line for the corresponding parameters. The parameters that affect the equivalent resistance of the drift region include the channel DC equivalent resistance rds and the first voltage parameter vv1. Step S3: Obtain the mathematical relationship between the parameters of the equivalent resistance of the drift region of different application voltage devices and PA and PF from the mathematical fitting trend line, wherein, PF is the overlapping region of the gate polysilicon, shallow channel isolation region, and N-type drift region of the LDMOS, and PA is the overlapping region of the shallow channel isolation region and N-type drift region of the LDMOS. In step S3, the following mathematical relationship between the DC equivalent resistance rds of different application voltage devices and PA and PF is obtained by mathematically fitting the trend line: rds = 2.5E - 3 * (pa + pf) + r0 Where r0 = 3E-3, pa is the length of PA, and pf is the length of PF; In step S3, the following mathematical relationship between the first voltage parameter vv1 of different application voltage devices and PA and PF is obtained by mathematically fitting the trend line: vv1 = -3.0E-2*(pa+pf)+v0 Where, v0 = 3E-1; Step S4: Add the obtained mathematical relationship to the SPICE model sub-circuit to obtain a new DC model file for LDMOS that can be applied to different voltages.

2. The LDMOS DC modeling method for different voltage applications as described in claim 1, characterized in that, In the mathematical formula, different pa+pf values ​​correspond to different voltages.

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