Semiconductor memory device and method of operating a semiconductor memory device

Abstract

A semiconductor memory device and a method of operating a semiconductor memory device are disclosed. A semiconductor memory device includes a plurality of memory blocks and a contact region. Each of the plurality of memory blocks includes a plurality of memory cells. The contact region is formed between the plurality of memory blocks. The semiconductor memory device differently uses a first memory block among the plurality of memory blocks that is not adjacent to the contact region and a second memory block that is adjacent to the contact region.

Description

Technical Field

[0001] This disclosure relates to semiconductor memory devices, and more specifically, to a three-dimensional semiconductor memory device and a method of operating the semiconductor memory device. Background Technology

[0002] Semiconductor memory devices can be formed as a two-dimensional structure with horizontally arranged strings on a semiconductor substrate, or as a three-dimensional structure with vertically stacked strings on a semiconductor substrate. Three-dimensional semiconductor memory devices are designed to overcome the integration limitations of two-dimensional memory devices and can include multiple memory cells vertically stacked on a semiconductor substrate. Summary of the Invention

[0003] According to embodiments of this disclosure, a semiconductor memory device includes a plurality of memory blocks and contact regions. Each of the plurality of memory blocks includes a plurality of memory cells. Contact regions are formed between the plurality of memory blocks. The semiconductor memory device uses a first memory block that is not adjacent to the contact regions and a second memory block that is adjacent to the contact regions, respectively.

[0004] According to another embodiment of this disclosure, a method of operating a semiconductor memory device involves receiving a command for a target memory block among a plurality of memory blocks from a memory controller, determining operation parameters for performing an operation corresponding to the command based on the type of the target memory block, and performing an operation on the target memory block based on the determined operation parameters.

[0005] According to another embodiment of this disclosure, by operating a semiconductor memory device, a plurality of memory blocks are distinguished into a first memory block that is not adjacent to the contact area and a second memory block that is adjacent to the contact area. Any one of the plurality of memory blocks belonging to the second memory block is selected as a target memory block. The program erase count value of the target memory block is checked, and when the program erase count value is greater than a predetermined threshold, the target memory block is converted into a first memory block.

[0006] According to another embodiment of this disclosure, a semiconductor memory device includes a plurality of memory blocks and contact regions. Each of the plurality of memory blocks includes a plurality of memory cells. Contact regions are formed between the plurality of memory blocks. A first operating parameter is used for a first operation on a first memory block spaced apart from the contact regions, and a second operating parameter is used for a second operation on a second memory block adjacent to the contact regions. The first operating parameter is different from the second operating parameter, and the first operation and the second operation are the same. Attached Figure Description

[0007] Figure 1 This is a block diagram schematically showing the semiconductor memory device 10.

[0008] Figure 2 It is shown Figure 1 A block diagram illustrating an embodiment of the peripheral circuit 30.

[0009] Figure 3 This is an equivalent circuit diagram of a storage block according to an embodiment.

[0010] Figure 4 This is a diagram showing the conductive layers disposed on the bit lines of a memory cell array.

[0011] Figure 5 This is a diagram showing multiple planes included in a memory cell array.

[0012] Figure 6 This is a diagram showing the arrangement of multiple storage blocks belonging to a plane.

[0013] Figure 7 It is shown Figure 6 A graph showing the threshold voltage distribution of memory cells included in a memory block.

[0014] Figure 8 It is a graph showing the threshold voltage distribution width of memory blocks adjacent to the contact area and memory cells included in other memory blocks.

[0015] Figure 9 This is a diagram illustrating a semiconductor memory device with different operating conditions applied according to embodiments of the present disclosure, namely a first memory block not adjacent to the contact region and a second memory block adjacent to the contact region.

[0016] Figure 10 This is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure.

[0017] Figure 11 It is shown Figure 10 A flowchart of an implementation method for step S130.

[0018] Figure 12 This is a diagram illustrating a method for applying the purpose of the first storage block and the second storage block differently according to another embodiment of this disclosure.

[0019] Figure 13 This is a diagram illustrating a semiconductor memory device according to another embodiment of the present disclosure, wherein the number of bits stored in memory cells in a second memory block is relatively smaller than the number of bits stored in memory cells included in a first memory block.

[0020] Figure 14This is a diagram illustrating a semiconductor memory device according to another embodiment of the present disclosure, wherein the number of bits stored in memory cells in a second memory block is relatively greater than the number of bits stored in memory cells included in a first memory block.

[0021] Figure 15 This is a flowchart illustrating a method of operating a semiconductor memory device according to another embodiment of the present disclosure.

[0022] Figure 16 This is a block diagram illustrating the configuration of a memory system according to an embodiment.

[0023] Figure 17 This is a block diagram illustrating the configuration of a computing system according to an embodiment. Detailed Implementation

[0024] The specific structural or functional descriptions of embodiments based on the concepts disclosed in this specification or application are shown only for the purpose of describing embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be performed in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0025] It will be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another, and not to define the element itself or to indicate a particular order. It will be understood that when an element or layer is referred to as being "on" another element or layer, "connected to" another element or layer, or "attached to" another element or layer, it may be directly on, connected to, or attached to another element or layer, or there may be intermediate elements or layers. In contrast, when an element is referred to as being "directly on" another element or layer, "directly connected to" another element or layer, or "directly attached to" another element or layer, there are no intermediate elements or layers. For ease of description, spatial relative terms such as "below," "below," "under," "above," "upper," "lower," etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. It will be understood that, in addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figure is flipped, an element described as "below" or "under" other elements or features will be oriented as "above" other elements or features. Therefore, examples of the term "below" can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relative descriptors used herein are interpreted accordingly.

[0026] Embodiments of this disclosure provide a semiconductor memory device and a method of operating the same that can improve operational performance.

[0027] In one embodiment, the semiconductor memory device may include bit lines and logic circuitry. Bit lines may be disposed on multiple memory blocks and contact areas. Logic circuitry may be disposed below the multiple memory blocks and contact areas.

[0028] In one implementation, the logic circuitry may include peripheral circuitry that performs operations on a selected memory block among a plurality of memory blocks. The peripheral circuitry may use a first parameter during operation when the selected memory block is a first memory block, and a second parameter different from the first parameter during operation when the selected memory block is a second memory block.

[0029] In one implementation, the semiconductor memory device can store user data in a first memory block and system data in a second memory block.

[0030] In this implementation, N bits can be stored in the memory cells included in the first memory block, and M bits can be stored in the memory cells included in the second memory block. Here, N can be a natural number greater than 0, and M can be a natural number greater than N.

[0031] In this implementation, N bits can be stored in the memory cells included in the first memory block, and M bits can be stored in the memory cells included in the second memory block. Here, M can be a natural number greater than 0, and N can be a natural number greater than M.

[0032] In one implementation, when the program erase count of the second storage block exceeds a predetermined threshold, the second storage block can be operated using the same operating parameters as the first storage block.

[0033] In this implementation, a contact area can be formed between multiple storage blocks. Among the multiple storage blocks, the storage block that is not adjacent to the contact area can be a first storage block, and the storage block that is adjacent to the contact area can be a second storage block.

[0034] In an implementation, determining the operating parameters may include: checking the type of the target storage block; and selecting a first parameter when the target storage block is a first storage block.

[0035] In the implementation, determining the operating parameters may further include: when the target storage block is a second storage block, selecting a second parameter that is different from the first parameter.

[0036] In an implementation, the method may further include: maintaining the target storage block as a second storage block when the programmed erase count value is not greater than a predetermined threshold.

[0037] Various embodiments may provide a semiconductor memory device and its operation method that can improve operational performance.

[0038] Figure 1 This is a block diagram schematically showing the semiconductor memory device 10.

[0039] Reference Figure 1 The semiconductor memory device 10 includes a logic circuit LC and a memory cell array 40. The logic circuit LC may include an internal voltage generator 20 and peripheral circuitry 30.

[0040] The internal voltage generator 20 can be configured to receive external voltages and generate various internal voltages. As an implementation, the internal voltages may include internal ground voltages and internal power supply voltages.

[0041] The peripheral circuit 30 can be configured to perform programming operations for storing data in the memory cell array 40, reading operations for outputting data stored in the memory cell array 40, and erasing operations for erasing data stored in the memory cell array 40. The internal voltage required to enable the peripheral circuit 30 can be generated from the internal voltage generator 20 and supplied to the peripheral circuit 30.

[0042] Figure 2 It is shown Figure 1 A block diagram illustrating an embodiment of the peripheral circuit 30.

[0043] Reference Figure 2 The peripheral circuitry 30 may include control logic 39, an operating voltage generator 31, a line decoder 33, a source line driver 37, and a page buffer set 35. The control logic 39 may be implemented in hardware, software, or a combination of both. For example, the control logic 39 may be a control logic circuit operating according to an algorithm and / or a processor executing control logic code.

[0044] The memory cell array 40 may include multiple memory blocks. Each memory block may be connected to one or more drain select lines (DSLs), multiple word lines (WLs), one or more source select lines (SSLs), multiple bit lines (BLs), and at least one common source line (CSL).

[0045] Control logic 39 can control peripheral circuitry 30 in response to commands CMD and addresses ADD.

[0046] Operating voltage generator 31 can generate various operating voltages VOPs used in programming, reading, and erasing operations in response to control of control logic 39. Operating voltages VOPs may include programming voltage, verification voltage, pass voltage, selection line voltage, etc.

[0047] The line decoder 33 can select a memory block in response to the control logic 39. The line decoder 33 can be configured to apply operating voltages VOPs to the drain select lines DSLs, word lines WLs, and source select lines SSLs connected to the selected memory block.

[0048] Source line driver 37 can be connected to memory cell array 40 via common source line CSL. Source line driver 37 can be configured to perform a discharge operation on common source line CSL in response to control of control logic 39. Source line driver 37 can also apply pre-erase voltage and erase voltage to common source line CSL during erase operation in response to control of control logic 39.

[0049] Page buffer group 35 can be connected to memory cell array 40 via bit lines BLs. Page buffer group 35 can temporarily store data to be programmed received from input / output circuitry (not shown) during programming operations in response to control logic 39. Page buffer group 35 can sense the voltage or current of bit lines BLs during read or verification operations in response to control logic 39. Page buffer group 35 can selectively float bit lines BLs in response to control logic 39.

[0050] The internal voltage output from the internal voltage generator 20 can be supplied to the peripheral circuitry 30. Alternatively, an internal ground voltage VSSI can be output from the internal voltage generator 20. The internal ground voltage VSSI can be supplied to the peripheral circuitry 30 via a line overlapping with the memory cell array 40.

[0051] Figure 3 This is an equivalent circuit diagram of a storage block according to an embodiment.

[0052] Reference Figure 3 A memory block may include multiple memory cell strings STRs that are commonly connected to a common source line CSL. The memory cell strings STRs may be connected to multiple bit lines BL1 to BLm. The memory cell strings STRs STRs may be divided into multiple column groups, each connected to bit lines BL1 to BLm. The memory cell strings STRs STRs of each column group may be connected in parallel to their respective bit lines.

[0053] Each memory cell string STR may include one or more drain select transistors, multiple memory cells, and one or more source select transistors disposed between a corresponding bit line and a common source line CSL. The gate of each drain select transistor may be connected to its corresponding drain select line, the gate of each memory cell may be connected to its corresponding word line, and the gate of each source select transistor may be connected to its corresponding source select line.

[0054] As an implementation, each memory cell string STR can be connected to the drain select line DSL, multiple word lines WL1 to WLn, and the source select line SSL. In this case, each memory cell string STR may include a drain select transistor DST connected to the drain select line DSL, memory cells MC connected to word lines WL1 to WLn, and a source select transistor SST connected to the source select line SSL.

[0055] Multiple memory cells MC can be connected in series. A drain-select transistor DST can be disposed between the multiple memory cells MC and their corresponding bit lines. The drain-select transistor DST may include a junction region connected to the corresponding bit line. A source-select transistor SST can be disposed between the multiple memory cells MC and the common source line CSL. The source-select transistor SST may include a junction region connected to the common source line CSL.

[0056] The structure of each memory cell string STR is not limited to Figure 3 The illustrated implementation. In one implementation, each memory cell string STR may include two or more drain select transistors connected in series between a plurality of memory cells MC connected in series and their corresponding bit lines. In this case, two or more drain select lines may be provided between bit lines BL1 to BLm and word lines WL1 to WLn. In another implementation, each memory cell string STR may include two or more source select transistors connected in series between a plurality of memory cells MC connected in series and a common source line CSL. In this case, two or more source select lines may be provided between the common source line CSL and word lines WL1 to WLn.

[0057] As an implementation, at least one of word lines WL1 to WLn can be used as a dummy word line. For example, at least one of the word lines WL1 adjacent to the source select line SSL or WLn adjacent to the drain select line DSL can be used as a dummy word line.

[0058] Figure 4 This is a diagram showing the conductive layers disposed on the bit lines of a memory cell array.

[0059] Reference Figure 4 The memory cell array 40 may be disposed between the common source line CSL and bit lines BL1 to BLm. The memory cell array 40 may include a gate stack GST and multiple channel structures CH passing through the gate stack GST. Bit lines BL1 to BLm may extend in the first direction D1. Although... Figure 4 As not shown in the diagram, multiple word lines may extend in the second direction D2. Furthermore, the channel structure CH may extend in the third direction D3.

[0060] The gate stacks (GSTs) can be spaced apart from each other. Figure 4 Two gate stacks (GSTs) spaced apart from each other are shown, with a conductive electrode contact structure (SCT) interposed between them. Besides... Figure 4 In addition to the structure shown, the memory cell array 40 may include three or more gate stacks (GSTs) spaced apart from each other.

[0061] Each channel structure CH may include one end connected to the common source line CSL and the other end connected to a corresponding bit line among bit lines BL1 to BLm. Each channel structure CH and the common source line CSL may be directly connected. Alternatively, a lower channel structure or contact structure may be formed for connecting each channel structure CH and the common source line CSL. Each channel structure CH and its corresponding bit line may be directly connected. Alternatively, a contact structure may be formed for connecting each channel structure CH and its corresponding bit line.

[0062] The channel structure CH can be arranged in a sawtooth or matrix form in the corresponding gate stack.

[0063] A common source line (CSL) may be formed on a substrate including logic circuitry (LC). The common source line (CSL) may include a contact region (CTA) that does not overlap with the gate stack (GST). In one embodiment, the contact region (CTA) of the common source line (CSL) may be disposed between adjacent gate stacks (GST). A source contact structure (SCT) may extend from the contact region (CTA) of the common source line (CSL) toward the upper conductive layer (L1).

[0064] In the implementation method, such as Figure 4 As shown, the upper conductive layer L1 can be used to connect the common source line CSL to... Figure 2 The source line driver 37 is shown. Therefore, the potential level of the common source line CSL can be transmitted through the upper conductive layer L1. Figure 2 The source line driver 37 shown is discharged. Additionally, during the erase operation, through... Figure 2 The erase voltage provided by the source line driver 37 shown can be transmitted to the common source line CSL via the upper conductive layer L1. However, embodiments of this disclosure are not limited thereto. The upper conductive layer L1 according to embodiments of this disclosure may not be connected to the common source line CSL. In this case, the upper conductive layer L1 can be used to connect the common source line CSL to... Figure 2 The source line driver 37 shown here serves a purpose other than its intended use. For example, the upper conductive layer L1 can be used to... Figure 2 The lines connecting the internal voltage generator 20 and the peripheral circuit 30 shown are shown.

[0065] In addition, Figure 4In this configuration, an upper conductive layer L1 is formed between bit lines BL1 and BLm. However, this disclosure is not limited to this; multiple upper conductive layers can be formed on the first direction D1 or the second direction D2. Additionally, multiple upper conductive layers can be formed on the third direction D3.

[0066] The upper conductive layer L1 may include a low-resistance metal. The upper conductive layer L1 may include a metal such as copper or aluminum.

[0067] Reference Figure 4 The common source line CSL is connected to the upper conductive layer via a contact region CTA that does not overlap with the gate stack GST. In another embodiment, bit lines BL1 to BLm can be connected to the logic circuit LC via the contact region CTA.

[0068] Figure 5 This is a diagram illustrating multiple planes included in a memory cell array. (See reference...) Figure 5 The memory cell array 40 includes four planes 41 to 44. However, this is just an example, and the number of planes included in the memory cell array 40 is not limited to this. For example, the memory cell array 40 may include two planes or only one plane.

[0069] Each of the planes 41 to 44 included in the memory cell array 40 may include multiple memory blocks. Furthermore, each plane included in the memory cell array 40 may be composed of... Figure 4 The gate stack GST is formed.

[0070] Figure 6 This is a diagram showing the arrangement of multiple storage blocks belonging to a plane. (Refer to...) Figure 6 , showing Figure 5 The structure of plane 41 among planes 41 to 44. However, the other planes 42 to 44 may also have the same structure. Figure 5 The same structure as plane 41.

[0071] Reference Figure 6 Plane 41 may include multiple memory blocks BLK1 to BLKz. For example, memory blocks BLK1 to BLKz may be arranged sequentially in the first direction D1. Furthermore, bit lines BL1 to BLm may extend from memory blocks BLK1 to BLKz in the first direction D1. Bit lines BL1 to BLm may be arranged sequentially in the second direction D2.

[0072] Contact area CTA can be formed in Figure 6 The storage blocks shown are between BLK1 and BLKz. For example... Figure 4 As shown, the contact region CTA can be the region between the gate stacks GST. Therefore, in Figure 6In this configuration, the first memory block BLK1 to the i-th memory block BLKi can form a gate stack GST. Additionally, the j-th memory block BLKj to the p-th memory block BLKp can form a gate stack GST. Furthermore, the q-th memory block BLKq to the z-th memory block BLKz can also form a gate stack GST.

[0073] Bit line contacts BC can be formed in the contact area CTA. Bit line contacts BC can be formed in the contact area CTA to connect bit lines BL1 to BLm formed on memory blocks BLK1 to BLKz to logic circuits LC formed below the memory blocks.

[0074] Storage blocks BLK1 to BLK(i-1), BLK(j+1) to BLK(p-1), and BLK(q+1) to BLKz, which are not adjacent to the contact area CTA, are surrounded by other storage blocks. Therefore, these blocks experience relatively large interference effects due to their coupling with two adjacent storage blocks. On the other hand, unlike the other storage blocks, storage blocks BLKi, BLKj, BLKp, and BLKq, which are adjacent to the contact area CTA, are not surrounded by other storage blocks. Therefore, these blocks experience relatively less interference effects due to their coupling with other storage blocks. Therefore, in the implementation, compared with the remaining memory blocks BLK1 to BLK(i-1), BLK(j+1) to BLK(p-1), and BLK(q+1) to BLKz, the memory blocks BLKi, BLKj, BLKp, and BLKq adjacent to the contact region CTA have superior cell characteristics. In the implementation, memory blocks not adjacent to the contact region (e.g., BLK1 to BLK(i-1), BLK(j+1) to BLK(p-1), and BLK(q+1) to BLKz) can be referred to as memory blocks spaced apart from the contact region.

[0075] According to embodiments of this disclosure, memory blocks BLKi, BLKj, BLKp, and BLKq, which have excellent cell characteristics and are disposed adjacent to the contact region CTA, are applied under different operating conditions and for different purposes than the remaining memory blocks BLK1 to BLK(i-1), BLK(j+1) to BLK(p-1), and BLK(q+1) to BLKz. Therefore, according to embodiments of this disclosure, memory blocks included in the memory cell array can be used efficiently. As a result, in some embodiments, the operational performance of the semiconductor memory device is improved.

[0076] Figure 7 It is shown Figure 6A graph showing the threshold voltage distribution of the memory cells included in a memory block. Figure 7 In the graph, the horizontal axis indicates the threshold voltage Vth of the memory cell, and the vertical axis indicates the number of memory cells corresponding to each threshold voltage Vth.

[0077] Reference Figure 7 , Figure 7 The diagram illustrates the threshold voltage distribution DSB1 of memory cells in memory blocks BLKi, BLKj, BLKp, and BLKq adjacent to the contact area CTA, and the threshold voltage distribution DSB2 of memory cells in memory blocks BLK1 to BLK(i-1), BLK(j+1) to BLK(p-1), and BLK(q+1) to BLKz not adjacent to the contact area CTA, when programming operations are performed under the same conditions. The threshold voltage distribution DSB1 of memory cells in memory blocks BLKi, BLKj, BLKp, and BLKq adjacent to the contact area CTA has a first distribution width W1, and the threshold voltage distribution DSB2 of memory cells in memory blocks BLK1 to BLK(i-1), BLK(j+1) to BLK(p-1), and BLK(q+1) to BLKz not adjacent to the contact area CTA has a second distribution width W2. Since the first distribution width W1 is narrower than the second distribution width W2, the memory blocks BLKi, BLKj, BLKp and BLKq, which are located adjacent to the contact area CTA, have relatively superior operating characteristics in programming, reading or erasing operations.

[0078] Figure 8 This is a graph showing the threshold voltage distribution width of memory blocks adjacent to the contact area and memory cells included in other memory blocks. Figure 8 In the graph, the horizontal axis indicates the distance from storage block BLK1, and the vertical axis indicates the width of the threshold voltage distribution of the memory cells included in the storage block, which is set according to the distance from storage block BLK1.

[0079] Reference Figure 8The contact area (CTA) can be formed at the location indicated by the dashed line. The threshold voltage of the memory cells included in the memory block adjacent to the contact area CTA can have a first distribution width W1. The threshold voltage of the memory cells included in the memory block not adjacent to the contact area CTA can have a second distribution width W2 greater than the first distribution width W1. As described above, since the memory block adjacent to the contact area CTA and the remaining memory blocks have different threshold voltage distribution characteristics, the operating conditions, purposes, etc., of the memory block adjacent to the contact area CTA and the remaining memory blocks are applied differently. Therefore, according to the embodiments of this disclosure, memory blocks included in the memory cell array can be used efficiently. As a result, in some embodiments, the operating performance of the semiconductor memory device is improved.

[0080] Figure 9 This is a diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure, wherein the operating conditions of a first memory block not adjacent to the contact region and a second memory block adjacent to the contact region are applied differently.

[0081] Reference Figure 9 The storage blocks BLK1 to BLKz within the first plane 41 can be divided into a first storage block and a second storage block. The first storage blocks BLK1 to BLK(i-1), BLK(j+1) to BLK(p-1), and BLK(q+1) to BLKz are storage blocks not adjacent to the contact region CTA, while the second storage blocks BLKi, BLKj, BLKp, and BLKq are storage blocks adjacent to the contact region CTA. Figure 9 In the diagram, adjacent storage blocks are indicated by deflection lines.

[0082] According to embodiments of this disclosure, the operating parameters used in operations on the first storage block and the operating parameters used in operations on the second storage block may be applied differently. These operations may be any one of programming operations, read operations, or erase operations. The operating parameters may be any one of the parameters used in programming operations, parameters used in read operations, or parameters used in erase operations.

[0083] For example, in the case of programming operations, the operating parameters may include at least one of the following: a programming voltage applied to a selected word line, a programming pass voltage applied to an unselected word line, a programming enable voltage applied to a bit line connected to a programming enable cell, a programming disable voltage applied to a bit line connected to a programming disable cell, and a verification voltage used in verification operations. Additionally, various parameters used in programming operations may be included in the operating parameters.

[0084] As another example, in the case of a read operation, the operating parameters may include at least one of the read voltage applied to the selected word line, the read pass voltage applied to the unselected word line, and a precharge voltage or precharge time for precharging the bit lines. Additionally, various parameters used in the read operation may be included in the operating parameters.

[0085] As another example, in the case of an erase operation, the operating parameters may include at least one of an erase voltage applied via a bit line or common source line connected to the selected memory block and an erase verification voltage used to check whether the threshold voltage of the memory cell has become sufficiently low. Additionally, various parameters used in the erase operation may be included in the operating parameters.

[0086] As described above, in this embodiment, by applying different operating parameters used in the operation of the first storage block and the operation of the second storage block, the operational performance of each of the first and second storage blocks can be maximized. (Refer to...) Figure 10 and Figure 11 This describes implementations of operating parameters used in operations on a first memory block and operating parameters used in operations on a second memory block, respectively.

[0087] According to another embodiment of this disclosure, the types of data stored in the first memory block and the types of data stored in the second memory block can be applied differently. For example, user data may be stored in the first memory block comprising memory cells having a relatively wide threshold voltage distribution, and system data may be stored in the second memory block comprising memory cells having a relatively narrow threshold voltage distribution. User data may be data input to the memory system from outside the memory system. System data may be data required for the operation of the semiconductor memory device. As an example, system data may include parameters required for the operation of the semiconductor memory device. As another example, system data may include management information required by an external memory controller to control the operation of the semiconductor memory device. For example, system data may include boot code executed when the memory system is booted. As another example, system data may include metadata of the data stored in the semiconductor memory device. For example, metadata may include mapping data for mapping logical addresses to physical addresses. As another example, system data may include parity data used for error correction when reading data stored in the semiconductor memory device.

[0088] As described above, in this embodiment, by storing the system data required for the operation of the semiconductor memory device in a second memory block with higher reliability, the operational stability of the semiconductor memory device can be improved. (Refer to...) Figure 12 This describes implementations that apply different types of data stored in the first storage block and different types of data stored in the second storage block.

[0089] According to another embodiment of this disclosure, the number of bits stored in each memory cell included in the first memory block and the number of bits stored in each memory cell included in the second memory block can be applied differently. As an example, a memory block can be used such that the number of bits stored in the memory cells included in the second memory block is less than the number of bits stored in the memory cells included in the first memory block. As another example, a memory block can be used such that the number of bits stored in the memory cells included in the second memory block is greater than the number of bits stored in the memory cells included in the first memory block. See also... Figure 13 and Figure 14 This describes implementations that apply different numbers of bits stored in the various memory cells included in the first memory block and the various numbers of bits stored in the various memory cells included in the second memory block.

[0090] According to another embodiment of this disclosure, among memory blocks disposed adjacent to the contact area CTA and thus identified as second memory blocks, memory blocks with a program erase count exceeding a predetermined standard can be converted into first memory blocks. Since the second memory block is disposed adjacent to the contact area CTA, the threshold voltage distribution characteristics of the memory cells can be relatively satisfactory; however, the threshold voltage distribution characteristics of the memory cells can gradually deteriorate with the cumulative number of uses of the second memory block. Therefore, among the second memory blocks, memory blocks with a program erase count exceeding the predetermined standard can be converted into first memory blocks and used. (Refer to...) Figure 15 This describes an implementation where a second memory block whose programmable erase count exceeds a predetermined threshold is converted to a first memory block. The term "predetermined" (e.g., predetermined threshold and predetermined standard) used herein with respect to parameters means that the value of the parameter is determined before it is used in the processing or algorithm. In some implementations, the value of the parameter is determined before the processing or algorithm begins. In other implementations, the value of the parameter is determined during the processing or algorithm, but before it is used in the processing or algorithm.

[0091] Figure 10 This is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure.

[0092] Reference Figure 10 A method for operating a semiconductor memory device according to an embodiment of the present disclosure includes: receiving a command for a target memory block from a memory controller (S110); determining operating parameters for performing an operation corresponding to the received command based on the type of the target memory block (S130); and performing the operation corresponding to the received command on the target memory block based on the determined operating parameters (S150).

[0093] In step S110, the semiconductor memory device may receive from the memory controller a command instructing the execution of a specific operation, and the address of a target memory block that is the object of the operation corresponding to the received command. For example, the semiconductor memory device may receive a programming command and its corresponding address. The semiconductor memory device determines the target memory block based on the received address.

[0094] In step S130, operation parameters for performing the operation corresponding to the received command on the identified target storage block can be determined. That is, in step S130, based on the target storage block being... Figure 9 The operation parameters are determined by whether it is the first or second storage block shown. (Refer to...) Figure 11 Describe step S130.

[0095] In step S150, the target storage block can be operated on in response to the received command using the determined operation parameters.

[0096] Figure 11 It is shown Figure 10 A flowchart of an implementation method for step S130.

[0097] Reference Figure 11 Step S130 includes: checking the type of the target storage block (S210); and determining whether the target storage block is a first storage block (S230). Furthermore, step S130 may also include: when the target storage block is a first storage block (S230: Yes), selecting a first parameter. On the other hand, step S130 may also include: when the target storage block is a second storage block (S230: No), selecting a second parameter different from the first parameter.

[0098] In step S210, the control logic 39 of the semiconductor memory device 10 determines whether the target memory block is the first memory block or the second memory block based on the address received along with the command. For this purpose, the semiconductor memory device 100 may store information for identifying the first and second memory blocks.

[0099] As a result of step S230, when the target storage block is a storage block not adjacent to the contact area CTA (i.e., the first storage block) (S230: Yes), the first parameter is selected as the operating parameter (S250). The selected first parameter can be... Figure 10 It is used in the operation performed on the target storage block in step S150.

[0100] As a result of step S230, when the target storage block is a storage block adjacent to the contact area CTA (i.e., the second storage block) (S230: No), a second parameter different from the first parameter is used as an operating parameter (S270). The selected second parameter can be... Figure 10It is used in the operation performed on the target storage block in step S150.

[0101] For example, when in Figure 10 When the command received in step S110 is a programming command, Figure 11 The first and second parameters can be parameters related to the programming operation. As an example, the first and second parameters can indicate the magnitude of the programming voltage applied to the word line connected to the memory cell selected as the programming target. In this case, the magnitude of the programming voltage used in the programming operation can vary depending on whether the target memory block is the first memory block. As another example, the first and second parameters can indicate at least one of the magnitude of the programming pass voltage, the magnitude of the programming enable voltage, the magnitude of the programming disable voltage, and the magnitude of the verification voltage. Additionally, the first and second parameters can indicate various values ​​used in the programming operation.

[0102] As another example, when in Figure 10 When the command received in step S110 is a read command, Figure 11 The first and second parameters can be parameters related to the read operation. As an example, the first and second parameters can indicate the magnitude of the read voltage applied to the word line connected to the memory cell selected as the read target. In this case, the magnitude of the read voltage applied to the selected word line during data reading can vary depending on whether the target memory block is the first memory block. As another example, the first and second parameters can indicate at least one of the magnitude of the read pass voltage, the magnitude of the bit line precharge voltage, and the length of the bit line precharge time. Additionally, the first and second parameters can indicate various values ​​used in the read operation.

[0103] As another example, when in Figure 10 When the command received in step S110 is an erase command, Figure 11 The first and second parameters can be parameters related to the erase operation. As an example, the first and second parameters can indicate the erase voltage applied to the common source line connected to the memory block selected as the erase target. As another example, the first and second parameters can indicate at least one of a voltage applied to a bit line connected to the memory block selected as the erase target or an erase verification voltage. Additionally, the first and second parameters can indicate various values ​​used in the erase operation.

[0104] As described above, in the implementation, the operational performance of each of the first and second storage blocks can be maximized by applying different operating parameters used in the operation of the first storage block and the operation of the second storage block.

[0105] Figure 12This is a diagram illustrating a method for applying the purpose of the first storage block and the second storage block differently according to another embodiment of this disclosure.

[0106] Reference Figure 12 According to embodiments of the present disclosure, a semiconductor memory device may use a memory block whose target memory block is not adjacent to the contact area CTA (i.e., a first memory block) as a normal block, and a memory block whose target memory block is adjacent to the contact area CTA (i.e., a second memory block) as a system block. According to embodiments of the present disclosure, the types of data stored in the normal block and the system block are different.

[0107] For example, a first memory block comprising memory cells with a relatively wide threshold voltage distribution width can be used as a normal block for storing user data. Furthermore, a second memory block comprising memory cells with a relatively narrow threshold voltage distribution width can be used as a system block for storing system data.

[0108] As described above, user data can be data input to the memory system from outside the memory system. Furthermore, system data is data required for the operation of the semiconductor memory device and may include operating parameters required for the operation of the semiconductor memory device and management information required by the memory controller to control the operation of the semiconductor memory device. For example, system data may include any one of boot code, metadata, mapping data, and parity data.

[0109] As described above, in this embodiment, the operational stability of the semiconductor memory device can be improved by storing the system data required for the operation of the semiconductor memory device in a second memory block with higher reliability.

[0110] Figure 13 This is a diagram illustrating a semiconductor memory device according to another embodiment of the present disclosure, wherein the number of bits stored in the memory cells included in the second memory block is relatively smaller than the number of bits stored in the memory cells included in the first memory block.

[0111] Reference Figure 13According to embodiments of the present disclosure, a semiconductor memory device may use a memory block whose target memory block is not adjacent to the contact area CTA (i.e., a first memory block) as a three-level cell (TLC) block, and a memory block whose target memory block is adjacent to the contact area CTA (i.e., a second memory block) as a single-level cell (SLC) block. Therefore, three bits of data can be stored in the memory cells included in the first memory block, and one bit of data can be stored in the memory cells included in the second memory block. That is, the number of bits stored in the memory cells included in the second memory block is relatively less than the number of bits stored in the memory cells included in the first memory block. In this case, in the embodiment, by allowing fewer bits to be stored in the memory cells of the second memory block with relatively satisfactory distribution characteristics, operational performance can be further improved. As a result, in the embodiment, the second memory block can operate at a higher speed than the first memory block, and the data reliability of the second memory block is also higher than that of the first memory block.

[0112] By utilizing this characteristic, the second memory block can be used as an SLC buffer in a semiconductor memory device. When the second memory block is used as an SLC buffer, data to be stored in the first memory block is first temporarily programmed into the second memory block, and then the data in the second memory block is migrated to the first memory block. As described above, in this embodiment, the speed of programming operations using the SLC buffer can be improved when the second memory block is used as an SLC buffer.

[0113] also, Figure 13 The implementation method can be compared with Figure 12 The implementation methods are used in combination. That is, by using a second storage block as an SLC block, system data can be stored in the second storage block. In this case, high reliability of system data can be obtained in the implementation method, and the programming and reading speeds of system data can be greatly improved.

[0114] Figure 14 This is a diagram illustrating a semiconductor memory device according to another embodiment of the present disclosure, wherein the number of bits stored in the memory cells included in the second memory block is relatively greater than the number of bits stored in the memory cells included in the first memory block.

[0115] Reference Figure 14According to embodiments of the present disclosure, a semiconductor memory device may use a memory block whose target memory block is not adjacent to the contact area CTA (i.e., a first memory block) as a TLC block, and a memory block whose target memory block is adjacent to the contact area CTA (i.e., a second memory block) as a QLC block. Therefore, three bits of data can be stored in the memory cells included in the first memory block, and four bits of data can be stored in the memory cells included in the second memory block. That is, the number of bits stored in the memory cells included in the second memory block is relatively greater than the number of bits stored in the memory cells included in the first memory block. In this case, storing more bits in the memory cells of the second memory block with relatively satisfactory distribution characteristics ensures operational stability similar to that of the first memory block. As a result, in this embodiment, the storage space of the semiconductor memory device can be maximized.

[0116] Figure 15 This is a flowchart illustrating a method of operating a semiconductor memory device according to another embodiment of the present disclosure.

[0117] Reference Figure 15 A method for operating a semiconductor memory device according to another embodiment of the present disclosure may include: identifying a memory block not adjacent to a contact region CTA as a first memory block and identifying a memory block adjacent to the contact region CTA as a second memory block (S310); identifying any one of a plurality of memory blocks belonging to the second memory block as a target memory block (S320); and checking the program erase count value N of the target memory block. PE (S330); and determine the programming erase count value N. PE Is it greater than the predetermined threshold N? TH Furthermore, a method for operating a semiconductor memory device according to another embodiment of this disclosure may further include: when the programming erase count value N... PE Greater than the predetermined threshold N TH When (S340: Yes), the target memory block is converted from the second memory block to the first memory block (S350). Additionally, a method for operating a semiconductor memory device according to another embodiment of this disclosure may further include: when the program erase count value N... PE Not greater than the predetermined threshold N TH If the target storage block is maintained as the second storage block (S360) (S340: No), then the target storage block is maintained as the second storage block.

[0118] In one embodiment, step S310 can be executed when the memory system, including the semiconductor memory device 10, is turned on. In another embodiment, step S310 can be executed immediately after the semiconductor memory device 10 is manufactured. In step S310, as... Figure 9As shown, a memory block not adjacent to the contact region CTA is identified as a first memory block, and a memory block adjacent to the contact region CTA is identified as a second memory block. After performing step S310, information identifying the first and second memory blocks can be generated. This information can be stored in the semiconductor memory device 10 or in a memory controller external to the semiconductor memory device 10. In some embodiments, a memory block not adjacent to the contact region CTA may be initially identified as a second memory block, and a memory block adjacent to the contact region CTA may be initially identified as a first memory block. Therefore, in some embodiments, regardless of its physical location relative to the contact region CTA, a memory block can be arbitrarily identified as either a first or a second memory block.

[0119] When the memory controller sends a specific command to the semiconductor memory device 10, step S320 can be executed. In this case, when the memory block to which the specific command is applied corresponds to a second memory block, the memory block can be determined as the target memory block. That is, when a specific operation (e.g., erase operation, programming operation, or read operation) is performed on the second memory block, the selected second memory block can be determined as the target block to determine whether the target memory block is converted into the first memory block.

[0120] In another implementation, step S320 can be executed periodically regardless of the command. In this case, step S320 can be executed on the second memory block when the semiconductor memory device 10 is in an idle state. That is, during the idle time of the semiconductor memory device 10, a monitoring operation can be sequentially performed on the second memory block. Through the monitoring operation, it can be determined whether each of the second memory blocks included in the semiconductor memory device 10 has been converted into a first memory block.

[0121] In step S330, the program erase count value N of the target storage block is checked. PE Program the erase counter value N. PE This can be a value indicating how many programming or erasing operations are performed after the semiconductor memory device 10 is manufactured. A programming / erasing count value N is determined for each memory block. PE Therefore, the semiconductor memory device 10 can store the program-erase count value N of each memory block. PE In another embodiment, the storage controller may store individual programmable erase count values ​​N for each storage block. PE .

[0122] As a result of step S340, when the programming erase count value N is determined... PE Greater than threshold N THThis means that a relatively large number of programming or erasing operations are performed on the corresponding target memory block, which is the second memory block. Therefore, the characteristics of the memory cells in the target memory block are expected to deteriorate. Therefore, the target memory block is converted into the first memory block (S350). After executing step S350, the information identifying the first and second memory blocks can be updated.

[0123] As a result of step S340, when the programming erase count value N is determined... PE Not greater than threshold N TH This means that relatively few programming or erasing operations are performed on the corresponding target memory block, which is the second memory block. Therefore, the characteristics of the memory cells in the target memory block are not yet degraded. Thus, the target memory block is maintained as the second memory block (S360).

[0124] Figure 16 This is a block diagram illustrating the configuration of a memory system 1100 according to an embodiment.

[0125] Reference Figure 16 The memory system 1100 includes a memory device 1120 and a memory controller 1110.

[0126] The memory device 1120 may be a multi-chip package configured with multiple flash memory chips. As an embodiment, the memory device 1120 may include a memory cell array, bit lines connected to the memory cell array, and a first upper line and a second upper line that overlap with and are spaced apart from the bit lines by different distances.

[0127] The storage controller 1110 may be configured to control the memory device 1120 and may include a static random access memory (SRAM) 1111, a CPU 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 serves as the operating memory for the CPU 1112, which performs overall control operations on data exchange with the storage controller 1110. The host interface 1113 includes a data exchange protocol for a host connected to the memory system 1100. The error correction block 1114 detects and corrects errors included in data read from the memory device 1120. The memory interface 1115 performs interfacing with the memory device 1120. Additionally, the storage controller 1110 may also include a read-only memory (ROM) or similar storage for code data used for interfacing with the host.

[0128] The aforementioned memory system 1100 may be a memory card or a solid-state drive (SSD), wherein the memory device 1120 and the storage controller 1110 are combined. For example, when the memory system 1100 is an SSD, the storage controller 1110 may communicate with an external (e.g., a host) via one of various interface protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-E), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0129] In one embodiment, information identifying whether each of the plurality of memory blocks in the memory device 1120 is a first memory block or a second memory block can be stored in the memory device 1120. In another embodiment, information identifying whether each of the plurality of memory blocks is a first memory block or a second memory block can be stored in the memory controller 1110. In this case, the information can be stored in SRAM 1111.

[0130] Figure 17 This is a block diagram illustrating the configuration of the computing system 1200 according to an embodiment.

[0131] Reference Figure 17 The computing system 1200 may include a CPU 1220, random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. When the computing system 1200 is a mobile device, it may also include a battery for supplying operating voltage to the computing system 1200, and may also include an application chipset, a camera image processor (CIS), mobile DRAM, etc.

[0132] Memory system 1210 may include memory device 1212 and memory controller 1211. In one embodiment, information identifying whether each of a plurality of memory blocks in memory device 1212 is a first memory block or a second memory block may be stored in memory device 1212. In another embodiment, information identifying whether each of a plurality of memory blocks in memory device 1212 is a first memory block or a second memory block may be stored in memory controller 1211. In yet another embodiment, information identifying whether each of a plurality of memory blocks in memory device 1212 is a first memory block or a second memory block may be stored in memory system 1210. For example, this information may be stored in RAM 1230 of computing system 1200.

[0133] Cross-references to related applications

[0134] This application claims priority to Korean Patent Application No. 10-2021-0133230, filed on October 7, 2021, with the Korean Intellectual Property Office, the full disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: Multiple storage blocks are arranged sequentially in a first direction, and each of the multiple storage blocks includes multiple memory cells; as well as A contact area is formed between the plurality of storage blocks. Among these, the first storage block that is not adjacent to the contact area and the second storage block that is adjacent to the contact area operate based on different operating parameters, and The first storage block, which is not adjacent to the contact area, is adjacent to two other storage blocks.

2. The semiconductor memory device according to claim 1, further comprising: Bit lines are disposed on the plurality of memory blocks and the contact area; as well as A logic circuit is disposed below the plurality of memory blocks and the contact area.

3. The semiconductor memory device according to claim 2, wherein, The logic circuit includes peripheral circuitry that performs operations on a selected memory block among the plurality of memory blocks, and when the selected memory block is the first memory block, the peripheral circuitry uses a first parameter during the operation, and when the selected memory block is the second memory block, the peripheral circuitry uses a second parameter different from the first parameter during the operation.

4. The semiconductor memory device according to claim 3, wherein, The operation is a programming operation, and The first parameter and the second parameter indicate the voltage values ​​used in the programming operation of the selected memory block.

5. The semiconductor memory device according to claim 3, wherein, The operation is a read operation, and The first parameter and the second parameter indicate the voltage values ​​used in the read operation of the selected memory block.

6. The semiconductor memory device according to claim 3, wherein, The operation is an erasing operation, and The first parameter and the second parameter indicate the voltage values ​​used in the erase operation on the selected storage block.

7. The semiconductor memory device according to claim 1, wherein, User data is stored in the first storage block, and system data is stored in the second storage block.

8. The semiconductor memory device according to claim 7, wherein, The system data includes parameters used in the operation of the plurality of storage blocks.

9. The semiconductor memory device according to claim 7, wherein, The system data includes any one of the following: boot code, metadata, mapping data, or parity data.

10. The semiconductor memory device according to claim 1, wherein, N bits are stored in the memory cells included in the first memory block, and M bits are stored in the memory cells included in the second memory block. Where N is a natural number greater than 0, and M is a natural number greater than N.

11. The semiconductor memory device according to claim 1, wherein, N bits are stored in the memory cells included in the first memory block, and M bits are stored in the memory cells included in the second memory block. Where M is a natural number greater than 0, and N is a natural number greater than M.

12. The semiconductor memory device according to claim 1, wherein, When the program erase count of the second storage block exceeds a predetermined threshold, the second storage block operates using the same operating parameters as the first storage block.

13. A method of operating a semiconductor memory device, the method comprising the following steps: Distinguish between the storage blocks that are the first storage blocks and are not adjacent to the contact area, and the storage blocks that are the second storage blocks and are adjacent to the contact area. Select any one of the storage blocks belonging to the second storage block as the target storage block; Check the program erase count value of the target storage block; as well as When the program erase count value is greater than a predetermined threshold, the target storage block is converted into the first storage block. The first storage block and the second storage block are arranged sequentially along a first direction and operate based on different operating parameters.

14. The method of claim 13, further comprising the step of: When the program erase count value is not greater than the predetermined threshold, the target storage block is maintained as the second storage block.

15. A semiconductor memory device, the semiconductor memory device comprising: Multiple storage blocks are arranged sequentially in a first direction, and each of the multiple storage blocks includes multiple memory cells; as well as A contact area is formed between the plurality of storage blocks. Wherein, a first operating parameter is used for a first operation on a first storage block spaced apart from the contact area, and a second operating parameter is used for a second operation on a second storage block adjacent to the contact area, wherein the first operating parameter is different from the second operating parameter, and the first operation and the second operation are the same. The first storage block, which is spaced apart from the contact area, is adjacent to the two storage blocks.

16. The semiconductor memory device according to claim 15, wherein, The first operation and the second operation are at least one of a read operation, an erase operation, and a program operation.

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