Apparatus system and method for automatic soft package post repair

Abstract

Embodiments of the present disclosure relate to apparatuses, systems, and methods for automatic soft package post repair (ASPPR). A memory can receive a row address and a signal indicating an ASPPR operation, such as setting a bad page flag. A word line engine generates a physical address based on the row address, and an ASPPR register stores the physical address. The time taken from receiving the row address to storing the physical address can be within the timing (e.g., tRAS) of an access operation to the memory. The row address can specify a single page of information. If the bad page flag is set, a subsequent PPR operation can blow a fuse to encode the physical address stored in the ASPPR register.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more specifically, to semiconductor memory devices. In particular, this disclosure relates to memory, such as dynamic random access memory (DRAM). Background Technology

[0002] Information can be stored in memory cells, which can be organized into rows (word lines) and columns (bit lines). At various points in the manufacture and use of the memory device, one or more memory cells may fail (e.g., become unable to store information, become inaccessible by the memory device, etc.) and may require repair.

[0003] Memory devices can perform repair operations row by row. Rows containing faulty memory cells can be identified (also referred to as defective rows, bad rows, or erroneous rows). Memory devices may contain additional memory rows (also referred to as redundant rows) that can be used in the repair operation. During the repair operation, the address associated with the defective row can be redirected so that the address instead points to the redundant row. Some repairs may be performed after the device is packaged (e.g., in-chip, on-device, etc.). These repairs can often be quite time-consuming and may be difficult if the memory can remap the relationship between addresses and word lines. Temporary repairs may be required for fast and specific word lines for specific pages (e.g., logical addresses). Summary of the Invention

[0004] According to one embodiment of this disclosure, a method is provided. The method includes: accessing a memory row in a first time interval; and performing an Automatic Soft Packaging Repair (ASPPR) operation in a second time interval, wherein the second time interval is equal to or shorter than the first time interval. The ASPPR operation includes: receiving a row address and a bad page signal; generating a physical address based on the received row address using a word line engine; and storing the physical address in an ASPPR register in response to the bad page signal.

[0005] According to another embodiment of this disclosure, an apparatus is provided. The apparatus includes: a memory array including a plurality of word lines and redundant word lines; a word line engine configured to receive row addresses and generate physical addresses based on the row addresses, wherein the row addresses specify a single page; and automatic soft-pack repair (ASPPR) circuitry configured to store the physical addresses in response to setting a bad page flag in a mode register.

[0006] According to another embodiment of this disclosure, a system is provided. The system includes: a controller configured to provide a row address, a row activation command, and a bad page signal as part of an Automatic Package Post-Repair (ASPPR) operation; and a memory. The memory includes: an address latch configured to latch the row address in response to the row activation command; a word line engine configured to translate the row address into a physical address; and ASPPR circuitry configured to store the physical address in response to the row activation command and a bad page flag set in response to the bad page signal. Attached Figure Description

[0007] Figure 1 This is a block diagram of a semiconductor device according to at least some embodiments of the present disclosure.

[0008] Figure 2 This is a block diagram of a memory system according to some embodiments of the present disclosure.

[0009] Figure 3 This is a schematic diagram of ASPPR logic according to some embodiments of the present disclosure.

[0010] Figure 4 This is a flowchart of operations in a memory according to some embodiments of the present disclosure. Detailed Implementation

[0011] The following description of certain embodiments is exemplary in nature and is in no way intended to limit the scope of this disclosure or its application or use. In the following detailed description of embodiments of the systems and methods of the invention, reference is made to the accompanying drawings, which form a part of this document, and to specific embodiments in which the described systems and methods can be practiced by means of the description. These embodiments are described in sufficient detail to enable those skilled in the art to practice the currently disclosed systems and methods, and it should be understood that other embodiments may be utilized, and structural and logical changes may be made without departing from the spirit and scope of this disclosure. Furthermore, for clarity, detailed descriptions of certain features will not be elaborated where they would be obvious to those skilled in the art, so as not to obscure the description of embodiments of this disclosure. Therefore, the following detailed description should not be construed in a limiting sense, and the scope of this disclosure is defined only by the appended claims.

[0012] Semiconductor memory devices can store information across multiple memory cells. Information can be stored as binary code, and each memory cell can store a single information bit as either logic high (e.g., "1") or logic low (e.g., "0"). Memory cells can be organized at the intersection of word lines (rows) and bit lines (columns). The memory can be further organized into one or more memory banks, each of which can contain multiple rows and columns. During operation, the memory device can receive commands and specify addresses for one or more rows and one or more columns, and then execute the commands on memory cells at the intersection of the specified rows and columns (and / or along the entire row / column). Data associated with a single logical row address can also be called a page. The memory can contain logic that maps logical addresses (e.g., row, column, and bank addresses) to physical addresses (e.g., word lines, bit lines, and bank). Some memories may use wear leveling and periodically change the mapping of logical and physical addresses to redistribute access operations among physical memory cells.

[0013] Some memory cells may be defective, and rows containing defective memory cells may be broadly referred to as defective rows (or bad rows or error rows). Defective rows may not be able to store or retain information and / or may additionally become inaccessible to the memory device. In some cases, the memory may become defective (and / or identifiable as defective) after the memory device has been packaged (e.g., sealed in a chip package). The memory device may undergo one or more types of post-package repair (PPR) operations to resolve defective rows.

[0014] For example, a memory bank may generally contain multiple additional rows of memory, which may be broadly referred to as redundant rows. During a repair operation, the row address associated with the defective row may be redirected so that it is instead associated with one of the redundant rows. In some operating modes, the repair operation may be a hard (or permanent) repair operation, in which the updated row address information is stored in memory in a non-volatile form (e.g., in a manner that is maintained even when the memory device is powered off). For example, a memory device may contain a fuse array, which may contain fuses (and / or antifuses) that may have a state that can be permanently changed (e.g., when a fuse / antifuse “blows”). For the sake of brevity, the term “fuse” as used herein may be understood to include any non-volatile memory element, such as a fuse, antifuse, etc. The state of the fuses in the fuse array can partially determine which addresses are associated with which memory rows.

[0015] During a soft PPR operation (SPPR operation), non-volatile elements can be used to track repairs. The address of the row to be repaired can be stored in a non-volatile element (e.g., latch circuitry) such that information that should be directed to the row to be repaired is instead directed to a redundant row. In some embodiments, SPPR latches may each be associated with a designated redundant row. In some embodiments, SPPR circuitry may scan to locate open redundant rows and may assign each defective address to an open redundant row. The SPPR process may allow for temporary repairs prior to permanent repairs (e.g., for testing purposes). However, in some devices (e.g., those using wear leveling), SPPR operations can be problematic. For example, the process of loading SPPR addresses can be relatively slow, and situations may arise where the device changes the logic-to-physical address mapping between receiving the logical address of a defective row and performing a soft repair to remap access on the physical word line. Therefore, a relatively fast and automatic SPPR operation is needed to capture the physical address (e.g., word line) to be repaired.

[0016] This disclosure generally relates to Automated Soft Post-Packaging Repair (ASPPR). A controller can monitor the memory to locate defective pages of data (e.g., data associated with a single logical row address). The controller can provide row addresses and defective page commands. Defective page commands can utilize existing communication architectures. For example, the controller can provide row addresses and row activation commands via a command / address (CA) bus, and also provide a defective page flag that can be set in a mode register of the memory. Setting the defective page flag indicates that the address provided along the bus is for ASPPR operation and not for access. The logical address can be provided along a normal address bus through the memory to the bank logic, which includes a word line engine that translates the received logical address into a physical address. The physical address can be stored in an ASPPR register. Because the physical address (rather than the logical address) is saved, the appropriate physical address associated with the defective word line will be preserved even if the relationship between the physical and logical addresses is remapped (e.g., as part of wear leveling). If a subsequent hard repair is performed and the bad page flag is set, indicating that an ASPPR operation was previously performed, the physical address stored in the ASPPR register can be used for the hard repair (e.g., by fusing one or more fuses based on the stored physical address). The bad page flag can be reset after the PPR operation.

[0017] Using a standard CA bus and row address bus in memory allows physical addresses to be saved to ASPPR (e.g., via fuse logic scan operations) much faster than loading SPPR addresses in the conventional way. For example, loading a word address into an ASPPR latch may take approximately the same amount of time as, or less than, a normal access operation (e.g., the timing of tRAS). In some embodiments, data from a faulty word line can be rewritten to a redundant word line, which can help retain data in memory.

[0018] Figure 1 This is a block diagram of a semiconductor device according to at least some embodiments of the present disclosure. Semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

[0019] Semiconductor device 100 includes memory array 118. Memory array 118 is shown as containing multiple memory banks. Figure 1 In one embodiment, the memory array 118 is shown to include eight memory banks BANK0 to BANK7. In other embodiments, the memory array 118 may include more or fewer memory banks. Each memory bank includes multiple word lines WL, multiple bit lines BL and / BL, and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BL and / BL. The selection of word lines WL is performed by the row decoder 108, and the selection of bit lines BL and / BL is performed by the column decoder 110. Figure 1 In this embodiment, row decoder 108 includes a corresponding row decoder for each memory bank, and column decoder 110 includes a corresponding column decoder for each memory bank. Bit lines BL and / BL are coupled to corresponding sense amplifiers (SAMPs). Read data from bit lines BL or / BL is amplified by the sense amplifier SAMP and transmitted to read / write amplifier 120 via complementary local data line (LIOT / B), transmission gate (TG), and complementary main data line (MIOT / B). Conversely, write data output from read / write amplifier 120 is transmitted to the sense amplifier SAMP via complementary main data line MIOT / B, transmission gate TG, and complementary local data line LIOT / B, and written to the memory cell MC coupled to bit line BL or / BL.

[0020] The device also includes a fuse array 125 containing multiple non-volatile memory elements (fuses) that can store address-related information in a memory array 118. Each fuse can start from a first state (e.g., an anti-fuse can be insulating) and can "blow" to permanently change the state of the fuse (e.g., a blown anti-fuse can be conductive). Each fuse can be considered as a bit, which is in a state before it blows and permanently in a second state after it blows. For example, a fuse can represent a logic low before it blows and a logic high after it blows.

[0021] A specific group of fuses may be represented by a fuse group address (FBA), which specifies the physical location of each fuse in the group within fuse array 125. A group of fuses associated with a specific FBA may act as a row repair element (RRE). An RRE can be encoded with the row address to be repaired (e.g., by fusing the fuses to encode a binary string of the row address). An RRE may be associated with a specific redundant row of memory array 118. Address information in fuse array 125 may be 'scanned' out along fuse buses (FB and xFB) 128 to row latches 119. Each row latch 119 may be associated with a specific word line of memory array 118. In some embodiments, only redundant rows of memory array 118 (e.g., rows designated for repair operations) may be associated with one of the row latches 119. An address stored in a given RRE may be scanned out along fuse bus 128 from fuse array 125 and may be latched by a specific row latch 119. In this way, an address stored in the RRE of fuse array 125 can be associated with a specific row of memory array 118. An address stored in row latch 119 can then direct access commands to the word line associated with row latch 119. Therefore, programming a row address into the RRE of fuse array 125 can correct the row address by reallocating it to redundant word lines.

[0022] Fuse logic circuitry 126 may be located along fuse bus 128. Fuse logic circuitry 126 may include post-package repair (PPR) circuitry (e.g., hard PPR circuitry) which may be used to modify fuse array 125 after the memory device 100 is packaged (e.g., packaged in a chip). For example, the PPR circuitry may perform hard repair, wherein fuses in the RREs of fuse array 125 are blown to 'repair' rows by permanently encoding the repaired row address into the RREs in fuse array 125. Fuse logic circuitry 126 may also include soft PPR circuitry (SPPR circuitry) (not shown) which includes volatile memory elements that can be used to perform non-permanent repair. Fuse logic circuitry 126 may monitor data along fuse bus 128 and may selectively modify data based on addresses stored in the SPPR circuitry to provide a modified fuse bus xFB.

[0023] The semiconductor device 100 may use multiple external terminals, including: a command and address (C / A) terminal coupled to a command and address bus to receive commands and addresses; a clock terminal for receiving clock CK and / CK; a data terminal DQ for providing data; and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0024] An external clock CK and / or CK is supplied to the clock terminals, and this external clock is provided to input circuitry 112. Input circuitry 112 generates an internal clock ICLK based on the CK and / or CK clock. The ICLK clock is provided to command decoder 110 and internal clock generator 114. Internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used for timing operations of various internal circuits. The internal data clock LCLK is provided to input / output circuitry 122 to time the operation of circuits contained within input / output circuitry 122, for example, to a data receiver to time the reception of written data.

[0025] The C / A terminal can be supplied with a memory address. The memory address supplied to the C / A terminal is passed to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder 108 and the decoded column address YADD to the column decoder 110. The address decoder 104 can also supply a decoded bank address BADD, which indicates a bank in the memory array 118 containing the decoded row address XADD and column address YADD. Commands can be supplied to the C / A terminal. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory, such as read commands for performing read operations and write commands for performing write operations, and other commands and operations. Access operations are typically accompanied by a row activation command ACT. Access commands can be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD indicating the memory cell to be accessed.

[0026] Commands can be provided as internal command signals to command decoder 106 via command / address input circuitry 102. Command decoder 106 includes circuitry for decoding the internal command signals to generate various internal signals and commands for performing operations. For example, command decoder 106 can provide row command signals for selecting word lines and column command signals for selecting bit lines.

[0027] Device 100 can receive access commands as row activation commands ACT. When the row activation command ACT is received, the device promptly supplies the row activation command ACT to the memory address BADD and the row address XADD.

[0028] Device 100 can receive access commands as read commands. When a read command is received, read data is read from the memory cell in memory array 118 corresponding to row address XADD and column address YADD, provided in a timely manner with the read command. For example, a row decoder can access the word line associated with a row latch 119 having an address matching XADD. The read command is received by command decoder 106, which provides an internal command to provide read data from memory array 118 to read / write amplifier 120. Row decoder 108 can match address XADD to the address stored in row latch 119 and then access the physical row associated with row latch 119. The read data is output to the outside via input / output circuitry 122 from data terminal DQ.

[0029] Device 100 can receive access commands as write commands. When a write command is received and the bank address BADD and column address YADD are supplied in a timely manner along with the write command, write data supplied to the data terminal DQ is written to the memory cells in memory array 118 corresponding to the row address and column address. The write command is received by command decoder 106, which provides an internal command to cause the write data to be received by the data receiver in input / output circuit 122. Row decoder 108 can match address XADD with the address stored in row latch 119 and then access the physical row associated with row latch 119. A write clock can also be provided to an external clock terminal for timing the data receiver of input / output circuit 122 to receive the write data. The write data is supplied to read / write amplifier 120 via input / output circuit 122 and to memory array 118 via read / write amplifier 120 for writing into memory cell MC.

[0030] Apparatus 100 includes ASPPR circuitry 130, which can be used to perform ASPPR operations quickly and automatically. ASPPR operations can replace and / or supplement any other form of ASPPR operation that fuse logic 126 can perform. ASPPR circuitry 130 includes a plurality of ASPPR registers for storing addresses used for repair. Each ASPPR register can be associated with a redundancy line. In some embodiments, these redundancy lines are reserved for ASPPR operations and cannot be used for other types of repair operations.

[0031] The ASPPR register stores physical addresses associated with specific word lines, rather than logical addresses (e.g., XADD). Each stored physical address can be a row address XADD based on the data value of a single page (e.g., data along a single word line). The word line engine can translate the received logical address XADD into a physical address PA that can be stored in the ASPPR register. Subsequently, when accessing a row address XADD, the row address is translated into a physical address and compared with the stored physical address. If a match is found, an ASPPR match signal is provided. In response to an ASPPR match, the redundant row associated with the ASPPR register is accessed by the row decoder 108, instead of any word line previously associated with the physical address.

[0032] In some embodiments, when performing an ASPPR operation, data can be copied from a word line previously associated with a physical address to a redundant word line associated with the ASPPR register.

[0033] The address to be repaired can be loaded into the ASPPR register via a standard C / A bus. For example, the controller can provide the address XADD and the ACT signal, and can also write ASPPR flags (e.g., bad page flags) into mode register 132. The ASPPR flags can indicate that the address XADD is expected to be a row to be repaired as part of the ASPPR operation, rather than for access. The row address XADD can be automatically translated into a physical address, and the physical address can be loaded into an available ASPPR register. The ASPPR flags (or different ASPPR flags) can be set in mode register 132 to indicate that ASPPR repair should be performed. For example, multiple memory-specific ASPPR flags can exist, each ASPPR flag indicating that ASPPR repair should be performed in one of the memory banks of memory device 100.

[0034] If a subsequent PPR operation is performed and one or more ASPPR flags are set, the address (e.g., physical address PA) stored in the ASPPR register can be provided to the fuse logic, which can then perform the PPR operation based on the stored PA. This can be useful in situations where the mapping between logical and physical addresses changes over time (e.g., adjustments for wear leveling). This also allows the controller to automatically perform the PPR operation by providing a PPR signal and allowing memory device 100 to repair the address already stored in the ASPPR register.

[0035] Power supply potentials VDD and VSS are supplied to the power supply terminals. These potentials VDD and VSS are then supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VOD, VARY, VPERI, etc., based on the power supply potentials VDD and VSS supplied to the power supply terminals. Internal potential VPP is primarily used in the line decoder 108, internal potentials VOD and VARY are primarily used in the sense amplifier SAMP included in the memory array 118, and internal potential VPERI is used in many peripheral circuit blocks.

[0036] Power potentials VDDQ and VSSQ are also supplied to the power terminals. These power potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In embodiments of this disclosure, the power potentials VDDQ and VSSQ supplied to the power terminals may be the same as the power potentials VDD and VSS supplied to the power terminals. In another embodiment of this disclosure, the power potentials VDDQ and VSSQ supplied to the power terminals may be different from the power potentials VDD and VSS supplied to the power terminals. The power potentials VDDQ and VSSQ supplied to the power terminals are used in the input / output circuit 122 to prevent power supply noise generated by the input / output circuit 122 from propagating to other circuit blocks.

[0037] Figure 2 This is a block diagram of a memory system according to some embodiments of the present disclosure. System 200 includes a controller 202 for operating memory 204. In some embodiments, memory 204 may be Figure 1 An embodiment of the memory device 100. Certain components in Figure 2 This is presented as part of a discussion of the ASPPR circuit and its operation.

[0038] Memory array 220 (e.g., Figure 1 The memory array 118) includes multiple word lines WL0 to WLN and multiple redundant word lines RWL0 and RWLM. Although Figure 2 Not shown, but the memory array 220 can be arranged as a storage bank, with each memory having its own word line and a set of redundant word lines. Each word line can be associated with a physical address specifying that word line (e.g., PA0 to PAN). The word line engine 212 receives, for example, a logical address of XADD and uses an internal mapping to provide the physical address PA currently associated with the row address XADD. For example, if the row address XADD is associated with the first word line WL0, the word line engine 212 can provide the physical address PA0.

[0039] The relationship between logical and physical addresses can be changed. For example, word line engine 212 can remap logical and physical address relationships to improve wear leveling in memory array 220. Thus, during a first access operation, row address XADD can be associated with first physical address PA0 and therefore with first word line WL0. During a second access operation (e.g., after wear leveling has been performed), the same row address XADD can be associated with second physical address PA2 and therefore with second word line PA2.

[0040] The controller 202 can perform access operations on the memory 204 by providing, for example, an address such as a row address XADD and various other commands such as a row activation command ACT. For example, the controller 202 can provide write data along a data terminal and a row address XADD. The command address circuit 210 provides the address to the word line engine 212, which translates the address XADD into a physical address PA, which the row decoder 222 uses to activate the corresponding word line.

[0041] Controller 202 may include fault detection circuitry 206 for locating defective word lines. For example, the fault detection circuitry may test a word line by writing test data to an address, reading data from said address, and then comparing the written and read data. If any discrepancy exists, the address can be identified as defective and, as part of an ASPPR operation, provided to memory 204. Controller 202 may operate according to a logical address, such as XADD, where the defect is located in a specific physical word line associated with a physical address PA. Memory 204 may undergo wear leveling, where the relationship between logical and physical addresses changes. Therefore, if fault detection circuitry 206 determines that a specific address is faulty, it may be important to save the physical address associated with the error as quickly as possible before the relationship between logical and physical addresses changes.

[0042] As part of the ASPPR operation, controller 202 can provide the identified defective address XADD, as well as various signals indicating that address XADD is part of the ASPPR operation. For example, address XADD, along with row activation signal ACT and ASPPR signal ASPPR, can be provided to CA input circuit 210 (e.g., along the standard command / address (CA) bus). Figure 1 (102). In some embodiments, the ASPPR signal can be provided to the mode register to set the flag PPR_Alert. The ASPPR signal can be used to set the flag because it can be used later to instruct memory 204 to perform an ASPPR operation. Figure 2In some embodiments, the signal ASPPR is provided and the flag PPR_Alert is set in response to the signal. In some embodiments, the controller 202 may set the flag PPR_Alert to the ASPPR signal (e.g., by performing a mode register write operation). In some embodiments, the controller 202 may provide the ASPPR signal and the memory 204 may manage the state of the PPR_Alert flag. Multiple PPR_Alert flags may exist, for example, one for each memory bank of the memory array 220. Each PPR_Alert flag may be associated with a different ASPPR operation.

[0043] Upon receiving address XADD, CA circuit 210 provides the address to word line engine 212, which translates address XADD into physical address PA. This process can be similar to normal access operations, and the timing can be partially controlled by the row activation signal ACT. In response to the ASPPR signal (and / or setting the PPR_Alert flag), ASPPR register 218 can store the physical address PA. Each stored PA is associated with a redundant word line. In some embodiments, redundant word lines may exist in each memory bank reserved for ASPPR repair.

[0044] The physical address PA, associated with the defective word line and identified by controller 202 via row address XADD, can be loaded into ASPPR register 218 within the timing allowed for normal access operations. For example, the timing between controller 202 providing address XADD and storing address PA in ASPPR register 218 can be within timing tRAS or less. This helps ensure that the relationship between row address XADD identified by controller 202 and PA specifying the defective word line is maintained until the physical address PA is stored in memory 204.

[0045] During subsequent access operations, controller 202 can provide a row address XADD associated with the access operation, which word line engine 212 can translate into a physical address PA, which in turn indicates which word line of memory array 220 the row decoder 222 can access. ASPPR register 218 can compare the physical address from the word line engine with the stored physical addresses PA0 to PAk (if no ASPPR and / or PPR operations are performed). If a match is found, ASPPR register 218 provides a match signal ASPPR Match. The ASPPR Match signal can override other memory operations and can indicate that the current physical address PA was previously repaired as part of an ASPPR operation. In response to the ASPPR Match signal, row decoder 222 can access the redundant row associated with the ASPPR register stored at address PA. The ASPPR Match signal can override other signals, such as row access signals and other redundant signals (e.g., repairs based on fuse array 214 and fuse logic 216), to directly access the redundant word line associated with the ASPPR register.

[0046] In some embodiments, when the row address PA is saved to the ASPPR register, information (e.g., an information page) saved on the word line associated with PA can be copied to a redundant word line associated with the ASPPR register to which the address is saved. In this way, data in the information page can be saved. In some embodiments, data repair (e.g., using ECC circuitry) can be performed while data is being copied because the previous word line was defective. In some embodiments, data can be copied as is and repaired later.

[0047] In some embodiments, the row address XADD can specify a single information page. Therefore, the stored physical address PA can specify a single information row. This limits the amount of time the memory needs to access redundant word lines.

[0048] After an ASPPR operation has been performed, controller 202 may decide to perform a PPR operation (e.g., a hard PPR or hPPR operation) to encode the repairs in ASPPR register 218 in a non-volatile format. Since controller 202 does not know which physical addresses are stored in ASPPR register 218, it may rely on ASPPR register 218 to specify which repairs to perform. As part of the PPR operation, controller 202 provides a PPR signal. If any PPR_Alert flag is set in mode register 208, indicating that at least one ASPPR operation has been performed, one or more physical addresses PA can be provided from ASPPR register 218 to fuse logic 216. Fuse logic 216 can then blow fuses in fuse array 214 to encode the repairs of those physical addresses in a non-volatile format. As part of the PPR operation, the PPR_Alert flag can be cleared, and the stored physical addresses can be deleted from ASPPR register 218. This allows subsequent ASPPR repairs.

[0049] Once repair has been performed in fuse array 214, fuse logic 216 can receive the physical address PA from word line engine 212 as part of the access operation. If the physical address matches the repaired address stored in fuse array 214, fuse logic 216 can provide a match signal. In response to the match, line decoder 222 can access redundant word lines (unless the ASPPR Match signal is provided, in which case the accessed word line is associated with the ASPPR register).

[0050] Figure 3 This is a schematic diagram of ASPPR logic according to some embodiments of the present disclosure. In some embodiments, ASPPR logic 300 may be included in... Figure 1 The memory device 100 and / or Figure 2 In memory 204. ASPPR logic 300 can be broadly similar to that relative to Figure 2 The memory 204 describes the components and operations. ASPPR logic 300 illustrates how different components can be partitioned between the channel logic region 310 and the bank logic region 320 of the memory. The bank logic region 320 may contain repeating components for each different bank. Therefore, although a single bank logic region 320 is shown (in this case, Bank), <0> This is a collection of components and logic circuits (e.g., memory address latch 322, word line engine 324, and ASPPR register 326), but each of these components may be repeated for each memory bank. For the sake of brevity, the operation will be described relative to a single memory bank.

[0051] Channel logic region 310 includes mode register 312 (e.g., Figure 1 132 and / or Figure 2 208), command address circuit 314 (e.g., Figure 1 102 and / or Figure 2 210), multiplexer 316, and fuse logic 318 (e.g., Figure 1 126 and / or Figure 2 (216). The mode register contains various storage elements that store settings and adjustable values ​​related to memory operation. The controller (and / or the memory itself) can set various values ​​in the mode register 312 to manage memory operation. Specifically, the mode register 312 contains one or more PPR_Alert flags that can indicate that an ASPPR operation is being performed when it is set, and can indicate that an ASPPR operation has been performed before it is held. A PPR_Alert signal reflecting the state of the PPR_Alert flag can be provided to the memory bank logic area 320. In embodiments where each flag is associated with a given memory bank, a signal associated with the flag can be provided to the memory bank area associated with the flag. The mode register 312 also contains a PPR register that can be set to provide a PPR signal indicating that a PPR operation is being performed.

[0052] CA circuit 314 provides row activation command ACT and logical address LA (e.g., ...). Figures 1 to 2 (XADD). The activation signal ACT can be a multi-bit signal, where each bit is associated with a different memory bank. Therefore, each bit of ACT can be provided to the receiving ACT. <0> Different memory bank regions, such as memory bank region 320. The logical address LA can also be a multi-bit signal, which can be full-length (e.g., 16 bits) specifying a single information page (e.g., data along a single word line). The logical address LA is provided to memory bank region 320.

[0053] The memory bank region 320 includes a memory bank address latch 322 that stores a logical address received along the address bus during access to the memory bank. For example, when an activation signal associated with the memory bank (e.g., ACT) is triggered... <0> When the memory address latch 322 becomes active, it can capture the logical address LA. The memory address latch 322 provides the latched logical address LA to the word line engine 324, which translates the logical address LA into a physical address PA. The physical address PA can also be a multi-bit signal, but it can be linked to a specific word line (relative to the latched address LA of a specified data page, and the word line associated with it can be changed).

[0054] The physical address PA is provided to the ASPPR register 326 in response to the signal ACT. <0> The physical address PA is stored by the PPR_Alert flag signal from the mode register 312. The PPR_Alert flag signal can also be memory-specific. In some embodiments, the mode register may provide the PPR_Alert signal to the memory 320 only when the flag is first set as part of the ASPPR operation, and may not continue to provide the signal even if the flag remains set.

[0055] ASPPR register 326 can continue to receive physical address PA and row activation signal ACT. <0> As part of normal access operations, when the PPR_Alert signal is inactive (e.g., no ASPPR operation is being performed), the ASPPR register 326 can compare the physical address PA with a previously stored physical address, and provide the ASPPR Match signal if a match exists between the received PA and one of the stored PAs. In some embodiments, the ASPPR register 326 may store only a single address (e.g., one ASPPR address per memory bank). Each stored address may be associated with a specific redundant row of the memory bank. In response to the ASPPR Match signal, the row decoder may access the redundant row instead of any row previously associated with the address PA. In some embodiments, if the memory bank has more than one ASPPR redundant row, the ASPPR Match signal may indicate which redundant row to access.

[0056] When the PPR mode register is enabled, the memory can enter PPR mode. Mode register 312 provides the PPR signal. In response to the PPR signal, ASPPR registers 326 in one or more memory banks provide the physical address PA they store. A multiplexer can pass the logical address LA to fuse logic 318 without setting the bad page flag, indicating that no PA is stored in the ASPPR register (e.g., logical address LA can therefore be stored in fuse logic 318), and can pass the physical address PA from ASPPR register 326 during a PPR operation. During a PPR operation, if any PPR_Alert flag is set in mode register 312, indicating a previous ASPPR operation, fuse logic 318 can write temporary repairs from ASPPR register 326 to the fuse array to make these repairs permanent.

[0057] Figure 4 This is a flowchart of operations in a memory according to some embodiments of the present disclosure. Method 400 may be performed by relative to... Figures 1 to 3 The implementation of any or all of the components described.

[0058] Method 400 includes step 405, which describes a memory in a power-off state. The memory may remain in a power-off state (e.g., standby) until a power-on signal is received, which moves the memory to a state 410 describing normal memory operation. During normal memory operation, the controller (e.g., Figure 2 (202) The memory can be accessed, for example, by providing commands and addresses across the CA bus. Block 415 describes a power-down command that can return the memory to state 405. When the memory is powered off, repairs performed in a non-volatile manner (e.g., hard repairs), such as those programmed in the fuse array, can be retained. Meanwhile, temporary repairs performed using volatile memory devices (e.g., ASPPR repairs) may be lost.

[0059] From normal memory operation of block 410, the memory can be moved to ASPPR operation based on block 420, which describes a fault detected by the controller. For example, during a read operation, the fault detection circuitry (e.g., Figure 2 (206) can determine that the read data is incorrect (e.g., a mismatch with the written data). The controller can log the logical address associated with the detected fault (e.g., XADD). If no fault is detected, method 400 returns to block 410. If a fault is detected, method 400 can proceed to block 422.

[0060] Block 422 describes the issuance of an ASPPR command from the controller and the logical address associated with the fault detected in block 420. For example, the controller may issue a logical address and a row activation command along a standard CA bus, and may also issue a bad page flag. The bad page flag may be written to a mode register of memory. Method 400 may include setting a bad page flag (e.g., PPR_Alert) that indicates the performance of an ASPPR operation.

[0061] Box 422 is followed by box 424, which describes translating a logical address (e.g., XADD or LA) into a physical address and latching the physical address into the ASPPR register (e.g., ...). Figure 1 130 Figure 2 218, and / or Figure 3 The memory in block 326). Since the ASPPR register contains volatile elements, the steps in block 424 can be used to repair the word line associated with the logical address by means of a temporary repair (when it is detected as faulty). The timing from block 422 to block 424 can occur similarly to the timing of a normal access operation (e.g., within tRAS).

[0062] Following box 424, the method may return to box 410, which describes normal operation. During normal operation, when accessing a row, method 400 may include receiving a logical address, translating the logical address into a physical address, and comparing the physical address with the physical address stored in the ASPPR register. If a match is found, a redundant word line may be accessed instead of any word line previously associated with the physical address.

[0063] From normal operation, the memory can enter PPR mode at block 430. For example, the controller may provide a PPR signal and / or set a PPR mode flag in the memory's mode register. If PPR mode is entered, method 400 may proceed to block 432, which describes checking to see if a page flag was previously issued (e.g., if an ASPPR repair was previously performed). For example, if a page flag was previously issued, the page flag (e.g., PPR_Alert) may be active in the mode register. If no previously issued page flag exists, the memory may enter block 434, which describes performing a hard PPR using a logical address supplied via a PPR command. As part of entering PPR mode (e.g., block 430), the memory may receive a row address (e.g., a logical address) specifying the row to be repaired. If no page flag is set (e.g., no previously issued page flag), fuse logic may blow one or more fuses based on the logical address provided with the PPR command.

[0064] If a previously issued bad page flag exists, then box 432 will be followed by box 436 describing the performance of a hard PPR operation. Box 436 may include retrieving the physical address from the ASPPR register and blowing one or more fuses (e.g., in...). Figure 1 Fuse array 125 and / or Figure 2 (as in 214) to encode the physical address in the fuse array. Box 436 may also include clearing bad page flags. For example, box 436 may include the PPR_Alert flag not being set in the mode register.

[0065] Following block 434 or 436, method 400 proceeds to block 438, which checks whether the PPR operations have been completed. If they have not been completed (e.g., more addresses need to be programmed into the fuse array), method 400 holds. If no further PPR operations are needed, method 400 returns to normal memory operation 410. As part of normal memory operation, the memory receives a row address, compares it with the address programmed in the fuse array, and accesses the redundant row of memory if a match is found.

[0066] Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined with or separated from one or more other examples, embodiments, and / or processes and / or performed in a separate device or device portion of a system, apparatus, or method according to the present invention.

[0067] Finally, the foregoing discussion is intended to illustrate the system of the invention only and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, although the system of the invention has been described in detail with reference to exemplary embodiments, it should be understood that numerous modifications and alternative embodiments can be devised by those skilled in the art without departing from the broader and established spirit and scope of the system of the invention as set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A method comprising: Access the memory row in the first time value; and An ASPPR (Automatic Soft Packaging and Repair) operation is performed within a second time period, wherein the second time period is equal to or shorter than the first time period, and wherein the ASPPR operation includes: Receive row address and bad page signal; The physical address is generated based on the received row address using the word line engine; and In response to the bad page signal, the physical address is stored in the ASPPR register.

2. The method of claim 1, further comprising receiving the row address along the command / address bus and providing the row address to the word line engine along the address bus of the memory.

3. The method of claim 1, further comprising setting a bad page flag in the mode register of the memory in response to the bad page signal.

4. The method of claim 3, further comprising: Receive PPR commands as part of the PPR operation; Check the status of the defective page flag; and In response to setting the bad page flag, one or more fuses in the fuse array are blown based on the physical address stored in the ASPPR register.

5. The method of claim 4, further comprising clearing the bad page flag in response to the PPR operation.

6. The method of claim 1, wherein the ASPPR operation comprises: Receive the second line of address as part of the access operation; A second physical address is generated based on the second row address; Compare the second physical address with the physical address stored in the ASPPR register; In response to a match between the second physical address and the physical address, the redundant word line associated with the ASPPR register is accessed.

7. The method of claim 1, wherein the ASPPR operation further comprises copying data from a word line associated with the physical address to a redundant word line associated with the ASPPR register.

8. The method of claim 1, wherein the row address specifies a single page.

9. An apparatus comprising: A memory array, which includes multiple word lines and redundant word lines; A word line engine configured to receive line addresses and generate physical addresses based on the line addresses, wherein the line addresses specify a single page; An automated soft-packaged repair ASPPR circuit is configured to store the physical address in response to setting a bad page flag in the mode register.

10. The device of claim 9, wherein the ASPPR circuitry is further configured to receive a second physical address as part of an access operation and to provide a matching signal in response to a match between the second physical address and the stored physical address.

11. The device of claim 10, further comprising a line decoder configured to access redundant lines of memory in response to the matching signal.

12. The device of claim 9, wherein the word line engine is configured to receive the row address at a second time after a wear leveling operation, and to provide a second physical address different from the physical address.

13. The device of claim 9, wherein the ASPPR circuit is configured to provide the stored physical address in response to a PPR command; the device further includes fuse logic circuitry configured to blow one or more fuses of a fuse array based on the physical address from the ASPPR circuit and the PPR command.

14. The device of claim 13, wherein the defective page flag is reset in response to the PPR command.

15. The device of claim 9, further comprising command address (CA) circuitry configured to receive the row address and provide the row address to the word line engine along the address bus.

16. The device of claim 15, wherein the time from receiving the row address from the CA circuit to storing the physical address by the ASPPR circuit is within tRAS.

17. A system comprising: The controller is configured to provide row addresses, row activation commands, and bad page signals as part of the Automatic Packaging and Repair (ASPPR) operation. The memory includes: An address latch, configured to latch the row address in response to the row activation command; A word line engine, configured to translate the row address into a physical address; and An ASPPR circuit configured to store the physical address in response to the row activation command and a bad page flag set in response to the bad page signal.

18. The system of claim 17, wherein the controller is further configured to provide a second line address and a second line activation command as part of the access operation.

19. The system of claim 18, wherein the memory performs the access operation in a first time period and performs the ASPPR operation in a second time period less than or equal to the first time period.

20. The system of claim 18, wherein the word line engine is further configured to generate a second physical address based on the second row address, and wherein the ASPPR circuitry is configured to provide a matching signal in response to the second physical address matching the stored physical address, and the memory further includes a row decoder configured to access redundant rows of the memory in response to the matching signal.

21. The system of claim 17, wherein the controller is configured to provide a PPR signal as part of a PPR operation, and the memory further includes fuse logic circuitry configured to blow one or more fuses in the fuse array based on the physical address stored in the ASPPR circuitry when the bad page flag is set.

22. The system of claim 21, wherein the memory is further configured to reset the bad page flag as part of the PPR operation.

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