Thin film transistor and display device including the same

Abstract

A thin film transistor and a display device including the same are provided. The thin film transistor includes an active layer; and a gate electrode at least partially overlapping the active layer, wherein the active layer includes a channel portion overlapping the gate electrode; a first connection portion contacting one side of the channel portion; and a second connection portion contacting the other side of the channel portion, wherein the channel portion includes a first channel region and a second channel region, each of the first channel region and the second channel region extends from the first connection portion to the second connection portion, and a length of the first channel region is shorter than a length of the second channel region.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0135019, filed on October 12, 2021, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] The present invention relates to a thin-film transistor that can simultaneously improve the S-factor and the ON-current, and a display device including the thin-film transistor. Background Technology

[0004] In the field of electronic devices, transistors are widely used as switching or driving devices. In particular, because thin-film transistors can be fabricated on glass or plastic substrates, they are widely used as switching devices in display devices such as liquid crystal displays or organic light-emitting elements.

[0005] Display devices may include, for example, switching thin-film transistors and driving thin-film transistors. Advantageously, the driving thin-film transistors have a large S-factor to represent grayscale levels.

[0006] Thin-film transistors (TFTs) typically have a small S-factor to ensure on-off characteristics. Therefore, when these TFTs are used as driver transistors in display devices, it is difficult to reproduce the grayscale levels of the display.

[0007] Therefore, thin-film transistors (TFTs) with large S-factors are needed to drive TFTs in display devices and easily reproduce grayscale levels. Furthermore, even if a TFT has a large S-factor, it must also possess excellent current characteristics in the on-state. Summary of the Invention

[0008] The present invention was made in view of the above problems. One object of the present invention is to provide a thin-film transistor having a large S-factor and excellent current characteristics in the on state.

[0009] Another object of the present invention is to provide a thin-film transistor having a large S-factor and a large current value in the on state.

[0010] Another object of the present invention is to provide a thin-film transistor that is designed such that the first channel region and the second channel region of the channel portion have corresponding lengths that are different from each other in order to simultaneously improve the S-factor and the on-current.

[0011] Another object of the present invention is to provide a thin-film transistor designed such that the second channel region of the channel portion has a longer length than the first channel region to increase the S-factor.

[0012] Another object of the present invention is to provide a thin-film transistor that is designed such that the first channel region of the channel portion has a shorter length than the second channel region in order to have excellent conduction current characteristics.

[0013] Another object of the present invention is to provide a thin-film transistor that has excellent grayscale rendering capability and excellent current characteristics by including a driving thin-film transistor having a large S-factor and a large on-current characteristic.

[0014] In addition to the objectives of the invention as described above, those skilled in the art will clearly understand additional objectives and features of the invention from the following description.

[0015] According to one aspect of the invention, the above and other objects can be achieved by providing a thin-film transistor comprising: an active layer; and a gate at least partially overlapping the active layer, wherein the active layer comprises: a channel portion overlapping the gate; a first connection portion contacting one side of the channel portion; and a second connection portion contacting the other side of the channel portion, wherein the channel portion comprises a first channel region and a second channel region, each of the first channel region and the second channel region extending from the first connection portion to the second connection portion, the length of the first channel region being shorter than the length of the second channel region.

[0016] The width of the gate overlapping the first channel region may be smaller than the width of the gate overlapping the second channel region.

[0017] The gate overlapping the first channel region and the gate overlapping the second channel region can be formed as one unit.

[0018] The gate may have a width that varies gradually at the boundary between the first channel region and the second channel region.

[0019] The gate may have a width that varies gradually between the first channel region and the second channel region.

[0020] The gate may have a width that gradually varies along the direction from the first channel region to the second channel region.

[0021] The active layer may include: a first active layer including the first channel region; and a second active layer including the second channel region.

[0022] The first active layer and the second active layer may be located in the same layer and may be separated from each other.

[0023] The first active layer and the second active layer may be separated from each other in the region where they overlap with the gate.

[0024] The active layer can be configured in a plan view to overlap with the gate and surround the free area.

[0025] The active layer may not be located in the free area.

[0026] The active layer may include an oxide semiconductor material.

[0027] The oxide semiconductor material may include at least one of IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO (GaZnO)-based, ITZO (InSnZnO)-based, and FIZO (FeInZnO)-based oxide semiconductor materials.

[0028] The active layer may include: a first oxide semiconductor layer; and a second oxide semiconductor layer on the first oxide semiconductor layer.

[0029] The active layer may further include a third oxide semiconductor layer on the second oxide semiconductor layer.

[0030] According to another aspect of the invention, the above and other objectives can be achieved by providing a display device including the aforementioned thin-film transistors. Attached Figure Description

[0031] The above and other objects, features, and advantages of the invention will become more clearly understood from the following detailed description given with reference to the accompanying drawings. In the drawings:

[0032] Figure 1A This is a plan view illustrating a thin-film transistor according to one embodiment of the present invention;

[0033] Figure 1B and 1C This is a cross-sectional view illustrating a thin-film transistor according to an embodiment of the present invention;

[0034] Figure 2A This is a plan view illustrating a thin-film transistor according to another embodiment of the present invention;

[0035] Figure 2B , 2C 2D is a cross-sectional view illustrating a thin-film transistor according to another embodiment of the present invention;

[0036] Figure 3AThis is a plan view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0037] Figure 3B and Figure 3C This is a cross-sectional view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0038] Figure 4 This is a plan view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0039] Figure 5 This is a plan view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0040] Figure 6 This is a plan view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0041] Figure 7A and 7B This is a cross-sectional view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0042] Figure 8 This is a cross-sectional view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0043] Figure 9 It is a graph illustrating the threshold voltage of a thin-film transistor;

[0044] Figure 10 This is a schematic diagram illustrating a display device according to another embodiment of the present invention;

[0045] Figure 11 It is a diagram Figure 10 The circuit diagram of any pixel;

[0046] Figure 12 It is a diagram Figure 11 A planar image of pixels;

[0047] Figure 13 It is along Figure 12 A sectional view taken by line I-I';

[0048] Figure 14 This is a circuit diagram illustrating any pixel of a display device according to yet another embodiment of the present invention;

[0049] Figure 15 This is a circuit diagram illustrating any pixel of a display device according to another embodiment of the present invention. Detailed Implementation

[0050] The advantages and features of the invention, as well as its implementation, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments listed herein. Rather, these embodiments are provided to make the disclosure of the invention comprehensive and complete, and to fully convey the scope of the invention to those skilled in the art. Furthermore, the invention is defined only by the scope of the claims.

[0051] The shapes, sizes, proportions, angles, and quantities disclosed in the drawings to describe various embodiments of the invention are merely examples, and therefore the invention is not limited to the details illustrated. Similar reference numerals refer to similar elements throughout. In the following description, detailed descriptions of related known functions or constructions will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the focus of the invention.

[0052] Where the terms “including,” “having,” and “contains” are used in the description in this application, other parts may be added unless “only” is used.

[0053] When interpreting a factor, even if not explicitly stated, the factor should be interpreted as including a range of error.

[0054] When describing positional relationships, such as when the positional relationship is described as "on," "above," "below," and "after," one or more additional parts may be placed between the two parts, unless "exactly" or "directly" is used.

[0055] This document may use spatially relative terms such as “below,” “lower,” “below,” “above,” and “upper” to readily describe the relationship of one or more elements shown in the figures to other elements. It will be understood that these terms are intended to cover different orientations of the device beyond those depicted in the figures. For example, if the device shown in the figures is reversed, a device described as being “below” or “lower” to other devices may be arranged to be “above” to other devices. Thus, the exemplary term “below or lower” may include both “below or lower” and “upper” orientations. Similarly, the exemplary term “upper” or “above” may include both “above” and “below or lower” orientations.

[0056] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous situations may be included unless “exactly” or “directly” is used.

[0057] It will be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0058] The term "at least one" should be understood to include any one and all combinations of one or more of the relevant listed items. For example, "at least one of the first, second and third items" means a combination of all items selected from the first, second and third items, as well as the first, second or third item.

[0059] Those skilled in the art will fully understand that the features of the various embodiments of the present invention can be combined or integrated with each other, either partially or entirely, and can be technically interoperable and driven in various ways. The various embodiments of the present invention can be implemented independently of each other, or implemented jointly in a mutually dependent relationship.

[0060] In the accompanying drawings, even when depicted in different figures, the same or similar elements are referred to by the same reference numerals.

[0061] In embodiments of the present invention, for ease of description, the source and drain are distinguished from each other. However, the source and drain can be used interchangeably. The source can be the drain, and the drain can be the source. Furthermore, the source in any embodiment of the present invention can be the drain in another embodiment of the present invention, and the drain in any embodiment of the present invention can be the source in another embodiment of the present invention.

[0062] For ease of description, in some embodiments of the present invention, the source region is separated from the source, and the drain region is separated from the drain. However, the embodiments of the present invention are not limited to this structure. For example, the source region can be the source, and the drain region can be the drain. Furthermore, the source region can be the drain, and the drain region can be the source.

[0063] Figure 1A This is a plan view illustrating a thin-film transistor 100 according to an embodiment of the present invention; Figure 1B and 1C This is a cross-sectional view illustrating a thin-film transistor 100 according to an embodiment of the present invention.

[0064] A thin-film transistor 100 according to one embodiment of the present invention includes an active layer 130 and a gate 150 that at least partially overlaps with the active layer 130. The active layer 130 includes: a channel portion 130n; a first connection portion 130s contacting one side of the channel portion 130n; and a second connection portion 130d contacting the other side of the channel portion 130n.

[0065] According to an embodiment of the present invention, the channel portion 130n includes a first channel region 131n and a second channel region 132n, and each of the first channel region 131n and the second channel region 132n is connected from the first connection portion 130s to the second connection portion 130d. According to an embodiment of the present invention, the length L1 of the first channel region 131n is shorter than the length L2 of the second channel region 132n (L1<L2). According to an embodiment of the present invention, the first channel region 131n and the second channel region 132n may be arranged side by side. The first channel region 131n and the second channel region 132n may be in contact with each other, or may be spaced apart from each other.

[0066] Hereinafter, referring to Figures 1A to 1C the thin film transistor 100 according to an embodiment of the present invention will be described in more detail.

[0067] Figure 1A is a plan view of the thin film transistor 100 according to an embodiment of the present invention, Figure 1B is a cross-sectional view taken along line Ia-Ia' of Figure 1A , Figure 1C is a cross-sectional view taken along line Ib-Ib' of Figure 1A .

[0068] Referring to Figures 1A to 1C , the thin film transistor 100 is disposed on the substrate 110.

[0069] There is no particular limitation on the type of the substrate 110. A support member for supporting the thin film transistor 100 may be referred to as the substrate 110 without limitation. The substrate 110 may be, for example, glass or plastic. A transparent plastic having flexible properties, such as polyimide, may be used as the plastic. When polyimide is used as the substrate 110, in consideration of the high-temperature deposition process performed on the substrate 110, a heat-resistant polyimide capable of withstanding high temperatures may be employed.

[0070] A lower buffer layer 220 may be disposed on the substrate 110. The lower buffer layer 220 may planarize the upper portion of the substrate 110, have air and moisture barrier properties due to its insulating properties, and protect the thin film transistor 100. The lower buffer layer 220 may be omitted.

[0071] A light shielding layer 111 is disposed on the lower buffer layer 220. The light shielding layer 111 has light shielding properties. The light shielding layer 111 may block light incident from the outside to protect the channel portion 130n. The light shielding layer 111 may also have electrical conductivity.

[0072] The light-shielding layer 111 may comprise at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), and iron (Fe). The light-shielding layer 111 may have a multilayer structure, comprising at least two conductive layers having different physical properties from each other.

[0073] A buffer layer 120 is disposed on the light-shielding layer 111. The buffer layer 120 may include at least one insulating material selected from silicon oxide, silicon nitride, and metal-based oxides. According to one embodiment of the invention, the buffer layer 120 may include at least one of silicon oxide and silicon nitride. The buffer layer 120 may have a single-layer structure or a multi-layer structure.

[0074] The buffer layer 120 protects the active layer 130 by blocking air and moisture. In addition, the buffer layer 120 allows the light-shielding layer 111 and the channel portion 130n to be separated from and insulated from each other.

[0075] The active layer 130 is disposed on the buffer layer 120.

[0076] The active layer 130 may be formed of a semiconductor material. The active layer 130 may include any one of amorphous silicon semiconductor material, polycrystalline silicon semiconductor material, and oxide semiconductor material.

[0077] According to one embodiment of the present invention, the active layer 130 may include an oxide semiconductor material. The oxide semiconductor material may include, for example, at least one of IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO (GaZnO)-based, ITZO (InSnZnO)-based, and FIZO (FeInZnO)-based oxide semiconductor materials. However, one embodiment of the present invention is not limited thereto, and the active layer 130 may be made of other oxide semiconductor materials known in the art.

[0078] The active layer 130 includes a channel portion 130n, a first connection portion 130s, and a second connection portion 130d. One side of the channel portion 130n contacts the first connection portion 130s, and the other side of the channel portion 130n contacts the second connection portion 130d. The channel portion 130n overlaps with the gate 150 and serves as the channel of the thin-film transistor 100.

[0079] The first connection portion 130s and the second connection portion 130d of the active layer 130 do not overlap with the gate 150. The first connection portion 130s and the second connection portion 130d can be formed by selectively conductiveizing the semiconductor material. Providing conductivity to selected portions of the active layer 130 refers to selective conductiveizing. Selective conductiveizing can be performed by doping, plasma treatment, etc.

[0080] According to one embodiment of the present invention, the first connection portion 130s of the active layer 130 can be a source region, and the second connection portion 130d can be a drain region. According to one embodiment of the present invention, the first connection portion 130s can be referred to as the source, and the second connection portion 130d can be referred to as the drain.

[0081] However, one embodiment of the present invention is not limited to the above example; the first connection portion 130s may be a drain region, and the second connection portion 130d may be a source region. Furthermore, the first connection portion 130s may be a drain, and the second connection portion 130d may be a source.

[0082] According to one embodiment of the present invention, the channel portion 130n includes a first channel region 131n and a second channel region 132n. The first channel region 131n may be arranged parallel to the second channel region 132n. (Refer to...) Figure 1A and 1B The first channel region 131n and the second channel region 132n extend from the first connecting portion 130s to the second connecting portion 130d, respectively.

[0083] According to one embodiment of the present invention, the length L1 of the first channel region 131n is less than the length L2 of the second channel region 132n. For example, the length L1 can be close to 5 micrometers, and the length L2 can be close to 8 micrometers. The minimum length L1 is close to 1.5 micrometers, and the maximum length L2 is close to 12 micrometers. This applies throughout the specification.

[0084] Because the length L1 of the first channel region 131n is relatively small, the current can flow smoothly through the first channel region 131n when the thin-film transistor 100 is in the on state. The first channel region 131n can increase the on-current of the thin-film transistor 100, thereby improving the on-current characteristics of the thin-film transistor 100.

[0085] Because the length L2 of the second channel region 132n is relatively large, it prevents the current flowing through the thin-film transistor 100 from increasing rapidly before the thin-film transistor is fully turned on. As a result, the S-factor of the thin-film transistor 100 can be increased through the second channel region 132n.

[0086] The gate insulating layer 140 is disposed on the active layer 130. The gate insulating layer 140 may include at least one of silicon oxide, silicon nitride, and a metal-based oxide. The gate insulating layer 140 may have a single-layer structure, or may have a multi-layer structure.

[0087] Referring to Figure 1B and 1C , the gate insulating layer 140 may be integrally formed over the entire surface of the substrate 110. Specifically, the gate insulating layer 140 may cover the channel portion 130n, the first connection portion 130s, and the second connection portion 130d of the active layer 130.

[0088] However, one embodiment of the present invention is not limited thereto, and the gate insulating layer 140 may be patterned. For example, the gate insulating layer 140 may be patterned to correspond to the shape of the gate electrode 150.

[0089] The gate electrode 150 is disposed on the gate insulating layer 140. The gate electrode 150 at least partially overlaps the active layer 130. The gate electrode 150 may overlap the channel portion 130n of the active layer 130.

[0090] The gate electrode 150 may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrode 150 may have a multi-layer structure including at least two conductive layers having different physical properties from each other.

[0091] According to one embodiment of the present invention, the width and shape of the gate electrode 150 may be adjusted, so as to adjust the lengths of the first channel region 131n and the second channel region 132n. For example, referring to Figure 1A , the width w1 of the gate electrode 150 overlapping the first channel region 131n may be smaller than the width w2 of the gate electrode overlapping the second channel region 132n (w1<w2). As a result, the first channel region 131n may be manufactured to have a smaller length than the second channel region 132n (L1<L2).

[0092] According to one embodiment of the present invention, one gate electrode 150 may overlap the first channel region 131n and the second channel region 132n. Specifically, as shown in Figure 1A , the gate electrode 150 overlapping the first channel region 131n and the gate electrode 150 overlapping the second channel region 132n may be formed integrally.

[0093] Referring to Figure 1AThe gate 150 may have widths w1 and w2 that vary in a stepwise manner. Specifically, the gate 150 may have widths w1 and w2 that vary in a stepwise manner at the boundary between the first channel region 131n and the second channel region 132n. As a result, the first channel region 131n and the second channel region 132n, which have different channel lengths from each other, can be formed by a single gate 150.

[0094] In addition, Figure 1A In the process, the portion of the gate 150 whose widths w1 and w2 change in a gradual manner can be the boundary located between the first channel region 131n and the second channel region 132n.

[0095] An interlayer insulating layer 180 is disposed on the gate 150. The interlayer insulating layer 180 is an insulating layer made of insulating material. The interlayer insulating layer 180 may be made of organic material, may be made of inorganic material, or may be made of a stack of organic and inorganic layers.

[0096] The source 161 and the drain 162 are disposed on the interlayer insulating layer 180.

[0097] Source 161 can be connected to light-shielding layer 111 via contact hole CH1. Source 161 is connected to active layer 130 via contact hole CH2. Source 161 can be electrically connected to the first connection portion 130s of active layer 130 via contact hole CH2. As a result, light-shielding layer 111 can be connected to the first connection portion 130s of active layer 130. Since light-shielding layer 111 is connected to source 161, light-shielding layer 111 is not floating, and the same voltage as that applied to source 161 can be applied to light-shielding layer 111.

[0098] The drain 162 is separated from the source 161 and is connected to the active layer 130 via the contact hole CH3. Specifically, the drain 162 can be electrically connected to the second connection portion 130d of the active layer 130 via the contact hole CH3.

[0099] Each of the source electrode 161 and the drain electrode 162 may contain at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. Each of the source electrode 161 and the drain electrode 162 may be composed of a single layer made of metal or metal alloy, or may be composed of a multilayer of two or more layers.

[0100] Reference Figure 1A and 1B The first connection portion 130s and the source electrode 161 are shown as distinct from each other, but one embodiment of the invention is not limited thereto. The first connection portion 130s may be the source electrode, and the electrode indicated by the reference numeral "161" may be a connecting electrode or a bridge.

[0101] exist Figure 1A and 1B In the diagram, the second connection portion 130d and the drain 162 are shown as distinct from each other, but one embodiment of the invention is not limited thereto. The second connection portion 130d may be the drain, and the electrode indicated by reference numeral "162" may be a connecting electrode or a bridge.

[0102] The S factor will be described below.

[0103] In the drain-source current curve corresponding to the gate voltage of the thin-film transistor 100, the S-factor (sub-threshold oscillation) is obtained by the inverted value of the slope of the curve for the threshold voltage Vth. For example, for the threshold voltage Vth of the thin-film transistor 100, the S-factor can be used as an index to represent the rate of change of the drain-source current relative to the gate voltage.

[0104] When the S-factor increases, the drain-source current I... DS The rate of change relative to the gate voltage becomes lower.

[0105] The S-factor can be obtained, for example, through... Figure 9 The current change curve shown is used to describe this. Figure 9 This is a threshold voltage curve of a thin-film transistor. Specifically, Figure 9 The gate voltage V is illustrated. GS The corresponding drain-source current I DS .

[0106] for Figure 9 The curves shown represent the threshold voltage Vth and the gate voltage V. GS The corresponding drain-source current I DS The inverse gradient (reciprocal) of the slope of the curve is the S-factor. When the S-factor is large, the drain-source current I corresponding to the gate voltage is... DS The rate of change is low.

[0107] When the S factor increases (in) Figure 9 (On the left-hand side of the curve of Implementation 1 with a long channel), due to the drain-source current I DS The rate of change relative to the gate voltage is lower, so it is easier to adjust the gate voltage V. GS To adjust the drain-source current I DS The range.

[0108] In current-driven display devices, such as organic light-emitting display devices, the drain-source current I of the driving thin-film transistor can be adjusted. DS The grayscale level of a pixel is controlled by the amplitude of the gate voltage. The drain-source current I of the driving thin-film transistor is determined by the gate voltage. DSThe amplitude of the light-emitting diode (LED) is thus increased. Therefore, in an organic light-emitting display device driven by current, the gray level of the pixel becomes easier to adjust as the S-factor of the driving thin-film transistor increases.

[0109] Reference Figure 1A The length L2 of the second channel region 132n of the channel portion 130n is relatively large. Therefore, it prevents the current flowing through the thin-film transistor 100 from increasing rapidly, thereby increasing the S-factor of the thin-film transistor 100.

[0110] In related technologies, increasing the S-factor of a thin-film transistor (TFT) involves increasing the distance between the gate and the channel. However, this results in a problem where the TFT's on-state current decreases despite the increased S-factor.

[0111] However, according to one embodiment of the present invention, since the S-factor of the thin-film transistor 100 can be increased through the second channel region 132, it is not necessary to increase the distance between the gate 150 and the channel portion 130n.

[0112] According to one embodiment of the present invention, since the spacing between the channel portion 130n and the gate 150 is not increased, the on-current of the thin-film transistor 100 does not decrease when the thin-film transistor 100 is turned on. Furthermore, since the length L1 of the first channel region 131n is small, the current can flow smoothly through the first channel region 131n when the thin-film transistor 100 is turned on. Specifically, when the thin-film transistor 100 is turned on, the first channel region 131n of the channel portion 130n becomes the main current region, thereby improving the on-current of the thin-film transistor 100.

[0113] Therefore, the thin-film transistor 100 according to one embodiment of the present invention can have excellent S-factor and on-current characteristics. Since the thin-film transistor 100 according to one embodiment of the present invention has a large S-factor, the thin-film transistor 100 can be used as a driving transistor for a display device.

[0114] Figure 2A This is a plan view illustrating a thin-film transistor according to another embodiment of the present invention. Figure 2B , 2C 2D is a cross-sectional view illustrating a thin-film transistor according to another embodiment of the present invention. Specifically, Figure 2B It is along Figure 2A A sectional view taken from line IIa-IIa'. Figure 2C It is along Figure 2A A sectional view taken from line IIb-IIb'. Figure 2D It is along Figure 2A A sectional view taken from line IIc-IIc'.

[0115] compared to Figure 1AThe thin-film transistor 100, in Figure 2A In the thin-film transistor 200, the active layer 130 is divided into a first active layer 131 and a second active layer 132. To avoid repetition, descriptions of the already described elements will be omitted below.

[0116] Reference Figure 2A In a thin-film transistor 200 according to another embodiment of the present invention, the active layer 130 includes a first active layer 131 and a second active layer 132. The first active layer 131 and the second active layer 132 are disposed on the same layer and spaced apart from each other. The first active layer 131 and the second active layer 132 are planarly separated from each other. This has the advantage that, during the manufacturing process, the first channel and the second channel are aligned with the first active layer and the second active layer, respectively. This has the operational advantage of providing the desired S-factor and Ion performance.

[0117] Reference Figure 2A and 2B The first active layer 131 includes a first channel region 131n, and the second active layer 132 includes a second channel region 132n.

[0118] The first active layer 131 includes a first channel region 131n, a first connecting portion 131s, and a second connecting portion 131d. The first channel region 131n becomes the channel portion of the first active layer 131.

[0119] Reference Figure 2A and 2C The second active layer 132 includes a second channel region 132n, a first connecting portion 132s, and a second connecting portion 132d. The second channel region 132n becomes the channel portion of the second active layer 132.

[0120] The first connection portion 131s of the first active layer 131 and the first connection portion 132s of the second active layer 132 constitute the first connection portions 131s and 132s of the active layer 130. The first connection portion 131s of the first active layer 131 and the first connection portion 132s of the second active layer 132 can be connected to the source electrode 161 via contact holes CH21 and CH22, respectively.

[0121] The second connection portion 131d of the first active layer 131 and the second connection portion 132d of the second active layer 132 constitute the second connection portions 131d and 132d of the active layer 130. The second connection portion 131d of the first active layer 131 and the second connection portion 132d of the second active layer 132 can be connected to the drain electrode 162 via contact holes CH31 and CH32, respectively.

[0122] Reference Figure 2A and 2DThe first active layer 131 and the second active layer 132 are separated from each other in the region overlapping with the gate 150. As a result, the first channel region 131n and the second channel region 132n are separated from each other.

[0123] The gate 150 has widths w1 and w2 that change gradually between the first channel region 131n and the second channel region 132n. Therefore, as... Figure 2A As shown, the length L1 of the first channel region 131n is shorter than the length L2 of the second channel region 132n (L1 <L2)。

[0124] Because the length L1 of the first channel region 131n is relatively small, the current can flow smoothly through the first channel region 131n when the thin-film transistor 200 is in the on state, thereby enabling the thin-film transistor 200 to have excellent on-current characteristics. This situation can be equally applied to other embodiments described below.

[0125] Furthermore, since the length L2 of the second channel region 132n is relatively large, a rapid increase in current can be prevented, thereby allowing the thin-film transistor 200 to have a large S-factor. This principle applies equally to other embodiments described below.

[0126] Figure 3A This is a plan view illustrating a thin-film transistor according to yet another embodiment of the present invention. Figure 3B and 3C This is a cross-sectional view illustrating a thin-film transistor according to yet another embodiment of the present invention. Specifically, Figure 3B It is along Figure 3A A sectional view taken from line IIIa-IIIa'. Figure 3C It is along Figure 3A A sectional view taken from line IIIb-IIIb'.

[0127] Reference Figures 3A to 3C A vacant area 135, surrounded by the active layer 130, is provided in the same layer as the active layer 130. According to one embodiment of the invention, the vacant area 135 is surrounded by the active layer 130 in the same layer as the active layer 130 and overlaps with the gate 150, and refers to the region where the active layer 130 is not provided. This has the advantage that, during the manufacturing process, the first channel and the second channel are aligned with the first active layer and the second active layer, respectively. This has the operational advantage of providing the desired S-factor and Ion performance.

[0128] Reference Figure 3A The active layer 130 may be configured to overlap with the gate 150 and surround the free area in the plan view. The active layer 130 is not disposed in the free area 135.

[0129] Reference Figure 3ASince the idle region 135 is located in the region overlapping with the gate 150, the first channel region 131n and the second channel region 132n are separated from each other. The active layer 130 may be integrally formed outside the idle region 135.

[0130] The first connecting portion 130s contacts the first channel region 131n and the second channel region 132n respectively, and can be integrally formed on the outside of the free space 135 to form a first connecting portion 130s. The second connecting portion 130d can contact the first channel region 131n and the second channel region 132n respectively, and can be integrally formed on the outside of the free space 135 to form a second connecting portion 130d.

[0131] The gate 150 has widths w1 and w2 that gradually change between the first channel region 131n and the second channel region 132n. The first channel region 131n and the second channel region 132n may have different lengths (L1) from each other. <L2)。

[0132] Figure 4 This is a plan view illustrating a thin-film transistor 400 according to another embodiment of the present invention.

[0133] Reference Figure 4 The gate 150 has a gradually varying width in the region overlapping with the active layer 130. Specifically, in the region overlapping with the active layer 130, the gate 150 may have a smaller width w1 and a larger width w2.

[0134] According to one embodiment of the present invention, the active layer 130 overlapping with a portion of the gate 150 having a smaller width w1 may be referred to as a first channel region 131n, and the active layer 130 overlapping with a portion of the gate 150 having a larger width w2 may be referred to as a second channel region 132n.

[0135] According to another embodiment of the present invention, the gate 150 may have widths w1 and w2 that gradually vary along the direction from the first channel region 131n to the second channel region 132n. Therefore, the channel portion 130n may have channel lengths L1 and L2 that gradually vary along the direction from the first channel region 131n to the second channel region 132n. As a result, the first channel region 131n may have a shorter length (L1) than the second channel region 132n. <L2)。

[0136] Figure 5 This is a plan view illustrating a thin-film transistor 500 according to another embodiment of the present invention.

[0137] Reference Figure 5The active layer 130 includes a first active layer 131 and a second active layer 132, which are separated from each other in a plane. The first active layer 131 includes a first channel region 131n, and the second active layer 132 includes a second channel region 132n.

[0138] Furthermore, the gate 150 has gradually varying widths w1 and w2 in the region overlapping with the active layer 130. For example... Figure 5 As shown, since the gate 150 has a width that gradually changes along the direction from the first channel region 131n to the second channel region 132n, the second channel region 132n can have a channel length that is longer than that of the first channel region 131n.

[0139] Figure 6 This is a plan view illustrating a thin-film transistor 600 according to another embodiment of the present invention.

[0140] Reference Figure 6 An idle region 135, surrounded by the active layer 130, is provided in the same layer as the active layer 130. According to one embodiment of the invention, the idle region 135 is surrounded by the active layer 130 in the same layer as the active layer 130 and overlaps with the gate 150. The active layer 130 is not provided in the idle region 135.

[0141] In addition, refer to Figure 6 The gate 150 has a gradually varying width in the region overlapping with the active layer 130. Since the gate 150 has a gradually varying width along the direction from the first channel region 131n to the second channel region 132n, the second channel region 132n may have a longer channel length than the first channel region 131n.

[0142] Figure 7A and 7B These are cross-sectional views illustrating thin-film transistors 701 and 702 according to another embodiment of the present invention. Figure 7A and 7B The structure of the active layer 130 shown can be applied to Figure 1A , 1B The active layer 130 of the thin-film transistors 100, 200, 300, 400, 500 and 600 shown in 1C, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 4, 5 and 6.

[0143] Reference Figure 7A The active layer 130 of the thin-film transistor 701 has a multilayer structure. Specifically, refer to... Figure 7AThe active layer 130 includes a first oxide semiconductor layer 1301 on the substrate 110 and a second oxide semiconductor layer 1302 on the first oxide semiconductor layer 1301. The first oxide semiconductor layer 1301 and the second oxide semiconductor layer 1302 may contain the same semiconductor material or may contain different semiconductor materials.

[0144] The first oxide semiconductor layer 1301 supports the second oxide semiconductor layer 1302. Therefore, the first oxide semiconductor layer 1301 is referred to as a "support layer". A channel portion 130n may be formed in the second oxide semiconductor layer 1302. Therefore, the second oxide semiconductor layer 1302 is referred to as a "channel layer", but one embodiment of the present invention is not limited thereto, and the channel portion 130n may be formed in the first oxide semiconductor layer 1301.

[0145] The structure of the active layer 130, which includes a first oxide semiconductor layer 1301 and a second oxide semiconductor layer 1302, is called a bi-layer structure.

[0146] compared to Figure 7A The thin-film transistor 701, according to Figure 7B In the thin-film transistor 702, the active layer 130 further includes a third oxide semiconductor layer 1303 located on the second oxide semiconductor layer 1302.

[0147] Reference Figure 7B The active layer 130 includes a first oxide semiconductor layer 1301, a second oxide semiconductor layer 1302, and a third oxide semiconductor layer 1303. However, another embodiment of the present invention is not limited to this, and the active layer 130 may further include other semiconductor layers. In the case of three oxide semiconductor layers, the intermediate layer 1302 can be protected from damage in two directions during manufacturing. For example, the bottom oxide semiconductor layer protects the intermediate semiconductor layer from the influence of gases during manufacturing, and the top oxide semiconductor layer protects the intermediate semiconductor layer from the influence of etchants or gases during the manufacturing process.

[0148] Figure 8 This is a cross-sectional view illustrating a thin-film transistor 800 according to yet another embodiment of the present invention. Figure 8 The structure of the gate insulating layer 140 shown can be applied to Figure 1A , 1B The gate insulating layer 140 of the thin film transistors 100, 200, 300, 400, 500, 600, 701 and 702 shown in 1C, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 4, 5, 6, 7A and 7B.

[0149] Reference Figure 8The gate insulating layer 140 can be patterned. For example, the gate insulating layer 140 can be patterned to cover the channel portion 130n. In the patterning process of the gate insulating layer 140, the active layer 130 can be selectively conductive, thereby forming the first connection portion 130s and the second connection portion 130d.

[0150] Figure 9 This is a graph illustrating the threshold voltage of a thin-film transistor (TFT). The threshold voltage graph of a TFT is determined by the gate voltage V. GS The corresponding drain-source current I DS It is represented by a curve graph.

[0151] exist Figure 9 In this embodiment, 1 is a threshold voltage curve of a thin-film transistor having the same structure as the thin-film transistor 100 in FIG1.

[0152] exist Figure 9 In this context, "short channel" corresponds to the threshold voltage curve of a thin-film transistor with only a short channel section of 130 nm. Figure 9 In the diagram, "long channel" corresponds to the threshold voltage curve of a thin-film transistor with only a relatively long channel portion of 130 nm. Figure 9 In the diagram, the arrow marked "S-factor increases" indicates the direction in which the S-factor increases. Similarly, the arrow marked "Ion increases" indicates the direction in which the amplitude of the conduction current (Ion) increases.

[0153] Reference Figure 9 Note that "short-channel" thin-film transistors with a shorter channel length of 130n have excellent on-current characteristics due to the increase in ions, but the current flowing through the thin-film transistor increases rapidly before it is fully turned on, resulting in a smaller S-factor.

[0154] On the other hand, note that "long-channel" thin-film transistors with a longer channel length of 130n have a larger S-factor but a smaller on-current value.

[0155] The thin-film transistor according to one embodiment of the present invention (Embodiment 1) has excellent on-current characteristics due to its first channel region 131n, which corresponds to a short length L1 of a "short channel", and excellent S-factor characteristics due to its second channel region 132n, which corresponds to a long length L2 of a "long channel".

[0156] The following will describe in detail display devices including the thin-film transistors 100, 200, 300, 400, 500, 600, 701, 702 and 800 described above. The display devices may include LED, OLED, LCD, PDP, microLED or miniLED display devices.

[0157] Figure 10 This is a schematic diagram illustrating a display device 900 according to another embodiment of the present invention.

[0158] like Figure 10 As shown, a display device 900 according to another embodiment of the present invention includes a display panel 310, a gate driver 320, a data driver 330, and a controller 340.

[0159] Gate lines GL and data lines DL are disposed in the display panel 310, and multiple pixels P are disposed in the intersection area of ​​gate lines GL and data lines DL. Images are displayed by driving the pixels P.

[0160] The controller 340 controls the gate driver 320 and the data driver 330.

[0161] The controller 340 outputs a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330 using signals provided from an external system (not shown). Furthermore, the controller 340 samples input image data from the external system, rearranges the sampled data, and provides the rearranged digital image data (RGB) to the data driver 330.

[0162] The gate control signal GCS includes the gate start pulse GSP, the gate shift clock GSC, the gate output enable signal GOE, the start signal Vst, and the gate clock GCLK. Additionally, control signals for controlling the shift register may be included in the gate control signal GCS.

[0163] The data control signal DCS includes the source start pulse SSP, the source shift clock signal SSC, the source output enable signal SOE, and the polarity control signal POL.

[0164] The data driver 330 provides data voltage to the data line DL of the display panel 310. Specifically, the data driver 330 converts the image data RGB input from the controller 340 into analog data voltage and provides the data voltage to the data line DL.

[0165] Gate driver 320 may include shift register 350.

[0166] The shift register 350 sequentially provides gate pulses to the gate line GL within a frame using a start signal and a gate clock transmitted from the controller 340. In this case, a frame refers to the time period during which an image is output through the display panel 310. The gate pulses have an on-state voltage capable of turning on the switching elements (thin-film transistors) disposed in the pixel P.

[0167] In addition, shift register 350 provides a gate cutoff signal to gate line GL during other periods of a frame when no gate pulse is provided, which enables the switching element to turn off. Hereinafter, the gate pulse and gate cutoff signal will be collectively referred to as the scan signal SS or Scan.

[0168] According to one embodiment of the present invention, the gate driver 320 may be packaged on the substrate 110. In this way, the structure in which the gate driver 320 is directly packaged on the substrate 110 is referred to as a gate-in-panel (GIP) structure.

[0169] Figure 11 It is a diagram Figure 10 The circuit diagram of any pixel P. Figure 12 It is a diagram Figure 11 A planar image of pixel P. Figure 13 It is along Figure 12 A sectional view taken from line I-I'.

[0170] Figure 11 The circuit diagram is an equivalent circuit diagram of the pixel P of the display device 900, which includes an organic light-emitting diode (OLED) as a display element 710.

[0171] Pixel P includes a display element 710 and a pixel driving circuit PDC for driving the display element 710.

[0172] Figure 11 The pixel driving circuit PDC includes a first thin-film transistor TR1 as a switching transistor and a second thin-film transistor TR2 as a driving transistor. For example, the thin-film transistors 100, 200, 300, 400, 500, 600, 701, 702 and 800 described in any of the above embodiments can be used as the second thin-film transistor TR2.

[0173] The first thin-film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by the scan signal SS provided via the gate line GL.

[0174] The data line DL provides the data voltage Vdata to the pixel driving circuit PDC, and the first thin-film transistor TR1 controls the application of the data voltage Vdata.

[0175] The driving power line PL provides a driving voltage Vdd to the display element 710, and the second thin-film transistor TR2 controls the driving voltage Vdd. The driving voltage Vdd is the pixel driving voltage used to drive the organic light-emitting diode (OLED) that serves as the display element 710.

[0176] When the first thin-film transistor TR1 is turned on by the scan signal SS applied from the gate driver 320 via the gate line GL, the data voltage Vdata provided via the data line DL is supplied to the gate G2 of the second thin-film transistor TR2, which is connected to the display element 710. The data voltage Vdata is charged into the first capacitor C1 formed between the gate G2 and the source S2 of the second thin-film transistor TR2. The first capacitor C1 is a storage capacitor Cst.

[0177] The amount of current supplied to the organic light-emitting diode (OLED) of the display element 710 via the second thin-film transistor TR2 is controlled according to the data voltage Vdata, thereby controlling the gray level of the light emitted from the display element 710.

[0178] Reference Figure 12 and 13 The first thin-film transistor TR1 and the second thin-film transistor TR2 are disposed on the substrate 110.

[0179] The substrate 110 may be made of glass or plastic. Plastics with flexible properties, such as polyimide (PI), may be used as the substrate 110.

[0180] The lower buffer layer 220 is disposed on the substrate 110, and the light-shielding layer 111 is disposed on the lower buffer layer 220.

[0181] A buffer layer 120 is disposed on the light-shielding layer 111. The buffer layer 120 is made of insulating material and protects the active layers A1 and A2 from external moisture or oxygen.

[0182] The active layer A1 of the first thin-film transistor TR1 and the active layer A2 of the second thin-film transistor TR2 are disposed on the buffer layer 120.

[0183] Each of the active layers A1 and A2 may include, for example, at least one of an amorphous silicon semiconductor material, a polycrystalline silicon semiconductor material, and an oxide semiconductor material. Each of the active layers A1 and A2 may be composed of an oxide semiconductor layer made of an oxide semiconductor material.

[0184] In the first thin-film transistor TR1, the active layer A1 may include a channel portion, a first connection portion, and a second connection portion. The channel portion of the active layer A1 overlaps with the gate G1. The first connection portion of the active layer A1 may be referred to as the first source S1, and the second connection portion may be referred to as the first drain D1.

[0185] In the second thin-film transistor TR2, the active layer A2 may include a channel portion, a first connection portion, and a second connection portion. The channel portion of the active layer A2 overlaps with the gate G2. The first connection portion of the active layer A2 may be referred to as the second source S2, and the second connection portion may be referred to as the second drain D2.

[0186] Reference Figure 12 and 13 A portion of the active layer A1 of the first thin-film transistor TR1 can be made conductive to become the first capacitor electrode C11 of the first capacitor C1.

[0187] A gate insulating layer 140 is disposed on the active layers A1 and A2. The gate insulating layer 140 may cover the entire upper surface of the active layers A1 and A2, or may cover only a portion of the active layers A1 and A2.

[0188] The gate G1 of the first thin-film transistor TR1 and the gate G2 of the second thin-film transistor TR2 are disposed on the gate insulating layer 140.

[0189] Reference Figure 12 The gate G2 of the second thin-film transistor TR2 may have a width that varies gradually. Specifically, the gate G2 may have widths w1 and w2 that vary gradually at the boundary between the first channel region 131n and the second channel region 132n. As a result, the first channel region 131n and the second channel region 132n, which have different channel lengths from each other, can be formed by the gate G2.

[0190] An interlayer insulating layer 180 is disposed on gates G1 and G2.

[0191] The data cable DL and the drive power cable PL are mounted on the interlayer insulation layer 180.

[0192] The data line DL contacts the first source S1 formed in the active layer A1 of the first thin-film transistor TR1 via the first contact hole H1. According to another embodiment of the present invention, the portion of the data line DL that overlaps with the active layer A1 of the first thin-film transistor TR1 may be referred to as the first source S1.

[0193] The driving power line PL contacts the second drain D2 formed in the active layer A2 of the second thin-film transistor TR2 via the fifth contact hole H5. According to another embodiment of the present invention, the portion of the driving power line PL that overlaps with the active layer A2 of the second thin-film transistor TR2 may be referred to as the second drain D2.

[0194] Reference Figure 12 and 13 The second capacitor electrode C12 of the first capacitor C1, the first bridge BR1 and the second bridge BR2 are disposed on the interlayer insulating layer 180.

[0195] The second capacitor electrode C12 overlaps with the first capacitor electrode C11 to form the first capacitor C1.

[0196] The first bridge BR1 can be integrated with the second capacitor electrode C2. The first bridge BR1 is connected to the light-shielding layer 111 via the second contact hole H2 and to the second source S2 via the third contact hole H3. As a result, the light-shielding layer 111 can be connected to the second source S2 of the second thin-film transistor TR2.

[0197] The second bridge BR2 is connected to the gate G2 of the second thin-film transistor TR2 via the fourth contact hole H4, and is connected to the first capacitor electrode C11 of the first capacitor C1 via the seventh contact hole H7.

[0198] In addition, refer to Figure 12 The third bridge BR3 is disposed on the interlayer insulating layer 180. The third bridge BR3 is connected to the gate line GL via the eighth contact hole H8, thereby connecting to the gate G1, and is connected to the light-shielding layer 111 of the first thin-film transistor TR1 via the ninth contact hole H9. Although Figure 12 The diagram illustrates the connection of the light-shielding layer 111 to the gate G1. However, one embodiment of the present invention is not limited to this, and the light-shielding layer 111 may also be connected to the first source S1 or the first drain D1.

[0199] A planarization layer 175 is disposed on the data line DL, the drive power line PL, the second capacitor electrode C12, the first bridge BR1, the second bridge BR2, and the third bridge BR3. The planarization layer 175 planarizes the upper portions of the first thin-film transistor TR1 and the second thin-film transistor TR2, and protects the first thin-film transistor TR1 and the second thin-film transistor TR2.

[0200] The first electrode 711 of the display element 710 is disposed on the planarization layer 175. The first electrode 711 of the display element 710 contacts the second capacitor electrode C12 integrally formed with the first bridge BR1 via a sixth contact hole H6 formed in the planarization layer 175. As a result, the first electrode 711 can be connected to the second source S2 of the second thin film transistor TR2.

[0201] The embankment 750 is disposed at the edge of the first electrode 711. The embankment 750 defines the light-emitting area of ​​the display element 710.

[0202] An organic light-emitting layer 712 is disposed on the first electrode 711, and a second electrode 713 is disposed on the organic light-emitting layer 712. Thus, the display element 710 is completed. Figure 13 The display element 710 shown is an organic light-emitting diode (OLED). Therefore, the display device 900 according to one embodiment of the present invention is an organic light-emitting display device.

[0203] Figure 14 This is a circuit diagram illustrating any pixel P of a display device 1000 according to another embodiment of the present invention. Figure 14This is an equivalent circuit diagram illustrating the pixel P of an organic light-emitting display device.

[0204] Figure 14 The pixel P of the display device 1000 shown includes an organic light-emitting diode (OLED) as a display element 710 and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0205] In pixel P, signal lines DL, GL, PL, RL, and SCL are set to provide signals to the pixel driving circuit PDC.

[0206] The data voltage Vdata is provided to the data line DL, the scan signal SS is provided to the gate line GL, the driving voltage Vdd for driving the pixel is provided to the driving power line PL, the reference voltage Vref is provided to the reference line RL, and the sensing control signal SCS is provided to the sensing control line SCL.

[0207] Reference Figure 14 Assume that the gate line of the nth pixel P is GLn, and the gate line of the (n-1)th pixel P adjacent to the nth pixel P is GLn-1. The gate line GLn-1 of the (n-1)th pixel P is used as the sensing control line SCL of the nth pixel P.

[0208] The pixel driving circuit PDC includes, for example, a first thin-film transistor TR1 (switching transistor) connected to the gate line GL and the data line DL; a second thin-film transistor TR2 (driving transistor) for controlling the amplitude of the current output to the display element 710 according to the data voltage Vdata transmitted via the first thin-film transistor TR1; and a third thin-film transistor TR3 (reference transistor) for sensing the characteristics of the second thin-film transistor TR2.

[0209] A first capacitor C1 is disposed between the gate G2 of the second thin-film transistor TR2 and the display element 710. The first capacitor C1 is referred to as the storage capacitor Cst.

[0210] The first thin-film transistor TR1 is turned on by a scan signal SS provided to the gate line GL to transmit the data voltage Vdata provided to the data line DL to the gate G2 of the second thin-film transistor TR2.

[0211] The third thin-film transistor TR3 is connected to the first node n1 and the reference line RL located between the second thin-film transistor TR2 and the display element 710, thereby being turned on or off by the sensing control signal SCS, and sensing the characteristics of the second thin-film transistor TR2 as a driving transistor during the sensing period.

[0212] A second node n2, connected to the gate G2 of the second thin-film transistor TR2, is connected to the first thin-film transistor TR1. A first capacitor C1 is formed between the second node n2 and the first node n1.

[0213] When the first thin-film transistor TR1 is turned on, the data voltage Vdata supplied via the data line DL is provided to the gate G2 of the second thin-film transistor TR2. The data voltage Vdata is charged into the first capacitor C1 formed between the gate G2 and the source S2 of the second thin-film transistor TR2.

[0214] When the second thin-film transistor TR2 is turned on, current is supplied to the display element 710 via the second thin-film transistor TR2 according to the driving voltage Vdd used to drive the pixel, thereby outputting light from the display element 710.

[0215] Figure 15 This is a circuit diagram illustrating the pixels of a display device 1100 according to another embodiment of the present invention.

[0216] Figure 15 The pixel P of the display device 1100 shown includes an organic light-emitting diode (OLED) as a display element 710 and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0217] The pixel drive circuit PDC includes thin-film transistors TR1, TR2, TR3, and TR4.

[0218] In pixel P, signal lines DL, EL, GL, PL, SCL, and RL are set to provide drive signals to the pixel drive circuit PDC.

[0219] and Figure 14 Compared to the pixel P, Figure 15 The pixel P further includes an emission control line EL. An emission control signal EM is provided to the emission control line EL.

[0220] In addition, with Figure 14 Compared to the pixel drive circuit PDC, Figure 15 The pixel driving circuit PDC further includes a fourth thin-film transistor TR4 as a light-emitting control transistor for controlling the light-emitting timing of the second thin-film transistor TR2.

[0221] Reference Figure 15 Assume that the gate line of the nth pixel P is GLn, and the gate line of the (n-1)th pixel P adjacent to the nth pixel P is GLn-1. The gate line GLn-1 of the (n-1)th pixel P is used as the sensing control line SCL of the nth pixel P.

[0222] The first capacitor C1 is disposed between the gate G2 of the second thin-film transistor TR2 and the display element 710. The second capacitor C2 is disposed between a terminal of the fourth thin-film transistor TR4, which is supplied with a drive voltage Vdd, and an electrode of the display element 710.

[0223] The first thin-film transistor TR1 is turned on by a scan signal SS provided to the gate line GL to transmit the data voltage Vdata provided to the data line DL to the gate G2 of the second thin-film transistor TR2.

[0224] The third thin-film transistor TR3 is connected to the reference line RL, thereby being turned on or off by the sensing control signal SCS, and sensing the characteristics of the second thin-film transistor TR2, which is the driving transistor, during the sensing period.

[0225] The fourth thin-film transistor TR4 transmits a driving voltage Vdd to the second thin-film transistor TR2 according to the light emission control signal EM, or shields the driving voltage Vdd. When the fourth thin-film transistor TR4 is turned on, current is supplied to the second thin-film transistor TR2, thereby outputting light from the display element 710.

[0226] In addition to the structure described above, the pixel driving circuit PDC according to another embodiment of the present invention can be formed in various structures. For example, the pixel driving circuit PDC may include five or more thin-film transistors.

[0227] According to the present invention, the following beneficial effects can be obtained.

[0228] The thin-film transistor according to one embodiment of the present invention has a large S-factor and excellent on-current characteristics.

[0229] According to one embodiment of the present invention, the thin-film transistor is designed such that the length of the second channel region of the channel portion is greater than the length of the first channel region, thereby having a larger S-factor.

[0230] According to one embodiment of the present invention, the thin-film transistor is designed such that the length of the first channel region of the channel portion is less than the length of the second channel region, thereby exhibiting excellent conduction current characteristics.

[0231] Display devices including thin-film transistors according to one embodiment of the present invention can have excellent grayscale rendering capabilities and excellent current characteristics.

[0232] It will be apparent to those skilled in the art that the disclosure described above is not limited to the embodiments and drawings described herein; various substitutions, modifications, and variations may be made in this invention without departing from its scope. Therefore, the scope of this invention is defined by the appended claims, and all variations or modifications derived from the meaning, scope, and equivalent concepts of the claims are intended to fall within the scope of this invention.

Claims

1. A thin-film transistor, comprising: Light-shielding layer; A buffer layer is disposed on the light-shielding layer; An active layer disposed on the buffer layer; A gate that at least partially overlaps with the active layer; as well as Connected to the source and drain of the active layer, The source electrode is connected to the light-shielding layer. The active layer includes: The channel portion overlapping the gate; The first connecting portion that contacts one side of the channel portion; and The second connecting portion that contacts the other side of the channel portion, The channel section includes a first channel region and a second channel region. Each of the first channel region and the second channel region extends from the first connecting portion to the second connecting portion. The length of the first channel region is shorter than the length of the second channel region. The active layer includes: A first active layer, comprising a first channel region having a rectangular shape in a plan view, a first connection portion contacting one side of the first channel region, and a second connection portion contacting the other side of the first channel region; and The second active layer includes a second channel region having a rectangular shape in a plan view, a first connection portion contacting one side of the second channel region, and a second connection portion contacting the other side of the second channel region. In the plan view, the first active layer and the second active layer are separated from each other in the region overlapping with the gate, the first connection portion, and the second connection portion. The gate includes a stepped portion disposed between the first channel region and the second channel region.

2. The thin-film transistor of claim 1, wherein the width of the gate overlapping the first channel region is smaller than the width of the gate overlapping the second channel region.

3. The thin-film transistor of claim 2, wherein the gate overlapping the first channel region and the gate overlapping the second channel region are formed integrally.

4. The thin-film transistor according to claim 1, wherein the first active layer and the second active layer are disposed in the same layer.

5. The thin-film transistor of claim 1, wherein the active layer comprises an oxide semiconductor material.

6. The thin-film transistor according to claim 5, wherein the oxide semiconductor material comprises at least one of IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO (GaZnO)-based, ITZO (InSnZnO)-based, and FIZO (FeInZnO)-based oxide semiconductor materials.

7. The thin-film transistor of claim 1, wherein the active layer comprises: First oxide semiconductor layer; as well as A second oxide semiconductor layer on top of the first oxide semiconductor layer.

8. The thin-film transistor of claim 7, wherein the active layer further comprises a third oxide semiconductor layer on the second oxide semiconductor layer.

9. A display device comprising a thin-film transistor according to any one of claims 1-8.

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