Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, the semiconductor structure comprising: a device gate structure on an isolation layer and across a channel structure; source / drain doped regions in the channel structure on both sides of the device gate structure; and a source / drain contact structure on both sides of the device gate structure and along a second direction, the source / drain contact structure contacting the source / drain doped regions of a plurality of adjacent device regions, the source / drain contact structure comprising first portions on the source / drain doped regions and second portions on the isolation layer between adjacent first portions and connected to the adjacent first portions along the second direction, the second portions having a top surface lower than a top surface of the first portions, thereby facilitating reduction of parasitic capacitance between the device gate structure and the source / drain contact structure and optimization of performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] A MOS transistor typically includes an active region, a gate structure located on the active region, and source / drain doped regions located in the active regions on both sides of the gate structure. Source / drain contact structures are usually formed on the source / drain doped regions to facilitate electrical connection between the source / drain doped regions and external circuitry.

[0003] The capacitance between the gate structure and the source / drain doped regions, as well as the source / drain contact structure, is a significant component of the transistor's parasitic capacitance. When the source / drain contact structure is connected to the source / drain doped regions of multiple transistors, the source / drain contact structure is located on both sides of the gate structure. The area of ​​the parallel front surface between the source / drain contact structure and the gate structure is relatively large, resulting in a large parasitic capacitance between the gate structure and the source / drain contact structure.

[0004] Gate sidewalls are usually formed on the sidewalls of the gate structure. Currently, the method to reduce the parasitic capacitance between the gate structure and the source-drain contact structure is to reduce the k value of the gate sidewall material.

[0005] However, the performance of semiconductor structures still needs to be improved. Summary of the Invention

[0006] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby optimizing the performance of the semiconductor structure.

[0007] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate and a plurality of protrusion structures discretely disposed on the substrate, the protrusion structures extending along a first direction and spaced apart along a second direction, each protrusion structure including a protrusion portion and a channel structure located on the protrusion portion; the substrate including a plurality of device regions arranged along the second direction; an isolation layer located on the substrate and surrounding the protrusion portions and exposing the channel structures; a device gate structure located on the isolation layer and spanning the channel structures; source / drain doped regions located within the channel structures on both sides of the device gate structure; and source / drain contact structures located on both sides of the device gate structure and along the second direction, the source / drain contact structures contacting the source / drain doped regions of a plurality of adjacent device regions, each source / drain contact structure including a first portion located on the source / drain doped regions and a second portion located on an isolation layer between adjacent first portions along the second direction and connected to adjacent first portions, the top surface of the second portion being lower than the top surface of the first portion.

[0008] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate and a plurality of protrusion structures discretely disposed on the substrate, the protrusion structures extending along a first direction and spaced apart along a second direction, each protrusion structure including a protrusion portion and a channel structure located on the protrusion portion; the substrate including a plurality of device regions arranged along the second direction; forming an isolation layer surrounding the protrusion portion on the substrate, the isolation layer exposing the channel structure; forming a device gate structure located on the isolation layer and spanning the channel structure, and source / drain doped regions located in the channel structures on both sides of the device gate structure; forming source / drain contact structures on both sides of the device gate structure, the source / drain contact structures contacting the source / drain doped regions of a plurality of adjacent device regions along the second direction, the source / drain contact structures including a first portion located on the source / drain doped regions, and a second portion located on the isolation layer between adjacent first portions along the second direction and connected to adjacent first portions, the top surface of the second portion being lower than the top surface of the first portion.

[0009] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0010] In the semiconductor structure provided by the embodiments of the present invention, along the second direction, the source / drain contact structure contacts a plurality of source / drain doped regions of adjacent device regions. The source / drain contact structure includes a first portion located on the source / drain doped regions and a second portion located on an isolation layer between adjacent first portions along the second direction and connected to adjacent first portions. The top surface of the second portion is lower than the top surface of the first portion, thereby reducing the parallel facing area between the source / drain contact structure and the device gate structure, thereby reducing the parasitic capacitance between the source / drain contact structure and the device gate structure and optimizing the performance of the semiconductor structure.

[0011] In the semiconductor structure formation method provided by the present invention, source-drain contact structures are formed on both sides of the device gate structure. Along the second direction, the source-drain contact structures are in contact with multiple source-drain doped regions of adjacent device regions. The source-drain contact structure includes a first portion located on the source-drain doped region and a second portion located on an isolation layer between adjacent first portions along the second direction and connected to adjacent first portions. The top surface of the second portion is lower than the top surface of the first portion, thereby reducing the parallel facing area between the source-drain contact structure and the device gate structure, thereby reducing the parasitic capacitance between the source-drain contact structure and the device gate structure and optimizing the performance of the semiconductor structure. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of a semiconductor structure.

[0013] Figure 2 This is a schematic diagram of another semiconductor structure;

[0014] Figures 3 to 4 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0015] Figures 5 to 15 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0016] As can be seen from the background technology, the performance of semiconductor structures still needs to be improved.

[0017] Reference Figure 1 Taking a fin field-effect transistor as an example, the parasitic capacitance of the transistor includes: a first parasitic capacitance C1 between the first metal layers 1; a second parasitic capacitance C2 between the source / drain contact plug 2 and the gate structure 3; a third parasitic capacitance C3 between the gate structure 3 and the source / drain doped region 4; and a parasitic capacitance C4 between the source / drain contact plug 2, which is in contact with the source region 4(S) in the source / drain doped region 4, and the drain region 4(D).

[0018] Among them, the capacitances C3 and C2 between the gate structure 3, the source / drain doped region 4, and the source / drain contact plug 2 are important components of the transistor's parasitic capacitance.

[0019] The transistor also includes a gate sidewall (not shown) located on the sidewall of gate structure 3, according to the capacitance formula. Accordingly, a gate sidewall is also provided between the gate structure 3 and the source / drain contact plug 2, wherein the dielectric constant ε of the gate sidewall material is... r The lower the value, the smaller the parasitic capacitance C2 between the gate structure 3 and the source / drain contact plug 2.

[0020] Therefore, in conjunction with the reference Figure 2 A semiconductor structure has been proposed in which a gate sidewall 7 with an air gap 6 is formed on the sidewall of the gate structure 5, thereby reducing the dielectric constant of the gate sidewall 7 material and thus reducing the parasitic capacitance between the source / drain contact structure 8 and the gate structure 5.

[0021] However, the current process for forming the gate sidewall 7 with air gap 6 is complex, and the air gap 6 has a limited effect on reducing the parasitic capacitance between the source / drain contact structure 8 and the gate structure 5.

[0022] To address the aforementioned technical problem, embodiments of the present invention provide a semiconductor structure in which the source / drain contact structure contacts multiple source / drain doped regions of adjacent device regions along the second direction. The source / drain contact structure includes a first portion located on the source / drain doped regions and a second portion located on an isolation layer between adjacent first portions along the second direction and connected to the adjacent first portions. The top surface of the second portion is lower than the top surface of the first portion, thereby reducing the parallel facing area between the source / drain contact structure and the device gate structure, and further reducing the parasitic capacitance between the source / drain contact structure and the device gate structure, thus optimizing the performance of the semiconductor structure.

[0023] To address the aforementioned technical problem, this invention also provides a method for forming a semiconductor structure. A source / drain contact structure is formed on both sides of the device gate structure. Along a second direction, the source / drain contact structure contacts multiple source / drain doped regions of adjacent device regions. The source / drain contact structure includes a first portion located on the source / drain doped regions and a second portion located on an isolation layer between adjacent first portions along the second direction and connected to the adjacent first portions. The top surface of the second portion is lower than the top surface of the first portion, thereby reducing the parallel facing area between the source / drain contact structure and the device gate structure, and further reducing the parasitic capacitance between the source / drain contact structure and the device gate structure, thus optimizing the performance of the semiconductor structure.

[0024] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0025] refer to Figures 3 to 4 , Figure 3 A three-dimensional structural schematic diagram of an embodiment of the semiconductor structure of the present invention is shown. Figure 4 It shows Figure 3 A cross-sectional view along the d-d2 direction.

[0026] like Figures 3 to 4As shown, in this embodiment, the semiconductor structure includes: a substrate 100 and a plurality of protrusion structures 200 discretely disposed on the substrate 100. The protrusion structures 200 extend along a first direction D1 and are spaced apart along a second direction D2. Each protrusion structure 200 includes a protrusion portion 110 and a channel structure 120 located on the protrusion portion 110. The substrate 100 includes a plurality of device regions 100a arranged along the second direction D2. An isolation layer 130 is located on the substrate 100 and surrounds the protrusion portion 110, exposing the channel structure 120. A device gate structure 140 is located on the isolation layer 130 and spans the channel structure 120. Source / drain The doped region 160 is located within the channel structure 120 on both sides of the device gate structure 140; the source / drain contact structure 300 is located on both sides of the device gate structure 140 and along the second direction D2. The source / drain contact structure 300 is in contact with a plurality of source / drain doped regions 160 adjacent to the device region 100a. The source / drain contact structure 300 includes a first portion 310 located on the source / drain doped region 160 and a second portion 320 located on an isolation layer 130 between adjacent first portions 310 along the second direction D2 and connected to adjacent first portions 310. The top surface of the second portion 320 is lower than the top surface of the first portion 310.

[0027] Substrate 100 is used to provide a process platform for the formation of semiconductor structures.

[0028] The device region 100a is used to form a transistor.

[0029] In this embodiment, the substrate 100 is made of one or more of the following materials: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. As an example, the substrate 100 is a silicon substrate, that is, the material of the substrate 100 is single-crystal silicon.

[0030] The protrusion structure 200 includes a protrusion 110 and a channel structure 120 located on the protrusion 110.

[0031] The protrusion 110 is used to support the channel structure 120. The protrusion 110 is also used to form an isolation layer 130 to provide space so that the isolation layer 130 can surround the protrusion 110 and expose the channel structure 120, and so that the isolation layer 130 can isolate the substrate 100 and the subsequently formed device gate structure.

[0032] In this embodiment, the protrusion 110 and the substrate 100 are an integral structure, and the protrusion 110 and the substrate 100 are made of the same material, silicon. In other embodiments, the material of the protrusion may be different from the material of the substrate. The material of the protrusion may be other suitable materials, such as one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0033] The channel structure 120 is used to provide a conductive channel for the field-effect transistor.

[0034] In this embodiment, the material of the channel structure 120 includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. As an example, the material of the channel structure 120 is single-crystal silicon.

[0035] In this embodiment, the formation of a fin field-effect transistor is used as an example for explanation. The protrusion structure 200 is a fin, and the channel structure 120 is a corresponding effective fin. The effective fin is used to provide a conductive channel for the fin field-effect transistor. Accordingly, the channel structure 120 and the protrusion 110 are integral structures.

[0036] In other embodiments, when forming other types of field-effect transistors, the channel structure is correspondingly another type of channel structure.

[0037] For example, when forming a gate-all-around (GAA) transistor or a nanosheet field-effect transistor (NSFET), the channel structure is suspended at intervals on the protrusion. The channel structure includes one or more channel layers that are suspended at intervals in sequence, and the stacking direction of the channel layers is perpendicular to the substrate surface. The channel layers are used to provide conductive channels for the gate-all-around transistor or the nanosheet field-effect transistor.

[0038] The top surface of the isolation layer 130 is lower than the top surface of the protrusion structure 200.

[0039] The isolation layer 130 is used to isolate adjacent protrusions 110 and also to isolate the substrate 100 from the subsequent device gate structure.

[0040] In this embodiment, the material of the insulating layer 130 is silicon oxide. The material of the insulating layer 130 can also be other insulating materials, such as one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon germanium silicon oxide, boron nitride, boron carbonitride, and silicon germanium silicon oxide.

[0041] When the device is operating, the device gate structure 140 is used to control the opening and closing of the conductive channel of the device. In this embodiment, the device gate structure 140 is used to control the opening and closing of the conductive channel of the fin field-effect transistor, and the device gate structure 140 covers part of the top and part of the sidewall of the fin.

[0042] In other embodiments, when forming a fully enclosed gate transistor or a nanosheet field-effect transistor, the device gate structure surrounds the channel layer.

[0043] In this embodiment, the device gate structure 140 is a metal gate structure.

[0044] In this embodiment, the device gate structure 140 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) located on the gate dielectric layer.

[0045] The gate dielectric layer is used to achieve electrical insulation between the gate electrode layer and the conductive channel.

[0046] The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, and Al2O3.

[0047] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3. In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer.

[0048] The gate electrode layer is used as an external electrode for electrically connecting the device gate structure 140 to an external circuit. The material of the gate electrode layer includes one or more of TiN, TaN, Ti, Ta, TiAl, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

[0049] In a specific embodiment, the gate electrode layer may include: a capping layer (not shown), a work function layer (not shown), a barrier layer (not shown), and a metal electrode layer, which are stacked sequentially on the gate dielectric layer.

[0050] A gate sidewall 150 is also formed on the sidewall of the gate structure 140 of the device.

[0051] The gate sidewall 150 is used to define the formation location of the source / drain doped region 160, and the gate sidewall 150 is also used to protect the sidewall of the device gate structure.

[0052] In this embodiment, the material of the gate sidewall 150 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, silicon carbonitride, boron nitride, boron carbonitride, low-k materials, and ultra-low-k materials. The gate sidewall 150 is a single-layer or multi-layer structure. As an example, the gate sidewall 150 is a single-layer structure, and the material of the gate sidewall 150 is silicon nitride.

[0053] The source / drain doped region 160 is used as the source or drain of the field-effect transistor. When the field-effect transistor is working, the source / drain doped region 160 is used to provide a carrier source for the PMOS device.

[0054] In this embodiment, the source / drain doped region 160 includes a stress layer doped with ions. The stress layer is used to provide stress to the channel region, thereby improving the carrier mobility.

[0055] Specifically, when forming an NMOS transistor, the material of the source / drain doped region 160 is a stress layer doped with N-type ions. The material of the stress layer includes Si or SiC. The stress layer provides tensile stress to the channel region of the NMOS transistor, thereby improving the carrier mobility of the NMOS transistor. The N-type ions are P ions, As ions, or Sb ions.

[0056] When forming a PMOS transistor, the source and drain doped regions 160 are made of a stress layer doped with P-type ions. The stress layer is made of Si or SiGe. The stress layer provides compressive stress to the channel region of the PMOS transistor, which helps to improve the carrier mobility of the PMOS transistor. The P-type ions are B ions, Ga ions, or In ions.

[0057] It should be noted that the shape of the source / drain doped region 160 shown in the figure is only an example. In other embodiments, the source / drain doped region may have other shapes.

[0058] Along the second direction D2, the source / drain contact structure 300 contacts the source / drain doped regions 160 of a plurality of adjacent device regions 100a, and the top surface of the second portion 320 is lower than the top surface of the first portion 310, thereby reducing the parallel facing area between the source / drain contact structure 300 and the device gate structure 140, thereby reducing the parasitic capacitance between the source / drain contact structure 300 and the device gate structure 140, and optimizing the performance of the semiconductor structure.

[0059] The source / drain contact structure 300 is used to realize the electrical connection between the source / drain doped region 160 and external circuits or other interconnect structures.

[0060] In this embodiment, the source-drain contact structure 300 is located on both sides of the device gate structure 140 and the gate sidewall 150, so that the source-drain contact structure 300 and the device gate structure 140 are electrically isolated through the gate sidewall 150.

[0061] Along the second direction D2, the source-drain contact structure 300 contacts the source-drain doped regions 160 of a plurality of adjacent device regions 100a, thereby realizing the interconnection of the source-drain doped regions 160 of the plurality of device regions 100a, and also helps to increase the volume of the source-drain contact structure 300, thereby helping to reduce the resistance of the source-drain contact structure 300.

[0062] The source / drain contact structure 300 is made of a conductive material. In this embodiment, the source / drain contact structure 300 is made of a metallic material. Metallic materials have low resistivity, which helps to further reduce the resistance of the source / drain contact structure 300 and improve its conductivity. For example, the material of the source / drain contact structure 300 includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

[0063] As an example, the source / drain contact structure 300 is made of Co. Co has low resistivity, which helps reduce the resistance of the source / drain contact structure 300. Furthermore, Co has low chemical reactivity and weak electromigration, which helps improve the electromigration problem of the source / drain contact structure 300, thus facilitating device miniaturization. In addition, Co can be formed through an electrochemical plating process, which simplifies the process of forming the source / drain contact structure 300.

[0064] In this embodiment, a groove 301 is formed between the first portion 310 and the second portion 320. Specifically, the sidewall of the first portion 310 and the top surface of the second portion 320 form the groove 301.

[0065] It should be noted that the height difference between the top surfaces of the second portion 320 and the first portion 310 should not be too small or too large. If the height difference between the top surfaces of the second portion 320 and the first portion 310 is too small, the reduction effect on the parallel facing area between the source / drain contact structure 300 and the device gate structure 140 will be insignificant, and consequently, the reduction effect on the parasitic capacitance between the source / drain contact structure 300 and the device gate structure 140 will be insignificant. If the height difference between the top surfaces of the second portion 320 and the first portion 310 is too large, the volume reduction of the source / drain contact structure 300 will be too significant, which will be detrimental to reducing the resistance of the source / drain contact structure 300. Therefore, in this embodiment, the height difference between the top surfaces of the second portion 320 and the first portion 310 is 5 nm to 100 nm.

[0066] In this embodiment, a recess is formed in the isolation layer 130 between the source and drain doped regions 160 adjacent to the device region 100a along the second direction; the second portion 320 is also filled in the recess.

[0067] By forming a recess in the isolation layer 130 between the source / drain doped regions 160 adjacent to the device region 100a along the second direction, the source / drain contact structure 300 can be formed within the recess during the formation process. When a process with strong conformal coverage is used to form the source / drain contact structure 300, the bottom of the recess is lower than the bottom surface of the source / drain contact opening, so that the top surface of the source / drain contact structure 300 located in the recess is lower than the top surface of the source / drain contact structure 300 located on the source / drain doped region 160. In other words, without using an additional photomask, the top surface of the second part 320 can be lower than the top surface of the first part 310, which helps to save costs.

[0068] In this embodiment, the source-drain contact structure 300 is an integral structure, which is beneficial to reduce the resistance of the source-drain contact structure 300 and improve the electrical connection performance of the source-drain contact structure 300.

[0069] In this embodiment, the semiconductor structure further includes: a first dielectric layer 170 (e.g., Figure 4 As shown, the isolation layer 130 is located on the side of the device gate structure 140 and covers the source / drain doped region 160. The source / drain contact structure 300 is located within the first dielectric layer 170 on both sides of the device gate structure 140 and the gate sidewall 150.

[0070] The first dielectric layer 170 is an interlayer dielectric (ILD) used to isolate adjacent devices. In this embodiment, the material of the first dielectric layer 170 is silicon oxide. The material of the first dielectric layer 170 can also be other insulating materials.

[0071] In this embodiment, for ease of illustration and explanation, only the first dielectric layer 170 is shown in the cross-sectional view.

[0072] It should be noted that, in this embodiment, the semiconductor structure further includes: an etch barrier layer (not shown), located between the source / drain doped region 160 and the first dielectric layer 170, and between the isolation layer 130 and the first dielectric layer 170.

[0073] In the process of forming the source / drain contact structure 300, a source / drain contact opening is typically formed first through the first dielectric layer 170 above the source / drain doped region 160, and then the source / drain contact structure 300 is formed within the source / drain contact opening. The etching barrier layer is used to temporarily define the etching stop position during the process of forming the source / drain contact opening, thereby reducing the probability of damage to the source / drain doped region 160 caused by the process of forming the source / drain contact opening.

[0074] The etch barrier layer is made of a material that has etch selectivity with the first dielectric layer 170 to ensure that the etch barrier layer serves to define the etch stop position. As an example, the material of the etch barrier layer is silicon nitride.

[0075] It should be noted that, in this embodiment, the source / drain contact structure 300 penetrates the etch barrier layer and the first dielectric layer 170 on the source / drain doped region 160, thereby enabling the source / drain contact structure 300 to contact the source / drain doped region 160 and achieve electrical connection with the source / drain doped region 160.

[0076] In this embodiment, the first portion 310 and the second portion 320 form a groove 301; the semiconductor structure further includes a second dielectric layer 360, which fills the groove 301.

[0077] Specifically, in this embodiment, the top surface of the second part 320 is lower than the top surface of the first part 310, so that the top surface of the second part 320 and the side wall of the first part 310 form the groove 301.

[0078] A second dielectric layer 360 is filled into the groove 301, thereby providing a flat surface for the semiconductor structure formation process.

[0079] The material of the second dielectric layer 360 is an electrically insulating material. The material of the second dielectric layer 360 is silicon oxide. The material of the second dielectric layer 360 can also be other insulating materials.

[0080] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 5 to 15 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0081] The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.

[0082] refer to Figures 5 to 6 , Figure 5 This is a schematic diagram of the three-dimensional structure. Figure 6 for Figure 5 A cross-sectional view along the d-d2 direction provides a substrate 100 and a plurality of protrusion structures 200 discretely disposed on the substrate 100. The protrusion structures 200 extend along a first direction D1 and are spaced apart along a second direction D2. Each protrusion structure includes a protrusion portion 110 and a channel structure 120 located on the protrusion portion 110. The substrate 100 includes a plurality of device regions 100a arranged along the second direction. An isolation layer 130 is formed on the substrate 100 surrounding the protrusion portion 110, and the isolation layer 130 exposes the channel structure 120.

[0083] Substrate 100 is used to provide a process platform for the formation of semiconductor structures.

[0084] The device region 100a is used to form a transistor.

[0085] In this embodiment, the substrate 100 is made of one or more of the following materials: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. As an example, the substrate 100 is a silicon substrate, that is, the material of the substrate 100 is single-crystal silicon.

[0086] The protrusion structure 200 includes a protrusion 110 and a channel structure 120 located on the protrusion 110.

[0087] The protrusion 110 is used to support the channel structure 120. The protrusion 110 is also used to form an isolation layer 130 to provide space so that the isolation layer 130 can surround the protrusion 110 and expose the channel structure 120, and so that the isolation layer 130 can isolate the substrate 100 and the subsequently formed device gate structure.

[0088] In this embodiment, the protrusion 110 and the substrate 100 are an integral structure, and the protrusion 110 and the substrate 100 are made of the same material, silicon. In other embodiments, the material of the protrusion may be different from the material of the substrate. The material of the protrusion may be other suitable materials, such as one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0089] The channel structure 120 is used to provide a conductive channel for the field-effect transistor.

[0090] In this embodiment, the material of the channel structure 120 includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. As an example, the material of the channel structure 120 is single-crystal silicon.

[0091] In this embodiment, the formation of a fin field-effect transistor is used as an example for explanation. The protrusion structure 200 is a fin, and the channel structure 120 is a corresponding effective fin. The effective fin is used to provide a conductive channel for the fin field-effect transistor. Accordingly, the channel structure 120 and the protrusion 110 are integral structures.

[0092] In other embodiments, when forming other types of field-effect transistors, the channel structure is correspondingly another type of channel structure.

[0093] For example, when forming a gate-all-around (GAA) transistor or a nanosheet field-effect transistor (NSFET), the channel structure is suspended at intervals on the protrusion. The channel structure includes one or more channel layers that are suspended at intervals in sequence, and the stacking direction of the channel layers is perpendicular to the substrate surface. The channel layers are used to provide conductive channels for the gate-all-around transistor or the nanosheet field-effect transistor.

[0094] In the step of providing a substrate, a sacrificial layer is formed between the channel structure and the protrusion, or between adjacent channel layers in the channel structure. The sacrificial layer is used to support the channel layer, thereby providing a process basis for the subsequent implementation of the spacing and floating arrangement of the channel layer. The sacrificial layer is also used to occupy space for the subsequent formation of the device gate structure.

[0095] The top surface of the isolation layer 130 is lower than the top surface of the protrusion structure 200.

[0096] The isolation layer 130 is used to isolate adjacent protrusions 110 and also to isolate the substrate 100 from the subsequent device gate structure.

[0097] In this embodiment, the material of the insulating layer 130 is silicon oxide. The material of the insulating layer 130 can also be other insulating materials, such as one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon germanium silicon oxide, boron nitride, boron carbonitride, and silicon germanium silicon oxide.

[0098] refer to Figure 7 and Figure 8 , Figure 7 This is a schematic diagram of the three-dimensional structure. Figure 8 for Figure 7 A cross-sectional view along the d-d2 direction shows a device gate structure 140 located on the isolation layer 130 and spanning the channel structure 120, and source / drain doped regions 160 located in the channel structures 120 on both sides of the device gate structure 140.

[0099] When the device is operating, the device gate structure 140 is used to control the opening and closing of the conductive channel of the device. In this embodiment, the device gate structure 140 is used to control the opening and closing of the conductive channel of the fin field-effect transistor, and the device gate structure 140 covers part of the top and part of the sidewall of the fin.

[0100] In other embodiments, when forming a fully enclosed gate transistor or a nanosheet field-effect transistor, the device gate structure surrounds the channel layer.

[0101] In this embodiment, the device gate structure 140 is a metal gate structure.

[0102] In this embodiment, the device gate structure 140 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) located on the gate dielectric layer.

[0103] The gate dielectric layer is used to achieve electrical insulation between the gate electrode layer and the conductive channel.

[0104] The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, and Al2O3.

[0105] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3. In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer.

[0106] The gate electrode layer is used as an external electrode for electrically connecting the device gate structure 140 to an external circuit. The material of the gate electrode layer includes one or more of TiN, TaN, Ti, Ta, TiAl, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

[0107] In a specific embodiment, the gate electrode layer may include: a capping layer (not shown), a work function layer (not shown), a barrier layer (not shown), and a metal electrode layer, which are stacked sequentially on the gate dielectric layer.

[0108] A gate sidewall 150 is also formed on the sidewall of the gate structure 140 of the device.

[0109] The gate sidewall 150 is used to define the formation location of the source / drain doped region 160, and the gate sidewall 150 is also used to protect the sidewall of the device gate structure.

[0110] In this embodiment, the material of the gate sidewall 150 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, silicon carbonitride, boron nitride, boron carbonitride, low-k materials, and ultra-low-k materials. The gate sidewall 150 is a single-layer or multi-layer structure. As an example, the gate sidewall 150 is a single-layer structure, and the material of the gate sidewall 150 is silicon nitride.

[0111] The source / drain doped region 160 is used as the source or drain of the field-effect transistor. When the field-effect transistor is working, the source / drain doped region 160 is used to provide a carrier source for the PMOS device.

[0112] In this embodiment, the source / drain doped region 160 includes a stress layer doped with ions. The stress layer is used to provide stress to the channel region, thereby improving the carrier mobility.

[0113] Specifically, when forming an NMOS transistor, the material of the source / drain doped region 160 is a stress layer doped with N-type ions. The material of the stress layer includes Si or SiC. The stress layer provides tensile stress to the channel region of the NMOS transistor, thereby improving the carrier mobility of the NMOS transistor. The N-type ions are P ions, As ions, or Sb ions.

[0114] When forming a PMOS transistor, the source and drain doped regions 160 are made of a stress layer doped with P-type ions. The stress layer is made of Si or SiGe. The stress layer provides compressive stress to the channel region of the PMOS transistor, which helps to improve the carrier mobility of the PMOS transistor. The P-type ions are B ions, Ga ions, or In ions.

[0115] It should be noted that the shape of the source / drain doped region 160 shown in the figure is only an example. In other embodiments, the source / drain doped region may have other shapes.

[0116] It should also be noted that, in this embodiment, during the steps of forming the device gate structure 140 and the source / drain doped region 160, an etch barrier layer (not shown) is formed on the source / drain doped region 160 and the isolation layer 130, and a first dielectric layer 170 covering the etch barrier layer is formed on the side of the device gate structure 140.

[0117] In the subsequent steps of forming the source-drain contact structure, a source-drain contact opening is usually formed first through the first dielectric layer 170 above the source-drain doped region 160, and then the source-drain contact structure is formed in the source-drain contact opening. The etching barrier layer is used to temporarily define the etching stop position during the formation of the source-drain contact opening, thereby reducing the probability of damage to the source-drain doped region 160 caused by the process of forming the source-drain contact opening.

[0118] The etch barrier layer is made of a material that has etch selectivity with the first dielectric layer 170 to ensure that the etch barrier layer serves to define the etch stop position. As an example, the material of the etch barrier layer is silicon nitride.

[0119] The first dielectric layer 170 is an interlayer dielectric (ILD) used to isolate adjacent devices. In this embodiment, the material of the first dielectric layer 170 is silicon oxide. The material of the first dielectric layer 170 can also be other insulating materials.

[0120] In this embodiment, for ease of illustration and explanation, only the first dielectric layer 170 is shown in the cross-sectional view.

[0121] refer to Figures 9 to 12 Source / drain contact structures 300 are formed on both sides of the device gate structure 140. Along the second direction D2, the source / drain contact structures 300 are in contact with a plurality of source / drain doped regions 160 adjacent to the device region 100a. The source / drain contact structures 300 include a first portion 310 located on the source / drain doped region 160 and a second portion 320 located on an isolation layer 130 between adjacent first portions 310 along the second direction D2 and connected to adjacent first portions 310. The top surface of the second portion 320 is lower than the top surface of the first portion 310.

[0122] Along the second direction D2, the source / drain contact structure 300 contacts the source / drain doped regions 160 of a plurality of adjacent device regions 100a, and the top surface of the second portion 320 is lower than the top surface of the first portion 310, thereby reducing the parallel facing area between the source / drain contact structure 300 and the device gate structure 140, thereby reducing the parasitic capacitance between the source / drain contact structure 300 and the device gate structure 140, and optimizing the performance of the semiconductor structure.

[0123] The source / drain contact structure 300 is used to realize the electrical connection between the source / drain doped region 160 and external circuits or other interconnect structures.

[0124] In this embodiment, during the step of forming the source-drain contact structure 300, the source-drain contact structure 300 is located on both sides of the device gate structure 140 and the gate sidewall 150, thereby achieving electrical isolation between the source-drain contact structure 300 and the device gate structure 140 through the gate sidewall 150.

[0125] Along the second direction D2, the source-drain contact structure 300 contacts the source-drain doped regions 160 of a plurality of adjacent device regions 100a, thereby realizing the interconnection of the source-drain doped regions 160 of the plurality of device regions 100a, and also helps to increase the volume of the source-drain contact structure 300, thereby helping to reduce the resistance of the source-drain contact structure 300.

[0126] The source / drain contact structure 300 is made of a conductive material. In this embodiment, the source / drain contact structure 300 is made of a metallic material. Metallic materials have low resistivity, which helps to further reduce the resistance of the source / drain contact structure 300 and improve its conductivity. For example, the material of the source / drain contact structure 300 includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

[0127] As an example, the source / drain contact structure 300 is made of Co. Co has low resistivity, which helps reduce the resistance of the source / drain contact structure 300. Furthermore, Co has low chemical reactivity and weak electromigration, which helps improve the electromigration problem of the source / drain contact structure 300, thus facilitating device miniaturization. In addition, Co can be formed through an electrochemical plating process, which simplifies the process of forming the source / drain contact structure 300.

[0128] It should be noted that, in this embodiment, the source / drain contact structure 300 penetrates the etch barrier layer and the first dielectric layer 170 on the source / drain doped region 160, thereby enabling the source / drain contact structure 300 to contact the source / drain doped region 160 and achieve electrical connection with the source / drain doped region 160.

[0129] In this embodiment, a groove 301 is formed between the first portion 310 and the second portion 320. Specifically, the sidewall of the first portion 310 and the top surface of the second portion 320 form the groove 301.

[0130] It should be noted that the height difference between the top surfaces of the second portion 320 and the first portion 310 should not be too small or too large. If the height difference between the top surfaces of the second portion 320 and the first portion 310 is too small, the reduction effect on the parallel facing area between the source / drain contact structure 300 and the device gate structure 140 will be insignificant, and consequently, the reduction effect on the parasitic capacitance between the source / drain contact structure 300 and the device gate structure 140 will be insignificant. If the height difference between the top surfaces of the second portion 320 and the first portion 310 is too large, the volume reduction of the source / drain contact structure 300 will be too significant, which will be detrimental to reducing the resistance of the source / drain contact structure 300. Therefore, in this embodiment, the height difference between the top surfaces of the second portion 320 and the first portion 310 is 5 nm to 100 nm.

[0131] The steps for forming the source-drain contact structure 300 in this embodiment will be described in detail below with reference to the accompanying drawings.

[0132] like Figures 9 to 10 As shown, source / drain contact openings 190 are formed on both sides of the device gate structure 140 (e.g., Figure 10 As shown, the source / drain doped regions 160 of the adjacent device region 100a along the second direction D2 and the isolation layer 130 located between the source / drain doped regions 160 of the adjacent device region 100a along the second direction D2 are exposed.

[0133] The source / drain contact opening 190 is used to provide a spatial location for forming the source / drain contact structure.

[0134] The source / drain contact opening 190 exposes the source / drain doped region 160 of the adjacent device region 100a along the second direction D2 and the isolation layer 130 between the source / drain doped region 160 of the adjacent device region 100a along the second direction D2, so that the source / drain contact structure subsequently formed in the source / drain contact opening 190 can connect the source / drain doped region 160 of the adjacent device region 100a.

[0135] It should be noted that, in the step of forming the source-drain contact opening 190, a recess 330 is formed in the isolation layer 130 exposed at the bottom of the source-drain contact opening 190.

[0136] By forming the recess 330 in the isolation layer 130 that exposes the bottom of the source / drain contact opening 190, the source / drain contact structure can be formed within the recess 330 during the subsequent formation of the source / drain contact structure. When a process with strong conformal coverage is used to form the source / drain contact structure, since the bottom of the recess 330 is lower than the bottom surface of the source / drain contact opening 190, the top surface of the source / drain contact structure located in the recess 330 can be lower than the top surface of the source / drain contact structure located on the source / drain doped region 160. In other words, the purpose of the top surface of the second part being lower than the top surface of the first part can be achieved without using an additional photomask, thereby saving costs.

[0137] Specifically, the steps of forming the source / drain contact opening 190 and the recess 330 include: as follows Figure 9 As shown, a primary etching process is performed on the first dielectric layer 170 on the source / drain doped regions 160 and on the isolation layer 130 located between adjacent source / drain doped regions 160 along the second direction D2 to form an initial opening 195, which exposes the etch barrier layer (not shown); as Figure 10 As shown, the etch barrier layer exposed by the initial opening 195 is overetched to form the source / drain contact opening 190 in the first dielectric layer 170; wherein, during the overetching process, the isolation layer 130 below the initial opening 195 is also overetched to form the recess 330 in the isolation layer 130.

[0138] By over-etching the etch barrier layer exposed by the initial opening 195, the recess 330 is formed using the over-etching process. This integrates the process of forming the recess 330 with the process of forming the source / drain contact opening 190, which improves process integration and process compatibility. Furthermore, it eliminates the need for an additional photomask to form the recess 330 in the isolation layer 130, thus saving costs.

[0139] In the step of forming the initial opening 195, the etching barrier layer can be used to define the etching stop position, thereby reducing the probability of the process of forming the initial opening 195 damaging the source / drain doped region 160, and ensuring the integrity and formation quality of the source / drain doped region 160.

[0140] In this embodiment, before forming the initial opening 195, a hard mask layer 180 is also formed on the first dielectric layer 170, and the hard mask layer 180 is used as an etching mask for forming the initial opening 195.

[0141] The hard mask layer 180 is made of a material that has etching selectivity with the material of the first dielectric layer 170, such as silicon nitride, aluminum oxide, aluminum nitride, tantalum nitride, etc.

[0142] As one embodiment, an anisotropic dry etching process is employed, using the hard mask layer 180 as a mask, to perform main etching on the first dielectric layer 170 on the source / drain doped regions 160 and on the isolation layer 130 located between adjacent source / drain doped regions 160 along the second direction D2. The anisotropic dry etching process possesses the characteristics of anisotropic etching, and offers high etching precision and process controllability, which is beneficial in ensuring that the position, size, and morphology of the initial opening 195 meet process requirements.

[0143] As one embodiment, a wet etching process is used to overetch the etch barrier layer and the isolation layer 130 exposed by the initial opening 195. The wet etching process has isotropic etching characteristics, which makes it easy to completely remove the etch barrier layer located on the surface of the source / drain doped region 140. Furthermore, the wet etching process can easily achieve a large etch selectivity, thereby helping to reduce damage to the source / drain doped region 140.

[0144] In other embodiments, other etching processes (such as dry etching) may be used to overetch the etch barrier layer and the isolation layer exposed by the initial opening.

[0145] like Figure 11 and Figure 12 As shown, Figure 11 This is a schematic diagram of the three-dimensional structure. Figure 12 for Figure 11 A cross-sectional view along the d-d2 direction shows that the source-drain contact structure 300 is formed within the source-drain contact opening 190.

[0146] In this embodiment, in the step of forming the source-drain contact structure 300, the source-drain contact structure 300 fills the recess 330 and the source-drain contact opening 190.

[0147] As one embodiment, an electrochemical plating process is used to form the source / drain contact structure 300 within the recess 330 and the source / drain contact opening 190. The electrochemical plating process forms the source / drain contact structure 300 in a bottom-up growth manner on a seed layer (not shown), allowing the source / drain contact structure 300 to grow based on the morphology of the source / drain contact opening 190 and the recess 330. This results in the top surface of the second portion 320 of the source / drain contact structure 300 being higher than the top surface of the first portion 310, eliminating the need to remove the source / drain contact structure material located on the isolation layer 130 between adjacent source / drain doped regions 160 along the second direction D2. Furthermore, the electrochemical plating process helps reduce the probability of defects such as voids in the source / drain contact structure 300. Additionally, the electroplating process has lower costs and improves the efficiency of forming the source / drain contact structure 300, thereby saving process time and improving manufacturing efficiency.

[0148] In this embodiment, the source / drain contact structure 300 is formed using an electrochemical plating process as an example. In other embodiments, other process steps may be used to form the source / drain contact structure.

[0149] For example, the step of forming the source / drain contact structure within the source / drain contact opening may further include: filling the source / drain contact opening with conductive material; removing a portion of the conductive material on the isolation layer between the source / drain doped regions of adjacent device regions, with the remaining conductive material on the source / drain doped regions used as the first part, and the remaining conductive material on the isolation layer and connected to the first part used as the second part.

[0150] The steps for forming the conductive material may include one or more of the following processes: electrochemical plating, chemical vapor deposition, and physical vapor deposition.

[0151] In this embodiment, the first portion 310 and the second portion 320 form a groove 301; Reference Figure 13 , Figure 14 and Figure 15 , Figure 13 This is a cross-sectional view. Figure 14 This is a schematic diagram of the three-dimensional structure. Figure 15 for Figure 14 A cross-sectional view along the d-d2 direction shows that the method of forming the semiconductor structure further includes filling the groove 301 with a second dielectric layer 360.

[0152] A second dielectric layer 360 is filled into the groove 301 to provide a flat surface for subsequent process steps.

[0153] The material of the second dielectric layer 360 is an electrically insulating material. The material of the second dielectric layer 360 is silicon oxide. The material of the second dielectric layer 360 can also be other insulating materials.

[0154] In this embodiment, the step of forming the second dielectric layer 360 includes: as follows Figure 13 As shown, a dielectric material layer 350 is filled in the groove 301, and the dielectric material layer 350 is also formed on the hard mask layer 180; as Figure 14 and Figure 15 As shown, the dielectric material layer 350 above the top surface of the first dielectric layer 170 is removed, and the remaining dielectric material layer 350 filling the groove 301 is used as the second dielectric layer 360.

[0155] Specifically, one or more of the following processes can be used to form the dielectric material layer 350: chemical vapor deposition, atomic layer deposition, flow-through chemical vapor deposition, high aspect ratio deposition, and plasma-enhanced chemical vapor deposition.

[0156] In this embodiment, a planarization process is used to remove the dielectric material layer 350 that is higher than the top surface of the first dielectric layer 170.

[0157] In the step of removing the dielectric material layer 350 above the top surface of the first dielectric layer 170, the hard mask layer 180 and the source / drain contact structure 300 above the top surface of the first dielectric layer 170 are also removed.

[0158] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, include: The substrate and a plurality of protrusions discretely disposed on the substrate, the protrusions extending along a first direction and spaced apart along a second direction, each protrusion including a protrusion portion and a channel structure located on the protrusion portion; the substrate includes a plurality of device regions arranged along the second direction; An isolation layer is located on the substrate and surrounds the protrusion and exposes the channel structure, and a recess is formed in the isolation layer between the source and drain doped regions of the adjacent device region along the second direction; The device gate structure is located on the isolation layer and spans the channel structure; The source and drain doped regions are located within the channel structures on both sides of the gate structure of the device; A source / drain contact structure is located on both sides of the gate structure of the device and along the second direction. The source / drain contact structure contacts a plurality of source / drain doped regions of adjacent device regions. The source / drain contact structure includes a first portion located on the source / drain doped regions and a second portion located on an isolation layer between adjacent first portions along the second direction and connected to adjacent first portions. The second portion is connected to adjacent first portions on both sides along the second direction. The second portion is also filled in the recess such that the top surface of the second portion is lower than the top surface of the first portion.

2. The semiconductor structure of claim 1, wherein, The source-drain contact structure is an integral structure.

3. The semiconductor structure of claim 1, wherein, The source-drain contact structure is made of one or more of the following materials: Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

4. The semiconductor structure of claim 1, wherein, The semiconductor structure further includes: a first dielectric layer, located on an isolation layer on the side of the device gate structure and covering the source / drain doped regions; and a gate sidewall, located on the sidewall of the device gate structure. The source / drain contact structure is located within the first dielectric layer on both sides of the gate structure and the gate sidewall.

5. The semiconductor structure as described in claim 1, characterized in that, The first part and the second part form a groove; the semiconductor structure further includes a second dielectric layer filling the groove.

6. The semiconductor structure as described in claim 1, characterized in that, The height difference between the top surface of the second part and the first part is 5nm to 100nm.

7. The semiconductor structure as described in claim 4, characterized in that, The material of the gate sidewall includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and low-k materials.

8. The semiconductor structure as described in claim 1, characterized in that, The protruding structure is a fin, and the channel structure is an effective fin; the device gate structure covers part of the top and part of the sidewall of the fin. Alternatively, the channel structure is suspended at intervals on the protrusion, and the channel structure includes one or more channel layers that are suspended at intervals in sequence, with the stacking direction of the channel layers perpendicular to the substrate surface; the device gate structure surrounds the channel layers.

9. The semiconductor structure as described in claim 1, characterized in that, The substrate material includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; The material of the protrusion includes one or more of the following: single crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; The channel structure is made of one or more of the following materials: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; The material of the isolation layer includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon germanium oxide, boron nitride, and boron carbonitride.

10. The semiconductor structure as claimed in claim 1, characterized in that, The gate structure of the device includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer.

11. The semiconductor structure as claimed in claim 10, characterized in that, The material of the gate dielectric layer includes one or more of the following: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, Al2O3, silicon oxide, and nitrogen-doped silicon oxide; The material of the gate electrode layer includes any one or more of TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

12. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, and a plurality of protrusion structures discretely disposed on the substrate are provided. The protrusion structures extend along a first direction and are spaced apart along a second direction. Each protrusion structure includes a protrusion portion and a channel structure located on the protrusion portion. The substrate includes a plurality of device regions arranged along the second direction. An isolation layer is formed on the substrate surrounding the protrusion portion, and the isolation layer exposes the channel structure. A device gate structure is formed on the isolation layer and spans the channel structure, and source / drain doped regions are formed within the channel structures on both sides of the device gate structure. Source / drain contact structures are formed on both sides of the device gate structure. Along the second direction, the source / drain contact structures are in contact with multiple source / drain doped regions of adjacent device regions. The source / drain contact structures include a first portion located on the source / drain doped regions and a second portion located on an isolation layer between adjacent first portions along the second direction and connected to the adjacent first portions. The second portion is connected to the adjacent first portions on both sides along the second direction. In the step of forming the source / drain contact structures, a recess is formed in the isolation layer between the source / drain doped regions of adjacent device regions along the second direction. The second portion is also filled in the recess, such that the top surface of the second portion is lower than the top surface of the first portion.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The step of forming the source-drain contact structure includes: forming source-drain contact openings on both sides of the device gate structure to expose the source-drain doped regions of adjacent device regions along the second direction and the isolation layer between the source-drain doped regions of adjacent device regions along the second direction. The source-drain contact structure is formed within the source-drain contact opening.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the step of forming the source-drain contact opening, the recess is formed in the isolation layer exposed at the bottom of the source-drain contact opening; In the step of forming the source-drain contact structure, the source-drain contact structure fills the recess and the source-drain contact opening.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, In the step of forming the device gate structure and the source / drain doped region, an etch barrier layer is formed on the source / drain doped region and the isolation layer, and a first dielectric layer covering the etch barrier layer is formed on the side of the device gate structure. The steps of forming the source / drain contact opening and the recess include: performing a main etching process on the first dielectric layer on the source / drain doped region and on the isolation layer located between adjacent source / drain doped regions along the second direction to form an initial opening, the initial opening exposing the etch barrier layer; performing an over-etching process on the etch barrier layer exposed by the initial opening to form the source / drain contact opening in the first dielectric layer; wherein, during the over-etching process, the isolation layer below the initial opening is also over-etched to form the recess in the isolation layer.

16. The method for forming a semiconductor structure as described in claim 13 or 14, characterized in that, The step of forming the source-drain contact structure within the source-drain contact opening includes: filling the source-drain contact opening with conductive material; A portion of the conductive material on the isolation layer between the source and drain doped regions of adjacent device regions is removed, and the remaining conductive material on the source and drain doped regions is used as the first part, and the remaining conductive material on the isolation layer and connected to the first part is used as the second part.

17. The method for forming a semiconductor structure as described in claim 12, characterized in that, The process for forming the source-drain contact structure includes an electrochemical plating process.

18. The method for forming a semiconductor structure as described in claim 12, characterized in that, A groove is formed between the first part and the second part; the method of forming the semiconductor structure further includes filling the groove with a second dielectric layer.

19. The method for forming a semiconductor structure as described in claim 12, characterized in that, A gate sidewall is also formed on the sidewall of the gate structure of the device; In the step of forming the source-drain contact structure, the source-drain contact structure is located on both sides of the device gate structure and the gate sidewall.

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