An LED chip and its fabrication method

Abstract

This application discloses an LED chip and its fabrication method. The LED chip includes a Si substrate, a first buffer layer, a second buffer layer, and a GaN light-emitting layer composed of a first type GaN layer, a multi-quantum-well layer, and a second type GaN layer, stacked sequentially. The first buffer layer is an AlN layer, and the second buffer layer includes multiple AlGaN layers, thereby allowing the Si substrate to gradually transition to the GaN light-emitting layer through the AlN layers. Furthermore, in the second buffer layer, a defect-blocking layer is inserted between two adjacent AlGaN layers, and the defect-blocking layer includes at least a SiN layer. This allows the SiN layer to suppress some dislocations and defects in the AlGaN layer and effectively guide the release of stress in the AlGaN layer, thereby improving the internal stress condition and crystal quality of the subsequently grown GaN light-emitting layer, reducing defect density, improving the wavelength uniformity and internal quantum efficiency of the LED chip, and increasing brightness.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to an LED chip and its fabrication method. Background Technology

[0002] Light-emitting diodes (LEDs), as a new type of semiconductor solid-state light source, have created a new wave in the lighting field due to their superior performance and are hailed as the fourth generation of green lighting. GaN, as one of the representatives of third-generation semiconductor materials, has excellent properties such as direct bandgap, wide bandgap, high breakdown electric field and high thermal conductivity, making it the main material for the light-emitting layer in the fabrication of blue and white LED chips.

[0003] High-quality GaN emissive layers are generally obtained through heteroepitaxial growth. Sapphire, a commonly used substrate for growing GaN emissive layers, possesses stable physicochemical properties; however, it exhibits significant lattice mismatch (16%) and thermal mismatch (25%) with GaN, resulting in poor quality GaN emissive layers. While SiC has a lattice mismatch of only 3.5% with GaN, its thermal mismatch (25.6%) is comparable to that of sapphire. Furthermore, SiC is expensive, and its epitaxial growth technology is monopolized by Cree, hindering widespread adoption. In contrast, Si substrates offer numerous advantages, including low cost, large single-crystal size, high quality, high thermal conductivity, and good electrical conductivity. Moreover, GaN emissive layers on Si substrates hold promise for integration with Si-based microelectronic counters. Therefore, LED chips with GaN emissive layers on Si substrates are gaining increasing attention.

[0004] However, due to the large lattice and thermal mismatch between Si and GaN materials, the quality of GaN light-emitting layers currently prepared on Si substrates is not as good as that prepared on sapphire substrates. The defect density is higher, which makes the LED epitaxial wafers more prone to stress, cracking, and warping. At the same time, the wavelength uniformity is poor, the internal quantum efficiency is low, and the brightness is low. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides an LED chip and its fabrication method to improve the quality of the GaN light-emitting layer fabricated on a Si substrate, reduce the defect density in the GaN light-emitting layer, thereby obtaining a high-quality LED epitaxial wafer with fewer defects and lower stress, achieving the goal of improving wavelength uniformity and internal quantum efficiency, and thus increasing brightness.

[0006] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0007] An LED chip, comprising:

[0008] Si substrate;

[0009] A first buffer layer located on one side of the Si substrate, wherein the first buffer layer is an AlN layer;

[0010] A second buffer layer is located on the side of the first buffer layer away from the Si substrate. The second buffer layer includes AlGaN layers and defect blocking layers arranged alternately in the direction away from the Si substrate. In the second buffer layer, the layer closest to the Si substrate is an AlGaN layer. The defect blocking layer includes at least a SiN layer.

[0011] And a first type GaN layer, a multiple quantum well layer, and a second type GaN layer are arranged sequentially along the direction away from the Si substrate on the side of the second buffer layer away from the Si substrate.

[0012] Optionally, in the second buffer layer, the Al composition of the AlGaN layer gradually decreases along the direction away from the Si substrate.

[0013] Optionally, in the second buffer layer, the thickness of the defect barrier layer gradually decreases along the direction away from the Si substrate.

[0014] Optionally, the defect blocking layer is a SiN layer.

[0015] Optionally, the defect blocking layer is a superlattice layer, which includes SiN layers and InN layers arranged alternately in a direction away from the Si substrate.

[0016] A method for fabricating an LED chip, comprising:

[0017] Provide a Si substrate;

[0018] A first buffer layer is formed on one side of the Si substrate, and the first buffer layer is an AlN layer;

[0019] On the side of the first buffer layer away from the Si substrate, AlGaN layers and defect barrier layers are alternately formed along the direction away from the Si substrate to form a second buffer layer. In the second buffer layer, the layer closest to the Si substrate is an AlGaN layer, and the defect barrier layer includes at least a SiN layer.

[0020] On the side of the second buffer layer away from the Si substrate, a first type GaN layer, a multiple quantum well layer, and a second type GaN layer are sequentially formed along the direction away from the Si substrate.

[0021] Optionally, in the second buffer layer, the Al composition of the AlGaN layer gradually decreases along the direction away from the Si substrate.

[0022] Optionally, the formation process of the defect barrier layer includes:

[0023] Ammonia and silane are introduced into the reaction chamber at a first preset temperature and a first preset pressure for a first preset time to grow a SiN layer as the defect barrier layer.

[0024] Optionally, the formation process of the defect barrier layer includes:

[0025] Ammonia and silane are introduced into the reaction chamber at a second preset temperature and a second preset pressure for a second preset time to grow a SiN layer.

[0026] Stop introducing silane into the reaction chamber, continue to introduce ammonia into the reaction chamber, and introduce an indium source into the reaction chamber. After a third preset time, grow an InN layer.

[0027] The defect barrier layer is formed by alternating growth of SiN and InN layers, wherein the defect barrier layer is either a SiN layer or a superlattice layer, and the superlattice layer comprises SiN and InN layers arranged alternately in a direction away from the Si substrate.

[0028] Optionally, during the growth of the SiN layer, the flow rate of ammonia gas introduced into the reaction chamber ranges from 2L to 20L, including the endpoint value; the flow rate of silane introduced into the reaction chamber ranges from 200sccm to 2000sccm, including the endpoint value.

[0029] Compared with existing technologies, the above technical solution has the following advantages:

[0030] The LED chip provided in this application includes a Si substrate, a first buffer layer, a second buffer layer, a first type GaN layer, a multi-quantum-well layer, and a second type GaN layer stacked sequentially. The first type GaN layer, the multi-quantum-well layer, and the second type GaN layer constitute a GaN light-emitting layer. The first buffer layer is an AlN layer, and the second buffer layer includes multiple AlGaN layers, thus allowing the Si substrate to gradually transition to the GaN light-emitting layer through the AlN and AlGaN layers. However, when growing an AlN layer on the Si substrate, the significant lattice mismatch between the two layers generates a large number of dislocations and defects, accompanied by internal stress. If the AlN layer transitions to the GaN light-emitting layer only through the AlGaN layer on the side away from the Si substrate, these defects will extend into the GaN light-emitting layer along with the growth of the AlGaN layer. This results in uneven stress distribution and high defect density in the GaN light-emitting layer (especially the multi-quantum-well layer), negatively impacting wavelength uniformity and internal quantum efficiency. Therefore, in the LED chip provided in this application embodiment, a second buffer layer is provided, which includes AlGaN layers and defect blocking layers arranged alternately along the direction away from the Si substrate. In the second buffer layer, the layer closest to the Si substrate is an AlGaN layer. That is, a defect blocking layer is inserted between two adjacent AlGaN layers, and the defect blocking layer includes at least a SiN layer. In this way, the SiN layer is used to deflect the direction of dislocations and defects in the AlGaN layer, thereby canceling out some dislocations and defects in the AlGaN layer, isolating some dislocations and defects in the AlGaN layer, and effectively guiding the release of stress in the AlGaN layer. This improves the internal stress condition and crystal quality of the subsequently grown GaN light-emitting layer (especially the multi-quantum well layer), reduces its defect density, and obtains a high-quality LED epitaxial wafer with fewer defects and lower stress. This improves the wavelength uniformity and internal quantum efficiency of the LED chip and increases its brightness. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the structure of an LED chip provided in an embodiment of this application;

[0033] Figure 2 A partial transmission electron microscope (TEM) image of an LED chip provided in an embodiment of this application;

[0034] Figure 3This is a schematic diagram of another LED chip structure provided in an embodiment of this application;

[0035] Figure 4 This is a schematic diagram of the structure of another LED chip provided in an embodiment of this application;

[0036] Figure 5 This is a schematic diagram of another LED chip structure provided in the embodiments of this application;

[0037] Figure 6 This is a schematic diagram of the structure of another LED chip provided in an embodiment of this application;

[0038] Figure 7 A comparative schematic diagram of X-ray diffraction (XRD) patterns of an LED chip with an AlGaN layer whose second buffer layer is only an Al composition gradient and an LED chip with a second buffer layer consisting of multiple SiN defect blocking layers inserted into an AlGaN layer with an Al composition gradient.

[0039] Figure 8 This is a schematic flowchart illustrating the method for fabricating an LED chip according to an embodiment of this application.

[0040] Figures 9(a)-9(c) This is a schematic diagram of the device structure corresponding to each process step in the LED chip fabrication method provided in the embodiments of this application. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0042] As described in the background section, due to the large lattice and thermal mismatch between Si and GaN materials, the quality of GaN light-emitting layers currently prepared on Si substrates is not as good as that prepared on sapphire substrates. The defect density is higher, which makes the LED epitaxial wafers more prone to stress, cracking, and warping. At the same time, the wavelength uniformity is poor, the internal quantum efficiency is low, and the brightness is low.

[0043] In view of this, embodiments of this application provide an LED chip, Figure 1 This application provides a schematic diagram of the structure of an LED chip according to an embodiment of the present application. Figure 1 As shown, the LED chip includes:

[0044] Si substrate 10;

[0045] A first buffer layer 20 is located on one side of the Si substrate 10, and the first buffer layer 20 is an AlN layer;

[0046] The second buffer layer 30 is located on the side of the first buffer layer 20 away from the Si substrate 10. The second buffer layer 30 includes AlGaN layers 31 and defect blocking layers 32 arranged alternately in the direction away from the Si substrate 10. In the second buffer layer 30, the layer closest to the Si substrate 10 is the AlGaN layer 31, and the defect blocking layer 32 includes at least a SiN layer.

[0047] And a first type GaN layer 40, a multi-quantum well layer 50, and a second type GaN layer 60 are arranged sequentially along the direction away from the Si substrate 10 on the side of the second buffer layer 30 away from the Si substrate 10.

[0048] In this embodiment, the crystal orientation of the Si substrate 10 can be 111.

[0049] In this embodiment, the first type GaN layer 40, the multiple quantum well layer 50, and the second type GaN layer 60 constitute a GaN light-emitting layer. The multiple quantum well layer 50 may include an InGaN potential well layer and a GaN barrier layer arranged alternately along the direction away from the Si substrate 10. The internal stress state and crystal quality of the InGaN potential well layer and the GaN barrier layer in the multiple quantum well layer 50 determine the wavelength uniformity, internal quantum efficiency, and brightness of the LED chip.

[0050] Optionally, if the first type GaN layer 40 is an N-type GaN layer, then the second type GaN layer 60 is a P-type GaN layer, or vice versa, if the first type GaN layer 40 is a P-type GaN layer, then the second type GaN layer 60 is an N-type GaN layer, depending on the specific situation.

[0051] In this embodiment, a first buffer layer 20 and a second buffer layer 30 are first grown on the Si substrate 10. The first buffer layer 20 is an AlN layer, and the second buffer layer 30 includes multiple AlGaN layers 31. Then, a first type GaN layer 40, a multiple quantum well layer 50, and a second type GaN layer 60 are sequentially grown on the side of the second buffer layer 30 away from the Si substrate 10, thereby gradually transitioning the Si substrate to the GaN light-emitting layer through the AlN layer 20 and the AlGaN layer 31.

[0052] The inventors discovered that when growing an AlN layer 20 on a Si substrate 10, a large number of dislocations and defects are generated due to the huge lattice mismatch between the two, accompanied by the generation of internal stress. If the AlN layer 20 is transitioned to the GaN light-emitting layer only through an AlGaN layer 31 on the side away from the Si substrate 10, these defects will extend to the GaN light-emitting layer (especially the multi-quantum well layer 50) as the AlGaN buffer layer 31 grows. This results in uneven stress distribution and high defect density in the GaN light-emitting layer (especially the multi-quantum well layer 50), which has a negative impact on wavelength uniformity and internal quantum efficiency. Therefore, in the LED chip provided in this application embodiment, a second buffer layer 30 is provided, which includes AlGaN layers 31 and defect blocking layers 32 arranged alternately in the direction away from the Si substrate 10. In the second buffer layer 30, the layer closest to the Si substrate 10 is the AlGaN layer 31, that is, a defect blocking layer 32 is inserted between two adjacent AlGaN layers 31, and the defect blocking layer 32 includes at least a SiN layer. In this way, the SiN layer is used to deflect the direction of dislocations and defects in the AlGaN layer 31, thereby canceling out some dislocations and defects in the AlGaN layer 31, isolating some dislocations and defects in the AlGaN layer 31, and effectively guiding the release of stress in the AlGaN layer 31. This improves the internal stress condition and crystal quality of the subsequently grown GaN light-emitting layer (especially the multi-quantum well layer 50), reduces its defect density, and obtains a high-quality LED epitaxial wafer with fewer defects and lower stress. This improves the wavelength uniformity and internal quantum efficiency of the LED chip and increases its brightness.

[0053] Specifically, Figure 2 This illustration shows a partial transmission electron microscopy (TEM) image of an LED chip provided in an embodiment of this application. Figure 2 In the black area, dislocations and defects are represented; the darker the black, the more dislocations and defects are present. From... Figure 2 It can be seen that when the first AlGaN layer 31 is grown on the side of AlN layer 20 away from Si substrate 10, due to the large lattice mismatch between Si substrate 10 and AlN layer 20, a large number of dislocations and defects exist in the first AlGaN layer 31. Most of these dislocations and defects are located along directions perpendicular to the plane of Si substrate 10 (e.g., Figure 2 Extending in the Y direction, and after a first defect barrier layer 32, including at least a SiN layer, is formed on the side of the first AlGaN layer 31 facing away from the Si substrate 10, dislocations and defects in the first AlGaN layer 31 reach the interface between the first AlGaN layer 31 and the first defect barrier layer 32, and then turn to a direction parallel to the plane of the Si substrate 10 (e.g., in the Y direction). Figure 2If the first AlGaN layer 31 and the first defect barrier layer 32 extend in the X direction, then some dislocations and defects at the interface can extend in two opposite directions parallel to the plane of the Si substrate 10, thereby allowing some dislocations and defects at the interface of the first AlGaN layer 31 and the first defect barrier layer 32 to cancel each other out, thereby reducing the dislocations and defects propagated to subsequent film layers.

[0054] Continue as Figure 2 As shown, after passing through the first defect barrier layer 32, the dislocations and defects inside the second AlGaN layer 31 in the second buffer layer 30 along the direction away from the Si substrate 10 are greatly reduced, thus confirming that the defect barrier layer 32, which includes at least the SiN layer, has an isolation effect on some dislocations and defects in the AlGaN layer 31. At the same time, the defect barrier layer 32 can also effectively guide the release of stress in the AlGaN layer 31.

[0055] Similarly, since the defect blocking layer 32 isolates some dislocations and defects in the AlGaN layer 31 on the side close to the Si substrate 10 and can effectively guide the release of stress in the AlGaN layer 31 on the side close to the Si substrate 10, the dislocations and defects in the AlGaN layer 31 further away from the Si substrate 10 in the second buffer layer 30 are fewer, and the stress is gradually released, thereby improving the internal stress condition and crystal quality of the subsequently grown GaN light-emitting layer (especially the multi-quantum well layer 50).

[0056] It should be noted that since it is difficult to form a film by directly growing a SiN layer on the AlN layer 20, in this embodiment of the application, the layer closest to the Si substrate 10 in the second buffer layer 30 is an AlGaN layer 31. Thus, the first AlGaN layer 31 is grown first on the side of the AlN layer 20 away from the Si substrate 10, and then a defect barrier layer 32 including at least a SiN layer is grown on the side of the first AlGaN layer 31 away from the Si substrate 10, so as to facilitate film growth and reduce the difficulty of the process.

[0057] It should also be noted that, since the AlGaN layer 31 in the second buffer layer 30, which is further away from the Si substrate 10, has fewer dislocations and defects, and the stress is gradually released, the layer in the second buffer layer 30 that is furthest from the Si substrate 10 can optionally be an AlGaN layer 31. This AlGaN layer 31 has fewer dislocations and defects, and the stress is released to a greater extent. Thus, the first type GaN layer 40 can be directly grown on the AlGaN layer 31 in the second buffer layer 30 that is furthest from the Si substrate 10, and the multi-quantum well layer 50 and the second type GaN layer 60 can be grown sequentially thereafter.

[0058] Alternatively, the layer furthest from the Si substrate 10 in the second buffer layer 30 may be a defect barrier layer 32 comprising at least a SiN layer. This defect barrier layer 32 is used to continue to isolate some dislocations and defects in the AlGaN layer 31 furthest from the Si substrate 10 in the second buffer layer 30, and to continue to release stress in the AlGaN layer 31 furthest from the Si substrate 10 in the second buffer layer 30. In this case, a first-type GaN layer 40 is directly grown on the defect barrier layer 32 furthest from the Si substrate 10 in the second buffer layer 30, followed by the sequential growth of a multi-quantum well layer 50 and a second-type GaN layer 60.

[0059] It should also be noted that this application does not limit the number of AlGaN layers 31 in the second buffer layer 30, nor does it limit the number of defect barrier layers 32 in the second buffer layer 30. Since the layer closest to the Si substrate 10 in the second buffer layer 30 is the AlGaN layer 31, and the AlGaN layers 31 and defect barrier layers 32 are arranged alternately in the second buffer layer 30, optionally, the number of defect barrier layers 32 in the second buffer layer 30 is the same as the number of AlGaN layers 31, that is, a defect barrier layer 32 is provided on the side of each AlGaN layer 31 facing away from the Si substrate 10. In this case, the layer furthest from the Si substrate 10 in the second buffer layer 30 is the defect barrier layer 32, as specifically... Figure 1 As shown, Figure 1 The second buffer layer 30 is shown to include three AlGaN layers 31 and three defect barrier layers 32.

[0060] Alternatively, the number of defect blocking layers 32 in the second buffer layer 30 is one less than the number of AlGaN layers 31, that is, a defect blocking layer 32 is provided between two adjacent AlGaN layers 31, and the layer in the second buffer layer 30 furthest from the Si substrate 10 is the AlGaN layer 31.

[0061] Based on the above embodiments, optionally, in one embodiment of this application, the Al composition of each AlGaN layer 31 in the second buffer layer 30 is equal. In this case, the Al composition of each AlGaN layer 31 in the second buffer layer 30 should not be too large, so as to facilitate the transition from AlN layer 20 to the first type GaN layer 40.

[0062] Optionally, in another embodiment of this application, in the second buffer layer 30, the Al composition of the AlGaN layer 31 gradually decreases along the direction away from the Si substrate 10.

[0063] In this embodiment, in the second buffer layer 30, along the direction away from the Si substrate, the Al composition of the AlGaN layer 31 gradually decreases, that is, the Al composition of the (i+1)th AlGaN layer 31 is less than the Al composition of the ith AlGaN layer 31, where i is greater than or equal to 1. For example, in the second buffer layer 30, along the direction away from the Si substrate, the Al composition of the second AlGaN layer 31 is less than the Al composition of the first AlGaN layer 31, the Al composition of the third AlGaN layer 31 is less than the Al composition of the second AlGaN layer 31, and so on, thereby completing the transition from the AlN layer 20 to the first-type GaN layer 40.

[0064] Furthermore, in the second buffer layer 30, along the direction away from the Si substrate 10, the Al composition of the AlGaN layer 31 gradually decreases, causing the lattice constant of the AlGaN layer 31 to gradually change. This gradually improves the internal stress in the AlGaN layer 31, thereby improving the internal stress condition and crystal quality of the subsequently grown GaN light-emitting layer (especially the multi-quantum well layer 50). The GaN light-emitting layer (especially the multi-quantum well layer 50) has better crystal quality and lower defect density, resulting in higher internal quantum efficiency and greater brightness of the LED chip. At the same time, the reduced internal stress of the GaN light-emitting layer (especially the multi-quantum well layer 50) can reduce the warping of the LED epitaxial wafer, thereby improving the wavelength uniformity of the LED chip.

[0065] Specifically, taking the second buffer layer 30, which includes three AlGaN layers 31 and three defect barrier layers 32, as an example, the following explanation is provided: Figure 1 As shown, in the second buffer layer 30, along the direction away from the Si substrate 10, the Al composition in the first AlGaN layer 31 is 0.8, that is, the first AlGaN layer 31 is Al 0.8 Ga 0.2 The N-layer; the Al composition in the second AlGaN layer 31 is 0.5, that is, the second AlGaN layer 31 is Al 0.5 Ga 0.5 The third AlGaN layer 31 has an Al composition of 0.2, meaning it is composed of Al. 0.2 Ga 0.8 N layers.

[0066] It should be noted that this application does not limit the specific Al composition of the AlGaN layer 31 in the second buffer layer 30, as long as the Al composition of the AlGaN layer 31 gradually decreases along the direction away from the Si substrate 10.

[0067] In this embodiment, since the AlGaN layer 31 closest to the Si substrate in the second buffer layer 30 has the highest Al composition and the highest defect density, its thickness must be relatively thin due to process limitations. Conversely, since the AlGaN layer 31 further away from the Si substrate 10 in the second buffer layer 30 has a lower Al composition and a lower defect density, the thickness of the AlGaN layer 31 in the second buffer layer 30 can gradually increase along the direction away from the Si substrate 10. Specifically, as follows... Figure 3 As shown, this is to facilitate a rapid transition to the first-type GaN layer 40.

[0068] Specifically, taking the second buffer layer 30, which includes three AlGaN layers 31 and three defect barrier layers 32, as an example, as follows: Figure 3 As shown, in the second buffer layer 30, along the direction away from the Si substrate 10, the thickness of the first AlGaN layer 31 can be 60nm-120nm, including the endpoint values; the thickness of the second AlGaN layer 31 can be 100nm-200nm, including the endpoint values; and the thickness of the third AlGaN layer 31 can be 200nm-300nm.

[0069] In other embodiments of this application, the thickness of the AlGaN layer 31 near the Si substrate 10 in the second buffer layer 30 may be equal, and the thickness of the AlGaN layer 31 away from the Si substrate 10 may be equal, and the thickness of the AlGaN layer 31 near the Si substrate 10 in the second buffer layer 30 may be less than the thickness of the AlGaN layer 31 away from the Si substrate 10, depending on the specific circumstances.

[0070] It should be noted that in the LED chip provided in this application embodiment, each defect blocking layer 32 in the second buffer layer 30 only serves to isolate defects and release stress. Therefore, the thickness of each defect blocking layer 30 in the second buffer layer 30 should be relatively thin to prevent it from affecting other performance of the LED chip.

[0071] As described above, in the second buffer layer 30, the defect density in the AlGaN layer 31 gradually decreases along the direction away from the Si substrate 10. Based on this, optionally, in one embodiment of this application, such as... Figure 4 As shown, in the second buffer layer 30, the thickness of the defect barrier layer 32 gradually decreases along the direction away from the Si substrate 10, so as to facilitate a rapid transition to the first type GaN layer 40.

[0072] Furthermore, the defect barrier layer 32 includes at least a SiN layer, that is, other material films are introduced into the LED chip. In this embodiment, the thickness of the defect barrier layer 32 gradually decreases along the direction away from the Si substrate 10, so that the thinner defect barrier layer 32 will not affect the performance of the LED chip.

[0073] In addition, as the Al content of the AlGaN layer 31 in the second buffer layer 30 gradually decreases along the direction away from the Si substrate 10, the thickness of the defect barrier layer 32 between two adjacent AlGaN layers 31 gradually decreases as the Al content in the AlGaN layer 31 decreases, thereby more effectively guiding the release of stress in the AlGaN layer 31.

[0074] It should be noted that this application does not limit the specific thickness of the defect blocking layer 32 in the second buffer layer 30. In other embodiments of this application, the thickness of each defect blocking layer 32 in the second buffer layer 30 may also be equal, depending on the specific circumstances.

[0075] Optionally, in one embodiment of this application, based on any of the above embodiments, the defect blocking layer 32 is a SiN layer, that is, in the second buffer layer 30, a SiN layer is disposed between two adjacent AlGaN layers 31 as a defect blocking layer. Since the function of the SiN layer as a defect blocking layer has been described in detail in the above embodiments, it will not be repeated here.

[0076] Optionally, in another embodiment of this application, such as Figure 5 As shown, the defect blocking layer 32 is a superlattice layer 32, which includes SiN layer 321 and InN layer 322 arranged alternately along the direction away from Si substrate 10.

[0077] It should be noted that in the superlattice layer 32, an adjacent SiN layer 321 and an InN layer 322 form a period. Optionally, the number of periods can be in the range of 3-5, including the endpoint value, that is, the logarithm of SiN layer 321 and InN layer 322 is 3-5. However, this application does not limit this and it depends on the specific situation.

[0078] It should also be noted that when preparing the superlattice layer 32, SiN layer 321 and InN layer 322 need to be grown alternately. SiN layer 321 still acts as a defect barrier layer to isolate dislocations and defects and guide stress release. InN layer 322 acts as an activator on the surface of SiN layer 321, which can improve the lateral mobility of Si and N atoms on the surface of SiN layer 321, making the surface of SiN layer 321 smoother and the uniformity of SiN layer 321 better, thereby improving the isolation effect of SiN layer 321 on dislocations and defects.

[0079] Furthermore, the In in the InN layer 322 is easily volatilized at high temperatures, but the AlGaN layer 31 requires relatively high temperatures to grow. Therefore, in practice, the InN layer 322 only acts as an activator for the SiN layer 321 during its growth process, and the In atoms in the InN layer 322 may then evaporate, making the second buffer layer 30 appear to be a SiN layer overall. Of course, some InN layer 322 may remain, making the second buffer layer 30 an overall superlattice layer composed of alternating SiN layers 321 and InN layers 322.

[0080] It should be noted that in the above embodiments, the side of the second buffer layer 30 facing away from the Si substrate 10 is not limited to the first type GaN layer 40, the multiple quantum well layer 50, and the second type GaN layer 60, such as... Figure 6 As shown, the LED chip provided in this application embodiment may further include a U-shaped GaN layer 70 located between the second buffer layer 30 and the first type GaN layer 40, and a stress relief layer 80 located between the first type GaN layer 40 and the multi-quantum well layer 50.

[0081] Figure 7A schematic diagram comparing the X-ray diffraction (XRD) patterns of an LED chip 100 with a second buffer layer 30 consisting solely of an AlGaN layer with a gradually varying Al composition and an LED chip 110 with a second buffer layer 30 consisting of multiple SiN defect blocking layers inserted into the AlGaN layer with a gradually varying Al composition, is shown. In the diagram, the horizontal axis represents the angle in arcseconds, and the vertical axis represents the intensity of the X-rays in individual photons. The intensity of the collected X-rays is characterized by the number of X-ray photons collected. As can be seen from the figure, the LED chip 110 with multiple SiN defect blocking layers inserted into the AlGaN layer with a graded Al composition has a narrower half-width at half-maximum (WHM) compared to the LED chip 100 without SiN defect blocking layers. This indicates that after inserting multiple SiN defect blocking layers into the AlGaN layer with a graded Al composition, the isolation effect of the SiN defect blocking layers on dislocations and defects, as well as the release of stress, results in better crystal quality and lower defect density in the GaN light-emitting layer (especially the multi-quantum well layer 50) of the LED chip 110. This leads to higher internal quantum efficiency and greater brightness in the LED chip. At the same time, the internal stress of the GaN light-emitting layer (especially the multi-quantum well layer 50) is reduced, which can reduce the warping of the LED epitaxial wafer and improve the wavelength uniformity of the LED chip. Specifically, tests show that the standard deviation of the wavelength of LED chip 110 after inserting multiple SiN defect blocking layers into the AlGaN layer with a graded Al composition is only 0.729, while the standard deviation of the wavelength of LED chip 100 without SiN defect blocking layers is 1.342. It can be seen that by inserting multiple SiN defect blocking layers into the AlGaN layer with a graded Al composition, the standard deviation of the wavelength of the LED chip is significantly reduced, indicating that the wavelength uniformity of the LED chip is significantly improved.

[0082] This application also provides a method for fabricating an LED chip. Figure 8 A schematic flowchart of the LED chip fabrication method provided in this application embodiment is shown, as follows: Figure 8 As shown, the method includes:

[0083] S100: As shown in Figure 9(a), a Si substrate 10 is provided.

[0084] Specifically, the Si substrate 10 can have a crystal orientation of 111 and undergo hydrogenation treatment to remove surface impurities from the Si substrate 10.

[0085] S200: As shown in Figure 9(b), a first buffer layer 20 is formed on one side of the Si substrate 10. The first buffer layer 20 is an AlN layer.

[0086] Specifically, trimethylaluminum (TMAl) and ammonia (NH3) are introduced into the reaction chamber, along with carrier gases (H2 and N2). The temperature of the reaction chamber is set to 1050℃ (which can be between 900℃ and 1100℃), and an AlN layer is grown on one side of the Si substrate 10 as the first buffer layer 20.

[0087] Optionally, the thickness of the first buffer layer 20 can be 100nm (between 60nm and 150nm), but this application does not limit the thickness of the first buffer layer 20, and it depends on the specific situation.

[0088] S300: As shown in Figure 9(c), AlGaN layer 31 and defect barrier layer 32 are alternately formed on the side of the first buffer layer 20 away from the Si substrate 10 along the direction away from the Si substrate 10, thereby forming a second buffer layer 30. In the second buffer layer 30, the layer closest to the Si substrate 10 is an AlGaN layer, wherein the defect barrier layer 32 includes at least a SiN layer.

[0089] S400: such as Figure 1 As shown, on the side of the second buffer layer 30 away from the Si substrate 10, a first type GaN layer 40, a multi-quantum well layer 50, and a second type GaN layer 60 are sequentially formed along the direction away from the Si substrate 10.

[0090] In this embodiment, the first type GaN layer 40, the multiple quantum well layer 50, and the second type GaN layer 60 constitute a GaN light-emitting layer. The multiple quantum well layer 50 may include an InGaN potential well layer and a GaN barrier layer arranged alternately along the direction away from the Si substrate 10. The internal stress state and crystal quality of the InGaN potential well layer and the GaN barrier layer in the multiple quantum well layer 50 determine the wavelength uniformity, internal quantum efficiency, and brightness of the LED chip.

[0091] Optionally, if the first type GaN layer 40 is an N-type GaN layer, then the second type GaN layer 60 is a P-type GaN layer, or vice versa, if the second type GaN layer 40 is a P-type GaN layer, then the second type GaN layer 60 is an N-type GaN layer, depending on the specific situation.

[0092] Specifically, in step S400, trimethylgallium (TMGa), silane (SiH4), and ammonia (NH3) are introduced into the reaction chamber, along with carrier gases (H2 and N2), to grow a first-type GaN layer 40 with a thickness of 2000 nm and a temperature of 1070 °C. At this temperature, the Si doping concentration in the first-type GaN layer can be 1E19 / cm³. 3 .

[0093] Next, a multi-quantum well layer 50 is grown. In any given period, an InGaN potential well layer is grown first. Specifically, trimethylgallium (TMGa), trimethylindium (TMIn), ammonia (NH3), and nitrogen (N2) are introduced into the reaction chamber at a growth temperature of 770°C, resulting in a thickness of 2.5 nm. Then, a GaN barrier layer is grown. At this time, trimethylgallium (TMGa), silane (SiH4), ammonia (NH3), hydrogen (H2), and nitrogen (N2) are introduced into the reverse chamber at a growth temperature of 880°C, resulting in a thickness of 12 nm and a Si doping concentration of 1E18 / cm³. 3 .

[0094] In this embodiment, a first buffer layer 20 and a second buffer layer 30 are first grown on the Si substrate 10. The first buffer layer 20 is an AlN layer, and the second buffer layer 30 includes multiple AlGaN layers 31. Then, a first type GaN layer 40, a multiple quantum well layer 50, and a second type GaN layer 60 are sequentially grown on the side of the second buffer layer 30 away from the Si substrate 10, thereby gradually transitioning the Si substrate to the GaN light-emitting layer through the AlN layer 20 and the AlGaN layer 31.

[0095] The inventors discovered that when growing an AlN layer 20 on a Si substrate 10, a large number of dislocations and defects are generated due to the huge lattice mismatch between the two, accompanied by the generation of internal stress. If the AlN layer 20 is transitioned to the GaN light-emitting layer only through an AlGaN layer 31 on the side away from the Si substrate 10, these defects will extend to the GaN light-emitting layer (especially the multi-quantum well layer 50) as the AlGaN buffer layer 31 grows. This results in uneven stress distribution and high defect density in the GaN light-emitting layer (especially the multi-quantum well layer 50), which has a negative impact on wavelength uniformity and internal quantum efficiency. Therefore, in the LED chip fabrication method provided in this application embodiment, the second buffer layer 30 includes AlGaN layers 31 and defect blocking layers 32 arranged alternately in the direction away from the Si substrate 10. In the second buffer layer 30, the layer closest to the Si substrate 10 is the AlGaN layer 31, that is, a defect blocking layer 32 is inserted between two adjacent AlGaN layers 31, and the defect blocking layer 32 includes at least a SiN layer. In this way, the SiN layer is used to deflect the direction of dislocations and defects in the AlGaN layer 31, thereby canceling out some dislocations and defects in the AlGaN layer 31, isolating some dislocations and defects in the AlGaN layer 31, and effectively guiding the release of stress in the AlGaN layer 31. This improves the internal stress condition and crystal quality of the subsequently grown GaN light-emitting layer (especially the multi-quantum well layer 50), reduces its defect density, and obtains a high-quality LED epitaxial wafer with fewer defects and lower stress. This improves the wavelength uniformity and internal quantum efficiency of the LED chip and increases its brightness.

[0096] Specifically, Figure 2 This image shows a partial transmission electron microscopy (TEM) image of an LED chip fabricated using the method provided in the embodiments of this application. Figure 2 In the black area, dislocations and defects are represented; the darker the black, the more dislocations and defects are present. From... Figure 2 It can be seen that when the first AlGaN layer 31 is grown on the side of AlN layer 20 away from Si substrate 10, due to the large lattice mismatch between Si substrate 10 and AlN layer 20, a large number of dislocations and defects exist in the first AlGaN layer 31. Most of these dislocations and defects are located along directions perpendicular to the plane of Si substrate 10 (e.g., Figure 2 Extending in the Y direction, and after a first defect barrier layer 32, including at least a SiN layer, is formed on the side of the first AlGaN layer 31 facing away from the Si substrate 10, dislocations and defects in the first AlGaN layer 31 reach the interface between the first AlGaN layer 31 and the first defect barrier layer 32, and then turn to a direction parallel to the plane of the Si substrate 10 (e.g., in the Y direction). Figure 2 If the first AlGaN layer 31 and the first defect barrier layer 32 extend in the X direction, then some dislocations and defects at the interface can extend in two opposite directions parallel to the plane of the Si substrate 10, thereby allowing some dislocations and defects at the interface of the first AlGaN layer 31 and the first defect barrier layer 32 to cancel each other out, thereby reducing the dislocations and defects propagated to subsequent film layers.

[0097] Continue as Figure 2 As shown, after passing through the first defect barrier layer 32, the dislocations and defects inside the second AlGaN layer 31 in the second buffer layer 30 along the direction away from the Si substrate 10 are greatly reduced, thus confirming that the defect barrier layer 32, which includes at least the SiN layer, has an isolation effect on some dislocations and defects in the AlGaN layer 31. At the same time, the defect barrier layer 32 can also effectively guide the release of stress in the AlGaN layer 31.

[0098] Similarly, since the defect blocking layer 32 isolates some dislocations and defects in the AlGaN layer 31 on the side close to the Si substrate 10 and can effectively guide the release of stress in the AlGaN layer 31 on the side close to the Si substrate 10, the dislocations and defects in the AlGaN layer 31 further away from the Si substrate 10 in the second buffer layer 30 are fewer, and the stress is gradually released, thereby improving the internal stress condition and crystal quality of the subsequently grown GaN light-emitting layer (especially the multi-quantum well layer 50).

[0099] It should be noted that since it is difficult to form a film by directly growing a SiN layer on the AlN layer 20, in this embodiment of the application, the layer closest to the Si substrate 10 in the second buffer layer 30 is an AlGaN layer 31. Thus, the first AlGaN layer 31 is grown first on the side of the AlN layer 20 away from the Si substrate 10, and then a defect barrier layer 32 including at least a SiN layer is grown on the side of the first AlGaN layer 31 away from the Si substrate 10, so as to facilitate film growth and reduce the difficulty of the process.

[0100] It should also be noted that, since the AlGaN layer 31 in the second buffer layer 30, which is further away from the Si substrate 10, has fewer dislocations and defects, and the stress is gradually released, the layer in the second buffer layer 30 that is furthest from the Si substrate 10 can optionally be an AlGaN layer 31. This AlGaN layer 31 has fewer dislocations and defects, and the stress is released to a greater extent. Thus, the first type GaN layer 40 can be directly grown on the AlGaN layer 31 in the second buffer layer 30 that is furthest from the Si substrate 10, and the multi-quantum well layer 50 and the second type GaN layer 60 can be grown sequentially thereafter.

[0101] Alternatively, the layer furthest from the Si substrate 10 in the second buffer layer 30 may be a defect barrier layer 32 comprising at least a SiN layer. This defect barrier layer 32 is used to continue to isolate some dislocations and defects in the AlGaN layer 31 furthest from the Si substrate 10 in the second buffer layer 30, and to continue to release stress in the AlGaN layer 31 furthest from the Si substrate 10 in the second buffer layer 30. In this case, a first-type GaN layer 40 is directly grown on the defect barrier layer 32 furthest from the Si substrate 10 in the second buffer layer 30, followed by the sequential growth of a multi-quantum well layer 50 and a second-type GaN layer 60.

[0102] It should also be noted that this application does not limit the number of AlGaN layers 31 in the second buffer layer 30, nor does it limit the number of defect barrier layers 32 in the second buffer layer 30. Since the layer closest to the Si substrate 10 in the second buffer layer 30 is the AlGaN layer 31, and the AlGaN layers 31 and defect barrier layers 32 are arranged alternately in the second buffer layer 30, optionally, the number of defect barrier layers 32 in the second buffer layer 30 is the same as the number of AlGaN layers 31, that is, a defect barrier layer 32 is provided on the side of each AlGaN layer 31 facing away from the Si substrate 10. In this case, the layer furthest from the Si substrate 10 in the second buffer layer 30 is the defect barrier layer 32, as specifically... Figure 1 As shown, Figure 1 The second buffer layer 30 is shown to include three AlGaN layers 31 and three defect barrier layers 32.

[0103] Alternatively, the number of defect blocking layers 32 in the second buffer layer 30 is one less than the number of AlGaN layers 31, that is, a defect blocking layer 32 is provided between two adjacent AlGaN layers 31, and the layer in the second buffer layer 30 furthest from the Si substrate 10 is the AlGaN layer 31.

[0104] Based on the above embodiments, optionally, in one embodiment of this application, the Al composition of each AlGaN layer 31 in the second buffer layer 30 is equal. In this case, the Al composition of each AlGaN layer 31 in the second buffer layer 30 should not be too large, so as to facilitate the transition from AlN layer 20 to the first type GaN layer 40.

[0105] Optionally, in another embodiment of this application, in the second buffer layer 30, the Al composition of the AlGaN layer 31 gradually decreases along the direction away from the Si substrate 10.

[0106] In this embodiment, in the second buffer layer 30, along the direction away from the Si substrate, the Al composition of the AlGaN layer 31 gradually decreases, that is, the Al composition of the (i+1)th AlGaN layer 31 is less than the Al composition of the ith AlGaN layer 31, where i is greater than or equal to 1. For example, in the second buffer layer 30, along the direction away from the Si substrate, the Al composition of the second AlGaN layer 31 is less than the Al composition of the first AlGaN layer 31, the Al composition of the third AlGaN layer 31 is less than the Al composition of the second AlGaN layer 31, and so on, thereby completing the transition from the AlN layer 20 to the first-type GaN layer 40.

[0107] Furthermore, in the second buffer layer 30, along the direction away from the Si substrate 10, the Al composition of the AlGaN layer 31 gradually decreases, causing the lattice constant of the AlGaN layer 31 to gradually change. This gradually improves the internal stress in the AlGaN layer 31, thereby improving the internal stress condition and crystal quality of the subsequently grown GaN light-emitting layer (especially the multi-quantum well layer 50). The GaN light-emitting layer (especially the multi-quantum well layer 50) has better crystal quality and lower defect density, resulting in higher internal quantum efficiency and greater brightness of the LED chip. At the same time, the reduced internal stress of the GaN light-emitting layer (especially the multi-quantum well layer 50) can reduce the warping of the LED epitaxial wafer, thereby improving the wavelength uniformity of the LED chip.

[0108] Specifically, taking the second buffer layer 30, which includes three AlGaN layers 31 and three defect barrier layers 32, as an example, the following explanation is provided: Figure 1 As shown, in the second buffer layer 30, along the direction away from the Si substrate 10, the Al composition in the first AlGaN layer 31 is 0.8, that is, the first AlGaN layer 31 is Al 0.8 Ga 0.2The N-layer; the Al composition in the second AlGaN layer 31 is 0.5, that is, the second AlGaN layer 31 is Al 0.5 Ga 0.5 The third AlGaN layer 31 has an Al composition of 0.2, meaning it is composed of Al. 0.2 Ga 0.8 N layers.

[0109] It should be noted that this application does not limit the specific Al composition of the AlGaN layer 31 in the second buffer layer 30, as long as the Al composition of the AlGaN layer 31 gradually decreases along the direction away from the Si substrate 10.

[0110] In this embodiment, since the AlGaN layer 31 closest to the Si substrate in the second buffer layer 30 has the highest Al composition and the highest defect density, its thickness must be relatively thin due to process limitations. Conversely, since the AlGaN layer 31 further away from the Si substrate 10 in the second buffer layer 30 has a lower Al composition and a lower defect density, the thickness of the AlGaN layer 31 in the second buffer layer 30 can gradually increase along the direction away from the Si substrate 10. Specifically, as follows... Figure 3 As shown, this is to facilitate a rapid transition to the first-type GaN layer 40.

[0111] Specifically, taking the second buffer layer 30, which includes three AlGaN layers 31 and three defect barrier layers 32, as an example, as follows: Figure 3 As shown, in the second buffer layer 30, along the direction away from the Si substrate 10, the thickness of the first AlGaN layer 31 can be 60nm-120nm, including the endpoint values; the thickness of the second AlGaN layer 31 can be 100nm-200nm, including the endpoint values; and the thickness of the third AlGaN layer 31 can be 200nm-300nm.

[0112] In other embodiments of this application, the thickness of the AlGaN layer 31 near the Si substrate 10 in the second buffer layer 30 may be equal, and the thickness of the AlGaN layer 31 away from the Si substrate 10 may be equal, and the thickness of the AlGaN layer 31 near the Si substrate 10 in the second buffer layer 30 may be less than the thickness of the AlGaN layer 31 away from the Si substrate 10, depending on the specific circumstances.

[0113] It should be noted that in the LED chip prepared using the method provided in the embodiments of this application, each defect blocking layer 32 in the second buffer layer 30 only serves to isolate defects and release stress. Therefore, the thickness of each defect blocking layer 30 in the second buffer layer 30 should be relatively thin to prevent it from affecting other performance of the LED chip.

[0114] As described above, in the second buffer layer 30, the defect density in the AlGaN layer 31 gradually decreases along the direction away from the Si substrate 10. Based on this, optionally, in one embodiment of this application, such as... Figure 4 As shown, in the second buffer layer 30, the thickness of the defect barrier layer 32 gradually decreases along the direction away from the Si substrate 10, so as to facilitate a rapid transition to the first type GaN layer 40.

[0115] Furthermore, the defect barrier layer 32 includes at least a SiN layer, that is, other material films are introduced into the LED chip. In this embodiment, the thickness of the defect barrier layer 32 gradually decreases along the direction away from the Si substrate 10, so that the thinner defect barrier layer 32 will not affect the performance of the LED chip.

[0116] In addition, as the Al content of the AlGaN layer 31 in the second buffer layer 30 gradually decreases along the direction away from the Si substrate 10, the thickness of the defect barrier layer 32 between two adjacent AlGaN layers 31 gradually decreases as the Al content in the AlGaN layer 31 decreases, thereby more effectively guiding the release of stress in the AlGaN layer 31.

[0117] It should be noted that this application does not limit the specific thickness of the defect blocking layer 32 in the second buffer layer 30. In other embodiments of this application, the thickness of each defect blocking layer 32 in the second buffer layer 30 may also be equal, depending on the specific circumstances.

[0118] Based on any of the above embodiments, optionally, in one embodiment of this application, the formation process of the defect blocking layer 32 includes:

[0119] Ammonia and silane are introduced into the reaction chamber at a first preset temperature and a first preset pressure for a first preset time to grow a SiN layer as a defect barrier layer 32.

[0120] Specifically, since the AlGaN layer 31 is grown first, and then the defect barrier layer 32 is grown, optionally, the temperature of the reaction chamber during the growth of the AlGaN layer 31 can be 1000℃ and the pressure can be 50 Torr. Therefore, the reaction chamber can be maintained at a first preset temperature of 1000℃ and a first preset pressure of 50 Torr. Ammonia (NH3) and silane (SiH4) are introduced into the reaction chamber, and after a first preset time, the SiN layer is grown as the defect barrier layer 32.

[0121] Optionally, in another embodiment of this application, reference is made to... Figure 5 As shown, the formation process of the defect barrier layer 32 includes:

[0122] S10: Maintain the reaction chamber at the second preset temperature and the second preset pressure, and introduce ammonia and silane into the reaction chamber for a second preset time to grow the SiN layer.

[0123] Specifically, since the AlGaN layer 31 is grown first, and then the defect barrier layer 32 is grown, optionally, the temperature of the reaction chamber during the growth of the AlGaN layer 31 can be 1000℃ and the pressure can be 50 Torr. Therefore, the reaction chamber can be maintained at a second preset temperature of 1000℃ and a second preset pressure of 50 Torr, and ammonia (NH3) and silane (SiH4) can be introduced into the reaction chamber for a second preset time to grow the SiN layer 321.

[0124] S20: Stop introducing silane into the reaction chamber, continue introducing ammonia gas into the reaction chamber, and introduce an indium source into the reaction chamber. After a third preset time, grow the InN layer 322. At this time, maintain the reaction chamber at the second preset temperature and the second preset pressure.

[0125] S30: Alternately grow SiN layer 321 and InN layer 322 to form defect barrier layer 32, such that defect barrier layer 32 is SiN layer, or defect barrier layer 32 is superlattice layer, the superlattice layer includes SiN layer 321 and InN layer 322 alternately arranged in the direction away from Si substrate 10.

[0126] It should be noted that in the superlattice layer 32, an adjacent SiN layer 321 and an InN layer 322 form a period. Optionally, the number of periods can be in the range of 3-5, including the endpoint value, that is, the logarithm of SiN layer 321 and InN layer 322 is 3-5. However, this application does not limit this and it depends on the specific situation.

[0127] It should also be noted that when preparing the superlattice layer 32, SiN layer 321 and InN layer 322 need to be grown alternately. SiN layer 321 still acts as a defect barrier layer to isolate dislocations and defects and guide stress release. InN layer 322 acts as an activator on the surface of SiN layer 321, which can improve the lateral mobility of Si and N atoms on the surface of SiN layer 321, making the surface of SiN layer 321 smoother and the uniformity of SiN layer 321 better, thereby improving the isolation effect of SiN layer 321 on dislocations and defects.

[0128] Furthermore, the In in the InN layer 322 is easily volatilized at high temperatures, but the AlGaN layer 31 requires relatively high temperatures to grow. Therefore, in practice, the InN layer 322 only acts as an activator for the SiN layer 321 during its growth process, and the In atoms in the InN layer 322 may then evaporate, making the second buffer layer 30 appear to be a SiN layer overall. Of course, some InN layer 322 may remain, making the second buffer layer 30 an overall superlattice layer composed of alternating SiN layers 321 and InN layers 322.

[0129] The second buffer layer 30 includes a first Al layer arranged sequentially along the direction away from the Si substrate 10. 0.8 Ga 0.2 N-layer, first SiN / InN superlattice layer, second Al layer 0.5 Ga 0.5 N-layer, second SiN / InN superlattice layer, third Al layer 0.2 Ga 0.8 The explanation will continue using the N-layer and the third SiN / InN superlattice layer as examples.

[0130] Example 1:

[0131] In this embodiment, the temperature of the reaction chamber for growing the AlGaN layer and the SiN / InN superlattice layer is 1000°C, and the pressure inside the reaction chamber is 50 Torr.

[0132] Among them, the first layer Al 0.8 Ga 0.2 The growth thickness of the N layer is 60 nm. For the first SiN / InN superlattice layer, the flow rate of ammonia (NH3) for growing SiN layer 321 is 5 L, the flow rate of silane (SiH4) is 800 sccm, and the time is 12 s. The flow rate of ammonia (NH3) for growing InN layer 322 is 5 L, the flow rate of indium source (TMIn) is 200 sccm, and the time is 10 s. The number of cycles of SiN layer 321 and InN layer 322 in the first SiN / InN superlattice layer is 5.

[0133] Second layer Al 0.5 Ga 0.5 The growth thickness of the N layer is 100 nm; for the second SiN / InN superlattice layer, the flow rate of ammonia (NH3) for growing SiN layer 321 is 5 L, the flow rate of silane (SiH4) is 800 sccm, and the time is 8 s; the flow rate of ammonia (NH3) for growing InN layer 322 is 5 L, the flow rate of indium source (TMIn) is 200 sccm, and the time is 10 s; the number of periods of SiN layer 321 and InN layer 322 in the second SiN / InN superlattice layer is 5.

[0134] Third layer Al 0.2 Ga 0.8 The growth thickness of the N layer is 200 nm. For the third SiN / InN superlattice layer, the flow rate of ammonia (NH3) for growing SiN layer 321 is 5 L, the flow rate of silane (SiH4) is 800 sccm, and the time is 4 s. The flow rate of ammonia (NH3) for growing InN layer 322 is 5 L, the flow rate of indium source (TMIn) is 200 sccm, and the time is 10 s. The number of periods for SiN layer 321 and InN layer 322 in the second SiN / InN superlattice layer is 5.

[0135] Compared to LED chips with only AlGaN layers of gradually varying Al composition and no SiN / InN superlattice layer in the second buffer layer 30, this embodiment, after inserting multiple SiN / InN superlattice layers into the second buffer layer 30, shows a significant reduction in the full width at half maximum (FWHM) of the LED chip as measured by XRD. This is due to the isolation effect of the SiN layers on dislocations and defects, as well as the release of corresponding forces, demonstrating a significant improvement in the crystal quality of its GaN light-emitting layer (especially the multi-quantum-well layer). Furthermore, the wavelength FWHM and standard deviation of the photoluminescence spectrum (PL spectrum) are significantly reduced, indicating a reduction in defects within the quantum well layer, clear well-barrier interface stratification, and decreased internal stress between heterojunctions. Additionally, after the LED chip is fabricated, photoelectric parameter tests show a significant improvement in the crystal quality and internal quantum efficiency of the multi-quantum-well layer.

[0136] Example 2:

[0137] Unlike Example 1, the growth time of the SiN layer in the first SiN / InN superlattice layer is shortened to 8s; the growth time of the SiN layer in the second SiN / InN superlattice layer is shortened to 5s; and the growth time of the SiN layer in the third SiN / InN superlattice layer is shortened to 2s.

[0138] As can be seen, compared with Example 1, in this example, the growth time of the SiN layer in each SiN / InN superlattice layer is shortened. Since the growth time of the SiN layer affects the thickness of the SiN layer, the thickness of the SiN becomes thinner. XRD test shows that the wavelength half-width of the LED chip is slightly reduced, indicating that the crystal quality of the GaN light-emitting layer (especially the multi-quantum well layer) is better and the defect density is smaller. However, the warpage of the LED epitaxial wafer is slightly larger, indicating that the stress of the GaN light-emitting layer (especially the multi-quantum well layer) is slightly increased. Therefore, in the fabrication process, the growth time of the SiN layer can be reasonably selected to reasonably control the relationship between defect density and stress in the GaN light-emitting layer (especially the multi-quantum well layer).

[0139] Example 3:

[0140] Unlike Example 1, in this example, the silane (SiH4) flow rate for growing the SiN layer in each SiN / InN superlattice layer is reduced to 600 sccm. Since the silane (SiH4) flow rate affects the growth rate and thickness of the SiN layer, the growth rate of the SiN layer in each SiN / InN superlattice layer is slower. Photoelectric parameter tests show that the wavelength half-width and wavelength standard deviation of the LED chip are slightly smaller, indicating that the wavelength uniformity of the LED chip is better, but the brightness is lower. Therefore, in the fabrication process, a small amount of brightness can be sacrificed to improve the wavelength uniformity of the LED chip.

[0141] Example 4:

[0142] Unlike Example 1, the flow rate of ammonia (NH3) used to grow the SiN layer was increased to 10L for each SiN / InN superlattice layer. The flow rate of ammonia (NH3) affects the growth mode, growth rate, and thickness of the SiN layer. Photoelectric parameter tests showed that the IR value of the LED chip decreased and the ESD (Electro-Static Discharge) was slightly improved. Therefore, during the fabrication process, the IR value and ESD yield of the LED chip can be controlled according to specific circumstances to improve electrical performance.

[0143] As can be seen from the above four embodiments, the growth time of the SiN layer in the SiN / InN superlattice layer affects the thickness of the SiN layer, the flow rate of silane (SiH4) in the SiN layer affects the growth rate and thickness of the SiN layer, and the flow rate of ammonia (NH3) in the SiN layer affects the growth mode, growth rate, and thickness of the SiN layer, thus slightly affecting various performance characteristics of the LED chip. However, overall, compared to the LED chip with only an AlGaN layer with a gradually changing Al composition and no SiN / InN superlattice layer in the second buffer layer 30, inserting multiple SiN / InN superlattice layers into the second buffer layer 30 can significantly reduce the longitudinal dislocation and defect density in the LED chip, improve the residual stress in the device, reduce epitaxial wafer warpage, reduce the wavelength standard deviation of the device, improve the crystal quality of the multi-quantum well layer, increase the internal quantum efficiency, and make the brightness higher.

[0144] Optionally, in one embodiment of this application, during the growth of the SiN layer, the flow rate of ammonia gas introduced into the reaction chamber ranges from 2L to 20L, including the endpoint value; the flow rate of silane introduced into the reaction chamber ranges from 200sccm to 2000sccm, including the endpoint value. This results in better uniformity of the SiN layer, better isolation of dislocations and defects, and effective stress release. In addition, it has little impact on the brightness, IR value, ESD performance, and other properties of the LED chip.

[0145] It should be noted that in the above embodiments, the side of the second buffer layer 30 facing away from the Si substrate 10 is not limited to the first type GaN layer 40, the multiple quantum well layer 50, and the second type GaN layer 60, such as... Figure 6 As shown, the method for fabricating an LED chip provided in this application embodiment further includes:

[0146] S5: Before forming the first type GaN layer 40, a U-shaped GaN layer 70 is formed on the side of the second buffer layer 30 away from the Si substrate 10.

[0147] Specifically, by introducing trimethylgallium (TMGa) and ammonia (NH3) into the reaction chamber, and introducing carrier gases (H2 and N2), a U-shaped GaN layer 70 can be grown at a temperature of 1100℃, with an optional thickness of 2500 nm.

[0148] S6: Before forming the multi-quantum well layer 50, a stress relief layer 80 is formed on the side of the first type GaN layer 40 away from the Si substrate 10.

[0149] Specifically, triethylgallium (TEGa), trimethylindium (TMIn), silane (SiH4), and ammonia (NH3) are introduced into the reaction chamber, along with carrier gases (H2 and N2), to grow 1-10 cycles of low-concentration InGaN / GaN shallow well layers as stress relief layers 80, with a thickness of up to 140 nm. The temperature of the shallow well InGaN layer can be 840 °C, and the temperature of the barrier GaN layer can be 900 °C.

[0150] In summary, the LED chip provided in this application includes a Si substrate, a first buffer layer, a second buffer layer, a first type GaN layer, a multi-quantum-well layer, and a second type GaN layer stacked sequentially. The first buffer layer is an AlN layer, and the second buffer layer includes an AlGaN layer, thereby allowing the Si substrate to gradually transition to the GaN light-emitting layer through the AlN and AlGaN layers. Furthermore, in the second buffer layer, a defect-blocking layer is inserted between two adjacent AlGaN layers, and the defect-blocking layer includes at least a SiN layer. This allows the SiN layer to suppress some dislocations and defects in the AlGaN layer and effectively guide the release of stress in the AlGaN layer, thereby improving the internal stress condition and crystal quality of the subsequently grown GaN light-emitting layer, reducing the defect density, and improving the wavelength uniformity and internal quantum efficiency of the LED chip, thus increasing its brightness.

[0151] The various parts of this manual are described in a combination of parallel and progressive methods. Each part focuses on the differences between the other parts, and the same or similar parts can be referred to each other.

[0152] The features described above regarding the disclosed embodiments can be substituted or combined with each other to enable those skilled in the art to implement or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An LED chip, characterized in that, include: Si substrate; A first buffer layer located on one side of the Si substrate, wherein the first buffer layer is an AlN layer; A second buffer layer is located on the side of the first buffer layer away from the Si substrate. The second buffer layer includes AlGaN layers and defect blocking layers arranged alternately in the direction away from the Si substrate. In the second buffer layer, the layer closest to the Si substrate is an AlGaN layer. The defect blocking layer is a superlattice layer. The superlattice layer includes SiN layers and InN layers arranged alternately in the direction away from the Si substrate. And a first type GaN layer, a multiple quantum well layer, and a second type GaN layer are arranged sequentially along the direction away from the Si substrate on the side of the second buffer layer away from the Si substrate.

2. The LED chip according to claim 1, characterized in that, In the second buffer layer, the Al composition of the AlGaN layer gradually decreases along the direction away from the Si substrate.

3. The LED chip according to claim 1, characterized in that, In the second buffer layer, the thickness of the defect barrier layer gradually decreases along the direction away from the Si substrate.

4. A method for fabricating an LED chip, characterized in that, include: Provide a Si substrate; A first buffer layer is formed on one side of the Si substrate, and the first buffer layer is an AlN layer; On the side of the first buffer layer away from the Si substrate, AlGaN layers and defect barrier layers are alternately formed along the direction away from the Si substrate to form a second buffer layer, wherein the layer closest to the Si substrate in the second buffer layer is an AlGaN layer. On the side of the second buffer layer away from the Si substrate, a first type GaN layer, a multiple quantum well layer, and a second type GaN layer are sequentially formed along the direction away from the Si substrate. The formation process of the defect barrier layer includes: Ammonia and silane are introduced into the reaction chamber at a second preset temperature and a second preset pressure for a second preset time to grow a SiN layer. Stop introducing silane into the reaction chamber, continue to introduce ammonia into the reaction chamber, and introduce an indium source into the reaction chamber. After a third preset time, grow an InN layer. The defect barrier layer is formed by alternating growth of SiN and InN layers, making the defect barrier layer a superlattice layer, which includes SiN and InN layers arranged alternately in a direction away from the Si substrate.

5. The method for preparing an LED chip according to claim 4, characterized in that, In the second buffer layer, the Al composition of the AlGaN layer gradually decreases along the direction away from the Si substrate.

6. The method for preparing an LED chip according to claim 4, characterized in that, During the growth of the SiN layer, the flow rate of ammonia gas introduced into the reaction chamber ranges from 2L to 20L, including the endpoint value; the flow rate of silane introduced into the reaction chamber ranges from 200sccm to 2000sccm, including the endpoint value.

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