Control method and device of PWM signal, electronic equipment, inverter and storage medium

Abstract

The application provides a PWM signal control method and device, electronic equipment, an inverter and a storage medium, and is applied to the inverter. The method comprises the following steps: when a PWM signal of a target switch tube is received, it is judged whether the target switch tube and other switch tubes except the target switch tube satisfy their respective preset timing conditions; when it is judged that the target switch tube and the other switch tubes except the target switch tube all satisfy their respective preset timing conditions, the PWM signal is sent to the target switch tube, so as to control the target switch tube to perform a corresponding switching action. According to the method, the switching of the switch tube device state is strictly controlled according to the circuit topology requirement through the control of the PWM signal of the switch tube under various working conditions, and the reliability and safety of the switch tube device switching and the stability of the inverter system are improved.

Description

Technical Field

[0001] This invention relates to the field of signal control technology, and in particular to a method, apparatus, electronic device, inverter, and storage medium for controlling PWM signals. Background Technology

[0002] In related technologies, IGBT (Insulated Gate Bipolar Transistor) is widely used in the field of power conversion technology. The PWM (Pulse Width Modulation) control signal of IGBT plays a crucial role in the operation and protection of IGBT, affecting the safety and control performance of the entire system.

[0003] Inverters are increasingly used in high-voltage, high-power converters, with IGBT devices in the converter module playing a crucial role. Therefore, precise control of the IGBT's PWM signal is paramount. Due to requirements on the dead time, minimum turn-on pulse width, minimum turn-off pulse width, and the switching sequence of the inner and outer transistors in the IGBT PWM signal, the raw control signals from the upper-level control system need to be processed. For common two-level inverters, the PWM signal processing must ensure the dead time and minimum pulse width requirements of the complementary transistor pulses in the same bridge arm. For three-level inverters, the switching sequence requirements of the inner and outer transistors in the same bridge arm also need to be ensured. If control is solely based on the raw pulse signals from the upper-level control system, in practical applications, abnormal state transitions often occur, such as direct switching between states 01 and 10, or the occurrence of a disabled state 11. This makes it impossible to guarantee that each transistor operates according to the switching sequence required by the topology, leading to invalid transistor states or invalid state transitions, thereby jeopardizing the performance and safety of the entire system. Summary of the Invention

[0004] The main objective of this invention is to provide a PWM signal control method, device, electronic device, inverter, and storage medium to ensure the reliability of PWM signal control over switching transistors, so that the switching transistors operate according to the correct timing logic.

[0005] In a first aspect, the present invention provides a PWM signal control method applied to an inverter, comprising: when a PWM signal for a target switch is received, determining whether the target switch and other switches besides the target switch meet their respective preset timing conditions; when it is determined that the target switch and other switches besides the target switch all meet their respective preset timing conditions, sending the PWM signal to the target switch to control the target switch to perform a corresponding switching action.

[0006] In one embodiment, the inverter includes: a two-level inverter and a three-level inverter: wherein the three-level inverter includes a three-level type I inverter.

[0007] In one embodiment, when the inverter is a three-level type I inverter, determining whether the target switch and other switches besides the target switch meet their respective preset timing conditions includes: obtaining the current state and duration of the current state of the target switch; determining whether the duration of the current state of the target switch meets the preset action condition corresponding to the current state; determining whether the dead time between the target switch and the switch interlocked with it meets the preset dead time condition; determining whether the switching between the target switch and the switch in the same bridge arm meets the preset switching condition; and determining whether the state of the in-phase switch of the target switch meets the preset state condition.

[0008] In one embodiment, the current state of the target switch includes an on state and an off state; determining whether the duration of the current state of the target switch meets the preset action conditions corresponding to the current state includes: when the current state of the target switch is on, determining whether the duration of the on state meets the preset off condition; when the current state of the target switch is off, determining whether the duration of the off state meets the preset on condition.

[0009] In one embodiment, the preset shutdown condition includes: the duration of the on state of the target switch is greater than or equal to a preset on-time threshold; the preset turn-on condition includes: the duration of the off state of the target switch is greater than or equal to a preset shutdown threshold.

[0010] In one embodiment, the preset dead time condition includes: the dead time between the target switch and the switch interlocked with it is greater than or equal to a preset dead time threshold.

[0011] In one embodiment, the preset switching conditions include: if the target switch is an external switch, when the PWM signal is used to control the target switch to turn on, the switch in the same bridge arm as the target switch is already in the on state before the target switch is turned on, and the interval between their on-time switching satisfies a first preset on-time switching duration condition; when the PWM signal is used to control the target switch to turn off, the switch in the same bridge arm as the target switch can only be turned off after the target switch is turned off, and the interval between their off-time switching satisfies a first preset off-time switching duration condition; if the target switch is an internal switch, when the PWM signal is used to control the target switch to turn on, the target switch is turned on before the switch in the same bridge arm as it is turned on, and the interval between their on-time switching satisfies a second preset on-time switching duration condition; when the PWM signal is used to control the target switch to turn off, the target switch is turned off after the switch in the same bridge arm as it is turned off, and the interval between their off-time switching satisfies a second preset off-time switching duration condition.

[0012] In one embodiment, the preset state conditions include: if the target switch is an outer transistor of the same bridge arm, when the PWM signal is used to control the target switch to turn on, the outer transistor of the target switch is in the off state; if the target switch is an inner transistor of the same bridge arm, when the PWM signal is used to control the target switch to turn off, the inner transistor of the target switch is in the on state.

[0013] In one embodiment, the switching transistor includes an insulated-gate bipolar transistor and a field-effect transistor.

[0014] In one embodiment, the preset timing conditions are set based on the state timing diagram jointly followed by the target switch and other switches besides the target switch.

[0015] Secondly, the present invention provides a PWM signal control device, comprising: a judgment module, configured to, when receiving a PWM signal for a target switch, determine whether the target switch and other switches besides the target switch meet their respective preset timing conditions; and a trigger module, configured to, when determining that the target switch and other switches besides the target switch all meet their respective preset timing conditions, send the PWM signal to the target switch to control the target switch to perform a corresponding switching action.

[0016] Thirdly, the present invention provides an electronic device, characterized in that it includes a processor, a memory, and a trigger. When the program code in the memory is executed by the processor, it implements the steps of the PWM signal control method described above, such that when a PWM signal for a target switch is received, it determines whether the target switch and other switches besides the target switch meet their respective preset timing conditions; when it is determined that the target switch and other switches besides the target switch all meet their respective preset timing conditions, the trigger sends the PWM signal to the target switch to control the target switch to perform a corresponding switching action.

[0017] In one embodiment, the electronic device includes at least one of the following: a field-programmable gate array and a complex programmable logic device.

[0018] Fourthly, the present invention provides an inverter, characterized in that it includes the electronic equipment described above for controlling the PWM signal of the switching transistor.

[0019] Fifthly, the present invention provides a storage medium characterized in that it stores program code, which, when executed by a processor, implements the steps of the inverter PWM signal control method described above.

[0020] According to the method of this embodiment, by controlling the PWM signal of the switching transistor under various operating conditions, the switching state of the switching transistor is controlled strictly in accordance with the circuit topology requirements, thereby improving the reliability and safety of the switching transistor and the stability of the converter system. Attached Figure Description

[0021] The accompanying drawings, which form part of this application, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0022] Figure 1 This is a flowchart of a PWM signal control method according to an exemplary embodiment of this application;

[0023] Figure 2 This is a circuit topology diagram of a type I three-level inverter in related technologies;

[0024] Figure 3 This is a timing diagram of the switching transistors in a type I three-level inverter in related technologies;

[0025] Figure 4 This is a schematic diagram of the PWM signal flow of a PWM signal control method according to an exemplary embodiment of this application;

[0026] Figure 5This is a schematic diagram of the PWM signal control logic of the switching transistor in a type I three-level inverter according to a specific embodiment of this application;

[0027] Figure 6 This is a schematic diagram of the signal flow of the PWM signal for a single switching transistor in a type I three-level inverter according to a specific embodiment of this application;

[0028] Figure 7 This is a schematic diagram of the various functional modules in the PWM signal control software according to a specific embodiment of this application. Detailed Implementation

[0029] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0030] Example 1

[0031] This embodiment provides a PWM signal control method applied to an inverter. Figure 1 This is a flowchart of a PWM signal control method according to an exemplary embodiment of this application. Figure 1 As shown, the method in this embodiment includes:

[0032] S100: When a PWM signal for the target switch is received, determine whether the target switch and other switches meet their respective preset timing conditions.

[0033] S200: When it is determined that the target switch and other switches meet their respective preset timing conditions, a PWM signal is sent to the target switch to control the target switch to perform the corresponding switching action.

[0034] Following the steps described above, when the PWM signal controls the target switch, it first determines whether each switch meets its corresponding preset timing conditions. Only when each switch meets its preset timing conditions is the received PWM signal sent to the target switch. This process transforms the switching timing sequence into switching logic conditions. Therefore, when each switch operates, all switches must meet their respective preset timing conditions before proceeding to the next step. This ensures the rigor of the switching sequence in the inverter, guaranteeing that the switches operate according to the correct timing logic and the required switching order of the topology. This improves the reliability of the PWM signal's control over the switches, ensuring the performance and safety of the entire system.

[0035] In the above steps, the inverter may include a two-level inverter and a three-level inverter, wherein the three-level inverter may include a three-level Type I inverter. Of course, if other devices partially or wholly apply some or all of the technical solutions of this application, they do not depart from the technical concept of this application and are within the protection scope of this application. The preset timing conditions can be set according to the state timing diagram jointly followed by the target switching transistor and other switching transistors besides the target switching transistor. Of course, they can also be flexibly set by those skilled in the art according to actual needs, all of which are within the protection scope of this application. The switching transistors may include insulated-gate bipolar transistors (IGBTs) and field-effect transistors (MOS).

[0036] In one example, when the inverter is a three-level Type-I inverter, determining whether the target switch and other switches meet their respective preset timing conditions may include: obtaining the current state and duration of the target switch; determining whether the duration of the target switch's current state meets the preset action condition corresponding to the current state; determining whether the dead time between the target switch and its interlocked switches meets the preset dead time condition; determining whether the switching between the target switch and its bridge arm switches meets the preset switching condition; and determining whether the state of the in-phase switches of the target switch meets the preset state condition. Of course, when the inverter is a two-level inverter or other devices, the preset timing conditions for each switch can be set according to the specific circumstances.

[0037] The current state of the target switch can include an ON state and an OFF state. Determining whether the duration of the current state of the target switch satisfies the preset action conditions corresponding to the current state includes: when the current state of the target switch is ON, determining whether the duration of the ON state satisfies a preset OFF condition; when the current state of the target switch is OFF, determining whether the duration of the OFF state satisfies a preset ON condition. In a specific example, the preset OFF condition may include: the duration of the ON state of the target switch is greater than or equal to a preset ON duration threshold; the preset ON condition may include: the duration of the OFF state of the target switch is greater than or equal to a preset OFF duration threshold.

[0038] The preset dead-time condition may include: the dead-time between the target switch and the switch interlocked with it is greater than or equal to the preset dead-time threshold.

[0039] The preset switching conditions may include: if the target switch is an external switch, when the PWM signal is used to control the target switch to turn on, the switch in the same bridge arm as the target switch is already in the on state before the target switch is turned on, and the interval between their on-time switching satisfies the first preset on-time switching duration condition; when the PWM signal is used to control the target switch to turn off, the switch in the same bridge arm as the target switch can only be turned off after the target switch is turned off, and the interval between their off-time switching satisfies the first preset off-time switching duration condition; if the target switch is an internal switch, when the PWM signal is used to control the target switch to turn on, the target switch is turned on before the switch in the same bridge arm as it is turned on, and the interval between their on-time switching satisfies the second preset on-time switching duration condition; when the PWM signal is used to control the target switch to turn off, the target switch is turned off after the switch in the same bridge arm as it is turned off, and the interval between their off-time switching satisfies the second preset off-time switching duration condition.

[0040] The preset state conditions may include: if the target switch is an outer switch of the same bridge arm, when the PWM signal is used to control the target switch to turn on, the outer switch of the target switch is in the off state; if the target switch is an inner switch of the same bridge arm, when the PWM signal is used to control the target switch to turn off, the inner switch of the target switch is in the on state.

[0041] According to the method of this embodiment, by controlling the PWM signal of the switching transistor under various operating conditions, the switching state of the switching transistor is controlled strictly in accordance with the circuit topology requirements, thereby improving the reliability and safety of the switching transistor and the stability of the converter system.

[0042] The topology control requirements of the three-level inverter are transformed into logic conditions for triggering the turn-on and turn-off of each IGBT device. The PWM signal of each switching device is controlled to ensure that the switching devices switch accurately according to the topology requirements, thereby improving the safety of the switching devices and the control performance and reliability of the system.

[0043] Example 2

[0044] This embodiment introduces a PWM signal control method based on FPGA or CPLD, taking an application to a type I three-level inverter as an example. The method in this embodiment is applicable to many fields such as experimental and industrial applications.

[0045] The terms used in this embodiment are as follows:

[0046] IGBT: Insulated Gate Bipolar Transistor.

[0047] FPGA: Field Programmable Gate Array.

[0048] CPLD: Complex Programmable Logic Device.

[0049] PWM: Pulse Width Modulation.

[0050] Taking a type I three-level inverter as an example, the topology diagram is as follows: Figure 2 As shown, there is a distinction between internal and external IGBTs in phase. Based on the topology switching requirements, the four IGBT switches in phase must satisfy pulse interlocking, and also ensure that the pulses of the internal and external IGBTs in the same bridge arm operate according to the principle that the internal IGBT turns on before the external IGBT and vice versa. Furthermore, the minimum pulse width requirement for turn-on and turn-off must be guaranteed. For example... Figure 2 As shown, T1 to T4 represent single-phase IGBT transistors. T1 and T3 are interlocked, as are T2 and T4. T1 and T4 are the outer transistors of the same phase, and T2 and T3 are the inner transistors of the same phase. T1 and T2 are the inner and outer transistors of the same bridge arm, respectively, and T3 and T4 are the inner and outer transistors of the same bridge arm, respectively. The timing diagram for normal switching of the switching transistors is shown below. Figure 3 As shown, S1 and S2 represent two original pulse signals sent by the upper control system. S1 produces complementary pulses T1 and T3, and S2 produces complementary pulses T4 and T2.

[0051] This embodiment of the PWM signal control method based on FPGA or CPLD converts various operating conditions required by the system topology (e.g., dead time, minimum turn-on pulse width, minimum turn-off pulse width, and device switching sequence) into several processing conditions that trigger the state transition of a single switch, in conjunction with the upper-level control signal. A schematic diagram for controlling a single PWM signal is shown below. Figure 4 As shown, when a PWM control signal is received, it is simultaneously determined whether conditions 1, 2 and 3 are met. If they are met, it is determined whether the limiting conditions of the controlled switch itself are met. If the controlled switch itself also meets the requirements, the PWM control signal is output.

[0052] Taking transistor T1 as an example, since it is required that the two external transistors T1 and T4 in phase cannot be turned on at the same time, it is required that the original pulse signals S1 and S2 be prohibited from having the state 11.

[0053] like Figure 5 As shown, the conditions under which transistor T1 is turned on according to the PWM signal may include:

[0054] ①The turn-off time of tube T3 reaches the dead time and remains off;

[0055] ② T2 pipe has been activated and the activation switching time has been reached and it remains activated;

[0056] ③ T4 tube remains off;

[0057] ④ Input control signal S1 is the turn-on signal;

[0058] ⑤ The PWM turn-off signal pulse width of transistor T1 is greater than or equal to the minimum turn-off pulse width.

[0059] T1 tube can only be turned on when all five conditions are met simultaneously.

[0060] Additionally, the conditions under which transistor T1 is turned off based on the PWM signal may include:

[0061] ①The turn-off time of tube T3 reaches the dead time and remains off;

[0062] ② T2 tube has been turned on and has reached the turn-off switching time and remains on;

[0063] ③ T4 tube remains off;

[0064] ④ Input control signal S1 is a shutdown signal;

[0065] ⑤ The PWM turn-on signal pulse width of transistor T1 is greater than or equal to the minimum turn-on pulse width.

[0066] The turn-off of transistor T1 can only be triggered when all five conditions are met simultaneously. The specific functional block diagram is as follows: Figure 6 As shown, S1 is the upper-level control signal, and PWM_T1, PWM_T2, PWM_T3, and PWM_T4 represent respectively. Figure 4 The pulse signals of transistors T1, T2, T3, and T4.

[0067] Similarly, the PWM signal control for other IGBT states is executed in a similar way. This control method enables the control of the PWM signal of the IGBT under various operating conditions, so that each IGBT switches its switching state according to the circuit topology requirements, thereby improving the accuracy and reliability of the IGBT device switching action.

[0068] This embodiment implements the above-mentioned PWM signal control method by executing a software program on an FPGA / CPLD. Its software architecture diagram is shown below. Figure 7 As shown, the PWM software function block for a single switching transistor can include a PWM control module and a constraint module.

[0069] The PWM control module can include two processing modules and one triggering module. The PWM control module primarily receives a PWM signal for the target switching transistor. Processing modules 1 and 2 determine whether other switching transistors besides the target transistor meet their respective preset timing conditions and send a flag signal indicating the determination result to the triggering module accordingly. Processing module 1 can perform dead-time processing on the pulse signals of the interlocked IGBT transistors, and processing module 2 can process the switching sequence of the inner and outer transistors within the same bridge arm, ensuring that the switching transistors in the same bridge arm follow the principle of the inner transistor turning on before the outer transistor and the outer transistor turning on after the inner transistor and turning off before the inner transistor.

[0070] The constraint module can contain three processing modules, which are used to perform minimum pulse width limitation processing on the pulse signal to be output, and feed back the minimum turn-on and minimum turn-off flag signals to the trigger module in the PWM control module.

[0071] The trigger module integrates all the flag signals it receives and outputs the final PWM pulse signal to trigger the IGBT to turn on and off, so as to control the PWM signal according to the specific topology requirements.

[0072] Of course, different settings can be applied to the various functional modules of the software; in this embodiment... Figure 7 This is just one example; those skilled in the art can configure it according to their actual needs.

[0073] For the PWM signal of a single IGBT device, there can be many conditions that trigger the IGBT device to turn on and off. The method in this embodiment can accurately switch the signal state when different constraints are input.

[0074] The control method in this embodiment can effectively and reliably control the PWM signal of the switching transistor under various operating conditions. It strictly controls the switching device to switch the switching state according to the circuit topology requirements, which helps to ensure the safety and reliability of the switching device. It is applicable to various operating conditions that control PWM signals and has wide applicability.

[0075] Example 3

[0076] This embodiment provides a PWM signal control device, including: a judgment module, used to determine whether the target switch and other switches besides the target switch meet their respective preset timing conditions when a PWM signal for the target switch is received; and a trigger module, used to send the PWM signal to the target switch to control the target switch to perform corresponding switching actions when it is determined that the target switch and other switches besides the target switch meet their respective preset timing conditions.

[0077] In another example, the PWM signal control device of this embodiment may further include a processor and a memory, wherein the processor is used to execute the following program modules stored in the memory: a judgment module and a trigger module, to realize the control of the PWM signal.

[0078] It should be noted that although several units / modules or sub-units / modules of the PWM signal control device are mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of the present invention, the features and functions of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functions of one unit / module described above can be further divided and embodied by multiple units / modules.

[0079] Example 4

[0080] This embodiment provides an electronic device, including a processor, a memory, and a trigger. When the program code in the memory is executed by the processor, it implements the steps of the PWM signal control method described above. When a PWM signal for a target switch is received, it determines whether the target switch and other switches meet their respective preset timing conditions. When it is determined that the target switch and other switches meet their respective preset timing conditions, the trigger sends the PWM signal to the target switch to control the target switch to perform a corresponding switching action.

[0081] The electronic device includes at least one of the following: field-programmable gate arrays and complex programmable logic devices.

[0082] In one embodiment, the electronic device may include one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0083] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash memory (flash FLASH RAM). Memory is an example of computer-readable media.

[0084] Example 5

[0085] This embodiment provides an inverter, including the electronic equipment described above, for controlling the PWM signal of the switching transistor.

[0086] Example 6

[0087] This embodiment provides a storage medium storing program code. When the program code is executed by a processor, it implements the steps of the inverter PWM signal control method described above.

[0088] The program code can be stored in any combination of one or more storage media. The storage media can be a readable signal medium or a readable storage medium.

[0089] Readable storage media may include, for example, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media may include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0090] A readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying readable program code. This propagated data signal may take various forms, such as electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any storage medium other than a readable storage medium that can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0091] The program code contained on the storage medium can be transmitted using any suitable medium, such as wireless, wired, fiber optic, RF, or any suitable combination thereof.

[0092] Program code for performing the operations of this invention can be written in any combination of one or more programming languages. Programming languages ​​may include object-oriented programming languages—such as Java, C++, etc.—as well as conventional procedural programming languages—such as the "C" language or similar programming languages. The program code may execute entirely on the user's computing device, partially on the user's device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device may be connected to the user's computing device via any type of network (e.g., may include a local area network or a wide area network), or it may be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0093] Although the operations of the method of the invention are described in a specific order in the accompanying drawings, this does not require or imply that the operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0094] While the spirit and principles of the invention have been described with reference to several specific embodiments, it should be understood that the invention is not limited to the disclosed specific embodiments, and the division of aspects does not imply that features in these aspects cannot be combined for benefit; such division is merely for ease of description. The invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[0095] It should be noted that the terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the exemplary implementations according to this application. When the terms “comprising” and / or “including” are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0096] It should be noted that the terms "first," "second," etc., used in the specification, claims, and drawings of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented, for example, in sequences other than those illustrated or described herein.

[0097] It should be understood that the exemplary embodiments described herein can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. These embodiments are provided so that the disclosure of this application is thorough and complete, and that the concept of these exemplary embodiments is fully conveyed to those skilled in the art, and should not be construed as limiting the invention.

Claims

1. A method for controlling a PWM signal, characterized in that, Applied to inverters, including: When a PWM signal is received for the target switch, it is determined whether the target switch and other switches meet their respective preset timing conditions. When it is determined that the target switch and other switches meet their respective preset timing conditions, the PWM signal is sent to the target switch to control the target switch to perform the corresponding switching action. The inverter includes: a two-level inverter and a three-level inverter; wherein the three-level inverter includes a three-level type I inverter; When the inverter is a three-level type I inverter, it is determined whether the target switch and other switches meet their respective preset timing conditions, including: Obtain the current state of the target switch and the duration of the current state, and determine whether the duration of the current state of the target switch meets the preset action conditions corresponding to the current state. Determine whether the dead time between the target switch and the switch interlocked with it meets the preset dead time condition; Determine whether the switching between the target switch and the switch in the same bridge arm meets the preset switching conditions; and Determine whether the state of the non-inverting switch of the target switch meets the preset state conditions; The preset switching conditions include: If the target switch is an external switch, when the PWM signal is used to control the target switch to turn on, the switch in the same bridge arm as the target switch is already in the on state before the target switch is turned on, and the interval between their on-to-off switching meets the first preset on-to-off switching time condition. When the PWM signal is used to control the target switch to turn off, the switch in the same bridge arm as the target switch can only be turned off after the target switch is turned off, and the interval between their off-to-off switching meets the first preset off-to-off switching time condition. If the target switch is an internal switch, when the PWM signal is used to control the target switch to turn on, the target switch turns on before the switch in the same bridge arm turns on, and the interval between their turn-on switching meets the second preset turn-on switching duration condition. When the PWM signal is used to control the target switch to turn off, the target switch turns off after the switch in the same bridge arm turns off, and the interval between their turn-off switching meets the second preset turn-off switching duration condition.

2. The PWM signal control method according to claim 1, characterized in that, The current state of the target switch includes: on state and off state; Determining whether the duration of the current state of the target switch meets the preset action conditions corresponding to the current state includes: When the target switch is currently in the ON state, determine whether the duration of the ON state meets the preset turn-off condition. When the target switch is currently in the off state, determine whether the duration of the off state meets the preset turn-on conditions.

3. The PWM signal control method according to claim 2, characterized in that, The preset shutdown conditions include: The duration of the target switch's on state is greater than or equal to a preset on-time threshold. The preset activation conditions include: The duration of the off state of the target switch is greater than or equal to a preset off duration threshold.

4. The PWM signal control method according to claim 1, characterized in that, The preset dead zone conditions include: The dead time between the target switch and the switch interlocked with it is greater than or equal to a preset dead time threshold.

5. The PWM signal control method according to claim 1, characterized in that, The preset state conditions include: If the target switch is an outer transistor in the same bridge arm, when the PWM signal is used to control the target switch to turn on, the outer transistor in the same phase of the target switch is in the off state. If the target switch is an inner switch in the same bridge arm, when the PWM signal is used to control the target switch to turn off, the inner switch of the target switch in the same phase is in the on state.

6. The PWM signal control method according to claim 1, characterized in that, The switching transistors include: insulated gate bipolar transistors and field-effect transistors.

7. The PWM signal control method according to claim 1, characterized in that, The preset timing conditions are set according to the state timing diagram that is followed by the target switch and other switches besides the target switch.

8. A control device for a PWM signal, characterized in that, Steps for executing the control method of the PWM signal as described in any one of claims 1-7.

9. An electronic device, characterized in that, The device includes a processor, a memory, and a trigger. When the program code in the memory is executed by the processor, it implements the steps of the PWM signal control method as described in any one of claims 1 to 7, wherein when a PWM signal for a target switch is received, the trigger determines whether the target switch and other switches satisfy their respective preset timing conditions; when it is determined that the target switch and other switches satisfy their respective preset timing conditions, the trigger sends the PWM signal to the target switch to control the target switch to perform a corresponding switching action.

10. The electronic device according to claim 9, characterized in that, The electronic device includes at least one of the following: field-programmable gate arrays and complex programmable logic devices.

11. An inverter, characterized in that, Includes the electronic device as described in claim 9 or 10, for controlling the PWM signal of the switching transistor.

12. A storage medium, characterized in that, The device stores program code that, when executed by a processor, implements the steps of the PWM signal control method as described in any one of claims 1 to 7.

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