Gate drive device

Abstract

This document discloses a gate driving device that drives the gate of a semiconductor switching element and controls a transient voltage corresponding to the voltage at the main terminal of the semiconductor switching element to a target value during switching of the semiconductor switching element. The gate driving device includes a calculation circuit, a driving circuit, a detection circuit, and a learning circuit. The calculation circuit executes a predetermined calculation mode to calculate an operational amount for operating on the gate driving speed of the semiconductor switching element. The driving circuit drives the gate of the semiconductor switching element according to this operational amount. The detection circuit detects the transient voltage. The learning circuit performs learning processing based on the operational amount calculated by the calculation circuit and the transient voltage detected by the detection circuit to change the predetermined calculation mode.

Description

Technical Field

[0001] This disclosure relates to a gate driving device for driving the gate of a semiconductor switching element. Background Technology

[0002] In a gate driving device used to drive the gate of a semiconductor switching element, the transient voltage corresponding to the voltage at the main terminal of the semiconductor switching element during the switching time is controlled to a desired target value for purposes such as reducing losses, reducing noise, and preventing element failure. The transient voltage includes the rate of change (i.e., dV / dt of the voltage at the main terminal during switching) and the peak value of the voltage at the main terminal during switching (i.e., surge voltage).

[0003] JP 2019-57757 A discloses a technique that detects the rate of change of the drain voltage (dV / dt) of a semiconductor switching element (such as a MOSFET), repeatedly adjusts the gate waveform to ensure that the detected value does not exceed a target value, and terminates the adjustment at the stage where the gate waveform with the detected value does not exceed the target value. In the following description, the technique disclosed in JP2019-57757 A will also be referred to simply as related technology. Summary of the Invention

[0004] In related technologies, circuits must be operated to learn the optimal gate waveform profile, and it is difficult to obtain the optimal waveform during the trial-and-error period in such a learning process. Therefore, these technologies can only be applied to, for example, adjustment processes before product shipment. In these technologies, the optimal gate signal is generated after learning is complete. Therefore, when various characteristics change after learning, the deviations accompanying those changes cannot be corrected.

[0005] While such related technologies can eliminate individual differences, adjustments cannot be made during actual operation. Therefore, dV / dt gradually deviates from the target value due to fluctuations caused by aging in the characteristics of the drive circuit, semiconductor switching elements, etc. In other words, in these related technologies, it is not possible to control dV / dt, which is the transient voltage during the switching of semiconductor switching elements, to the target value with high precision.

[0006] The purpose of this disclosure is to provide a gate control device that can control the transient voltage during the switching of a semiconductor switching element to a desired target value with high precision.

[0007] According to one aspect of this disclosure, a gate driving device drives the gate of a semiconductor switching element and controls the transient voltage during switching of the semiconductor element to a target value. The transient voltage corresponds to the voltage at the main terminal of the semiconductor switching element. The gate driving device includes a computing circuit, a driving circuit, a detection circuit, and a learning circuit.

[0008] The calculation circuit calculates the operating amount for controlling the gate drive speed of the semiconductor switching element based on the target value of the transient voltage using a predetermined calculation mode. The drive circuit drives the gate of the semiconductor switching element based on the operating amount calculated by the calculation circuit. The detection circuit detects the transient voltage. The learning circuit performs learning processing to change the calculation mode based on the operating amount calculated by the calculation circuit and the detected value of the transient voltage detected by the detection circuit.

[0009] In this configuration, by performing a learning process, the calculation pattern used by the computing circuit to calculate the operational quantity is optimized to conform to the transient voltage actually generated in the semiconductor switching element, which is the target of the gate drive device. In this way, through the above configuration, the calculation pattern is optimized according to the differences between individual products. Therefore, even in the presence of individual differences, the gate drive speed can be controlled to the desired speed, and furthermore, the transient voltage can be controlled to the desired target value. Attached Figure Description

[0010] The above-described objects, features, and advantages of this disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. In the drawings:

[0011] Figure 1 This is a schematic diagram showing the external structure of the gate driving device and the half-bridge circuit according to the first embodiment;

[0012] Figure 2 This is a schematic diagram showing the waveforms of each part when the semiconductor switching element is turned off according to the first embodiment;

[0013] Figure 3 This is a diagram schematically illustrating the main functions of the gate driving device according to the first embodiment;

[0014] Figure 4 This is a diagram illustrating an example of a specific construction of the gate driving device according to the first embodiment;

[0015] Figure 5 This is a schematic diagram illustrating the operation flow of the gate driving device according to the first embodiment;

[0016] Figure 6 This is a diagram schematically illustrating the main functions of the gate driving device according to the second embodiment;

[0017] Figure 7 This is a diagram illustrating an example of a specific construction of the gate driving device according to the second embodiment;

[0018] Figure 8 This is a diagram illustrating an example of mapping data according to the second embodiment;

[0019] Figure 9 This is a diagram illustrating an example of updated mapping data generated by the update process according to the second embodiment;

[0020] Figure 10 This is a schematic diagram illustrating the operation flow of the gate driving device according to the second embodiment;

[0021] Figure 11 This is a diagram illustrating an example of updated mapping data generated by the update process of the first modified form of the second embodiment;

[0022] Figure 12 This is a diagram illustrating an example of updated mapping data generated by the update process of the second modified form of the second embodiment;

[0023] Figure 13 This is a diagram schematically illustrating the main functions of the gate driving device according to the third embodiment;

[0024] Figure 14 This is a diagram illustrating an example of a specific construction of the gate driving device according to the third embodiment;

[0025] Figure 15 This is a diagram illustrating an example of mapping data according to a third embodiment;

[0026] Figure 16 This is a schematic diagram illustrating the operation flow of the gate driving device according to the third embodiment;

[0027] Figure 17 This is a diagram schematically illustrating the main functions of the gate driving device according to the fourth embodiment;

[0028] Figure 18 This is a diagram illustrating an example of a specific construction of the gate driving device according to the fourth embodiment;

[0029] Figure 19 This is a schematic diagram illustrating the operation flow of the gate driving device according to the fourth embodiment;

[0030] Figure 20 This is a diagram schematically illustrating the main functions of the gate driving device according to the fifth embodiment;

[0031] Figure 21 This is a diagram illustrating an example of a specific construction of the gate driving device according to the fifth embodiment;

[0032] Figure 22 This is a diagram illustrating an example of mapping data according to the fifth embodiment;

[0033] Figure 23This is a diagram illustrating an example of updated mapping data generated by the update process according to the fifth embodiment;

[0034] Figure 24 This is a schematic diagram illustrating the operation flow of the gate driving device according to the fifth embodiment;

[0035] Figure 25 This is a diagram schematically illustrating the main functions of the gate driving device according to the sixth embodiment;

[0036] Figure 26 This is a diagram illustrating an example of a specific construction of the gate driving device according to the sixth embodiment;

[0037] Figure 27 This is a diagram illustrating an example of mapping data according to the sixth embodiment;

[0038] Figure 28 This is a schematic diagram illustrating the operation flow of the gate driving device according to the sixth embodiment;

[0039] Figure 29 This is a diagram schematically illustrating the main functions of the gate driving device according to the seventh embodiment;

[0040] Figure 30 This is a diagram illustrating an example of a specific construction of the gate driving device according to the seventh embodiment;

[0041] Figure 31 This is a diagram schematically illustrating the operation flow of the gate driving device according to the seventh embodiment;

[0042] Figure 32 It is a graph that schematically shows the relationship between the rate of change of drain-source voltage and gate voltage;

[0043] Figure 33 It is a diagram that schematically illustrates the relationship between surge voltage and gate voltage;

[0044] Figure 34 It is a schematic diagram illustrating the relationship between the rate of change of drain-source voltage and gate resistance; and

[0045] Figure 35 This is a diagram that schematically illustrates the relationship between surge voltage and gate resistance. Detailed Implementation

[0046] In the following description, several embodiments will be illustrated with reference to the accompanying drawings. In the embodiments, the same reference numerals refer to substantially the same constructions, and repetitive descriptions will be omitted.

[0047] (First Embodiment)

[0048] In the following text, reference will be made to Figures 1 to 5 The first embodiment is described.

[0049] (Schematic structure of the gate drive device)

[0050] like Figure 1 As shown, in this embodiment, gate drive device 1A drives semiconductor switch element 5A, which forms the upper arm of half-bridge circuit 4 connected between a pair of DC power lines 2 and 3. In this embodiment, gate drive device 1B drives semiconductor switch element 5B, which forms the lower arm of half-bridge circuit 4. In this case, gate drive devices 1A and 1B have the same construction, and semiconductor switch elements 5A and 5B have the same construction. Therefore, in this specification, where it is not necessary to distinguish between gate drive devices 1A and 1B, nor between semiconductor switch elements 5A and 5B, they are generally referred to by omitting the letters at the end.

[0051] Half-bridge circuit 4 is included in an inverter for driving a motor (not shown). For example, a DC power source (e.g., a battery) (not shown) supplies source voltage Va to half-bridge circuit 4 via DC power lines 2 and 3. In this case, for example, it is assumed that gate drive device 1 is used for onboard applications in a vehicle (e.g., an automobile). The source voltage Va applied to semiconductor switching element 5 is a relatively high voltage (e.g., several hundred volts).

[0052] Semiconductor switching element 5 is a power element, and in this case, it has a configuration including an N-channel MOSFET and a freewheeling diode, with its source side connected as the anode between the drain and source of the MOSFET, i.e., connected to the MOSFET in reverse parallel. In this case, the freewheeling diode is provided as a different element from the MOSFET. Alternatively, the body diode of the MOSFET can be used as the freewheeling diode.

[0053] The drain of semiconductor switching element 5A is connected to the DC power supply line 2 on the high-potential side. The source of semiconductor switching element 5A is connected to the drain of semiconductor switching element 5B. The source of semiconductor switching element 5B is connected to the DC power supply line 3 on the low-potential side. Node N1, which serves as the interconnection node between semiconductor switching elements 5A and 5B, is connected to a motor (not shown). With this configuration, the load current IL, which is the output current of the half-bridge circuit 4, is supplied to the motor. The controller 6 has a configuration that includes, for example, a microcomputer, and controls the drive of the motor by controlling the operation of the half-bridge circuit 4, which is a component of the inverter.

[0054] A detection signal Sc, representing the detected value of the load current IL output by a current detection unit (not shown), is given to the controller 6. The controller 6 generates and outputs a command signal Sa instructing the operation of the gate drive device 1A and a command signal Sb instructing the operation of the gate drive device 1B based on the detection signal Sc, so that the load current IL is matched with the desired target current. Based on the command signal Sa given by the controller 6, the gate drive device 1A performs PWM control on the drive of the semiconductor switching element 5A. PWM stands for Pulse Width Modulation. Based on the command signal Sb from the controller 6, the gate drive device 1B performs PWM control on the drive of the semiconductor switching element 5B.

[0055] In this configuration, semiconductor switching elements 5A and 5B are switched on and off in a complementary manner. Therefore, during the period when semiconductor switching element 5A is on, semiconductor switching element 5B is off. During the period when semiconductor switching element 5B is on, semiconductor switching element 5A is off. In this configuration, during the period when the load current IL flows from node N1 to the motor, semiconductor switching element 5A is driven so that the current flows in the positive direction from the drain to the source, and semiconductor switching element 5B is driven so that the current flows in the reverse direction from the source to the drain.

[0056] In this configuration, during the period when the load current IL flows from the motor to node N1, semiconductor switching element 5B is driven so that the current flows in the positive direction from the drain to the source, and semiconductor switching element 5A is driven so that the current flows in the reverse direction from the source to the drain.

[0057] In this configuration, the drain-source voltage Vds in the semiconductor switching element 5 is the voltage at the main terminals of the semiconductor switching element 5 and corresponds to the element voltage. In this configuration, the drain current Id is the current flowing between the main terminals of the semiconductor switching element 5 and corresponds to the element current. In this specification, the drain current Id and the drain-source voltage Vds will also be simply referred to as current Id and voltage Vds, respectively.

[0058] The waveform of a portion of the switching time when semiconductor switching element 5 is switched (specifically, when semiconductor switching element 5 is turned off) is as follows: Figure 2 As shown. Although Figure 2 The waveform corresponding to semiconductor switch element 5B is shown, but semiconductor switch element 5A also has a similar waveform. The off-state voltage Vds_off when semiconductor switch element 5B is off is almost equal to the source voltage Va.

[0059] The peak value Vds_p of the voltage Vds when disconnected corresponds to the peak value of the voltage at the main terminal when the semiconductor switching element 5 switches. The peak value Vds_p is obtained by adding the voltage ΔVds to the disconnect voltage Vds_off, and is equal to the surge voltage superimposed on the semiconductor switching element 5B. Therefore, in the following description, the peak value Vds_p is also referred to as the surge voltage Vsrg. In this case, the slope of the voltage Vds fluctuation when disconnected (i.e., the switching rate) corresponds to the rate of change of the voltage at the main terminal when the semiconductor switching element 5 switches. In the specification, the slope of the voltage Vds fluctuation is also referred to as the rate of change dV / dt.

[0060] Each of the surge voltage Vsrg and the rate of change dV / dt corresponds to a transient voltage, which corresponds to the voltage at the main terminal of the semiconductor switching element 5 at the switching time when the semiconductor switching element 5 is switched. The gate driving device 1 of the embodiment has various functions, which will be described later, such that the transient voltage can be controlled to a desired target value. The transient voltage that is the control target of the gate driving device 1 of the embodiment has a rate of change dV / dt.

[0061] (Main functions of gate drive devices)

[0062] Then, refer to Figure 3 Describe the main functions of gate drive device 1. Figure 3 In the diagram, the main functions of the gate driving device 1 are represented as functional blocks. The specific implementation of these functions will be described later. In the following description, among the two semiconductor switching elements 5, the target driven by its own device will be referred to as the semiconductor switching element 5 of its own arm, and the target driven by another gate driving device 1 different from its own device will be referred to as the semiconductor switching element 5 of the opposite arm. When simply referring to the semiconductor switching element 5, the semiconductor switching element 5 of its own arm is used.

[0063] The computational circuit (CALCU CIRT) 11 uses a target value of the rate of change dV / dt to calculate the operational quantity for operating the gate drive speed of the semiconductor switching element 5 using a predetermined calculation method. The gate current, gate voltage, gate resistance, etc., of the semiconductor switching element 5 can be mentioned as operational quantities. The drive circuit (DRIV CIRT) 12 drives the gate of the semiconductor switching element 5 based on the operational quantity calculated by the computational circuit 11. The detection circuit (DET CIRT) 13 detects the rate of change dV / dt of the semiconductor switching element 5 on its own arm. The learning circuit (LEARN CIRT) 14 executes a learning process that can change the computational method based on the operational quantity calculated by the computational circuit 11 and the detected value of the rate of change dV / dt detected by the detection circuit 13. The computational method can also be referred to as a computational mode. The learning process can also be referred to as a learning process.

[0064] In this case, the calculation circuit 11 obtains in advance the target value of the rate of change dV / dt and the relational information representing the relationship between the operation quantity and the rate of change dV / dt, and calculates the operation quantity based on the target value of the rate of change dV / dt and the obtained relational information. Specifically, the calculation circuit 11 obtains the model parameters in advance as relational information, and calculates the operation quantity using the target value of the rate of change dV / dt and the model parameters through the model formula. As part of the learning process described above, the learning circuit 14 calculates a learning value as the value corresponding to the model parameters based on the operation quantity calculated by the calculation circuit 11 and the detected value of the rate of change dV / dt detected by the detection circuit 13, and updates the model parameters based on the calculated learning value, thereby changing the calculation method of the operation quantity.

[0065] In this case, the drive circuit 12 has a configuration that drives the gate of the semiconductor switching element 5 with a constant current. Therefore, the calculation circuit 11 calculates the gate current Ig of the semiconductor switching element 5 as an operating quantity. When the model parameter is set to K, the target value of the rate of change dV / dt is set to dV / dt*, and the gate current as an operating quantity is set to Ig, the calculation circuit 11 uses the following formula (1) as the model formula to calculate the gate current Ig.

[0066] Ig=K×dV / dt (1)

[0067] When the learning value is set to Ka, the gate current calculated by the calculation circuit 11 is set to Iga, and the detected value of the rate of change dV / dt detected by the detection circuit 13 is set to dV / dt as is. The learning circuit 14 uses the following formula (2) as the inverse model formula to calculate the learning value Ka.

[0068] Ka=Iga÷dV / dt (2)

[0069] Storage unit 15 can store model parameters K updated by learning circuit 14. Before the power is turned off by the gate drive device 1, learning circuit 14 stores the updated model parameters K in storage unit 15. At the start of the next operation after the power is turned off by the gate drive device 1, calculation circuit 11 calculates the operation quantity using the model parameters K stored in storage unit 15. In this case, during the learning process, learning circuit 14 changes the calculation method based on the current operation quantity calculated by calculation circuit 11 as the current operation quantity and the detected value of the current rate of change dV / dt detected by detection circuit 13, and further, based on the past operation quantity calculated by calculation circuit 11 as the past operation quantity and the detected value of the past rate of change dV / dt detected by detection circuit 13.

[0070] (Specific structure of the gate drive device)

[0071] For example, it can be adopted as follows Figure 4 The illustrated construction example is a specific construction of a gate drive device 1 having the functions described above. Although in Figure 4 The specific construction of the gate driving device 1 is shown using the gate driving circuit 1B as an example, but a similar construction can also be used for the gate driving device 1A. Figure 4 The gate drive device 1B shown includes a calculation circuit 11, a drive circuit 12, a detection circuit 13, a learning circuit 14, a storage unit 15, etc.

[0072] For example, storage cell 15 is a non-volatile memory that pre-stores the target value dV / dt* of the rate of change dV / dt, the value of the model parameter K, etc. In a system where the gate drive device 1 is always powered, volatile memory can be used as storage cell 15. In the specification, the target value dV / dt* of the rate of change dV / dt will also be referred to as the target rate of change dV / dt*, and the value of the model parameter K will also be referred to as the K value.

[0073] The target rate of change dV / dt* is sent as an instruction from the higher-order control device and can therefore be obtained in advance. For example, the value of K can be obtained in advance by performing various simulations. When the calculation circuit 11 requests to read the target rate of change dV / dt*, the storage unit 15 outputs a signal representing the target rate of change dV / dt*. When the calculation circuit 11 requests to read the model parameter K, the storage unit 15 outputs a signal representing the model parameter K. Figure 4 In the diagrams, for signals, the same reference numerals are shown as those representing the values ​​of the signals.

[0074] The detection circuit 13 is supplied with the voltage at node N1, i.e., the drain voltage of the semiconductor switching element 5B. The detection circuit 13 is configured to receive the drain voltage, i.e., the voltage Vds of the semiconductor switching element 5B when the potential of the source of the semiconductor switching element 5B is used as a reference and the waveform of the voltage Vds is monitored. The detection circuit 13 detects the rate of change dV / dt of the voltage Vds by monitoring the waveform of the voltage Vds. The detection circuit 13 outputs a signal representing the detected value of the rate of change dV / dt.

[0075] At the start of operation, the calculation circuit 11 requests the target rate of change dV / dt* and model parameter K from the storage unit 15. Through operation, the signals dV / dt* and K output from the storage unit 15 are supplied to the calculation circuit 11. The calculation circuit 11 has a register (REGIS) 21 (which stores the target rate of change dV / dt* represented by the signal dV / dt*), a register 22 (which stores the value of K represented by the signal K), and an arithmetic circuit 23. The calculation circuit 11 stores the target rate of change dV / dt* and model parameter K read from the storage unit 15 into registers 21 and 22.

[0076] The arithmetic circuit 23 reads the target rate of change dV / dt* stored in register 21 and the K value stored in register 22, and multiplies them. The value obtained by the arithmetic circuit 23 as the result of the operation corresponds to the gate current Ig mentioned above. The arithmetic circuit 23 outputs a signal representing the gate current Ig. In this case, the K value stored in register 22 is updated by the operation of the learning circuit 14, which will be described later. Before the power supply to the gate drive device 1B is turned off, register 22 outputs a signal representing the stored K value to the storage cell 15. In this way, the K value stored in the storage cell 15 is updated by rewriting the K value stored in register 22.

[0077] The signal dV / dt output from the detection circuit 13 and the signal Ig output from the calculation circuit 11 are input to the learning circuit 14. The learning circuit 14 has an arithmetic circuit 24 and a filtering circuit 25. The arithmetic circuit 24 divides the value of the gate current Ig, represented by the signal Ig, by the detected value of the rate of change dV / dt, represented by the signal dV / dt. The value obtained as a result of this calculation by the arithmetic circuit 24 corresponds to the aforementioned learning value Ka. The arithmetic circuit 24 outputs a signal representing the learning value Ka.

[0078] The filtering circuit 25 is configured as, for example, a digital filter. The filtering circuit 25 performs the following filtering process using a learning value Ka represented by a signal Ka output from the operational circuit 24 and a K value read from register 22. Based on the following formula (3), the filtering circuit 25 obtains a learning value Ka' as a value obtained by smoothing the learning value Ka by an exponential moving average of a smoothing coefficient α. The smoothing coefficient α is a value greater than 0 and less than 1, i.e., a value satisfying "0 < α < 1".

[0079] Ka'=Ka×α+K×(1-α) (3)

[0080] The filtering circuit 25 outputs a signal representing the learning value Ka' to register 22 in the calculation circuit 11. Through this operation, the K value stored in register 22 is updated by rewriting the learning value Ka'. The filtering process of the filtering circuit 25 can be a low-pass filter or a band-pass filter other than an exponential moving average, and can be a simple moving average that holds the values ​​of the most recent 10 values ​​and uses the average of these values; it can also be another FIR filter or IIR filter.

[0081] The driving circuit 12 is configured to drive the gate of the semiconductor switching element 5 with a constant current. Specifically, the driving circuit 12 has current sources 26 and 27 and switches 28 and 29. The upstream terminal of the current source 26 is connected to a power supply line 31 supplying a source voltage Vb, and the downstream terminal of the current source 26 is connected to the gate of the semiconductor switching element 5B via switch 28. The source voltage Vb is a voltage referenced using the potential of the power supply line 32 connected to the source of the semiconductor switching element 5B, and is a voltage sufficiently higher than the gate threshold voltage of the semiconductor switching element 5B.

[0082] Current source 26 is a constant current circuit that generates a constant current supplied to the gate of semiconductor switching element 5B when it is turned on; that is, a gate current Ig_on for turning on the gate of semiconductor switching element 5B. As a configuration of the turn-on side in drive circuit 12, a resistor with a constant resistance value can be provided instead of current source 26. That is, drive circuit 12 does not necessarily need to have a constant current drive configuration on the turn-on side. For example, switch 28 has a configuration including a semiconductor switching element (e.g., a P-channel MOS transistor) and is turned on / off between current source 26 and the gate of semiconductor switching element 5B.

[0083] The downstream terminal of current source 27 is connected to power line 32, and the upstream terminal of current source 27 is connected to the gate of semiconductor switching element 5B via switch 29. Current source 27 is a constant current circuit that generates a constant current to be drawn from the gate of semiconductor switching element 5B when it is turned off, i.e., a gate current Ig_off for turning off the gate of semiconductor switching element 5B. In this case, current source 27 has a configuration capable of changing its current value based on the signal Ig output from computing circuit 11. For example, switch 29 has a configuration including a semiconductor switching element (e.g., an N-channel MOS transistor) and is turned on / off between the gate of semiconductor switching element 5B and current source 27.

[0084] An ON command, an OFF command, and a switch-end command are given to the drive circuit 12. In this case, the ON command and the OFF command are generated based on the command signal Sb by logic circuitry (not shown), and the switch-end command END is given from the external controller 6. The ON command and the OFF command can be combined into a single signal. In this case, for example, it can be arranged such that a high level signal indicates an ON command, and a low level signal indicates an OFF command. The switch-end command END can also be generated internally in the gate drive device 1B.

[0085] The operation of drive circuit 12 is controlled by these instructions. Specifically, during periods when no switching end instruction END is given, drive circuit 12 performs switching operations in a complementary manner based on the ON instruction and the OFF instruction to turn switches 28 and 29 on / off. In this case, a period in which both switches 28 and 29 are off (the so-called dead time) is provided.

[0086] When an ON command is given, drive circuit 12 turns on switch 28. Through this operation, gate current Ig_on is supplied to the gate of semiconductor switching element 5B, and semiconductor switching element 5B is turned on. When an OFF command is given, drive circuit 12 turns on switch 29. Therefore, gate current Ig_off is drawn from the gate of semiconductor switching element 5B, and semiconductor switching element 5B is turned off. When an END command is given, drive circuit 12 ends the switching operation.

[0087] (Operation flow of the gate driving device)

[0088] Then, refer to Figure 5 The operation flow of the gate driving device 1 having the above structure is described. In the gate driving device 1, during the period from power-on to power-off, the following is performed: Figure 5The process is illustrated. In S101, which is executed first after the operation begins, the target rate of change dV / dt* and the K value are read from storage unit 15 and stored in registers 21 and 22 in calculation circuit 11. That is, in S101, the target rate of change dV / dt* and the K value stored in storage unit 15 are downloaded to registers 21 and 22 in calculation circuit 11.

[0089] After executing S101, the loop start process in S102 is executed. The loop start process in S102 is a process that repeats the process from S103 to S108 until the switching end instruction END is given (i.e., under the condition that the switching end instruction END is given in S109 as the loop end process). In S103, when the turn-on instruction ON is given, the drive circuit 12 outputs the gate current Ig_on, and the semiconductor switching element 5 is switched on. The current value of the gate current Ig_on at this time is a predetermined current value.

[0090] In S104, the arithmetic circuit 23 of the calculation circuit 11 calculates the gate current Ig based on model formula (1) as described above. S104 can be executed before S103. That is, the execution order of S103 and S104 can be changed. In S105, when the off command OFF is given, the drive circuit 12 outputs the gate current Ig_off, thereby switching the semiconductor switching element 5 off. The current value of the gate current Ig_off at this time is the value corresponding to the gate current Ig calculated in S104. In S106, the detection circuit 13 detects the rate of change dV / dt of the voltage Vds generated when the detection circuit 13 is off.

[0091] In S107, the arithmetic circuit 24 of the learning circuit 14 calculates the learning value Ka based on formula (2) of the inverse model formula described above. In S108, the K value stored in the register 22 is updated by rewriting the learning value Ka', which is obtained by smoothing the learning value Ka derived by the filtering process of the filtering process circuit 25 of the learning circuit 14. S107 and S108 correspond to the learning process performed by the learning circuit 14. In the gate drive device 1, the processes in S102 to S109 described above are repeated until the switching end instruction END is given.

[0092] Each time semiconductor switching element 5 is switched, the loop process from S102 to S109 is repeated. When the switching end instruction END is given, the loop process from S102 to S109 ends, and the program proceeds to S110. In S110, the K value stored in memory unit 15 is updated by being rewritten to the K value stored in register 22 of the calculation circuit 11. After executing S110, the operation ends.

[0093] In the gate driving device 1 of the above embodiment, the calculation method for calculating the gate current Ig, which is the operating amount for operating the gate driving speed when the semiconductor switching element 5 is turned off, is optimized by the learning circuit 14 to perform the learning process, so as to conform to the rate of change dV / dt that actually occurs when the semiconductor switching element 5, which is the driving target of the gate driving device 1, is turned off.

[0094] As described above, according to the embodiment, the calculation method is optimized based on the differences between individual products. Therefore, even if there are individual differences in the gate drive device 1 and the semiconductor switching element 5, the gate drive speed of the semiconductor switching element 5 can be controlled to a desired speed, and furthermore, the rate of change dV / dt when disconnected can be controlled to a desired target value.

[0095] In the gate driving device 1, a learning process via the learning circuit 14 can be performed simultaneously with the actual operation of the gate driving device 1, i.e., during actual operation. As described above, according to the embodiment, it is also possible to perform the learning process during actual operation, i.e., to optimize the calculation method. Therefore, even in the case of property fluctuations due to aging, in the case of load fluctuations such as temperature and source voltage Va, and in similar cases, the rate of change dV / dt can be controlled to the desired target value. Therefore, according to the embodiment, it is possible to obtain an excellent effect of controlling the rate of change dV / dt during the switching of the semiconductor switching element 5 (particularly, when it is turned off) to the desired target value with high precision.

[0096] As described above, according to the embodiment, the rate of change dV / dt during the switching of the semiconductor switching element 5 is set as the control target, and the rate of change dV / dt can be controlled to the desired target value with high precision. Therefore, both EMI reduction and switching loss reduction can be achieved. EMI stands for Electromagnetic Interference.

[0097] In this case, the calculation circuit 11 calculates the gate current Ig using the model formula with model parameter K as described in formula (1) above. In this case, the learning circuit 14 calculates the learning value Ka corresponding to model parameter K using the inverse model formula as described in formula (2) above, and updates the model parameter K based on the calculated learning value Ka, thereby changing the calculation method of the gate current Ig. In this way, the calculation method of the gate current Ig can be optimized without complex processes in the calculation circuit 11 and the learning circuit 14, allowing the calculation circuit 11 and the learning circuit 14 to have relatively simple structures.

[0098] The gate driving device 1 has a storage cell 15 capable of storing the model portion updated by the learning circuit 14. The learning circuit 14 stores the updated model parameters K in the storage cell 15 before the power of the gate driving device is turned off. At the start of the next operation performed after the power of the gate driving device 1 is turned off, the calculation circuit 11 calculates the gate current Ig using the model parameters K stored in the storage cell 15. In this way, in the second and subsequent operations, the gate current Ig is calculated using the model parameters K learned in the last operation from the start time of the operation. Therefore, the rate of change dV / dt can be stably controlled to the target value with high accuracy immediately after the start of the operation.

[0099] During the learning process, the learning circuit 14 modifies its calculation method based on the current gate current Ig calculated by the calculation circuit 11 and the current rate of change dV / dt, which is the current detection value detected by the detection circuit 13, as well as the past gate current Ig calculated by the calculation circuit 11 and the past rate of change dV / dt, which is the past detection value detected by the detection circuit 13. Specifically, during the learning process, the learning circuit 14 updates the model parameter K based on the learning value Ka' obtained by smoothing the learning value Ka. The learning value Ka is derived by performing a filtering process using the current learning value Ka output from the arithmetic circuit 24 and the K value read from the register 22 of the calculation circuit 11 (i.e., the past learning value Ka). In this way, even if erroneous learning occurs where the learning value Ka becomes an incorrect value due to noise, temporary anomalies, etc., the rate of change dV / dt deviating from the target value due to this influence can be suppressed.

[0100] (Modifications regarding K-value updates)

[0101] In this embodiment, the learning circuit 14 writes and stores the updated model parameter K, that is, the K value stored in the storage cell 15 is updated before the power to the gate drive device 1 is turned off. This can be modified as follows.

[0102] The learning circuit 14 can store the updated model parameters K in the storage unit 15 after executing the learning process a specified number of times (once or more). Specifically, the learning circuit 14 can execute S110 each time S107 and S108 are executed a specified number of times. That is, it can change... Figure 5 The process shown causes S110 to be executed during the loop process.

[0103] If the difference between the value of the model parameter K updated by the learning circuit 14 before the power is turned off of the gate drive device 1 or after the learning process has been performed a specified number of times (once or more) and the value of the model parameter K at the start of the operation exceeds a preset allowable value, then the learning circuit 14 can store the updated model parameter K in the storage cell 15. In this way, while suppressing the number of times it is written to the storage cell 15, the stability of the rate of change dV / dt can be maintained very well immediately after the start of the second and subsequent operations.

[0104] Furthermore, the learning circuit 14 may not store the updated model parameter K in the storage cell 15; that is, the K value stored in the storage cell 15 may not be updated. In this way, although the stability of controlling the rate of change dV / dt immediately after the start of the second and subsequent operations is reduced, the number of writes to the storage cell 15 can be suppressed to a lower level. Therefore, it is suitable for situations where the number of writes to the storage cell 15 is limited. In such cases, the gate drive device 1 does not need to have a storage cell 15, and using a pre-fixed value as the initial value of K is sufficient.

[0105] (Second Embodiment)

[0106] In the following text, reference will be made to Figures 6 to 12 The second embodiment is described.

[0107] (Main functions of gate drive devices)

[0108] Reference Figure 6 The main functions of the gate driving device 41 in this embodiment are described. For example... Figure 6 As shown, the gate driving device 41 of the second embodiment differs from the gate driving device 1 of the first embodiment in that: a computing circuit 42 is provided instead of a computing circuit 11, a learning circuit 43 is provided instead of a learning circuit 14, a storage unit 44 is provided instead of a storage unit 15, and so on.

[0109] The calculation circuit 42 obtains the mapping data in advance as relational information, and calculates the gate current Ig as an operating quantity using the target value of the rate of change dV / dt and the mapping data. In this case, the mapping data is a one-dimensional mapping representing the relationship between the gate current Ig as an operating quantity and the rate of change dV / dt as a transient voltage, and specifically, for example, is as follows: Figure 8 The data shown. Figure 8 In the mapping data shown, the unit of the rate of change dV / dt is [kV / μs], and the unit of the gate current Ig is [A]. In the following description, unless otherwise stated, the units of the rate of change dV / dt and the gate current Ig are consistent with... Figure 8The units indicated in the text are similar, and by omitting the units, only the values ​​will be described.

[0110] As a learning process, the learning circuit 43 updates the mapping data based on the operation quantity calculated by the calculation circuit 42 and the detected value of the rate of change dV / dt detected by the detection circuit 13, thereby changing the calculation method of the operation quantity. The storage unit 44 can store the mapping data updated by the learning circuit 43. The learning circuit 43 stores the updated mapping data in the storage unit 44 if the difference between the value of the mapping data updated by the learning circuit 43 before the power is turned off from the gate drive device 41 and the value of the mapping data at the start of operation exceeds a preset allowable value.

[0111] The value of the mapping data MAP is either the value of the gate current Ig as an operating quantity or the value of the rate of change of transient voltage dV / dt, and such determination can be made for each of the values ​​of the gate current Ig or the rate of change dV / dt in the mapping data MAP. At the start of the next operation performed after the power is turned off from the gate drive device 1, the calculation circuit 42 calculates the operating quantity using the mapping data stored in the memory cell 44.

[0112] (Specific structure of the gate drive device)

[0113] For example, it can be adopted as follows Figure 7 The example shown is a specific construction of a gate drive device 41 having the functions described above. Figure 7 The gate driving device 41 shown is Figure 4 The gate driving device 1 shown is different in that it provides a computing circuit 42 instead of a computing circuit 11, a learning circuit 43 instead of a learning circuit 14, a storage unit 44 instead of a storage unit 15, and so on.

[0114] The difference between storage unit 44 and storage unit 15 is that storage unit 44 stores in advance the mapping data MAP, which is the one-dimensional mapping described above, instead of the value of the model parameter K. The mapping data MAP can be obtained in advance by, for example, performing various simulations. When the computing circuit 42 requests to read the mapping data MAP, storage unit 44 outputs a signal representing the mapping data MAP.

[0115] The calculation circuit 42 differs from the calculation circuit 11 in that it provides a register 45 for storing the mapped data MAP instead of register 22, and a retrieval process circuit 46 instead of the arithmetic circuit 23, etc. At the start of operation, the calculation circuit 42 requests the target rate of change dV / dt* and the mapped data MAP from the storage unit 44. Through this operation, the signals dV / dt* and MAP output from the storage unit 44 are input to the calculation circuit 42. The calculation circuit 42 stores the target rate of change dV / dt* and the mapped data MAP read from the storage unit 44 into registers 21 and 45.

[0116] The retrieval process circuit 46 reads the target rate of change dV / dt* stored in register 21 and the mapping data MAP stored in register 45. The retrieval process circuit 46 performs the following retrieval process: it retrieves the gate current Ig corresponding to the value of the target rate of change dV / dt* read from register 21 in the mapping data MAP, and outputs a signal Ig representing the value of the retrieved gate current Ig. For example, when the value of the target rate of change dV / dt* read from register 21 is "6", the retrieval process circuit 46 retrieves the gate current Ig = 0.15 corresponding to the rate of change dV / dt = 6 in the mapping data MAP, and outputs a signal Ig representing "0.15" as the value of the retrieved gate current Ig.

[0117] In this case, the mapping data MAP stored in register 45 is updated by the operation of the learning circuit 43, which will be described later. If the difference between the value of the mapping data updated by the learning circuit 43 before the power to the gate drive device 41 is turned off and the value of the mapping data at the start of operation exceeds a preset allowable value, register 45 outputs a signal representing the stored mapping data MAP to memory cell 44. Through this operation, the mapping data MAP stored in memory cell 44 is updated by being rewritten into the mapping data MAP stored in register 45.

[0118] The learning circuit 43 differs from the learning circuit 14 in that it provides an update process circuit 47 instead of the arithmetic circuit 24 and the filtering process circuit 25. The signal dV / dt output from the detection circuit 13 and the signals MAP and Ig output from the calculation circuit 42 are input to the learning circuit 43. The update process circuit 47 performs the following update process: it retrieves the gate current Ig corresponding to the detected value of the rate of change dV / dt detected by the detection circuit 13 on the mapped data MAP, generates an updated mapped data MAP' by changing the value of the gate current Ig retrieved on the mapped data MAP to the value of the gate current Ig calculated by the calculation circuit 42, and outputs a signal representing the updated mapped data MAP'.

[0119] For example, if the detection value of the rate of change dV / dt detected by the detection circuit 13 is "7" and the value of the gate current Ig calculated by the calculation circuit 42 is "0.15", the update process circuit 47 retrieves the gate current Ig = 0.20 corresponding to the rate of change dV / dt = 7 from the mapping data MAP. The update process circuit 47 generates an updated data MAP', which is obtained by changing the value of the gate current Ig corresponding to the rate of change dV / dt = 7 retrieved from the mapping data MAP to "0.15" of the value of the gate current Ig calculated by the calculation circuit 42.

[0120] For example, the updated mapping data MAP' is specifically as follows: Figure 9 The data shown. For example... Figure 9 As shown, in the updated mapping data MAP', the value of the gate current Ig corresponding to the rate of change dV / dt = 7 changes from "0.20" to "0.15". The update process circuit 47 outputs a signal representing the updated mapping data MAP' generated through such an update process to the register 45 of the calculation circuit 42. The mapping data MAP stored in register 45 is updated by being rewritten with the updated mapping data MAP'.

[0121] (Operation flow of the gate driving device)

[0122] Then, refer to Figure 10 The operation flow of the gate driving device 41 having the above-described structure is described. In the gate driving device 41, the following operations are performed during the period from power-on to power-off: Figure 10The process described herein. In S201, which is executed first after the operation begins, the target rate of change dV / dt* and the mapping data MAP are read from storage unit 44 and stored in registers 21 and 45 in calculation circuit 42. That is, in S201, the target rate of change dV / dt* and the mapping data MAP stored in storage unit 44 are downloaded to registers 21 and 45 in calculation circuit 42.

[0123] After executing S201, the loop start process in S202 is executed. The loop start process in S202 is a process that repeats the process from S203 to S207 until a switching end instruction END is given in S208 as the loop end process (i.e., under the condition that the switching end instruction END is given). In S203, when the ON instruction is given, the drive circuit 12 outputs a gate current Ig_on that switches the semiconductor switching element 5 to ON. The current value of the gate current Ig_on at this time is a predetermined current value.

[0124] In S204, the retrieval process circuit 46 of the calculation circuit 42 performs the aforementioned retrieval process. Specifically, in S204, the calculation circuit 42 retrieves the gate current Ig from the mapping data MAP stored in the register 45 using the target rate of change dV / dt* stored in the register 21. S204 can be executed before S203. That is, the execution order of S203 and S204 can be changed.

[0125] In S205, when the OFF command is given, the drive circuit 12 outputs a gate current Ig_off that switches the semiconductor switching element 5 to the off state. The current value of the gate current Ig_off at this time corresponds to the value of the gate current Ig retrieved in S204. In S206, the detection circuit 13 detects the rate of change dV / dt of the voltage Vds generated during the OFF state.

[0126] In S207, the update process circuit 47 of the learning circuit 43 performs the above-described update process, thereby updating the mapping data MAP stored in the register 45 of the calculation circuit 42 so that the updated mapping data MAP' is rewritten. S207 corresponds to the learning process performed by the learning circuit 43. In the gate driving device 41, the processes in S202 to S208 described above are repeated until a switching end instruction END is given.

[0127] Each time semiconductor switching element 5 is switched, the loop process from S202 to S208 is repeated. When the switching end instruction END is given, the loop process from S202 to S208 ends, and the program proceeds to S209. In S209, it is determined whether the difference between the current value of the mapping data MAP stored in register 45 and the value of the mapping data MAP stored in memory cell 44 (i.e., the initial value of the mapping data MAP at the start of operation) exceeds a preset allowable value. In this case, the value of the mapping data MAP is the value of the gate current Ig as the operation quantity, and this determination is performed for each value of the gate current Ig in the mapping data MAP.

[0128] If the difference between the current value and the initial value is equal to or less than the allowed value, "No" is determined in S209, and the operation ends without executing S210. On the other hand, if the difference between the current value and the initial value exceeds the allowed value, "Yes" is determined in S209, and the program proceeds to S210. In S210, the mapping data MAP stored in the storage unit 44 is updated by being rewritten to the mapping data MAP stored in the register 45 of the calculation circuit 42. After executing S210, the operation ends.

[0129] The gate driving device 41 of the above embodiment also achieves similar effects to the first embodiment. Specifically, it achieves excellent results in controlling the rate of change dV / dt of the semiconductor switching element 5 during switching (particularly, during disconnection) to a desired target value with high precision. In this case, the calculation circuit 42 calculates the value of the gate current Ig using mapping data MAP, which is a one-dimensional mapping representing the relationship between the gate current Ig and the rate of change dV / dt.

[0130] In this case, the learning circuit 43 updates the mapping data MAP by updating the calculation method of the gate current Ig based on the value of the gate current Ig calculated by the calculation circuit 42 and the detected value of the rate of change dV / dt detected by the detection circuit 13. Through this operation, the calculation error of the calculation circuit 42 on the gate current Ig is reduced, enabling the rate of change dV / dt to be controlled to the target value with higher accuracy.

[0131] The gate driving device 41 has a storage cell 44 capable of storing the mapping data MAP updated by the learning circuit 43. If the difference between the value of the mapping data MAP updated by the learning circuit 43 before the power-off of the gate driving device 41 and the value of the mapping data MAP at the start of operation exceeds a preset allowable value, the learning circuit 43 stores the updated mapping data MAP in the storage cell 44. At the start of the next operation performed after the power-off of the gate driving device 41, the calculation circuit 42 calculates the gate current Ig using the mapping data MAP stored in the storage cell 44. In this way, while suppressing the number of writes to the storage cell 44, in the second and subsequent operations, the gate current Ig is calculated using the mapping data MAP learned in the last operation from the start time of the operation. Therefore, the rate of change dV / dt can be stably controlled to the target value with high accuracy immediately after the start of operation.

[0132] (Modifications regarding mapping data updates)

[0133] In an embodiment, if the difference between the value of the mapping data MAP updated by the learning circuit 43 before the power is turned off of the gate drive device 41 and the value of the mapping data MAP at the start of operation exceeds a preset allowable value, then the learning circuit 43 writes the updated mapping data MAP into the storage cell 44, that is, updates the mapping data MAP stored in the storage cell 44. This can be modified as follows.

[0134] Specifically, in the following situation, that is, when the difference between the value of the mapping data MAP updated by the learning circuit 43 after the learning process has been executed a specified number of times (once or more) and the value of the mapping data MAP at the start of the operation exceeds a preset allowable value, the learning circuit 43 can store the updated mapping data MAP in the storage unit 44. Specifically, the learning circuit 43 can execute S209 and S210 each time S207 is executed a specified number of times. That is, it can change... Figure 10 The process shown causes S209 and S210 to be executed during the loop process.

[0135] The learning circuit 43 can store the updated mapping data MAP in the storage cell 44 before the power is turned off by the gate drive device 41 or after the learning process has been executed a specified number of times (once or more). Specifically, the learning circuit 43 can execute S210 instead of S209 after the loop process ends. That is, it can be changed Figure 10The process shown here omits S209. In this way, in the second and subsequent operations, the gate current Ig is calculated deterministically using the mapping data MAP learned in the last operation from the start time of the operation, so that the rate of change dV / dt can be stably controlled to the target value with high accuracy immediately after the start of the operation.

[0136] Furthermore, the learning circuit 43 does not need to store the updated mapping data MAP in the memory cell 44; that is, it does not need to update the mapping data MAP stored in the memory cell 44. In this way, although the stability of controlling the rate of change dV / dt immediately after the start of the second and subsequent operations is reduced, the number of writes to the memory cell 44 can be suppressed, making it suitable for situations where the number of writes to the memory cell 44 is limited. In such a case, the gate driving device (gate driving circuit) 41 does not need to have a memory cell 44, and it is sufficient to use the value that has been pre-fixed to an initial value as the mapping data MAP.

[0137] (Revisions regarding the learning process)

[0138] During the learning process, the learning circuit 43 can modify its calculation method based on the current gate current Ig calculated by the calculation circuit 42 and the current rate of change dV / dt detected by the detection circuit 13, as well as the past gate current Ig calculated by the calculation circuit 42 and the past rate of change dV / dt detected by the detection circuit 13. Specifically, during the learning process, the learning circuit 43 can update the mapping data using updated mapping data obtained by smoothing the updated mapping data MAP'. The updated mapping data MAP' is derived by performing a filtering process using the current updated mapping data MAP' output from the update process circuit 47 and the mapping data MAP corresponding to the past updated mapping data MAP' stored in the register 45 of the calculation circuit 42.

[0139] For example, the various processes described in the first embodiment can be used as filtering processes. In this way, even in the case of erroneous learning where the updated value of the mapping data MAP' becomes an incorrect value due to noise, temporary anomalies, etc., the rate of change dV / dt can be suppressed from deviating from the target value due to this influence.

[0140] (Modifications regarding the update process)

[0141] The update process of the learning circuit 43, which generates the updated mapping data MAP' by the update process circuit 47, i.e., the process of updating the mapping data, can be modified as follows.

[0142] (First revised form)

[0143] The update process circuit 47 of the learning circuit 43 is modified to update the mapping data MAP such that the value of the gate current Ig retrieved on the mapping data MAP only changes the difference between the value of the gate current Ig retrieved on the mapping data MAP and the value of the gate current Ig calculated by the calculation circuit 42, and the value of the gate current Ig within a predetermined range centered on the gate current Ig retrieved on the mapping data MAP only changes the above difference.

[0144] For example, if the detected value of the rate of change dV / dt detected by the detection circuit 13 is "7" and the value of the gate current Ig calculated by the calculation circuit 42 is "0.15", then when the predetermined range is ±2 [kV / μs], the updated mapping data MAP' generated by the update process of the first modification form becomes as follows: Figure 11 The data shown. For example... Figure 11 As shown, in this case, the value of the gate current Ig corresponding to the rate of change dV / dt = 7 changes from "0.20" to "0.15".

[0145] In this case, for each data point within the range of ±2 for a rate of change dV / dt = 7, that is, for the gate current Ig corresponding to rates of change dV / dt = 5, dV / dt = 6, dV / dt = 8, and dV / dt = 9, only "-0.05" is changed. "-0.05" is the difference between "0.20" as the retrieved value of gate current Ig and "0.15" as the value of gate current Ig calculated by calculation circuit 42.

[0146] Along with this change, the value of the gate current Ig corresponding to the rate of change dV / dt = 5 changes to "0.07", which is "0.09" of the value of the gate current Ig corresponding to the rate of change dV / dt = 4, and the values ​​of the gate current Ig corresponding to the rates of change dV / dt = 4 and dV / dt = 5 are reversed. Therefore, the value of the changed gate current Ig can be predetermined to prevent such reversal from occurring.

[0147] According to the update process of the first modified form, through a single learning process, not only a single value but also its surrounding values ​​are similarly updated, enabling faster learning of the mapped data, i.e., optimization of the calculation method. Therefore, since the calculation error of the gate current Ig by the calculation circuit 42 is reduced through the update process of the first modified form, the rate of change dV / dt can be controlled to the target value with high precision. The predetermined range is not limited to the range described above, but can, for example, be the entire range of the mapped data MAP.

[0148] (Second revised form)

[0149] The update process circuit 47 of the learning circuit 43 can be modified to update the mapping data MAP by changing only the difference between the value of the gate current Ig retrieved on the mapping data MAP and the value of the gate current Ig calculated by the calculation circuit 42, and by changing only each value of the gate current Ig within a predetermined range centered on the gate current Ig retrieved on the mapping data MAP by multiplying the above difference by a weighting coefficient that decays with distance from the center.

[0150] For example, if the detected value of the rate of change dV / dt detected by the detection circuit 13 is "7" and the value of the gate current Ig calculated by the calculation circuit 42 is "0.15", then when the predetermined range is ±2 [kV / μs], the updated mapping data MAP' generated by the update process of the second modification form becomes as follows: Figure 12 The data shown. For example... Figure 12 As shown, in this case, the value of the gate current Ig corresponding to the rate of change dV / dt = 7 changes from "0.20" to "0.15".

[0151] In this case, for each data point within the range of ±2 for a rate of change dV / dt = 7, that is, for the gate current Ig corresponding to rates of change dV / dt = 5, 6, 8, and 9, only a "-0.05 × weighting coefficient" is changed. "-0.05" is the difference between "0.20" as the retrieved value of gate current Ig and "0.15" as the value of gate current Ig calculated by calculation circuit 42. For rates of change dV / dt = 6 and 8, the weighting coefficient is "0.5", and for rates of change dV / dt = 5 and 9, the weighting coefficient is "0.25".

[0152] Specifically, the value of the gate current Ig corresponding to the rate of change dV / dt = 5 changes from "0.12" to "0.11", the value of the gate current Ig corresponding to the rate of change dV / dt = 6 changes from "0.15" to "0.13", the value of the gate current Ig corresponding to the rate of change dV / dt = 8 changes from "0.25" to "0.23", and the value of the gate current Ig corresponding to the rate of change dV / dt = 9 changes from "0.30" to "0.29".

[0153] Through this second modified form of the update process, not only a single value but also the values ​​surrounding that value are similarly updated through a single learning process, enabling faster learning of the mapped data, i.e., optimization of the calculation method. Therefore, since the second modified form of the update process can reduce the calculation error of the calculation circuit 42 on the gate current Ig, the rate of change dV / dt can be controlled to the target value with higher accuracy.

[0154] According to the second modified update process, only each value of the gate current Ig within a predetermined range centered on the gate current Ig retrieved from the mapped data MAP is changed by multiplying the aforementioned difference by a weighting coefficient that decays with distance from the center, thus suppressing the possibility of the reversal phenomenon described in the first modified update process to a low level. The predetermined range is not limited to the aforementioned range, but may, for example, be the entire range of the mapped data MAP.

[0155] (Third Embodiment)

[0156] In the following text, reference will be made to Figures 13 to 16 The third embodiment is described.

[0157] (Main functions of gate drive devices)

[0158] Reference Figure 13 The main functions of the gate driving device 51 in the embodiment are described. For example... Figure 13 As shown, the gate driving device 51 of the third embodiment differs from the gate driving device 41 of the second embodiment in that: a computing circuit 52 is provided instead of a computing circuit 42, a detection circuit 53 is provided instead of a detection circuit 13, a learning circuit 54 is provided instead of a learning circuit 43, a storage unit 55 is provided instead of a storage unit 44, and so on.

[0159] In addition to detecting the rate of change dV / dt, the detection circuit 53 also detects the element temperature, i.e., the temperature Tj of the semiconductor switching element 5. Similar to the calculation circuit 42, the calculation circuit 52 pre-acquires mapping data as relational information. In this case, the mapping data maintains a multidimensional mapping of the gate current Ig, which is the operating quantity, by combining the rate of change dV / dt (the transient voltage) with the temperature Tj of the semiconductor switching element 5, and specifically, for example, as... Figure 15 The data shown. Figure 15 In the mapping data shown, the unit of temperature Tj is degrees Celsius (°C). In the following description, unless otherwise stated, the unit of temperature Tj is as follows: Figure 15 The units shown will be omitted, and by omitting the units, only the values ​​will be described.

[0160] The calculation circuit 52 calculates the target value of the rate of change dV / dt, the temperature Tj detected by the detection circuit 53, and the gate current Ig as the operating quantity using the mapped data. The learning circuit 54 can perform a learning process similar to that of the learning circuit 43. The storage unit 55 can store the mapped data updated by the learning circuit 54. Before the power is turned off by the gate drive device 51, the learning circuit 54 stores the updated mapped data in the storage unit 55. At the start of the next operation after the power is turned off by the gate drive device 51, the calculation circuit 52 calculates the operating quantity using the mapped data stored in the storage unit 55.

[0161] (Specific structure of the gate drive device)

[0162] For example, it can be adopted as follows Figure 14 The example shown is a specific construction of a gate drive device 51 having the above-described functions. Figure 14 The gate driving device 51 shown is Figure 7 The gate driving device 41 of the second embodiment shown differs in that: a computing circuit 52 is provided instead of a computing circuit 42, a detection circuit 53 is provided instead of a detection circuit 13, a learning circuit 54 is provided instead of a learning circuit 43, a storage unit 55 is provided instead of a storage unit 44, and so on.

[0163] Detection circuit 53, like detection circuit 13, detects the rate of change dV / dt and also detects the temperature Tj, as follows. In this case, temperature sensor 56 is placed near semiconductor switching element 5. Temperature sensor 56 outputs temperature information corresponding to the detected temperature of semiconductor switching element 5 as a voltage signal Vtj. The voltage signal Vtj output from temperature sensor 56 is input to detection circuit 53. Detection circuit 53 has a configuration for obtaining temperature information represented by voltage signal Vtj, thereby detecting the temperature Tj of semiconductor switching element 5. Detection circuit 53 outputs a signal representing the detected value of the rate of change dV / dt and a signal representing the detected value of temperature Tj.

[0164] The difference between storage unit 55 and storage unit 44 is that the stored mapping data MAP is the aforementioned two-dimensional mapping, etc. The difference between calculation circuit 52 and calculation circuit 42 is that a retrieval process circuit 57 is provided instead of retrieval process circuit 46, etc. Except for the operations performed by the retrieval process circuit 57, calculation circuit 52 performs operations almost identical to those of calculation circuit 42. Retrieval process circuit 57 reads the target rate of change dV / dt* stored in register 21 and the mapping data MAP stored in register 45. The signal Tj output from detection circuit 53 is input to retrieval process circuit 57.

[0165] The retrieval process circuit 57 performs the following retrieval process: it retrieves the gate current Ig corresponding to the target rate of change dV / dt* read from register 21 and the detected value of the temperature Tj of the semiconductor switching element 5 represented by signal Tj in the mapping data MAP, and outputs a signal Ig representing the value of the retrieved gate current Ig. For example, if the value of the target rate of change dV / dt* read from register 21 is "3" and the detected value of temperature Tj is "50", the retrieval process circuit 57 retrieves the gate current Ig = 0.09 corresponding to the rate of change dV / dt = 3 and the temperature Tj = 50 in the mapping data MAP, and outputs a signal Ig representing "0.09" as the value of the retrieved gate current Ig.

[0166] In this case, the mapping data MAP stored in register 45 is updated by the operation of the learning circuit 54, which will be described later. Register 45 outputs a signal indicating the mapping data MAP stored in memory cell 55 before the power to the gate drive device 51 was turned off. Through this operation, the mapping data MAP stored in memory cell 55 is updated by being rewritten into the mapping data MAP stored in register 45.

[0167] The learning circuit 54 differs from the learning circuit 43 in that it provides an update process circuit 58 instead of an update process circuit 47, and so on. The signals dV / dt and Tj output from the detection circuit 53, and the signals MAP and Ig output from the calculation circuit 52, are input to the learning circuit 54. The update process circuit 58 performs the following update process: it retrieves the gate current Ig corresponding to the detected value of the rate of change dV / dt detected by the detection circuit 53 and the detected value of the temperature Tj detected by the detection circuit 53 from the mapped data MAP; it generates an updated mapped data MAP' by changing the value of the gate current Ig retrieved from the mapped data MAP to the value of the gate current Ig calculated by the calculation circuit 52; and it outputs a signal representing the updated mapped data MAP'.

[0168] For example, if the detection circuit 53 detects a change rate dV / dt of "4" and a temperature Tj of "50", and the calculation circuit 52 calculates a gate current Ig of "0.09", the update process circuit 58 retrieves the gate current Ig = 0.10 corresponding to the change rate dV / dt = 4 and the temperature Tj = 50 from the mapping data MAP. The update process circuit 58 generates updated mapping data MAP', which is obtained by changing the value of the gate current Ig corresponding to the change rate dV / dt = 4 and the temperature Tj = 50 retrieved from the mapping data MAP to "0.09", which is the value of the gate current Ig calculated by the calculation circuit 52. The update process circuit 58 outputs a signal representing the updated mapping data MAP' generated through such an update process to the register 45 of the calculation circuit 52. Through this operation, the mapping data MAP stored in the register 45 is updated by being rewritten with the updated mapping data MAP'.

[0169] (Operation flow of the gate driving device)

[0170] Then, refer to Figure 16 The operation flow of the gate driving device 51 having the above-described structure is described. In the gate driving device 51, during the period from power-on to power-off, the following is performed: Figure 16 The process is illustrated. In S301, which is executed first after the operation begins, the target rate of change dV / dt* and the mapping data MAP are read from the storage unit 55 and stored in registers 21 and 45 in the calculation circuit 52. That is, in S301, the target rate of change dV / dt* and the mapping data MAP stored in the storage unit 55 are downloaded to registers 21 and 45 in the calculation circuit 52.

[0171] After executing S301, the loop start process in S302 is executed. The loop start process in S302 is a process that repeats the process from S303 to S308 until the switching end instruction END is given (that is, the giving of the switching end instruction END in S309 is the end condition of the loop end process). In S303, when the turn-on instruction ON is given, the drive circuit 12 outputs a gate current Ig_on that switches the semiconductor switching element 5 to the on state. The current value of the gate current Ig_on at this time is a predetermined current value.

[0172] In S304, the detection circuit 53 detects the temperature Tj of the semiconductor switching element 5, i.e., the element temperature. In S305, the retrieval process circuit 57 in the calculation circuit 52 executes the aforementioned retrieval process. Specifically, in S305, the calculation circuit 52 retrieves the gate current Ig from the mapping data MAP stored in the register 45 using the target rate of change dV / dt* stored in the register 21 and the temperature Tj detected in S304. S304 and S305 can also be executed before S303. That is, the execution order of S303, S304, and S305 can be changed.

[0173] In S306, when the OFF command is given, the drive circuit 12 outputs a gate current Ig_off that switches the semiconductor switching element 5 to the off state. The current value of the gate current Ig_off at this time corresponds to the value of the gate current Ig retrieved in S305. In S307, the detection circuit 13 detects the rate of change dV / dt of the voltage Vds generated during the OFF state. In S307, in addition to detecting the rate of change dV / dt, the detection circuit 53 can also detect the temperature Tj.

[0174] In S308, the update process circuit 58 of the learning circuit 54 performs the above-described update process, thereby updating the mapping data MAP stored in the register 45 of the calculation circuit 52 by rewriting the updated mapping data MAP'. S308 corresponds to the learning process performed by the learning circuit 54. In the gate driving device 51, the processes in S302 to S309 described above are repeated until a switching end instruction END is given.

[0175] Each time semiconductor switching element 5 is switched, the loop process from S302 to S309 is repeated. When the switching end instruction END is given, the loop process from S302 to S309 ends, and the program proceeds to S310. In S310, the mapping data MAP stored in memory unit 55 is updated by being rewritten to the mapping data MAP stored in register 45 in computing circuit 52. After executing S310, the operation ends.

[0176] The gate driving device 51 of the above embodiment can also achieve similar effects to the first embodiment, that is, it can achieve an excellent effect in which the rate of change dV / dt during the switching of the semiconductor switching element 5 (particularly, when it is turned off) can be controlled with high precision to the desired target value. The gate driving device 51 of the embodiment also achieves the following effect: the rate of change dV / dt that actually occurs when the semiconductor switching element 5, which is the driving target of the gate driving device 51, is turned off may vary depending on the temperature Tj of the semiconductor switching element 5, etc.

[0177] In this case, the calculation circuit 52 calculates the value of the gate current Ig using the mapping data MAP, which serves as a two-dimensional mapping to maintain the gate current Ig by combining the rate of change dV / dt and the temperature Tj. The learning circuit 54 then updates the mapping data MAP based on the value of the gate current Ig calculated by the calculation circuit 52 and the detected values ​​of the rate of change dV / dt and the temperature Tj detected by the detection circuit 53. In this way, due to the temperature Tj of the semiconductor switching element 5, the calculation error of the calculation circuit 52 on the gate current Ig is reduced, enabling the rate of change dV / dt to be controlled to the target value with higher accuracy.

[0178] The gate drive device 51 has a storage cell 55 capable of storing the mapping data MAP updated by the learning circuit 54. The learning circuit 54 stores the updated mapping data MAP in the storage cell 55 before the power is turned off of the gate drive device 51. At the start of the next operation performed after the power is turned off of the gate drive device 51, the calculation circuit 52 calculates the gate current Ig using the mapping data MAP stored in the storage cell 55. In this way, in the second and subsequent operations, the gate current Ig is calculated using the mapping data MAP learned in the last operation from the start time of the operation. Therefore, the rate of change dV / dt can be stably controlled to the target value with high accuracy immediately after the start of the operation.

[0179] (Regarding modifications to the mapping data)

[0180] The rate of change dV / dt that actually occurs when the semiconductor switching element 5, which is the driving target of the gate driving device 51, is turned off may vary not only depending on the temperature Tj of the semiconductor switching element 5, but also depending on the temperature of the gate driving device 51, the source voltage Va which is the voltage applied between the main terminals (i.e., the drain and source of the semiconductor switching element 5), the element current which is the current flowing between the main terminals (i.e., the drain and source of the semiconductor switching element 5), etc.

[0181] Therefore, the mapping data MAP can be a multidimensional mapping that maintains the gate current Ig as an operating quantity by combining at least one of the physical quantities of the transient voltage change rate dV / dt with the temperature Tj of the semiconductor switching element 5, the temperature of the gate driving device 51, the source voltage Va, and the element current. In this case, the detection circuit 53 must be configured to detect at least one of the physical quantities of the semiconductor switching element 5 temperature Tj, the temperature of the gate driving device 51, the source voltage Va, and the element current.

[0182] In this case, the calculation circuit 52 calculates the gate current Ig using the target value of the rate of change dV / dt*, the detection value of the physical quantity by the detection circuit 53, and the mapping data MAP. In this way, the calculation error of the gate current Ig caused by physical quantities such as the temperature Tj of the semiconductor switching element 5, the temperature of the gate drive device 51, the source voltage Va, and the element current (i.e., various disturbance factors) can be reduced. Therefore, the rate of change dV / dt can be controlled to the target value with high accuracy.

[0183] (Modifications regarding mapping data updates)

[0184] In this embodiment, the learning circuit 54 writes and stores the updated mapping data MAP into the storage cell 55; that is, the mapping data MAP stored in the storage cell 55 is updated before the power to the gate drive device 51 is turned off. This can be modified as follows.

[0185] The learning circuit 54 can store the updated mapping data MAP into the storage unit 55 after executing the learning process a specified number of times (once or more). Specifically, the learning circuit 54 can execute S310 each time S308 is executed a specified number of times. That is, it can change... Figure 16 The process in the loop causes S310 to be executed during the loop process.

[0186] In the following situation, that is, if the difference between the value of the mapping data MAP updated by the learning circuit 54 before the power is turned off of the gate driving device (gate driving circuit) 51 or after the learning process has been executed a specified number of times (once or more) and the value of the mapping data MAP at the start of operation exceeds a preset allowable value, then the learning circuit 54 may store the updated mapping data MAP in the storage unit 55. Specifically, the learning circuit 54 may execute the update after the loop process ends. Figure 10 The process in the second embodiment shown is similar to process S209, and after that, S310 is executed. That is to say, it can be modified. Figure 16 The process shown is such that a process similar to S209 is added between S309 and S310. In this way, while suppressing the number of writes to memory cell 55, it is possible to maintain excellent stability in controlling the rate of change dV / dt immediately after the start of the second and subsequent operations.

[0187] Furthermore, the learning circuit 54 may not store the updated mapping data MAP in the memory cell 55; that is, the mapping data MAP stored in the memory cell 55 may not be updated. In this way, although the stability of controlling the rate of change dV / dt immediately after the start of the second and subsequent operations is reduced, the number of writes to the memory cell 55 can be kept low. Therefore, it is suitable for situations where there is a limit to the number of writes to the memory cell 55. In such cases, the gate drive device 51 does not need to have a memory cell 55, and it is sufficient to use a pre-fixed value as the initial value of the mapping data MAP.

[0188] (Revisions regarding the learning process)

[0189] During the learning process, the learning circuit 54 can modify the calculation method based on the current gate current Ig calculated by the calculation circuit 52 and the current rate of change dV / dt and temperature Tj detected by the detection circuit 53. Furthermore, it can modify the calculation method based on past gate current Ig calculated by the calculation circuit 52 and past rate of change dV / dt and temperature Tj detected by the detection circuit 53. Specifically, during the learning process, the learning circuit 54 can update the mapping data using updated mapping data obtained by smoothing the updated mapping data MAP'. This updated mapping data MAP' is derived by performing a filtering process using the mapping data MAP corresponding to the current updated mapping data MAP' output from the update process circuit 58 and the mapping data MAP corresponding to the past updated mapping data MAP' stored in register 45 of the calculation circuit 52.

[0190] For example, the various processes described in the first embodiment can be used as filtering processes. In this way, even in the case of erroneous learning where the updated value of the mapping data MAP' becomes an incorrect value due to noise, temporary anomalies, etc., the rate of change dV / dt can be suppressed from deviating from the target value due to this influence.

[0191] (Modifications regarding the update process)

[0192] The update process of generating updated mapping data MAP' by update process circuit 58 in learning circuit 54, that is, the process of updating the mapping data, can be modified in a manner similar to the first and second modification forms related to the update process described in the second embodiment.

[0193] (Fourth Embodiment)

[0194] In the following text, reference will be made to Figures 17 to 19 The fourth embodiment is described.

[0195] (Main functions of gate drive devices)

[0196] Reference Figure 17 The main functions of the gate driving device 61 in this embodiment are described. For example... Figure 17 As shown, the gate driving device 61 of the fourth embodiment differs from the gate driving device 1 of the first embodiment in that: a computing circuit 62 is provided instead of a computing circuit 11, a detection circuit 63 is provided instead of a detection circuit 13, a learning circuit 64 is provided instead of a learning circuit 14, a storage unit 65 is provided instead of a storage unit 15, and so on.

[0197] The transient voltage of the control target of the gate drive device 61 in this embodiment is the surge voltage Vsrg of the semiconductor switching element 5 of its own arm. Except that the control target changes from the rate of change dV / dt to the surge voltage Vsrg, the components of the gate drive device 61 operate in a manner almost identical to that of the gate drive device 1. The detection circuit 63 detects the source voltage Va and the current Id, in addition to detecting the surge voltage Vsrg of the semiconductor switching element 5 of its own arm. Alternatively, the detection circuit 63 can detect the off-state voltage Vds_off, which is approximately equal to the source voltage Va, instead of the source voltage Va. In such a case, it is sufficient to replace the source voltage Va in the following description with the off-state voltage Vds_off.

[0198] When the model parameter is set to K, the target value of the surge voltage Vsrg is set to Vsrg*, the source voltage, which is the voltage applied between the main terminals of the semiconductor switching element 5, is set to Va, and the gate current, which is the operating quantity, is set to Ig. The calculation circuit 62 uses the following formula (4) as the model formula to calculate the gate current Ig.

[0199] Ig=(Vsrg*-Va)÷K (4)

[0200] When the learning value is set to Ka, the gate current calculated by the calculation circuit 62 is set to Iga, and the surge voltage Vsrg detected by the detection circuit 63 is set to Vsrg, the learning circuit 64 uses the following formula (5) as the inverse model formula to calculate the learning value Ka.

[0201] Ka=(Vsrg-Va)÷Iga (5)

[0202] (Specific structure of the gate drive device)

[0203] For example, it can be adopted Figure 18 The example shown is a specific construction of a gate drive device 61 having the functions described above. Figure 18 The gate driving device 61 shown is Figure 4The gate driving device 1 shown differs in that it provides a computing circuit 62 instead of a computing circuit 11, a detection circuit 63 instead of a detection circuit 13, a learning circuit 64 instead of a computing circuit 14, a storage unit 65 instead of a storage unit 15, and so on.

[0204] In storage unit 65, the target value Vsrg* of the surge voltage Vsrg and multiple K values ​​determined for the corresponding current Id are stored in advance. In this specification, the target value Vsrg* of the surge voltage Vsrg will also be referred to as the target surge voltage Vsrg*. The target surge voltage Vsrg* is transmitted as an instruction from a higher-order control device, and therefore it can be obtained in advance. For example, it can be obtained in advance by performing various simulations. When the calculation circuit 62 requests to read the target surge voltage Vsrg*, storage unit 65 outputs a signal representing the target surge voltage Vsrg*. When the calculation circuit 62 requests to read the K values, storage unit 65 outputs a signal representing the K value for each current Id.

[0205] By monitoring the waveform of voltage Vds, detection circuit 63 detects the surge voltage Vsrg and the disconnect voltage Vds_off. As mentioned above, since the disconnect voltage Vds_off is almost equal to the source voltage Va, it is detected here instead of the source voltage Va. Detection circuit 63 detects the current Id as follows. In this case, shunt resistor 66 is connected between the source of semiconductor switching element 5B and DC power supply line 3.

[0206] The terminal voltage of the shunt resistor 66 is input to the detection circuit 63; specifically, the voltage of the terminal of the shunt resistor 66 located on the semiconductor switching element 5 side is input. The detection circuit 63 is configured to detect the current Id based on the voltage value of the terminal voltage of the shunt resistor 66. The detection circuit 63 outputs a signal representing the detected value of the rate of change dV / dt, a signal representing the detected value of the disconnect voltage Vds_off, and a signal representing the detected value of the current Id.

[0207] At the start of operation, the calculation circuit 62 requests the storage unit 65 to read the target surge voltage Vsrg* and the K value. Through this operation, the signals Vsrg* and K output from the storage unit 65 are input to the calculation circuit 62. The calculation circuit 62 has a register 67 storing the target surge voltage Vsrg* represented by the signal Vsrg*, a register 68 storing the K value for each current Id represented by the signal K, a selector 69, and arithmetic circuits 70 and 71. The calculation circuit 62 stores the target surge voltage Vsrg* and the K value for each current Id read from the storage unit 65 into registers 67 and 68.

[0208] The signal Id output from the detection circuit 63 is input to the selector 69. The selector 69 reads multiple K values ​​stored in the register 68 and selects the K value corresponding to the detected value of the current Id represented by the signal Id. The selector 69 outputs a signal representing the selected K value as described above to the arithmetic circuit 71. The signal Vds_off output from the detection circuit 63 is input to the arithmetic circuit 70. The arithmetic circuit 70 reads the target surge voltage Vsrg* stored in the register 67 and subtracts the detected value of the disconnect voltage Vds_off represented by the signal Vds_off from the read target surge voltage Vsrg*.

[0209] The value obtained as a result of the operation by the arithmetic circuit 70 corresponds to the target value ΔVds* of the voltage ΔVds mentioned above. In this specification, the target value ΔVds* of the voltage ΔVds will also be referred to as the target voltage ΔVds*. The arithmetic circuit 70 outputs a signal representing the voltage ΔVds* to the arithmetic circuit 71. The arithmetic circuit 71 divides the value of the target voltage ΔVds* represented by the signal ΔVds* by the value of K represented by the signal K.

[0210] The value obtained as a result of the operation of the arithmetic circuit 71 corresponds to the aforementioned gate current Ig. The arithmetic circuit 71 outputs a signal representing the gate current Ig. In this case, the K value stored in the register 68 is updated by the operation of the learning circuit 64, which will be described later. Before the power supply to the gate drive device 61 is turned off, the register 68 outputs a signal representing the stored K value to the storage cell 65. Through this operation, the K value stored in the storage cell 65 is updated by rewriting the K value stored in the storage cell 65.

[0211] The signals Vsrg and Vds_off output from the detection circuit 63 and the signal Ig output from the calculation circuit 62 are input to the learning circuit 64. The learning circuit 64 has arithmetic circuits 72 and 73. The arithmetic circuit 72 subtracts the detected value of the disconnection voltage Vds_off, represented by the signal Vsrg, from the detected value of the surge voltage Vsrg, represented by the signal Vsrg. The value obtained as the result of the calculation by the arithmetic circuit 72 corresponds to the detected value of the voltage ΔVds. The arithmetic circuit 72 outputs a signal representing the detected value of the voltage ΔVds to the arithmetic circuit 73.

[0212] The arithmetic circuit 73 divides the detected value of the voltage ΔVds, represented by the signal ΔVds, by the value of the gate current Ig, represented by the signal Ig. The value obtained as a result of the arithmetic circuit 73 corresponds to the aforementioned learning value Ka. The arithmetic circuit 73 outputs a signal representing the learning value Ka to the register 68 of the calculation circuit 62. Through this operation, the K value among the multiple K values ​​stored in the register 68 corresponding to the detected value of the current Id, represented by the signal Id, is updated by being rewritten with the learning value Ka.

[0213] (Operation flow of the gate driving device)

[0214] Then, refer to Figure 19 The operation flow of the gate driving device 61 having the above-described structure is described. In the gate driving device 61, during the period from power-on to power-off, the following operations are performed: Figure 19 The process is illustrated. In S401, which is executed first after the operation begins, the target surge voltage Vsrg* and the K value for each current Id are read from storage unit 65 and stored in registers 67 and 68 in calculation circuit 62. That is, in S401, the target surge voltage Vsrg* and the K value for each current Id stored in storage unit 65 are downloaded to registers 67 and 68 in calculation circuit 62.

[0215] After executing S401, the loop start process in S402 is executed. The loop start process in S402 is a process that repeatedly executes the process from S403 to S410 until the switching end instruction END is given (i.e., the giving of the switching end instruction END in S411 is the end condition of the loop end process). In S403, the semiconductor switching element 5 is in the off state, and in this state, the detection circuit 63 detects the off voltage Vds_off.

[0216] In S404, when the ON command is given, the drive circuit 12 outputs a gate current Ig_on, and the semiconductor switching element 5 is switched on by the gate current Ig_on. The current value of the gate current Ig_on at this time is a predetermined current value. In S405, the semiconductor switching element 5 is in the ON state, and in this state, the detection circuit 63 detects the current Id. In S405, the selector 69 of the calculation circuit 62 selects a K value corresponding to the detected value of the current Id.

[0217] In S406, each operation is performed by the arithmetic circuits 70 and 71 of the calculation circuit 62, which calculates the gate current Ig based on formula (4), which is the model formula described above. In S407, when the off command OFF is given, the drive circuit 12 outputs the gate current Ig_off, and the semiconductor switching element 5 is switched off by the gate current Ig_off. The current value of the gate current Ig_off at this time is the value corresponding to the gate current Ig calculated in S406.

[0218] In S408, the detection circuit 63 detects the surge voltage Vsrg generated when the circuit is disconnected. In addition to detecting the surge voltage Vsrg, the detection circuit 63 can also detect the disconnection voltage Vds_off in S408. In S409, the learning circuit 64 calculates the learning value Ka based on formula (5), which is the inverse model formula described above, by performing each calculation via its arithmetic circuits 72 and 73. In S410, the K value corresponding to the detected value of the current Id among the multiple K values ​​stored in register 68 is updated by being rewritten with the learning value Ka.

[0219] S409 and S410 correspond to the learning process executed by the learning circuit 64. Although S410 is executed after S409, alternatively or additionally, S410 may be executed after S405. However, S410 cannot be executed after S405 during the first execution of the loop process.

[0220] In the gate driving device 61, the processes S402 to S411 described above are repeatedly executed until a switching end instruction END is given. That is, the loop process of S402 to S411 is repeated each time the semiconductor switching element 5 is switched. When the switching end instruction END is given, the loop process of S402 to S411 ends, and the program proceeds to S412. In S412, the K value stored in the memory cell 65 is updated by being rewritten to the K value stored in the register 68 of the calculation circuit 62. After executing S412, the operation ends.

[0221] According to the above embodiment, the gate driving device 61 is optimized by the learning circuit 64 performing a learning process, and the calculation method for calculating the gate current Ig by the calculation circuit 62 as the operating amount for operating the gate driving speed when the semiconductor switching element 5 is turned off is optimized so as to conform to the surge voltage Vsrg actually generated in the semiconductor switching element 5 that is the driving target of the gate driving device 61 when it is turned off.

[0222] As described above, according to the embodiment, the calculation method is optimized based on the differences between products. Therefore, even if there are individual differences between the gate drive device 1 and the semiconductor switching element 5, the gate drive speed of the semiconductor switching element 5 can be controlled to the desired speed, and furthermore, the surge voltage Vsrg when disconnected can be controlled to the desired target value.

[0223] In the gate driving device 61, a learning process via the learning circuit 64 can be performed simultaneously with the actual operation of the gate driving device 61, i.e., during actual operation. As described above, according to the embodiment, it is also possible to perform the learning process during actual operation, i.e., to optimize the calculation method. Therefore, in the event of property fluctuations due to aging or load fluctuations such as temperature and source voltage Va, the surge voltage Vsrg can be controlled to a desired target value. Therefore, according to the embodiment, an excellent effect can be obtained in which the surge voltage Vsrg during the switching of the semiconductor switching element 5 (particularly, when it is turned off) can be controlled to a desired target value with high precision.

[0224] As described above, according to the embodiment, the surge voltage Vsrg during the switching of the semiconductor switching element 5 is set as the control target, and the surge voltage Vsrg can be controlled to the desired target value with high precision. Therefore, for example, it is possible to prevent both malfunctions caused when the surge voltage Vsrg applied to the main terminal of the semiconductor switching element 5 exceeds the element's withstand voltage and to reduce switching losses.

[0225] In this case, the calculation circuit 62 calculates the gate current Ig using the model formula with model parameter K as described in formula (4) above. In this case, the learning circuit 64 calculates the learning value Ka corresponding to model parameter K using the inverse model formula as described in formula (5) above, and updates the model parameter K based on the calculated learning value Ka, thereby changing the calculation method of the gate current Ig. In this way, the calculation method of the gate current Ig can be optimized without complex processes in the calculation circuit 62 and the learning circuit 64, allowing the calculation circuit 62 and the learning circuit 64 to have relatively simple structures.

[0226] The gate drive device 61 has a storage cell 65 capable of storing model parameters K updated by the learning circuit 64. Before the power to the gate drive device 61 is turned off, the learning circuit 64 stores the updated model parameters K in the storage cell 65. At the start of the next operation performed after the power to the gate drive device 61 is turned off, the calculation circuit 62 calculates the gate current Ig using the model parameters K stored in the storage cell 65. In this way, in the second and subsequent operations, the gate current Ig is calculated using the model parameters K learned in the last operation from the start time of the operation. Therefore, the surge voltage Vsrg can be stably controlled to the target value with high accuracy immediately after the start of the operation.

[0227] (Modifications regarding K-value updates)

[0228] In this embodiment, the learning circuit 64 writes and stores the updated model parameter K, that is, the K value stored in the memory cell 65 is updated before the power to the gate drive device 61 is turned off. This can be modified as follows.

[0229] The learning circuit 64 can store the updated model parameters K in the storage unit 65 after executing the learning process a specified number of times (once or more). Specifically, the learning circuit 64 can execute S412 each time S409 and S410 are executed a specified number of times. That is, it can change... Figure 19 The process in the loop causes S412 to be executed during the loop process.

[0230] In the following situations, namely, before the power supply to the gate drive device 61 is turned off or after the learning process has been executed a specified number of times (once or more), and when the difference between the value of the model parameter K updated by the learning circuit 64 and the value of the model parameter K at the start of operation exceeds a preset allowable value, the learning circuit 64 may store the updated model parameter K in the memory cell 65. In this way, while suppressing the number of times the data is written to the memory cell 65, the stability of the surge voltage Vsrg can be well maintained immediately after the start of the second and subsequent operations.

[0231] Furthermore, the learning circuit 64 may not store the updated model parameter K in the memory cell 65; that is, the K value stored in the memory cell 65 may not be updated. In this way, although the stability of controlling the surge voltage Vsrg immediately after the start of the second and subsequent operations is reduced, the number of writes to the memory cell 65 can be suppressed to a lower level. Therefore, it is suitable for situations where there is a limit to the number of writes to the memory cell 65. In such cases, the gate drive device 61 does not need to have a memory cell 65, and it is sufficient to use the value that has been pre-fixed to the initial value as the K value.

[0232] (Regarding the modification of the K value)

[0233] In this embodiment, the characteristic that the surge voltage Vsrg depends on the current Id is considered, and the calculation and learning process of the gate current Ig is performed using a K value for each current Id. Alternatively, the calculation and learning process of the gate current Ig can be performed using a single K value. In this way, since the dependence of the surge voltage Vsrg on the current Id is ignored, although the stability of the control of the surge voltage Vsrg is slightly reduced, the process load and structural simplification of each circuit constituting the gate drive device 61 can be achieved.

[0234] (Revisions regarding the learning process)

[0235] During the learning process, the learning circuit 64 can change the calculation method based on the current gate current Ig calculated by the calculation circuit 62 and the current surge voltage Vsrg detected by the detection circuit 63. Furthermore, it can also change the calculation method based on the past gate current Ig calculated by the calculation circuit 62 and the past surge voltage Vsrg detected by the detection circuit 63.

[0236] Specifically, during the learning process, the learning circuit 64 can update the model parameter K based on a learning value obtained by smoothing the learning value Ka. The learning value Ka is derived by performing a filtering process using the current learning value Ka output from the arithmetic circuit 73 and the K value read from the register 68 of the arithmetic circuit 62 (i.e., the past learning value Ka). For example, various processes described in the first embodiment can be used as the filtering process. In this way, even in the case of erroneous learning where the learning value Ka becomes an incorrect value due to noise, temporary anomalies, etc., the surge voltage Vsrg can be suppressed from deviating from the target value due to such influence.

[0237] (Fifth Embodiment)

[0238] In the following text, reference will be made to Figures 20 to 24 The fifth embodiment is described.

[0239] (Main functions of gate drive devices)

[0240] Reference Figure 20 The main functions of the gate driving device 81 in this embodiment are described. For example... Figure 20As shown, the gate driving device 81 of the fifth embodiment differs from the gate driving device 61 of the fourth embodiment in that: a computing circuit 82 is provided instead of a computing circuit 62, a detection circuit 83 is provided instead of a detection circuit 63, a learning circuit 84 is provided instead of a learning circuit 64, a storage unit 85 is provided instead of a storage unit 65, and so on.

[0241] The calculation circuit 82 obtains the mapping data in advance as relational information, and calculates the gate current Ig as an operating quantity using the target value of the surge voltage Vsrg and the mapping data. In this case, the mapping data is a one-dimensional mapping representing the relationship between the gate current Ig as an operating quantity and the surge voltage Vsrg as a transient voltage, and specifically, it is as follows: Figure 22 The data shown. Figure 22 In the mapping data shown, the unit of surge voltage Vsrg is [V]. In the following description, unless otherwise stated, the unit of surge voltage Vsrg is the same as... Figure 22 The units indicated in the text are similar, and by omitting the units, only the numerical values ​​will be described.

[0242] Detection circuit 83 detects surge voltage Vsrg. As a learning process, learning circuit 84 updates the mapping data based on the operation quantity calculated by calculation circuit 82 and the detected value of surge voltage Vsrg detected by detection circuit 83, thereby changing the calculation method of the operation quantity. Storage unit 85 can store the mapping data updated by learning circuit 84. Before the power is turned off by gate drive device 81, learning circuit 84 stores the updated mapping data in storage unit 85. At the start of the next operation after the power is turned off by gate drive device 81, calculation circuit 82 calculates the operation quantity using the mapping data stored in storage unit 85.

[0243] (Specific structure of the gate drive device)

[0244] For example, it can be adopted as follows Figure 21 The example shown is a specific construction of a gate drive device 81 having the functions described above. Figure 21 The gate driving device 81 shown is Figure 18 The gate driving device 61 shown differs in that it provides a computing circuit 82 instead of a computing circuit 62, a detection circuit 83 instead of a detection circuit 63, a learning circuit 84 instead of a learning circuit 64, a storage unit 85 instead of a storage unit 65, and so on.

[0245] The difference between storage unit 85 and storage unit 65 is that storage unit 85 pre-stores the mapping data MAP, which is the one-dimensional mapping described above, instead of the value of the model parameter K. The mapping data MAP can be obtained in advance by, for example, performing various simulations. When the computing circuit 82 requests to read the mapping data MAP, storage unit 85 outputs a signal representing the mapping data MAP. Detection circuit 83 detects the surge voltage Vsrg in a similar manner to detection circuit 63.

[0246] The difference between calculation circuit 82 and calculation circuit 62 lies in that: register 86, which stores the mapped data MAP, replaces register 68; a retrieval process circuit 87 replaces selector 69; and arithmetic circuits 70 and 71, etc., are provided. At the start of operation, calculation circuit 82 requests the target surge voltage Vsrg* and the mapped data MAP from storage unit 85. In response, the signals Vsrg* and MAP output from storage unit 85 are input to calculation circuit 82. Calculation circuit 82 stores the target surge voltage Vsrg* and the mapped data MAP read from storage unit 85 into registers 67 and 86.

[0247] The retrieval process circuit 87 reads the target surge voltage Vsrg* stored in register 67 and the mapping data MAP stored in register 86. The retrieval process circuit 87 performs the following retrieval process: it retrieves the gate current Ig corresponding to the value of the target surge voltage Vsrg* read from register 67 in the mapping data MAP, and outputs a signal Ig representing the value of the retrieved gate current Ig. For example, when the value of the target surge voltage Vsrg* read from register 67 is "360", the retrieval process circuit 87 retrieves the gate current Ig = 0.15 corresponding to the surge voltage Vsrg = 360 in the mapping data MAP, and outputs an output signal Ig representing "0.15" as the value of the retrieved gate current Ig.

[0248] In this case, the mapping data MAP stored in register 86 is updated by the operation of the learning circuit 84, which will be described later. Before the power supply to the gate drive device 81 is turned off, register 86 outputs a signal representing the stored mapping data MAP to memory cell 85. Through this operation, the mapping data MAP stored in memory cell 85 is updated by being rewritten to the mapping data MAP stored in register 86.

[0249] The learning circuit 84 differs from the learning circuit 64 in that it provides an update process circuit 88 instead of the arithmetic circuits 72 and 73. The signal Vsrg output from the detection circuit 83 and the signals MAP and Ig output from the arithmetic circuit 82 are input to the learning circuit 84. The update process circuit 88 performs the following update process: it retrieves the gate current Ig corresponding to the detected value of the surge voltage Vsrg detected by the detection circuit 83 from the mapped data MAP; it generates an updated mapped data MAP' by changing the value of the gate current Ig retrieved from the mapped data MAP to the value of the gate current Ig calculated by the arithmetic circuit 82; and it outputs a signal representing the updated mapped data MAP'.

[0250] For example, if the surge voltage Vsrg detected by the detection circuit 83 is "370" and the gate current Ig calculated by the calculation circuit 82 is "0.15", the update process circuit 88 retrieves the gate current Ig = 0.20 corresponding to the surge voltage Vsrg = 370 from the mapping data MAP. The update process circuit 88 generates an updated data MAP', wherein the value of the gate current Ig corresponding to the surge voltage Vsrg = 370 retrieved from the mapping data MAP is changed to "0.15" as the value of the gate current Ig calculated by the calculation circuit 82.

[0251] For example, the updated mapping data MAP' is specifically as follows: Figure 23 The data shown. For example... Figure 23 As shown, in the updated mapping data MAP', the value of the gate current Ig corresponding to the surge voltage Vsrg = 370 is changed from "0.20" to "0.15". The update process circuit 88 outputs a signal representing the updated mapping data MAP' generated through such an update process to the register 86 of the calculation circuit 82. Through this operation, the mapping data MAP stored in the register 86 is updated by being rewritten with the updated mapping data MAP'.

[0252] (Operation flow of the gate driving device)

[0253] Then, refer to Figure 24 The operation flow of the gate driving device 81 having the above-described structure is described. In the gate driving device 81, the following operations are performed during the period from power-on to power-off: Figure 24The process is illustrated. In S501, which is executed first after the operation begins, the target surge voltage Vsrg* and the mapping data MAP are read from the storage unit 85 and stored in registers 67 and 86 in the calculation circuit 82. Specifically, in S501, the target surge voltage Vsrg* and the mapping data MAP stored in the storage unit 85 are downloaded to registers 67 and 86 in the calculation circuit 82.

[0254] After executing S501, the loop start process in S502 is executed. The loop start process in S502 is a process that repeats the process from S503 to S507 until the switching end instruction END is given (that is, the giving of the switching end instruction END in S508 is the end condition of the loop end process). In S503, when the turn-on instruction ON is given, the drive circuit 12 outputs a gate current Ig_on that switches the semiconductor switching element 5 to the on state. The current value of the gate current Ig_on at this time is a predetermined current value.

[0255] In S504, the retrieval process circuit 87 of the calculation circuit 82 performs the aforementioned retrieval process. Specifically, in S504, the calculation circuit 82 retrieves the gate current Ig from the mapping data MAP stored in register 86 using the target surge voltage Vsrg* stored in register 67. Alternatively, S504 can be executed before S503. That is, the execution order of S503 and S504 can be changed.

[0256] In S505, when the OFF command is given, the drive circuit 12 outputs a gate current Ig_off that switches the semiconductor switching element 5 to the off state. The current value of the gate current Ig_off at this time corresponds to the value of the gate current Ig retrieved in S504. In S506, the detection circuit 83 detects the surge voltage Vsrg generated during the OFF operation.

[0257] In S507, the update process circuit 88 of the learning circuit 84 executes the aforementioned update process. Through this update process, the mapping data MAP stored in the register 86 of the calculation circuit 82 is updated by being rewritten with the updated mapping data MAP'. S507 corresponds to the learning process executed by the learning circuit 84. In the gate driving device 81, the processes in S502 to S508 described above are repeatedly executed until a switching end instruction END is given.

[0258] In other words, the loop process from S502 to S508 is repeated each time semiconductor switching element 5 is switched. When the switching end instruction END is given, the loop process from S502 to S508 ends, and the program proceeds to S509. In S509, the mapping data MAP stored in memory unit 85 is updated by being rewritten to the mapping data MAP stored in register 86 of computing circuit 82. After executing S509, the operation ends.

[0259] The gate driving device 81 described in the above embodiment also achieves effects similar to those in the fourth embodiment. Specifically, it achieves the excellent effect that the surge voltage Vsrg can be controlled with high precision to the desired target value when the semiconductor switching element 5 is switched (particularly when it is turned off). In this case, the calculation circuit 82 calculates the value of the gate current Ig using mapping data MAP, which is a one-dimensional mapping representing the relationship between the gate current Ig and the surge voltage Vsrg.

[0260] In this case, the learning circuit 84 changes the calculation method of the gate current Ig by updating the mapping data MAP based on the value of the gate current Ig calculated by the calculation circuit 82 and the detected value of the surge voltage Vsrg detected by the detection circuit 83. Through this operation, the calculation error of the calculation circuit 82 on the gate current Ig is reduced, enabling the surge voltage Vsrg to be controlled to the target value with higher accuracy.

[0261] The gate drive device 81 has a storage cell 85 capable of storing the mapping data MAP updated by the learning circuit 84. Before the power is turned off of the gate drive device 81, the learning circuit 84 stores the updated mapping data MAP in the storage cell 85, and at the start of the next operation performed after the power is turned off of the gate drive device 81, the calculation circuit 82 calculates the gate current Ig using the mapping data MAP stored in the storage cell 85. In this way, in the second and subsequent operations, the gate current Ig is calculated using the mapping data MAP learned in the last operation from the start time of the operation. Therefore, the surge voltage Vsrg can be stably controlled to the target value with high accuracy immediately after the start of the operation.

[0262] (Modifications regarding mapping data updates)

[0263] In this embodiment, the learning circuit 84 writes and stores the updated mapping data MAP into the storage cell 85; that is, the mapping data MAP stored in the storage cell 85 is updated before the power to the gate drive device 81 is turned off. This can be modified as follows.

[0264] Specifically, after the learning process has been executed a specified number of times (once or more), the learning circuit 84 can store the updated mapping data MAP in the storage unit 85. Specifically, the learning circuit 84 can execute S509 each time S507 is executed a specified number of times. That is, it can change... Figure 24 The process shown causes S509 to be executed during the loop process.

[0265] In the following situation, namely, before the power is turned off by the gate drive device 81 or after a specified number of times (once or more) the learning process is executed, and the difference between the value of the updated mapping data MAP by the learning circuit 84 and the value of the mapping data MAP at the start of operation exceeds a preset allowable value, the learning circuit 84 may store the updated mapping data MAP in the memory cell 85. In this way, while suppressing the number of times it is written to the memory cell 85, the stability of the surge voltage Vsrg can be well maintained immediately after the start of the second and subsequent operations.

[0266] The value of the mapping data MAP is the value of the gate current Ig as an operating quantity or the value of the surge voltage Vsrg as a transient voltage, and for each of the values ​​of the gate current Ig or the surge voltage Vsrg in the mapping data MAP, it is determined whether the above difference exceeds the allowable value.

[0267] Furthermore, the learning circuit 84 does not need to store the updated mapping data MAP in the memory cell 85; that is, it does not need to update the mapping data MAP stored in the memory cell 85. In this way, although the stability of controlling the surge voltage Vsrg immediately after the start of the second and subsequent operations is reduced, the number of writes to the memory cell 85 can be suppressed, making it suitable for situations where the number of writes to the memory cell 85 is limited. In such cases, the gate drive device (gate drive circuit) 81 does not need to have a memory cell 85, and it is sufficient to use the value that has been fixed to the initial value in advance as the mapping data MAP.

[0268] (Revisions regarding the learning process)

[0269] During the learning process, the learning circuit 84 can modify its calculation method based on the current gate current Ig calculated by the calculation circuit 82 and the current surge voltage Vsrg detected by the detection circuit 83, as well as the past gate current Ig calculated by the calculation circuit 82 and the past surge voltage Vsrg detected by the detection circuit 83. Specifically, during the learning process, the learning circuit 84 can update the mapping data using updated mapping data obtained by smoothing the updated mapping data MAP'. The updated mapping data MAP' is derived by performing a filtering process using the current updated mapping data MAP' output from the update process circuit 88 and the mapping data MAP corresponding to the past updated mapping data MAP' stored in the register 86 of the calculation circuit 82.

[0270] For example, the various processes described in the first embodiment can be used as filtering processes. In this way, even in the case of erroneous learning where the updated mapping data MAP' becomes an incorrect value due to noise, temporary anomalies, etc., the surge voltage Vsrg can be suppressed from deviating from the target value due to such influence.

[0271] (Modifications regarding the update process)

[0272] The update process of generating updated mapping data MAP' by update process circuit 88 in learning circuit 84, that is, the process of updating the mapping data, can be modified in a manner similar to the first and second modification forms related to the update process described in the second embodiment.

[0273] (Sixth Embodiment)

[0274] In the following text, reference will be made to Figures 25 to 28 The sixth embodiment is described.

[0275] (Main functions of gate drive devices)

[0276] Reference Figure 25 The main functions of the gate driving device 91 in this embodiment are described. For example... Figure 25 As shown, the gate driving device 91 of the sixth embodiment differs from the gate driving device 81 of the fifth embodiment in that: a computing circuit 92 is provided instead of a computing circuit 82, a detection circuit 93 is provided instead of a detection circuit 83, a learning circuit 94 is provided instead of a learning circuit 84, a storage unit 95 is provided instead of a storage unit 85, and so on.

[0277] The detection circuit 93 detects the surge voltage Vsrg, and also detects the source voltage Va and the current Id. The detection circuit 93 can detect an off-state voltage Vds_off, which is approximately equal to the source voltage Va, instead of the source voltage Va. In this case, it is sufficient to replace the source voltage Va with the off-state voltage Vds_off in the following description.

[0278] Similar to calculation circuit 82, calculation circuit 92 obtains the mapping data in advance as relational information. However, in this case, the mapping data is a multidimensional mapping of the gate current Ig as an operating quantity, maintained by combining the voltage ΔVds and current Id associated with the surge voltage Vds as a transient voltage, and specifically, for example, is as follows: Figure 27 The data shown. Figure 27 In the mapping data shown, the unit of voltage ΔVds is "V". In the following description, unless otherwise stated, the unit of voltage ΔVds is Ω. Figure 27 Similar units are shown, and by omitting units, only numerical values ​​will be described.

[0279] The calculation circuit 92 calculates the gate current Ig, which is the operating quantity, using the target value of the voltage ΔVds corresponding to the target value of the transient voltage, the detection value of the current Id by the detection circuit 83, and the mapping data. As a learning process, the learning circuit 94 updates the mapping data based on the operating quantity calculated by the calculation circuit 92 and the detection value detected by the detection circuit 93, thereby changing the calculation method of the operating quantity. The storage unit 95 can store the mapping data updated by the learning circuit 94. Before the power is turned off by the gate drive device 91, the learning circuit 94 stores the updated mapping data in the storage unit 95. At the start of the next operation after the power is turned off by the gate drive device 91, the calculation circuit 92 calculates the operating quantity using the mapping data stored in the storage unit 95.

[0280] (Specific structure of the gate drive device)

[0281] For example, it can be adopted as follows Figure 26 The example shown is a specific construction of a gate drive device 91 having the functions described above. Figure 26 The gate driving device 91 shown is Figure 21 The gate driving device 81 of the fifth embodiment shown differs in that: a computing circuit 92 is provided instead of a computing circuit 82, a detection circuit 93 is provided instead of a detection circuit 53, a learning circuit 94 is provided instead of a learning circuit 84, a storage unit 95 is provided instead of a storage unit 85, and so on.

[0282] and Figure 18Similar to the detection circuit 63 shown, detection circuit 93 detects the surge voltage Vsrg and the disconnect voltage Vds_off. Detection circuit 93 detects the current Id based on the current detection signal output from the current sensor 96 provided along the path of current Id flowing in the semiconductor switching element 5B. Detection circuit 93 outputs signals representing the detected value of the surge voltage Vsrg, the detected value of the disconnect voltage Vds_off, and the detected value of the current Id.

[0283] The difference between storage unit 95 and storage unit 85 is that the stored mapping data MAP is the aforementioned two-dimensional mapping, etc. The difference between computing circuit 92 and computing circuit 82 is that: an arithmetic circuit 97 is added, and a retrieval process circuit 98 is provided to replace the retrieval process circuit 87, etc. Computing circuit 92 performs operations almost identical to those of computing circuit 82, except for the operations performed by the arithmetic circuit 97 and the retrieval process circuit 98.

[0284] The signal Vds_off output from the detection circuit 93 is input to the arithmetic circuit 97. The arithmetic circuit 97 reads the target surge voltage Vsrg* stored in the register 67 and subtracts the detected value of the disconnection voltage Vsd_off, represented by the signal Vds_off, from the read target surge voltage Vsrg*. The value obtained as the result of this calculation by the arithmetic circuit 97 corresponds to the target value ΔVds* of the aforementioned voltage ΔVds. The arithmetic circuit 97 outputs a signal representing the voltage ΔVds*.

[0285] The retrieval process circuit 98 reads the mapping data MAP stored in register 86. The signal ΔVds* output from the arithmetic circuit 97 and the signal Id output from the detection circuit 93 are input to the retrieval process circuit 98. The retrieval process circuit 98 performs the following retrieval process: it retrieves the gate current Ig corresponding to the value of the target voltage ΔVds* represented by the signal ΔVds* and the detected value of the current Id represented by the signal Id from the mapping data MAP, and outputs a signal Ig representing the value of the retrieved gate current Ig. For example, if the value of the target voltage ΔVds is "30" and the detected value of the current Id is "20", the retrieval process circuit 98 retrieves the gate current Ig = 0.08 corresponding to voltage ΔVds = 30 and current Id = 20 from the mapping data MAP, and outputs a signal Ig representing "0.08" as the value of the retrieved gate current Ig.

[0286] In this case, the mapping data MAP stored in register 86 is updated by the operation of the learning circuit 94, which will be described later. Before the power supply to the gate drive device 91 is turned off, register 86 outputs a signal representing the stored mapping data MAP to the memory cell 95. Through this operation, the mapping data MAP stored in memory cell 95 is updated by being rewritten to the mapping data MAP stored in register 86.

[0287] The learning circuit 94 differs from the learning circuit 84 in that it adds an arithmetic circuit 99, provides an update process circuit 100 instead of the update process circuit 88, and so on. The signals Vsrg, Vds_off, and Id output from the detection circuit 93, and the signal Ig output from the calculation circuit 92, are input to the learning circuit 94. The arithmetic circuit 99 subtracts the detected value of the disconnection voltage Vds_off, represented by the signal Vds_off, from the detected value of the surge voltage Vsrg, represented by the signal Vsrg. The resulting value of this calculation by the arithmetic circuit 99 corresponds to the detected value of the voltage ΔVds. The arithmetic circuit 99 outputs a signal representing the detected value of the voltage ΔVds to the update process circuit 100.

[0288] The update process circuit 100 performs the following update process: it retrieves the gate current Ig on the mapping data MAP that corresponds to the detected value of the voltage ΔVds represented by the signal ΔVds and the detected value of the current Id detected by the detection circuit 93, generates an updated mapping data MAP' by changing the value of the gate current Ig retrieved on the mapping data MAP to the value of the gate current Ig calculated by the calculation circuit 92, and outputs a signal representing the updated mapping data MAP'.

[0289] For example, if the detected values ​​of voltage ΔVds and current Id are "40" and "20" respectively, and the value of gate current Ig calculated by calculation circuit 92 is "0.08", the update process circuit 100 retrieves the gate current Ig = 0.09 corresponding to voltage ΔVds = 40 and current Id = 20 from the mapping data MAP. The update process circuit 100 generates updated data MAP', wherein the value of gate current Ig corresponding to voltage ΔVds = 40 and current Id = 20 retrieved from the mapping data MAP is changed to "0.08" as the value of gate current Ig calculated by calculation circuit 92. The update process circuit 100 outputs a signal representing the updated mapping data MAP' generated through such an update process to register 86 of calculation circuit 92. Through this operation, the mapping data MAP stored in register 86 is updated by being rewritten with the updated mapping data MAP'.

[0290] (Operation flow of the gate driving device)

[0291] Then, refer to Figure 28 The operation flow of the gate driving device 91 having the above-described structure is described. In the gate driving device 91, the following operations are performed during the period from power-on to power-off: Figure 28 The process is illustrated. In S601, which is executed first after the operation begins, the target surge voltage Vsrg* and the mapping data MAP are read from the storage unit 95 and stored in registers 67 and 86 in the calculation circuit 92. Specifically, in S601, the target surge voltage Vsrg* and the mapping data MAP stored in the storage unit 95 are downloaded to registers 67 and 86 in the calculation circuit 92.

[0292] After executing S601, the loop start process in S602 is executed. The loop start process in S602 is a process that repeatedly executes the process from S603 to S609 until the switching end instruction END is given (i.e., the giving of the switching end instruction END in S610 is the end condition of the loop end process). In S603, the semiconductor switching element 5 is in the off state, and in this state, the detection circuit 93 detects the off voltage Vds_off.

[0293] In S604, when an ON command is given, the drive circuit 12 outputs a gate current Ig_on that switches the semiconductor switching element 5 to ON. The current value of the gate current Ig_on at this time is a predetermined current value. In S605, the semiconductor switching element 5 is in the ON state, and in this state, the detection circuit 93 detects the current Id.

[0294] In S606, the retrieval process circuit 98 of the calculation circuit 92 performs the aforementioned retrieval process. Specifically, in S606, the calculation circuit 92 retrieves the gate current Ig from the mapping data MAP stored in the register 86 using the target surge voltage Vsrg* and the detected value of the current Id detected in S605. In S607, when an OFF command is given, the drive circuit 12 outputs a gate current Ig_off that switches the semiconductor switching element 5 to the off position. The current value of the gate current Ig_off at this time is the value corresponding to the gate current Ig retrieved in S604.

[0295] In S608, the detection circuit 93 detects the surge voltage Vsrg generated when the circuit is disconnected. In S608, the voltage ΔVds is detected when the arithmetic circuit 99 of the learning circuit 94 performs an arithmetic operation. In S608, in addition to detecting the surge voltage Vsrg, the detection circuit 93 can also detect the disconnection voltage Vds_off.

[0296] In S609, the update process circuit 100 of the learning circuit 94 executes the aforementioned update process. Through this update process, the mapping data MAP stored in the register 86 of the calculation circuit 92 is updated by being rewritten with the updated mapping data MAP'. S609 corresponds to the learning process executed by the learning circuit 94. In the gate driving device 91, the processes in S602 to S610 described above are repeatedly executed until a switching end instruction END is given.

[0297] In other words, the cycle from S602 to S610 is repeated each time semiconductor switching element 5 is switched. When the switching end instruction END is given, the cycle from S602 to S610 ends, and the program proceeds to S611.

[0298] In S611, the mapping data MAP stored in the storage unit 95 is updated by being rewritten to the mapping data MAP stored in the register 86 of the computing circuit 92. After executing S611, the operation ends.

[0299] The gate drive device 91 of the above embodiment also achieves the same effects as the fourth embodiment. Specifically, it achieves an excellent effect in which the surge voltage Vsrg during the switching of the semiconductor switching element 5 (particularly, during disconnection) can be controlled to a desired target value with high precision. The gate drive device 91 of this embodiment also achieves the following effect: the surge voltage Vsrg that actually occurs during disconnection in the semiconductor switching element 5, which is the driving target of the gate drive device 91, may vary depending on the current Id of the semiconductor switching element 5, etc.

[0300] In this case, the calculation circuit 92 calculates the value of the gate current Ig using mapping data MAP, which serves as a two-dimensional mapping to maintain the gate current Ig by combining the voltage ΔVds and current Id associated with the surge voltage Vsrg. The learning circuit 94 then modifies the calculation method of the gate current Ig by updating the mapping data MAP based on the value of the gate current Ig calculated by the calculation circuit 92 and the detected values ​​of the surge voltage Vsrg, the off-state voltage Vds_off, and the current Id detected by the detection circuit 93. In this way, the calculation error of the gate current Ig by the calculation circuit 92 due to the dependence of the surge voltage Vsrg on the current Id is reduced, enabling the surge voltage Vsrg to be controlled to the target value with higher accuracy.

[0301] The gate drive device 91 has a storage cell 95 capable of storing the mapping data MAP updated by the learning circuit 94. Before the power to the gate drive device 91 is turned off, the learning circuit 94 stores the updated mapping data MAP in the storage cell 95. At the start of the next operation performed after the power to the gate drive device 91 is turned off, the calculation circuit 92 calculates the gate current Ig using the mapping data MAP stored in the storage cell 95. In this way, in the second and subsequent operations, the gate current Ig is calculated using the mapping data MAP learned in the last operation from the start time of the operation. Therefore, the surge voltage Vsrg can be stably controlled to the target value with high accuracy immediately after the start of the operation.

[0302] (Regarding modifications to the mapping data)

[0303] The surge voltage Vsrg actually generated when the semiconductor switching element 5, which is the driving target of the gate driving device 91, may vary not only depending on the current Id of the semiconductor switching element, but also on the temperature of the semiconductor switching element 5, the temperature of the gate driving device 51, the source voltage Va, etc.

[0304] Therefore, the mapping data MAP can be a multidimensional mapping of the gate current Ig, which is an operating quantity, by combining at least one of the physical quantities of the surge voltage Vsrg (a transient voltage) or the voltage ΔVds associated with the surge voltage Vsrg, the temperature of the semiconductor switching element 5, the temperature of the gate driving device 91, the source voltage Va, and the current Id. In this case, the detection circuit 93 must be configured to detect at least one of the physical quantities of the semiconductor switching element 5, the temperature of the gate driving device 91, the source voltage Va, and the current Id.

[0305] In this case, the calculation circuit 92 calculates the gate current Ig using the target value Vsrg* of the surge voltage Vsrg, the detection value of the physical quantity by the detection circuit 93, and the mapping data MAP. Through this operation, the calculation error of the gate current Ig caused by physical quantities such as the temperature of the semiconductor switching element 5, the temperature of the gate driving device 91, the source voltage Va, and the current Id (i.e., various disturbance factors) is reduced, enabling the surge voltage Vsrg to be controlled to the target value with high accuracy.

[0306] (Modifications regarding mapping data updates)

[0307] In this embodiment, the learning circuit 94 writes and stores the updated mapping data MAP into the storage cell 85; that is, the mapping data MAP stored in the storage cell 95 is updated before the power to the gate drive device 91 is turned off. This can be modified as follows.

[0308] Specifically, after the learning process is executed a specified number of times (once or more), the learning circuit 94 can store the updated mapping data MAP in the storage unit 95. Specifically, the learning circuit 94 can execute S611 each time S609 is executed a specified number of times. That is, it can change... Figure 28 The process shown causes S611 to be executed during the loop process.

[0309] In the following cases, namely, before the power is turned off by the gate drive device 91 or after the learning process has been performed a specified number of times (once or more), and the difference between the value of the mapping data MAP updated by the learning circuit 94 and the value of the mapping data MAP at the start of operation exceeds a preset allowable value, the learning circuit 94 may store the updated mapping data MAP in the storage unit 95.

[0310] Specifically, learning circuit 94 can execute the following after the loop process ends: Figure 10 The process in the second embodiment shown is similar to S209, and after that, S611 is executed. That is to say, it can be modified. Figure 28 The process shown is modified to add a process similar to S209 between S610 and S611. In this way, while suppressing the number of writes to memory cell 95, it is possible to maintain excellent stability in controlling the surge voltage Vsrg immediately after the start of the second and subsequent operations.

[0311] Furthermore, the learning circuit 94 does not need to store the updated mapping data MAP in the memory cell 95; that is, it does not need to update the mapping data MAP stored in the memory cell 95. In this way, although the stability of controlling the surge voltage Vsrg immediately after the start of the second and subsequent operations is reduced, the number of writes to the memory cell 95 can be suppressed, making it suitable for situations where the number of writes to the memory cell 95 is limited. In such cases, the gate drive circuit 91 does not need to have a memory cell 95, and it is sufficient to use the value that has been fixed to an initial value in advance as the mapping data MAP.

[0312] (Revisions regarding the learning process)

[0313] During the learning process, the learning circuit 94 can modify its calculation method based on the current gate current Ig calculated by the calculation circuit 92 and the current detection value detected by the detection circuit 93, as well as based on the past gate current Ig calculated by the calculation circuit 92 and the past detection value detected by the detection circuit 93. Specifically, during the learning process, the learning circuit 94 can update the mapping data using updated mapping data obtained by smoothing the updated mapping data MAP'. The updated mapping data MAP' is derived by performing a filtering process using the current updated mapping data MAP' output from the update process circuit 100 and the mapping data MAP corresponding to the past updated mapping data MAP' stored in the register 86 of the calculation circuit 92.

[0314] For example, the various processes described in the first embodiment can be used as filtering processes. In this way, even in the case of erroneous learning where the updated mapping data MAP' becomes an incorrect value due to noise, temporary anomalies, etc., the surge voltage Vsrg can be suppressed from deviating from the target value due to such influence.

[0315] (Modifications regarding the update process)

[0316] The update process of generating updated mapping data MAP' by update process circuit 100 in learning circuit 94, that is, the process of updating the mapping data, can be modified in a manner similar to the first and second modification forms related to process update described in the second embodiment.

[0317] (Seventh Embodiment)

[0318] In the following text, reference will be made to Figures 29 to 31 The seventh embodiment is described.

[0319] (Main functions of gate drive devices)

[0320] Reference Figure 29 The main functions of the gate driving device 111 in the embodiment are described. For example... Figure 29 As shown, the gate driving device 111 of this embodiment differs from the gate driving device 41 of the second embodiment in that a driving circuit 112 is provided instead of a driving circuit 12, and a detection circuit 113 is provided instead of a detection circuit 53, etc. The transient voltage that is the control target of the gate driving device 111 in this embodiment is the rate of change dV / dt of the semiconductor switching element 5 of the opposite arm. Similar to the driving circuit 12, the driving circuit 112 drives the gate of the semiconductor switching element 5 based on the operating quantity calculated by the calculation circuit 11. The detection circuit 113 detects the rate of change dV / dt of the semiconductor switching element 5 of the opposite arm.

[0321] (Specific structure of the gate drive device)

[0322] For example, it can be adopted as follows Figure 30 The example shown is a specific construction of a gate drive device 111 having the functions described above. Figure 30 The gate drive device 111 shown in the figure and Figure 7 The gate driving device 41 shown is different in that it provides a driving circuit 112 instead of a driving circuit 12, a detection circuit 113 instead of a detection circuit 53, and so on.

[0323] The detection circuit 113 detects the rate of change dV / dt of the voltage Vds of the semiconductor switching element 5 located on the opposite arm side and outputs a signal representing the detected value. The difference between the drive circuit 112 and the drive circuit 12 is as follows. In this case, the current source 26 has a configuration capable of changing its current value based on the signal Ig output from the calculation circuit 42. In this case, as a configuration on the disconnected side in the drive circuit 112, a resistor with a specific resistance value can be provided instead of the current source 27. That is, the drive circuit 112 does not necessarily have a configuration for constant current drive with respect to the disconnected side.

[0324] (Operation flow of the gate driving device)

[0325] Then, refer to Figure 31 The operation flow of the gate driving device 111 having the above-described structure is described. In the gate driving device 111, during the period from power-on to power-off, the following is performed: Figure 31 The process is illustrated. In S701, which is executed first after the operation begins, the target rate of change dV / dt* and the mapping data MAP are read from the storage unit 44 and stored in registers 21 and 45 in the calculation circuit 42. That is, in S701, the target rate of change dV / dt* and the mapping data MAP stored in the storage unit 44 are downloaded into registers 21 and 45 in the calculation circuit 42.

[0326] After S701 is executed, the loop start procedure in S702 is executed. The loop start procedure in S702 is a process that repeatedly executes the process from S703 to S707 until the switch end instruction END is given (that is, the switch end instruction END in S708 is given as the end condition of the loop end procedure).

[0327] In S703, the retrieval process circuit 46 in the calculation circuit 42 executes the aforementioned retrieval process. Specifically, in S703, the calculation circuit 42 retrieves the gate current Ig from the mapping data MAP stored in the register 45 using the target change rate dV / dt* stored in the register 21. In S704, when an ON command is given, the drive circuit 112 outputs a gate current Ig_on that switches the semiconductor switching element 5 to ON. The current value of the gate current Ig_off at this time is the value corresponding to the gate current Ig retrieved in S703.

[0328] In S705, the detection circuit 113 detects the rate of change dV / dt of the semiconductor switching element 5 on the opposite arm side when it is turned on. In S706, the update process circuit 47 of the learning circuit 43 performs the above-mentioned update process, through which the mapping data MAP stored in the register 45 of the calculation circuit 42 is updated by being rewritten with the updated mapping data MAP'. S706 corresponds to the learning process performed by the learning circuit 43.

[0329] In S707, when the OFF command is given, the drive circuit 112 outputs the gate current Ig_off, thereby switching the semiconductor switching element 5 to ON. The current value of the gate current Ig_on at this time is a predetermined current value. In the gate drive device 111, the processes described in S702 to S708 are repeated until the END command is given.

[0330] Each time semiconductor switching element 5 is switched, the loop process from S702 to S708 is repeated. When the switching end instruction END is given, the loop process from S702 to S708 ends, and the program proceeds to S709. In S709, it is determined whether the difference between the current value of the mapping data MAP stored in register 45 and the value of the mapping data MAP stored in memory cell 44 (i.e., the initial value of the mapping data MAP at the start of the operation) exceeds a preset allowable value. In this case, the value of the mapping data MAP is the value of the gate current Ig as the operation quantity, and this determination is performed for each value of the gate current Ig in the mapping data MAP.

[0331] If the difference between the current value and the initial value is equal to or less than the allowed value, "No" is determined in S709, and the operation ends without executing S710. On the other hand, if the difference between the current value and the initial value exceeds the allowed value, "Yes" is determined in S709, and the program proceeds to S710. In S710, the mapping data MAP stored in the storage unit 44 is updated by being rewritten to the mapping data MAP stored in the register 45 of the calculation circuit 42. After executing S710, the operation ends.

[0332] The gate driving device 111 of the above embodiment optimizes the calculation method for the gate current Ig, which is the operating amount for operating the gate driving speed when the semiconductor switching element 5 is turned on, by performing a learning process by the learning circuit 43, so as to conform to the actual rate of change dV / dt that occurs in the semiconductor switching element 5 located on the opposite arm side when the semiconductor switching element 5 located on its own arm side is turned on.

[0333] As described above, according to the embodiment, the calculation method is optimized based on the differences between products. Therefore, even if there are individual differences between the gate drive device 111 and the semiconductor switching element 5, the gate drive speed of the semiconductor switching element 5 can be controlled to a desired speed, and furthermore, the rate of change dV / dt of the semiconductor switching element 5 on the opposite arm side when turned on can be controlled to a desired target value. As described above, according to the embodiment, except that the transient voltage as the control target is the rate of change dV / dt of the semiconductor switching element 5 on the opposite arm, similar effects to the second embodiment can be obtained.

[0334] (Other embodiments)

[0335] This disclosure is not limited to the various embodiments shown above and in the accompanying drawings, and can be modified, combined or extended in any way without departing from the spirit.

[0336] The numerical values ​​indicated in the foregoing embodiments are examples, and the present invention is not limited thereto.

[0337] The driving target of the gate driving device in each of the foregoing embodiments is not limited to an N-channel MOSFET, but can be various semiconductor switching elements such as a P-channel MOSFET or an IGBT.

[0338] The operating quantity used to control the gate drive speed of the semiconductor switching element 5 is not limited to the gate current Ig, but can be any one of the gate voltage Vg and gate resistance Rg of the semiconductor switching element 5. The rate of change dV / dt and the gate voltage Vg have, for example, as follows: Figure 32 The relationship shown is such that the surge voltage Vsrg and the gate voltage Vg have (for example) the following relationship: Figure 33 The relationship is shown. Therefore, when using the gate voltage Vg as the operating quantity, considering the following... Figure 32 and Figure 33 The relationship shown in the figure is sufficient to set the optimal model formula and inverse model formula.

[0339] exist Figure 32 and Figure 33 In this context, the gate threshold voltage of semiconductor switching element 5 is denoted as Vth. Figure 32 and Figure 33 In the diagram, the on-side indicator corresponds to the positive gate voltage Vg that turns on the gate of the semiconductor switching element 5, and the off-side indicator corresponds to the negative gate voltage Vg that turns off the gate of the semiconductor switching element 5.

[0340] The rate of change dV / dt and the gate resistance Rg have (for example) as Figure 34 The relationship shown is given, and the surge voltage Vsrg and gate resistance Rg have (for example) the following characteristics: Figure 35 The relationship is shown in the figure. When using the gate resistance Rg as the operating variable, considering... Figure 34 and Figure 35 The relationship shown in the figure is sufficient to set the optimal model formula and inverse model formula.

[0341] Here, the process described in the flowchart or infographic of this application consists of multiple parts (or steps), and each part is represented, for example, S101. Each part can be divided into several sub-parts, and several parts can be combined into one part. Furthermore, each part configured in this way can be referred to as an apparatus, module, or assembly.

[0342] Although embodiments have been described in detail above, these are merely examples and do not limit the scope of this disclosure. The techniques described in this disclosure include various modifications and variations of the specific examples shown above. The technical elements described in this disclosure or the accompanying drawings demonstrate technical usefulness individually or in various combinations, and are not limited to the combinations described in this disclosure at the time of application. Furthermore, the techniques shown in this specification or the accompanying drawings achieve multiple objectives simultaneously, and achieving one of these objectives is itself technically useful.

Claims

1. A gate driving device configured to drive the gate of a semiconductor switching element and, when switching the semiconductor switching element, control a transient voltage corresponding to the voltage of the main terminal of the semiconductor switching element to a target value of the transient voltage, the gate driving device comprising: A computing circuit is configured to execute a predetermined computing mode using the target value of the transient voltage to calculate the amount of operation for operating the gate drive speed of the semiconductor switching element. A driving circuit configured to drive the gate of the semiconductor switching element according to the operating amount calculated by the computing circuit; A detection circuit configured to detect the transient voltage; as well as A learning circuit is configured to perform learning processing to change the predetermined computation mode based on the following: The operation quantity calculated by the computing circuit, and The detected value of the transient voltage detected by the detection circuit. The computing circuit is further configured as follows: Pre-acquisition: The target value of the transient voltage, and Relationship information representing the relationship between the operational quantity and the transient voltage; and The operational quantity is calculated based on the target value of the transient voltage and the relationship information pre-acquired by the calculation circuit. The computing circuit is further configured as follows: The model parameters are obtained in advance as the relation information; and The operational quantity is calculated based on the model formula using the target value of the transient voltage and the model parameters, and The learning circuit is further configured as follows: The learned values, corresponding to the model parameters, are calculated based on the following: The operation quantity calculated by the computing circuit, and The detected value of the transient voltage detected by the detection circuit; and The model parameters are updated based on the learning values ​​calculated by the learning circuit.

2. The gate driving device according to claim 1, in, The transient voltage is the rate of change of the voltage at the main terminal during the switching of the semiconductor switching element.

3. The gate driving device according to claim 1, in, The transient voltage is the peak value of the voltage at the main terminal during the switching of the semiconductor switching element.

4. The gate driving device according to claim 1, in, The driving circuit has a structure configured to drive the gate of the semiconductor switching element with a constant current, and The computing circuit is further configured to calculate the gate current of the semiconductor switching element, which is the operational quantity.

5. The gate driving device according to claim 1, in, The transient voltage is the rate of change of the voltage at the main terminal during the switching of the semiconductor switching element. The driving circuit has a structure configured to drive the gate of the semiconductor switching element with a constant current. The computing circuit is further configured to calculate the gate current of the semiconductor switching element as the operational quantity based on the following formula (1) which is the model formula: Ig=K×dV / dt (1), Where K represents the model parameters, dV / dt The target value represents the rate of change of the transient voltage, and Ig represents the gate current as the operating quantity. The learning circuit is further configured to calculate the learning value based on the following formula (2): Ka = Iga ÷ dV / dt (2), Wherein, Ka represents the learning value, Iga represents the gate current calculated by the computing circuit as the operating quantity, and dV / dt represents the detected value as the rate of change of the transient voltage detected by the detection circuit.

6. The gate driving device according to claim 1, in, The transient voltage is the peak value of the voltage at the main terminal during the switching of the semiconductor switching element. The driving circuit has a structure configured to drive the gate of the semiconductor switching element with a constant current. The computing circuit is further configured to calculate the gate current of the semiconductor switching element as the operational quantity based on the following formula (3) which is the model formula: Ig=(Vsrg -Va)÷K (3), Where K represents the model parameters, Vsrg The target value represents the peak value of the transient voltage, Va represents the voltage applied between the main terminals of the semiconductor switching element, and Ig represents the gate current as the operating quantity. The learning circuit (64) is configured to calculate the learning value based on the following formula (4): Ka=(Vsrg-Va)÷Iga (4), Wherein, Ka represents the learning value, Iga represents the gate current calculated by the computing circuit as the operational quantity, and Vsrg represents the detection value detected by the detection circuit as the peak value of the transient voltage.

7. The gate driving device according to claim 1, further comprising: A storage unit configured to store the model parameters updated by the learning circuit. The learning circuit is further configured to store the model parameters updated by the learning circuit into the storage unit under the following conditions: Before the power is turned off by the gate drive device, or After the learning process has been performed a predetermined number of times, and The computing circuit is further configured to calculate the operational quantity based on the model parameters stored in the memory cell after the power is turned off from the gate driving device and at the start of subsequent operations of the gate driving device.

8. The gate driving device according to claim 1, further comprising: A storage unit configured to store the model parameters updated by the learning circuit. Wherein, based on the condition that the difference between the value of the model parameter updated by the learning circuit and the value of the model parameter at the start of the current operation of the gate driving device exceeds a preset allowable value, the learning circuit is further configured to store the model parameter updated by the learning circuit into the memory cell under the following conditions: Before the power is turned off by the gate drive device, or After the learning process has been performed a predetermined number of times, and The computing circuit is further configured to calculate the operational quantity based on the model parameters stored in the memory cell after the power supply to the gate driving device is turned off and at the start of subsequent operation of the gate driving device.

9. The gate driving device according to any one of claims 1 to 8, in, The operational quantities calculated by the computing circuit include: The current operation quantity calculated by the computing circuit; and The past operation amount calculated by the computing circuit relative to the current operation amount. The detected value of the transient voltage detected by the detection circuit includes: The current detection value detected by the detection circuit; and The past detection value previously detected by the detection circuit relative to the current detection value, and The learning circuit is further configured to change the predetermined calculation mode based on the current operation quantity, the current detection value, the past operation quantity, and the past detection value.

10. A gate driving device configured to drive the gate of a semiconductor switching element and, when switching the semiconductor switching element, control a transient voltage corresponding to the voltage of the main terminal of the semiconductor switching element to a target value of the transient voltage, the gate driving device comprising: A computing circuit is configured to execute a predetermined computing mode using the target value of the transient voltage to calculate the amount of operation for operating the gate drive speed of the semiconductor switching element. A driving circuit configured to drive the gate of the semiconductor switching element according to the operating amount calculated by the computing circuit; A detection circuit configured to detect the transient voltage; as well as A learning circuit is configured to perform learning processing to change the predetermined computation mode based on the following: The operation quantity calculated by the computing circuit, and The detected value of the transient voltage detected by the detection circuit. The computing circuit is further configured as follows: Pre-acquisition: The target value of the transient voltage, and Relationship information representing the relationship between the operational quantity and the transient voltage; and The operational quantity is calculated based on the target value of the transient voltage and the relationship information pre-acquired by the calculation circuit. The computing circuit is further configured as follows: Pre-acquire mapping data as the relationship information, wherein the mapping data is a mapping representing the relationship between the operational quantity and the transient voltage, and The operational quantity is calculated based on the target value of the transient voltage and the mapping data, and The learning circuit is further configured to update the mapping data based on the following: The operation quantity calculated by the computing circuit, and The detected value of the transient voltage detected by the detection circuit.

11. The gate driving device according to claim 10, in, The learning circuit is further configured to: The operation quantity is retrieved from the mapping data as the retrieved operation quantity corresponding to the detected value of the transient voltage detected by the detection circuit; The retrieved operation quantity is changed only by altering the difference between the retrieved operation quantity and the operation quantity calculated by the computing circuit; and The mapping data is updated so that the difference between the operations within the predetermined range centered on the retrieved operation amount is changed only.

12. The gate driving device according to claim 10, in, The learning circuit is further configured to: The operation quantity is retrieved from the mapping data as the retrieved operation quantity corresponding to the detected value of the transient voltage detected by the detection circuit; The retrieved operation quantity is changed only by altering the difference between the retrieved operation quantity and the operation quantity calculated by the computing circuit; and The mapping data is updated so that the operation within the predetermined range centered on the retrieved operation is changed only by multiplying the difference by a weighting coefficient that decays with distance from the center.

13. The gate driving device according to claim 10, in, The mapping data is a multidimensional mapping, which maintains the operational quantity based on a combination of the transient voltage and at least one physical quantity selected from the group consisting of: The temperature of the semiconductor switching element; The temperature of the gate driving device; As the source voltage for the voltage applied between the main terminals of the semiconductor switching element; as well as The element current is the current flowing between the main terminals of the semiconductor switching element. The detection circuit is further configured to detect at least one physical quantity selected from the group consisting of the temperature of the semiconductor switching element, the temperature of the gate driving device, the source voltage, and the element current. The computing circuit is further configured to calculate the operational quantity based on the following: The target value of the transient voltage, The detection value corresponding to the at least one physical quantity detected by the detection circuit, and The mapping data.

14. The gate driving device according to claim 10, A storage unit configured to store the mapping data updated by the learning circuit. in, The learning circuit is also configured to store the mapped data updated by the learning circuit into the storage unit under the following conditions: Before the power is turned off by the gate drive device, or After the learning process has been performed a predetermined number of times, and The computing circuit is further configured to calculate the operation amount based on the mapping data stored in the memory cell after the power is turned off from the gate driving device and at the start of subsequent operation of the gate driving device.

15. The gate driving device according to claim 10, further comprising: A storage unit configured to store the mapping data updated by the learning circuit. Wherein, based on the condition that the difference between the value of the mapping data updated by the learning circuit and the value of the mapping data at the start of the current operation of the gate driving device exceeds a preset allowable value, the learning circuit is further configured to store the mapping data updated by the learning circuit into the memory cell under the following conditions: Before the power is turned off by the gate drive device, or After the learning process has been performed a predetermined number of times, and The computing circuit is further configured to calculate the operation amount based on the mapping data stored in the memory cell when subsequent operations of the gate drive device begin after the power is turned off.

16. The gate driving device according to claim 10, in, The transient voltage is the rate of change of the voltage at the main terminal during the switching of the semiconductor switching element.

17. The gate driving device according to claim 10, in, The transient voltage is the peak value of the voltage at the main terminal during the switching of the semiconductor switching element.

18. The gate driving device according to claim 10, in, The driving circuit has a structure configured to drive the gate of the semiconductor switching element with a constant current, and The computing circuit is further configured to calculate the gate current of the semiconductor switching element, which is the operational quantity.

19. The gate driving device according to any one of claims 10 to 18, in, The operational quantities calculated by the computing circuit include: The current operation quantity calculated by the computing circuit; and The past operation amount calculated by the computing circuit relative to the current operation amount. The detected value of the transient voltage detected by the detection circuit includes: The current detection value detected by the detection circuit; and The past detection value previously detected by the detection circuit relative to the current detection value, and The learning circuit is further configured to change the predetermined calculation mode based on the current operation quantity, the current detection value, the past operation quantity, and the past detection value.

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