Method of manufacturing a MEMS device
By using a capping layer to protect the hinge metal during the through-hole formation process, the problem of organometallic residues in the development process is solved, thereby improving the image quality and reliability of MEMS devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TEXAS INSTRUMENTS INC
- Filing Date
- 2016-04-13
- Publication Date
- 2026-05-29
Smart Images
Figure CN115973994B_ABST
Abstract
Description
[0001] Information related to divisional application
[0002] This application is a divisional application of the invention patent application filed on April 13, 2016, with application number 201610230215.1 and entitled "Method for Manufacturing MEMS Device". Technical Field
[0003] This invention generally relates to the fabrication of microelectromechanical systems (MEMS), and more particularly, to the fabrication of digital micromirror devices (DMDs). Background Technology
[0004] Microelectromechanical systems (MEMS) devices (such as those from Texas Instruments) Digital micromirror devices (DMDs) use individually positionable arrays of mirrors to form images for projection onto a display surface. Electromechanical components for the mirror array are fabricated on a substrate containing CMOS circuitry for resolving and controlling the positioning of the mirrors. Information on the fabrication of such devices is given in the following literature: L.J. Hornbeck, “Digital Light Processing for High-Brightness, High Resolution Applications” (SPIE Conference Proceedings, Vol. 3013, pp. 27–40, Projection Display III, February 1997), and C. Gong and T. Hogn, “CMOS Compatible Fabrication Processes for the Digital Micromirror Device” (IEEE Journal of Electronics and Devices, Vol. 2, No. 3, pp. 27–32, May 2014), the entire contents of which are incorporated herein by reference.
[0005] Figure 1 (Prior art) shows a cross-sectional image of a DMD MEMS device 100 manufactured according to, for example, the process described by Gong et al. Figure 1 The diagram describes the interconnects between the mirror and hinge layers of the underlying CMOS structure, supported by hinges and mirrors, through vias. Device 100 includes an electromechanical assembly portion 102 above the CMOS portion 104. Substrate 106 includes SRAM cell transistors 108 and other circuitry for data loading and voltage application for mirror positioning.
[0006] A first dielectric layer 110 is formed above transistor 108. A first metal layer (M1) 112 is formed and patterned above the first dielectric layer 110. A second dielectric layer 114 is formed and patterned above layer M1 112. A second metal layer (M2) 116 is formed and patterned above layer M2 114. A third dielectric layer 118 is deposited and patterned above layer M2 116. A third metal layer (M3) 120 is formed and patterned above layer M3 118.
[0007] A spacer layer 122 (typically a photoresist material) is deposited over a third metal layer 120. The spacer layer 122 is sacrificial and is removed in a later step. A hinge via 124 is patterned within the spacer layer 122. Hinge metal is deposited over the spacer layer 122 to form a hinge 126 and is deposited within the hinge via 124 to form the wall of the hinge via 128. Another spacer layer 130 (typically a photoresist material) is deposited over the hinge 126. The spacer layer 130 is sacrificial and will be removed in a later process. A mirror via 132 is patterned within the spacer layer 130, and mirror metal is deposited over the spacer layer 130 and within the mirror via 132 to form a mirror 134. The mirror via 132 may remain partially unfilled after the mirror metal 134 is deposited, and a central indentation 136 may remain within the mirror surface above the mirror via 132. After processing, the sacrificial spacer layer is removed by plasma ashing undercutting.
[0008] In the photolithographic patterning step, a developer (e.g., tetramethylamine hydroxide) is used to remove exposed photoresist. This developer is required for pattern formation.
[0009] Figure 2 (Prior art) Shows a top-down image of a device 200 including a mirror 202.
[0010] The developing process results in the formation of residue 204 within the space 206 of the separation individual mirror 202. Residue 204 is an organometallic material and can interfere with the undercutting process. It can also cause discoloration of the crossing device and hinge torque, and lead to image quality defects in the DMD.
[0011] Residue 204 can form when titanium atoms detach from the exposed hinge metal 126 during the development process and are transported from the bottom of the mirror via to the top of the spacer layer 130. The titanium atoms interact with the spacer layer 130 and the mirror metal / aluminum alloy to form residue 204. Residue 204 acts as a barrier against reactants during the etching process, and the sacrificial spacer layer can be removed non-uniformly.
[0012] The photolithography used in this process is 365nm (i-line). i-line lithography is typical in semiconductor manufacturing and has been extensively studied and tested. Experiments have shown that different other typical photoresists used in this process cannot resolve the formation of residue 204.
[0013] Figure 3 (Prior art) A top-down image of an array 300 of mirrors 302 is shown. Organometallic residues 304 are visible above multiple regions of the array 300. The residues 304 are visible as slight discoloration in the spaces between individual mirrors 302. The residues 304 become more significant as the size of the mirrors 302 decreases and as a larger number of mirrors 302 are deposited across the same surface area. The residues 304 hinder optimal undercutting of the mirrors 302 used for removing the spacer layer and for releasing the hinges and mirrors 302. The residues 304 occur randomly across the substrate. Device performance, contrast, and reliability can be adversely affected.
[0014] Figure 4A and 4B (Prior art) describes the formation of residues above portion 400 of mirror 302.
[0015] exist Figure 4A In this process, hinge metal 402 is formed over spacer layer 404 (typically photoresist). Spacer layer 406 (typically photoresist) is formed over hinge metal 402 and patterned to form via 408. After patterning via 408, top surface 412 of hinge metal 402 is exposed. During the development process, titanium atoms migrate from top surface 412 to top surface 410 of spacer layer 406.
[0016] Figure 4B The portion 400 is shown once the residue has formed. The residue forms layer 414 on the top surface 410 of layer 406. Mirror metal 416 is formed above spacer layer 406 and layer 414. Layer 414 prevents the removal of spacer layer 406 used for releasing the mirror. Summary of the Invention
[0017] A method for manufacturing a MEMS device addresses organometallic residues. A first spacer layer is formed over a substrate. The first spacer layer is patterned to form hinge via openings. A layer of hinge metal is deposited over the first spacer layer to form hinges and hinge vias. A capping layer (e.g., carbon or silicon oxynitride) is formed over the hinge metal layer. A second spacer layer is formed over the capping layer and patterned using a developer to form mirror via openings. The capping layer forms a barrier between the developer and the hinge metal within the mirror via. The capping layer within the mirror via is removed before mirror metal deposition. Attached Figure Description
[0018] Referring to the accompanying drawings, exemplary embodiments are described, in which:
[0019] Figure 1 (Prior art) is a cross-sectional view of a micromirror device.
[0020] Figure 2 (Prior art) is a scanning electron microscope image of organometallic residues at the intersection of cross-scopes.
[0021] Figure 3 (Prior art) is a scanning electron microscope image of a mirror array containing organometallic residues.
[0022] Figure 4A and 4B (Prior art) describes the formation of residue above the mirror portion.
[0023] Figure 5A and 5B This describes the portion of the mirror that has a covering layer.
[0024] Figure 6 This is a cross-sectional view of the micromirror device.
[0025] Figures 7A to 7D Describe the sequence of the micromirror apparatus during manufacturing. Detailed Implementation
[0026] The steps described below are typically performed at the wafer-level, wherein multiple instances of the illustrated structure are simultaneously formed to define an array of such structures formed at corresponding die regions of the corresponding simultaneously formed DMD.
[0027] Figure 5A and 5B This describes part 500 of a micromirror device having a cover layer 506.
[0028] Hinge metal 502 is formed over spacer layer 504 (typically photoresist). Capping layer 506 is formed over metal 502. Capping layer 506 has a thickness of approximately 100 to 500 angstroms. Spacer layer 508 (typically photoresist) is formed over capping layer 506 and patterned to form through-hole 510. Hinge metal 502 is protected by capping layer 506 from the developer used in the patterning process. Capping layer 506 shields hinge metal 502 from reaction with developer and from residue formation. Reference Figure 5B The cover layer 506 within the mirror via 510 is removed using a plasma etching process. Mirror metal 512 is formed above the spacer layer 508 and within the mirror via 510.
[0029] This process is particularly useful when using a lithography wavelength of 365 nm (i-line). Evaluations of multiple i-line photoresists have resulted in the formation of similar organometallic residues. Accordingly, the process can be alternatively applied to lithography processes at other wavelengths that are susceptible to organometallic residues.
[0030] Figure 6 The micromirror device 600 is described as consisting of a CMOS portion 602 and a MEMS portion 604.
[0031] The CMOS portion 602 includes a substrate 606 having transistors and metal interconnect layers. A first metal is deposited over the substrate 606 and patterned to form a first interconnect 608. A first dielectric layer 610 is formed over layer 608. A second metal is deposited over dielectric layer 610 and patterned to form a second interconnect 612. A second dielectric layer 614 is formed over layer 612 and patterned to form a plug 616. The plug 616 is filled with a metal, such as tungsten. A third metal is formed over dielectric layer 614 and patterned to form a third interconnect 618.
[0032] A hinge via 620, made of metal (e.g., titanium), is formed above the CMOS portion 602 and supports the hinge 622. Figure 6 The image shows two hinge vias (one at each end of the CMOS portion 602). The hinge via 620 is a vertical structure supporting the plane and the horizontal hinge 622. A centrally located mirror via 624 is formed above the hinge 622. A metal layer is deposited above the mirror via 624 to form a mirror 626.
[0033] Mirror 626 is reflective and is typically formed of an alloy comprising 99% aluminum and 1% titanium. A central indentation 628 is retained within the top surface of mirror 626.
[0034] Figure 7A D describes the steps involved in manufacturing the device.
[0035] Figure 7A This explains the formation of MEMS portion 604 above CMOS portion 602.
[0036] The CMOS portion 602 includes multiple metal and oxide layers. Metal is formed and patterned over a substrate 606 to create a first interconnect layer 608. Oxide is formed over the first interconnect layer 608 for an insulating layer 610. Metal is formed and patterned over the insulating layer 610 to form a second interconnect layer 612. Oxide is again formed over the interconnect layer 612 for an insulating layer 614. Layer 614 is patterned to form a central plug 616 within layer 614. Metal is formed and patterned over the insulating layer 614 to form a third interconnect layer 618. A sacrificial layer 700 is formed over the third interconnect layer 618 and patterned to form two hinged vias 620 as part of a MEMS 604 portion of a micromirror device 600. Metal (e.g., titanium) is formed over the vias 620 and the sacrificial layer 700 to create hinges 622. The hinged vias 620 may be filled with additional metal for the mechanical strength of the via walls.
[0037] Figure 7B A blanket-like cover layer 702 is formed above the hinge 622 and the hinge through-hole 620. A sacrificial layer 704 is formed above the cover layer 702 and patterned to form a mirror through-hole 624. Forming the through-hole 624 exposes the surface of the cover layer 702 to the developer solution used to pattern the device 600. Layer 702 blocks the hinge 622 from the influence of the developer solution.
[0038] Layer 702 is conformal and formed using processes such as chemical vapor deposition or sputtering. It is sacrificial and can be removed using processes typical of semiconductor manufacturing (e.g., O2 and CF4 ashing). The capping layer 702 does not alter the physical, electrical, or mechanical functions of the micromirror device 600. The deposition temperature of layer 702 is limited by the temperature limits of the material (e.g., photoetchant) and is lower than the temperature used for spacers. The film thickness of the capping layer 702 is approximately 100 to 500 angstroms. Layer 702 may be composed of organic materials (e.g., carbon) or inorganic materials (e.g., silicon oxynitride).
[0039] In one example embodiment, layer 702 is composed of carbon deposited by chemical vapor deposition at approximately 200 degrees Celsius, with a thickness of approximately 200 Å.
[0040] exist Figure 7C In the process, a plasma etching operation is used to remove the capping layer 702 from the via 624. The capping layer 702 remains within the via 624.
[0041] exist Figure 7D In this process, mirror metal is deposited above layer 704 and within mirror via 624 to form mirror 626. Cover layer 702 is retained between sacrificial layer 704 and hinge via 620 and hinge 622. Central indentation 628 originates from the metal deposition above mirror via 624.
[0042] After the formation of mirror 626, the remaining sacrificial spacer layers 700 and 704 and the remaining capping layer 702 are removed using O2 and CF4 ashing in a plasma etching undercut operation. The removal of spacer layers 700 and 704 releases hinge 622 and mirror 626. Hinge through-hole 620 forms a freestanding support for hinge 622, and mirror through-hole 624 forms a freestanding support for mirror 626.
[0043] One method for dealing with organometallic residues is to use solution washing of the mirror array to remove the residues. This method results in the formation of defects on the surface of the mirror metal.
[0044] Another method is to increase the etching time of the mirror metal to remove the residue. This method cannot remove the residue and may damage the mirror surface.
[0045] Another approach is to form a polymer material over the hinge metal to prevent interaction between the developer and the hinge metal. This method addresses the formation of organometallic residues, but may also lead to other defects.
[0046] The described method offers many advantages.
[0047] The cover layer 702 protects the hinge 622 and forms a barrier against the developer during the formation of the mirror aperture 624.
[0048] Layer 702 is sacrificial and can be removed during the release process of hinge 622 and mirror 626.
[0049] Layer 702 forms a barrier against electrochemical attacks from the hinge metal.
[0050] Experimental data have shown that the 702 coating layer effectively resists organometallic residues and improves device reliability in case of failure.
[0051] Those skilled in the art will understand that modifications can be made to the described exemplary embodiments within the scope of the invention as claimed, and many other embodiments are also possible.
Claims
1. A method for manufacturing a microelectromechanical system (MEMS) device, the method comprising: A first photoresist spacer layer is deposited over a substrate with circuitry. The hinge through-hole openings are patterned in the first photoresist spacer layer; A hinge metal layer is deposited above the first photoresist spacer layer and in the hinge through-hole opening to form a hinge and a hinge through-hole; A capping layer is deposited over the hinge metal layer and over the hinge through-hole; A second photoresist spacer layer is deposited over the capping layer; A developer is used in the second photoresist spacer layer to pattern the through-hole opening, wherein the cover layer shields the hinge metal layer at the bottom of the through-hole opening to prevent it from reacting with the developer and from forming residues on the second photoresist spacer layer. Remove the cover layer at the bottom of the through-hole opening to expose the hinge metal layer at the bottom of the through-hole opening; Mirror metal is deposited in the opening of the mirror via and above the second photoresist spacer layer to form a mirror and a mirror via, wherein the mirror metal contacts the hinge metal layer at the bottom of the mirror via; as well as Oxygen ashing is used to remove the first photoresist spacer layer, the second photoresist spacer layer, and the remainder of the cover layer to release the hinge and the mirror.
2. The method according to claim 1, wherein the hinge through-hole forms a free-standing support for the hinge, and the mirror through-hole forms a free-standing support for the mirror.
3. The method according to claim 1, wherein the covering layer is conformal.
4. The method of claim 1, wherein the overlay is sacrificial.
5. The method of claim 1, wherein the thickness of the covering layer is from 100 angstroms to 500 angstroms.
6. The method of claim 1, wherein the developer is used for i-line lithography.
7. The method of claim 1, wherein the covering layer comprises a dielectric.
8. The method of claim 1, wherein the capping layer comprises a carbon material deposited by chemical vapor deposition.
9. The method of claim 1, wherein the covering layer comprises a silicon oxynitride material.
10. The method of claim 1, wherein the cover layer is removed using an O2 and CF4 ashing process.
11. A method for manufacturing a digital micromirror device, the method comprising: A first photoresist spacer layer is deposited on the substrate, the first photoresist spacer layer comprising a photoresist; The hinge through-hole openings are patterned in the first photoresist spacer layer; A hinge metal layer is deposited above the first photoresist spacer layer and in the hinge through-hole opening to form a hinge and a hinge through-hole; A capping layer is deposited over the hinge metal layer, wherein the capping layer comprises carbon material deposited by chemical vapor deposition; A second photoresist spacer layer is deposited over the capping layer, the second photoresist spacer layer comprising a photoresist; A mirror aperture opening is patterned in the second photoresist spacer layer to expose the cover layer, wherein the patterning step uses a developer, and wherein the cover layer shields the hinge metal layer at the bottom of the mirror aperture opening to prevent it from reacting with the developer and from forming residues on the second photoresist spacer layer. After the patterning step, the cover layer in the through-hole opening is removed using a plasma etching process to expose the hinge metal layer in the through-hole opening; A mirror metal is deposited in the mirror via opening and above the second photoresist spacer layer to form a mirror and a mirror via, wherein the mirror metal contacts the hinge metal layer at the bottom of the mirror via. as well as Oxygen ashing is used to remove the first photoresist spacer layer, the second photoresist spacer layer, and the remainder of the cover layer to release the hinge and the mirror.
12. The method of claim 11, wherein the hinge through-hole forms a freestanding support for the hinge, and the mirror through-hole forms a freestanding support for the mirror.
13. The method of claim 11, wherein the covering layer is conformal.
14. The method of claim 11, wherein the overlay is sacrificial.
15. The method of claim 11, wherein the thickness of the covering layer is from 100 angstroms to 500 angstroms.
16. The method of claim 11, wherein the developer is used for i-line lithography.
17. The method of claim 11, wherein the cover layer is removed using an O2 and CF4 ashing process.