XNOR operation device based on 6T-SRAM and method thereof

Abstract

This invention discloses an XNOR operation unit and method based on 6T-SRAM. The input terminal of transmission gate TG0 is connected to bit line BL, and the input terminal of transmission gate TG3 is connected to bit line BLB. The high-level enable terminals of both transmission gate TG0 and TG3 are connected to read word line RWL, and the low-level enable terminals of both TG0 and TG3 are connected to read word line BLB. The output terminal of transmission gate TG0 is connected to transmission gate TG1, and the output terminal of transmission gate TG3 is connected to the input terminal of transmission gate TG2. The high-level enable terminal of transmission gate TG1 is connected to weighted storage node Q, and the low-level enable terminal of transmission gate TG1 is connected to weighted non-storage node QB. The high-level enable terminal of transmission gate TG2 is connected to weighted non-storage node QB, and the low-level enable terminal of transmission gate TG2 is connected to weighted storage node Q. The output terminals of transmission gates TG1 and TG2 are shorted to read bit line RBL. This invention reduces the area and power consumption of the input signal driving circuit, effectively saving circuit area in circuit layout and routing.

Description

Technical Field

[0001] This invention relates to an XNOR computing device and method based on 6T-SRAM, belonging to the field of in-memory computing design technology. Background Technology

[0002] In current in-memory computing designs, the "0" and "1" values ​​of input data require different driving circuits, which increases the burden on the input signal driving circuit, resulting in a larger area and higher energy consumption for the input signal driving circuit. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to overcome the defects of the prior art and provide an XNOR computing device and method based on 6T-SRAM, which reduces the area and energy consumption of the input signal driving circuit and fundamentally reduces the number of input signals.

[0004] To achieve the above objectives, the present invention provides an XNOR computing device based on 6T-SRAM, comprising a 6T-SRAM cell and an XNOR computing unit, wherein the 6T-SRAM cell is electrically connected to the XNOR computing unit; The XNOR operation unit includes transmission gate TG0 and transmission gate TG3. The input of transmission gate TG0 is connected to bit line BL, and the input of transmission gate TG3 is connected to bit line NOT BLB. The high-level enable terminals of transmission gate TG0 and transmission gate TG3 are both connected to read word line RWL, and the low-level enable terminals of transmission gate TG0 and transmission gate TG3 are both connected to read word line NOT RWLB.

[0005] Preferably, the XNOR operation unit includes transmission gate TG1 and transmission gate TG2, the output of transmission gate TG0 is connected to transmission gate TG1, and the output of transmission gate TG3 is connected to the input of transmission gate TG2. The high-level enable terminal of transmission gate TG1 is connected to the weighted storage node Q, and the low-level enable terminal of transmission gate TG1 is connected to the weighted non-storage node QB. The high-level enable terminal of transmission gate TG2 is connected to the weighted non-storage node QB, and the low-level enable terminal of transmission gate TG2 is connected to the weighted storage node Q. The output terminals of transmission gates TG1 and TG2 are shorted to the read bit line RBL.

[0006] Preferably, the 6T-SRAM cell includes NMOS transistor N1, NMOS transistor N2, PMOS transistor P1, and PMOS transistor P2. The source of PMOS transistor P1 and the source of PMOS transistor P2 are connected to the power supply voltage VDD. The gate of PMOS transistor P1, the gate of NMOS transistor N1, the drain of PMOS transistor P2, and the drain of NMOS transistor N2 are interconnected. The gate of PMOS transistor P2, the gate of NMOS transistor N2, the drain of PMOS transistor P1, and the drain of NMOS transistor N1 are interconnected. The source of NMOS transistor N1 and the source of NMOS transistor N2 are connected to the ground potential VSS.

[0007] Preferably, the 6T-SRAM cell includes NMOS transistor N3 and NMOS transistor N4. The source of NMOS transistor N3 is connected to the weighted storage node Q, and the source of NMOS transistor N4 is connected to the weighted non-storage node QB. The gates of both NMOS transistor N3 and NMOS transistor N4 are connected to the word line WL. The drain of NMOS transistor N3 is connected to the bit line BL, and the drain of NMOS transistor N4 is connected to the non-BLB bit line.

[0008] Priority is that when the read word line RWL is high and the read word line other than RWLB is low, transmission gates TG0 and TG3 are turned on. When the read word line RWL is low and the read word line other than RWLB is high, transmission gates TG0 and TG3 are turned off.

[0009] An XNOR operation method based on 6T-SRAM, utilizing the XNOR operation device based on 6T-SRAM described above, performs the following steps: In the first step, initially, transmission gates TG0, TG1, TG2, and TG3 are all in the off state; Bit line BL is enabled according to the weight value, and the potential of non-BLB bit lines is opposite to the potential of bit line BL. The second step is to enable the word line WL, which turns on NMOS transistors N3 and NMOS transistor N4. If the bit line BL is low and the non-BLB bit line is high, the weighted storage node Q discharges to the bit line BL until the weighted storage node Q is low, and the non-BLB bit line charges the weighted non-storage node QB until the weighted non-storage node QB is high. If bit line BL is high and non-BLB bit line is low, then bit line BL charges the weighted storage node Q until Q is high, and storage node QB discharges to non-BLB bit line until QB is low. Third, bit line BL is enabled according to the input signal; the potential of non-BLB bit line is opposite to that of bit line BL. If the input signal is "1", then bit line BL is enabled to be high and non-BLB bit line is enabled to be low; if the input signal is "0", then bit line BL is enabled to be low and non-BLB bit line is enabled to be high. Step 4: Enable read word line RWL and read word line not RWLB, turn on transmission gate TG0 and transmission gate TG3, turn on or off transmission gate TG1 and transmission gate TG2 according to their weights, and output the operation result of the XNOR operation unit at read bit line RBL.

[0010] Prioritize enabling bit line BL according to the weight value. If a weight "0" needs to be written, precharge the potential of bit line BL to low level and precharge the potential of bit line other than BLB to high level. If a weight of "1" needs to be written, the bit line BL will be precharged to a high level, and the bit lines other than BLB will be precharged to a low level.

[0011] Prioritize the second step by enabling word line WL to turn on NMOS transistors N3 and NMOS transistor N4. If bit line BL is low and non-BLB bit line is high, then the weighted storage node Q discharges to bit line BL. If the potential of weighted storage node Q was originally low, then the low level of weighted storage node Q is maintained. If the potential of weighted non-storage node QB was originally high, then the high level of weighted non-storage node QB is maintained. If bit line BL is high and bit line non-BLB is low, then bit line BL charges the weighted storage node Q until the weighted storage node Q is high. If the potential of the weighted storage node Q was originally high, then the high level of the weighted storage node Q remains unchanged. If the potential of the weighted non-storage node QB was originally low, then the low level of the weighted non-storage node QB remains unchanged.

[0012] An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of any of the methods described above.

[0013] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the methods described above.

[0014] The beneficial effects achieved by this invention are as follows: This invention utilizes a 6T-SRAM cell and an XNOR operation unit. The XNOR operation unit consists of only 4 transmission gates, so the structure is relatively simple and the cost is low. It reduces the area and power consumption of the input signal driving circuit, fundamentally reducing the number of input signals. The use of the XNOR operation unit makes this invention symmetrical, which can effectively save circuit area in circuit layout and wiring. Attached Figure Description

[0015] Figure 1 This is the circuit diagram of the present invention. Detailed Implementation

[0016] The following embodiments are only used to illustrate the technical solutions of the present invention more clearly, and should not be used to limit the scope of protection of the present invention.

[0017] The XNOR computing device based on 6T-SRAM includes a 6T-SRAM cell and an XNOR computing unit; The XNOR operation unit comprises four transmission gates. The input signal is transmitted through bit line BL and bit line not connected to BLB via transmission gates TG0 and TG3, respectively, to the input terminals of transmission gates TG1 and TG2. Transmission gates TG1 and TG2 are controlled to be turned on or off by weighted storage node Q and weighted non-storage node QB, thereby realizing the XNOR operation. This design scheme can achieve the XNOR operation with a smaller number of input signals; the actual input signal is only one signal input to bit line BL. The signal input to bit line not connected to BLB can be obtained by inverting the signal input to bit line BL. Furthermore, the designed circuit structure is simple and symmetrical.

[0018] The operation of this XNOR unit is completed in the following four steps (initially all four transmission gates are in the off state): Step 1: Enable bit line BL according to the weight value. The potential of non-BLB bit lines is opposite to that of bit line BL. If a weight "0" needs to be written, precharge the potential of bit line BL to low level and the potential of non-BLB bit lines to high level. If a weight of "1" needs to be written, the bit line BL will be precharged to a high level, and the bit lines other than BLB will be precharged to a low level. Step 2: Enable word line WL to turn on NMOS transistors N3 and NMOS transistor N4, and write the weight. If bit line BL and bit line non-BLB are low and high respectively, the weight storage node Q discharges to bit line BL until the weight storage node Q is low (if the weight storage node Q was originally low, then the weight storage node Q remains low). Bit line non-BLB charges the weight non-storage node QB until the weight non-storage node QB is high (if the weight non-storage node QB was originally high, then the weight non-storage node QB remains high). If bit line BL and bit line non-BLB are at high and low levels respectively, then bit line BL charges the weighted storage node Q until the weighted storage node Q is at a high level (if the potential of the weighted storage node Q is already at a high level, then the high level of the weighted storage node Q remains unchanged), and storage node QB discharges to bit line non-BLB until the weighted non-storage node QB is at a low level (if the potential of the weighted non-storage node QB is already at a low level, then the low level of the weighted non-storage node QB remains unchanged).

[0019] Step 3: Enable bit line BL according to the input signal. The potential of bit line BL is opposite to that of bit line BL. If the input signal is "1", then bit line BL is high and bit line BL is low; if the input signal is "0", then bit line BL is low and bit line BL is high. Step 4: Enable read word line RWL and read word line non-RWLB, turn on transmission gate TG0 and transmission gate TG3, turn on or off transmission gate TG1 and transmission gate TG2 according to weight, and output the operation result of XNOR operation unit at read bit line RBL. The XNOR operation logic table based on this design is shown below: Table 1 XNOR Operation Logic Table

[0020] Because the input data is represented by the bit line BL, and the values ​​of non-BLB bits are always opposite to the values ​​of the bit line BL, and the weights are represented by the weight storage node Q, and the values ​​of non-weight storage nodes QB are always opposite to the values ​​stored in the weight storage node Q (opposite values ​​mean one is high level "1" and the other is low level "0"), the XNOR operation logic table can be simplified as follows: Table 2 Simplified logic table for XNOR operation

[0021] The simplified logic table using XNOR operation clearly shows that the input data and weights underwent XNOR operation, yielding the result.

[0022] Figure 1The 6T-SRAM cell circuit includes NMOS transistors N1, NMOS transistor N2, NMOS transistor N3, NMOS transistor N4, PMOS transistor P1, and PMOS transistor P2. The sources of PMOS transistors P1 and P2 are connected to the power supply voltage VDD. The gates of PMOS transistors P1, NMOS transistor N1, PMOS transistor P2, and NMOS transistor N2 are interconnected. The gates of PMOS transistors P2, NMOS transistor N2, PMOS transistor P1, and NMOS transistor N1 are also interconnected. The source of NMOS transistor N1 and the source of NMOS transistor N2 are connected to ground potential VSS; The source of NMOS transistor N3 is connected to the weighted storage node Q, the source of NMOS transistor N4 is connected to the weighted non-storage node QB, the gates of both NMOS transistor N3 and NMOS transistor N4 are connected to the word line WL, the drain of NMOS transistor N3 is connected to the bit line BL, and the drain of NMOS transistor N4 is connected to the non-BLB bit line.

[0023] The XNOR operation unit includes transmission gates TG0, TG1, TG2, and TG3. Each transmission gate is controlled by two control signals to be turned on or off: one control signal is enabled at a high level, and the other control signal is enabled at a low level. The input of transmission gate TG0 is connected to bit line BL, and the input of transmission gate TG3 is connected to bit line NOT BLB. The output of transmission gate TG0 is connected to transmission gate TG1, and the output of transmission gate TG3 is connected to the input of transmission gate TG2. The high-level enable terminals of both transmission gate TG0 and TG3 are connected to the read word line RWL, and the low-level enable terminals of both transmission gate TG0 and TG3 are connected to the read word line NOT BRLB. When the read word line RWL is high and the read word line other than RWLB is low, transmission gates TG0 and TG3 are turned on. When the read word line RWL is low and the read word line other than RWLB is high, transmission gates TG0 and TG3 are turned off. The high-level enable terminal of transmission gate TG1 is connected to the weighted storage node Q, and the low-level enable terminal of transmission gate TG1 is connected to the weighted non-storage node QB. The high-level enable terminal of transmission gate TG2 is connected to the weighted non-storage node QB, and the low-level enable terminal of transmission gate TG2 is connected to the weighted storage node Q. The output terminals of transmission gates TG1 and TG2 are shorted to the read bit line RBL.

[0024] An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of any of the methods described above.

[0025] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the methods described above.

[0026] The meanings of the relevant terms in this invention are as follows: WL (Word Line): The control signal for writing weights; BL (Bit Line): Bit line, which can be reused as a signal path when writing weights; BLB (Bit Line Bar): Bit line inversion, which can be reused as a signal path when writing weighted inversion; RBL (Read Bit Line): The XNOR calculation result is output through the RBL. RWL (Read Word Line): The read word line is the enable signal that controls the switching states of transmission gates TG0 and TG3. RWLB (Read Word Line Bar): Read word line inverted, enable signal controlling the switching state of transmission gates TG0 and TG3; Q: Weighted storage node; QB: Weighted non-storage node; VDD: Power supply voltage; VSS: Ground potential; P1, P2: PMOS transistors; N1, N2, N3, N4: NMOS transistors; TG0, TG1, TG2, TG3: Transmission gates.

[0027] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0028] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0029] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0030] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An XNOR computing device based on 6T-SRAM, characterized in that, It includes a 6T-SRAM cell and an XNOR operation unit, with the 6T-SRAM cell electrically connected to the XNOR operation unit; The XNOR operation unit includes transmission gate TG0 and transmission gate TG3. The input of transmission gate TG0 is connected to bit line BL, and the input of transmission gate TG3 is connected to bit line NOB. The high-level enable terminals of transmission gate TG0 and transmission gate TG3 are both connected to read word line RWL, and the low-level enable terminals of transmission gate TG0 and transmission gate TG3 are both connected to read word line NOB. The XNOR operation unit includes transmission gate TG1 and transmission gate TG2. The output of transmission gate TG0 is connected to transmission gate TG1, and the output of transmission gate TG3 is connected to the input of transmission gate TG2. The high-level enable terminal of transmission gate TG1 is connected to the weighted storage node Q, and the low-level enable terminal of transmission gate TG1 is connected to the weighted non-storage node QB. The high-level enable terminal of transmission gate TG2 is connected to the weighted non-storage node QB, and the low-level enable terminal of transmission gate TG2 is connected to the weighted storage node Q. The output terminals of transmission gate TG1 and TG2 are shorted to the read bit line RBL. When the read word line RWL is high and the read word line other than RWLB is low, transmission gates TG0 and TG3 are turned on. When the read word line RWL is low and the read word line other than RWLB is high, transmission gates TG0 and TG3 are turned off.

2. The XNOR computing device based on 6T-SRAM according to claim 1, characterized in that, The 6T-SRAM cell includes NMOS transistor N1, NMOS transistor N2, PMOS transistor P1, and PMOS transistor P2. The source of PMOS transistor P1 and the source of PMOS transistor P2 are connected to the power supply voltage VDD. The gate of PMOS transistor P1, the gate of NMOS transistor N1, the drain of PMOS transistor P2, and the drain of NMOS transistor N2 are interconnected. The gate of PMOS transistor P2, the gate of NMOS transistor N2, the drain of PMOS transistor P1, and the drain of NMOS transistor N1 are interconnected. The source of NMOS transistor N1 and the source of NMOS transistor N2 are connected to the ground potential VSS.

3. The XNOR computing device based on 6T-SRAM according to claim 2, characterized in that, The 6T-SRAM cell includes NMOS transistor N3 and NMOS transistor N4. The source of NMOS transistor N3 is connected to the weighted storage node Q, and the source of NMOS transistor N4 is connected to the weighted non-storage node QB. The gates of both NMOS transistor N3 and NMOS transistor N4 are connected to the word line WL. The drain of NMOS transistor N3 is connected to the bit line BL, and the drain of NMOS transistor N4 is connected to the non-BLB bit line.

4. An XNOR operation method based on 6T-SRAM, characterized in that, Using the XNOR computing device based on 6T-SRAM as described in any one of claims 1-3, perform the following steps: In the first step, initially, transmission gates TG0, TG1, TG2, and TG3 are all in the off state; according to the weight value, bit line BL is enabled, and the potential of bit line BL other than BLB is opposite to the potential of bit line BL. The second step is to enable the word line WL, which turns on NMOS transistors N3 and NMOS transistor N4. If the bit line BL is low and the non-BLB bit line is high, the weighted storage node Q discharges to the bit line BL until the weighted storage node Q is low, and the non-BLB bit line charges the weighted non-storage node QB until the weighted non-storage node QB is high. If bit line BL is high and non-BLB is low, then bit line BL charges the weighted storage node Q until Q is high, and storage node QB discharges to non-BLB until QB is low. Third, bit line BL is enabled according to the input signal; the potential of non-BLB is opposite to that of bit line BL. If the input signal is "1", then bit line BL is enabled to be high and non-BLB is enabled to be low; if the input signal is "0", then bit line BL is enabled to be low and non-BLB is enabled to be high. Step 4: Enable read word line RWL and read word line not RWLB, turn on transmission gate TG0 and transmission gate TG3, turn on or off transmission gate TG1 and transmission gate TG2 according to their weights, and output the operation result of the XNOR operation unit at read bit line RBL.

5. The XNOR operation method based on 6T-SRAM according to claim 4, characterized in that, Enable bit line BL according to the weight value. If weight "0" needs to be written, the potential of bit line BL will be precharged to low level, and the potential of bit line other than BLB will be precharged to high level. If a weight of "1" needs to be written, the bit line BL will be precharged to a high level, and the bit lines other than BLB will be precharged to a low level.

6. The XNOR operation method based on 6T-SRAM according to claim 4, characterized in that, In the second step, the word line WL is enabled, turning on NMOS transistors N3 and NMOS transistor N4. If the bit line BL is low and the non-BLB bit line is high, the weighted storage node Q discharges to the bit line BL. If the potential of the weighted storage node Q is already low, the low level of the weighted storage node Q is maintained. If the potential of the weighted non-storage node QB is already high, the high level of the weighted non-storage node QB is maintained. If bit line BL is high and bit line non-BLB is low, then bit line BL charges the weighted storage node Q until the weighted storage node Q is high. If the potential of the weighted storage node Q was originally high, then the high level of the weighted storage node Q remains unchanged. If the potential of the weighted non-storage node QB was originally low, then the low level of the weighted non-storage node QB remains unchanged.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method according to any one of claims 4 to 6.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the steps of the method according to any one of claims 4 to 6.

Images