Task exit handling methods, processor system, and storage media

Abstract

A processing method, a processor system and a storage medium for exiting tasks. The processing method is used for an object processor selected from a plurality of processors included in the processor system, and comprises: providing an exit task queue, wherein the exit task queue comprises a plurality of task units, each of which is used for storing an exit task of the plurality of processors; providing a state marker array, wherein the state marker array comprises a plurality of state elements, the plurality of state elements correspond to the plurality of task units one by one, and each state element is used for marking a state of the exit task in the corresponding task unit; recording the state of the corresponding exit task through the state marker array, and processing the corresponding exit task through the exit task queue. The processing method solves the synchronization problem among the plurality of processors when the exit task is executed.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a method for processing task exits in a processor system, a processor system, and a storage medium. Background Technology

[0002] With the development of technology, the requirements for equipment are becoming increasingly demanding, computing power is increasing, and the amount of data being processed is growing larger. Relying solely on a traditional central processing unit (CPU) to complete all calculations is no longer sufficient, necessitating the addition of other processors to assist the CPU in handling tasks. The most common non-CPU processors include graphics processing units (GPUs). GPUs primarily handle graphics display-related calculations, but later developments led to the use of GPUs for general-purpose computing tasks, resulting in general-purpose graphics processing units (GPGPUs).

[0003] In GPGPUs, a large number of general-purpose computing tasks are processed simultaneously, including various vector operations. With the further increase in the amount of computing tasks and the slowing of Moore's Law, single-die chips are increasingly unable to meet the actual demands of computing tasks. At the same time, the silicon area, yield, and power consumption of single-die chips are facing increasing challenges, leading to the emergence of multi-die interconnect systems (SoCs), which provide new ideas and solutions to meet the growing demands of computing tasks. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a method for processing exit tasks, for an object processor selected from a plurality of processors in a processor system. The method includes: providing an exit task queue, wherein the exit task queue includes a plurality of task units, each task unit being used to store exit tasks of the plurality of processors; providing a status tag array, wherein the status tag array includes a plurality of status elements, the plurality of status elements corresponding one-to-one with the plurality of task units, and each status element being used to mark the status of the exit task in the corresponding task unit; recording the status of the corresponding exit task through the status tag array, and processing the corresponding exit task through the exit task queue.

[0005] At least one embodiment of this disclosure provides a processor system including multiple processors and a first module, a second module, and a third module. The multiple processors include object processors; the first module is configured to provide an exit task queue, wherein the exit task queue includes multiple task units, each task unit storing exit tasks from the multiple processors; the second module is configured to provide a status tag array, wherein the status tag array includes multiple status elements, each status element corresponding one-to-one with the multiple task units, and each status element indicating the status of the exit task in the corresponding task unit; the third module is configured so that the object processors record the status of the corresponding exit tasks through the status tag array and process the corresponding exit tasks through the exit task queue.

[0006] At least one embodiment of this disclosure also provides a processor system including a plurality of processors and a memory. The plurality of processors includes an object processor; executable instructions are stored in the memory; when executed by the object processor, the executable instructions implement the task exit processing method of any embodiment of this disclosure as described above.

[0007] Some embodiments of this disclosure also provide a non-transitory readable storage medium, wherein computer-executable instructions are stored on the non-transitory readable storage medium, wherein when the computer-executable instructions are executed by a processor, they implement the task exit processing method described in any embodiment of this disclosure as above. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0009] Figure 1 A schematic diagram of a data processing device for parallel computing is shown.

[0010] Figure 2 A schematic diagram is shown of a processor system and a method for exiting a task provided according to at least one embodiment of the present disclosure.

[0011] Figure 3 A schematic diagram is shown of a processor system and a method for exiting a task provided according to at least one embodiment of the present disclosure.

[0012] Figure 4 A flowchart of an exemplary write operation according to an embodiment of the present disclosure is shown.

[0013] Figure 5 A flowchart of an exemplary read operation according to an embodiment of the present disclosure is shown.

[0014] Figure 6 A schematic diagram of an electronic device provided for at least one embodiment of this disclosure. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0016] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0017] Multiprocessor architectures can be implemented in various ways, such as centralized shared memory systems and distributed memory systems. Figure 1 This is a schematic diagram of a centralized shared memory architecture. (Example) Figure 1 As shown, in this multiprocessor system, processors core0, core1, core2, and core3 share a cache and have their own dedicated caches, sharing the same main memory and input / output (I / O). For example, the dedicated cache for each processing core may include a Level 1 cache, etc. Processors core0, core1, core2, and core3 can be CPUs, GPUs, or coprocessors such as ISPs (Image Signal Processors), TPUs (Tensor Processors), or other types of coprocessors, and communicate with main memory (e.g., RAM), I / O systems, etc., via the system bus, thereby sharing main memory and implementing the required operations and functions.

[0018] In a System-on-a-Chip (SoC), which consists of multiple dies, multiple processors (typically one processor per die) need to perform a series of exit tasks during the exit phase after completing a series of operations / tasks (e.g., initializing the processor, initializing software data structures, executing computational tasks, etc.). These tasks include, but are not limited to, flushing caches, reporting interrupts, and updating status registers and memory. The efficiency of these exit tasks has a crucial impact on the overall system performance. Each processor in the SoC must execute an exit task to release hardware resources and report its completion status. However, currently, each processor in the SoC completes its exit tasks independently. This approach is not only inefficient but also prone to operational conflicts and resource contention due to the lack of synchronization mechanisms between the multiple processors, leading to functional errors.

[0019] To address the aforementioned issues, embodiments of this disclosure propose a method for processing exit tasks in a processor system (e.g., a System-on-a-Chip) that includes multiple processors. This method merges the exit tasks of these processors, resolves the synchronization problem between multiple processors when executing exit tasks, optimizes the execution efficiency of exit tasks while ensuring correct functionality, and thereby improves the performance of the processor system.

[0020] At least one embodiment of this disclosure provides a processor system and a method for processing exit tasks of the processor system. The method is used for an object processor selected from a plurality of processors included in the processor system, and includes the following steps: providing an exit task queue, wherein the exit task queue includes a plurality of task units, each task unit being used to store exit tasks of the plurality of processors; providing a status tag array, wherein the status tag array includes a plurality of status elements, the plurality of status elements corresponding one-to-one with the plurality of task units, and each status element being used to mark the status of the exit task in the corresponding task unit; recording the status of the corresponding exit task through the status tag array and processing the corresponding exit task through the exit task queue.

[0021] Figure 2 A schematic diagram is shown illustrating a processor system and a method for exiting a task according to at least one embodiment of the present disclosure. The processor system includes multiple (e.g., two or more) processors and system memory 110. The multiple processors include processor 101 and processor 102, and may also include other processors not shown. These processors (including processors 101 and 102) can be CPUs, GPUs, ISPs, TPUs, etc. Processors 101 and 102 can be of the same type or different types. The multiple processors are packaged in the same chip, implementing a multiple chip module (MCM), constituting an on-chip interconnect system (e.g., a System-on-a-Chip Module) including multiple dies.

[0022] like Figure 2 As shown, in this method for handling exit tasks, firstly, an exit task queue 111 is provided, which includes multiple task units (each square in the figure represents a task unit). Each task unit is used to store exit tasks from multiple processors. Secondly, a status flag array 112 is provided, which includes multiple status elements (each square in the figure represents a status element). The multiple status elements of the status flag array 112 correspond one-to-one with the multiple task units of the exit task queue 111, and each status element is used to mark the status of the exit task in the corresponding task unit. Then, at least one (e.g., any one) of the multiple processors can record the status of the corresponding exit task through the status flag array and process the corresponding exit task through the exit task queue.

[0023] In the following description, "object processor" is used to refer to the processor currently being targeted. An object processor can be any of a number of processors rather than being limited to a particular processor.

[0024] like Figure 2 As shown, the exit task queue 111 includes task 1 and task 2, while the remaining task units are empty; correspondingly, the status flag array 112 includes flag 1 and flag 2 corresponding to task 1 and task 2 respectively, while the remaining status elements correspond to empty task units.

[0025] The exit task queue 111 can be an array or a linked list, for example, a first-in-first-out (FIFO) queue. Each task unit stores the exit tasks that the processor needs to process, including but not limited to tasks such as flushing the cache, reporting interrupts, and updating the status register. The status elements in the status flag array 112 can take values ​​of 0 or 1, where 0 indicates that the corresponding task unit is empty, and 1 indicates that an exit task has been written into the corresponding task unit; or, the status elements can also take values ​​of 0 / 1 / 2 / ..., where 0 indicates that the corresponding task unit is empty, 1 indicates that an exit task has been written into the corresponding task unit and that the exit task is in progress, 2 indicates that an exit task has been written into the corresponding task unit and that the exit task has been completed, and so on.

[0026] In at least one embodiment of this disclosure, even for the same task, processor 101 and processor 102 can each execute a portion of the task. For example, if the task is matrix operation (such as matrix addition), processor 101 executes the calculation corresponding to the left half of the matrix, and processor 102 executes the calculation corresponding to the right half of the matrix. After processors 101 and 102 have completed their respective portions, they need to notify the system that they have completed their parts of the task. Only after all processors have completed their parts will an interrupt be reported, the task exit operation be performed, and subsequent processing steps be initiated via the interrupt system to combine the parts completed by each processor and output the result.

[0027] The embodiments disclosed above avoid the need to assign a primary responsible processor (master processor) to each exit task, as this approach can be inefficient. The embodiments of this disclosure provide a masterless architecture for executing exit tasks: the processor that completes its own task first creates the exit task in the exit task queue and marks its status in the status flag array, thus implicitly completing the task and can continue executing the next task; the processor that completes its task last will actually execute the operations specified by the exit task, such as reporting interrupts, flushing caches, and modifying memory data structures.

[0028] exist Figure 2 In this embodiment, an exit task queue 111 and a status flag array 112 are provided in system memory 110. Alternatively, either the exit task queue or the status flag array can be provided in a shared cache, or both can be provided in the shared cache. Embodiments of this disclosure are not limited to the above methods, as long as the exit task queue and the status flag array can be accessed and processed by the object processor.

[0029] For example, in at least one example, the status of the corresponding exit task is recorded using a status flag array, and the corresponding exit task is processed using an exit task queue, including writing the target exit task to the exit task queue and reading the target exit task from the exit task queue. Here, "target exit task" is used to refer to the exit task currently described, and it can be used to represent any possible exit task rather than being limited to a specific exit task.

[0030] For example, in at least one example, writing a target exit task to the exit task queue includes: locking a selected state element in a state flag array to operate on the selected state element; and writing the target exit task to the task unit corresponding to the selected state element in response to the selected state element indicating that the task unit corresponding to the selected state element has not been written.

[0031] For example, in at least one example, reading a target exit task from an exit task queue includes: locking a selected state element in a state flag array to operate on the selected state element; and processing the target exit task written in the task unit corresponding to the selected state element in response to the selected state element indicating that the task unit corresponding to the selected state element has not been processed.

[0032] By locking the selected state elements in the state flag array, conflicts (and resulting exceptions) can be avoided, for example, when two processors simultaneously operate on the task units corresponding to the selected state elements. If a processor finds that the selected state element is locked, it must wait for the selected state element to be unlocked before trying again, or it must change the selected state element (and thus change the corresponding task unit) depending on the task type.

[0033] For example, in at least one example, locking a selected state element of a state flag array involves performing an atomic operation on the selected state element. An atomic operation means that the operation will never be interrupted by any other task or event before it is completed, thus effectively avoiding conflicts.

[0034] Figure 3 A schematic diagram is shown of a processor system and a task exit processing method provided according to at least one embodiment of the present disclosure. This processor system and task exit processing method, in addition to being similar to... Figure 2 In addition to the common parts in the illustrated embodiments, each processor also includes a write pointer and a read pointer.

[0035] For example, in at least one example, writing the target exit task into the task unit corresponding to the selected state element includes: after writing the target exit task into the corresponding task unit, updating the write pointer to point to a task unit that is not occupied in the exit task queue.

[0036] For example, in at least one example, writing the target exit task into the task unit corresponding to the selected state element includes: in response to the selected state element indicating that the task unit corresponding to the selected state element has been previously written, skipping the write operation to update the write pointer to point to a task unit that is not occupied in the exit task queue.

[0037] For example, an unoccupied task unit can be the next unoccupied task unit in the exit task queue that the task unit pointed to before the write pointer was updated (i.e., all task units before this one were occupied), or it can be any unoccupied task unit in the exit task queue.

[0038] For example, in at least one example, processing the target exit task written in the task unit corresponding to the selected state element includes: after processing the target exit task written in the corresponding task unit, updating the read pointer to point to the task unit that has not been processed in the exit task queue.

[0039] For example, in at least one example, processing the target exit task written in the task unit corresponding to the selected state element includes: in response to the selected state element indicating that the task unit corresponding to the selected state element has been previously processed, skipping the read operation to update the read pointer to point to the task unit that has not been processed in the exit task queue.

[0040] For example, an unprocessed task unit can be the next unprocessed task unit in the task queue immediately following the task unit pointed to by the read pointer before it was updated (i.e., all task units before it were processed), or it can be any unprocessed task unit in the task queue.

[0041] Once an exit task recorded in any task unit has been processed, it can be set to "empty" to indicate that it is not occupied and can be used later. Both write and read operations always operate on the next unoccupied task unit and the next unprocessed task unit. This avoids empty bubbles in the exit task queue and thus prevents resource waste.

[0042] Similarly, when performing write or read operations via the write pointer or read pointer respectively, conflicts can be avoided by locking the state elements in the state array (e.g., through atomic operations).

[0043] Figure 4 A flowchart illustrating an exemplary write operation according to an embodiment of this disclosure is shown. Figure 4As shown, firstly, the object processor is in an idle state (step 400). When the object processor needs to create an exit task, that is, when there is a need to write to the exit task queue (step 401), according to the current write pointer in the object processor, the corresponding state element of the state flag array is selected to perform an atomic operation (step 402). The state of the corresponding task unit is determined from the corresponding state element, and the value of the corresponding state element is updated. If it is determined that the corresponding task unit in the exit task queue has been written (that is, the exit task has been created by another processor) and there is an unprocessed exit task (step 403), then only the write pointer is updated, for example, to point to the next unoccupied task unit (step 405), and then the write operation ends. If it is determined that the corresponding task unit in the exit task queue has not been written before and there is no unprocessed exit task (step 403), then the above exit task is written to the corresponding task unit, and then the write pointer is updated, for example, to point to the next unoccupied task unit (step 405), and then the write operation ends.

[0044] Figure 5 A flowchart illustrating an exemplary read operation according to an embodiment of this disclosure is shown. Figure 5 As shown, firstly, the object processor is in an idle state (step 500). When the object processor needs to read exit tasks from the exit task queue, that is, when there is a need to process exit tasks from the exit task queue (step 501), according to the current read pointer in the object processor, the corresponding state element of the state flag array is selected to perform an atomic operation (step 502). The state of the corresponding task unit is determined from the corresponding state element, and the value of the corresponding state element is updated. If it is determined that the corresponding task unit in the exit task queue has been processed (that is, the exit task has been processed by other processors) and there are no unprocessed exit tasks (step 503), then the read pointer is updated, for example, to point to the next unprocessed task unit (step 505), and then the read operation ends. If it is determined that the corresponding task unit in the exit task queue has not been processed before and there are unprocessed exit tasks (step 503), then the exit tasks in the corresponding task unit are processed and the exit tasks are executed. Then the read pointer is updated, for example, to point to the next unprocessed task unit (step 505), and then the read operation ends.

[0045] Embodiments of this disclosure provide a processor system including multiple processors and a first module, a second module, and a third module. The multiple processors include object processors; the first module is configured to provide an exit task queue, wherein the exit task queue includes multiple task units, each task unit storing exit tasks from the multiple processors; the second module is configured to provide a status tag array, wherein the status tag array includes multiple status elements, each status element corresponding one-to-one with the multiple task units, and each status element indicating the status of the exit task in the corresponding task unit; the third module is configured so that the object processors record the status of the corresponding exit tasks through the status tag array and process the corresponding exit tasks through the exit task queue.

[0046] This processor system implements the aforementioned exit task processing method through the first to third modules, merging exit tasks from multiple processors. This solves the synchronization problem between multiple processors when executing exit tasks, optimizing the execution efficiency of exit tasks while ensuring correct functionality, thereby improving the performance of electronic devices (such as computers) including this processor system.

[0047] Furthermore, in at least one example, the first module is also configured to provide an exit task queue in system memory, and the second module is also configured to provide an array of status flags in system memory.

[0048] Furthermore, in at least one example, the third module is also configured to: write the target exit task to the exit task queue and read the target exit task from the exit task queue.

[0049] Furthermore, in at least one example, the third module is also configured to: for writing a target exit task in the exit task queue, lock the selected state element in the state flag array to operate on the selected state element; in response to the selected state element indicating that the task unit corresponding to the selected state element has not been written, write the target exit task in the task unit corresponding to the selected state element.

[0050] Furthermore, in at least one example, the object processor includes a write pointer, and the third module is further configured to: after writing the target exit task in the task unit corresponding to the selected state element, update the write pointer to point to a task unit that is not occupied in the exit task queue.

[0051] Furthermore, in at least one example, the object processor includes a write pointer, and the third module is further configured to: for writing a target exit task in the task unit corresponding to the selected state element, in response to the selected state element indicating that the task unit corresponding to the selected state element has been previously written, skip the write operation to update the write pointer to point to a task unit that is not occupied in the exit task queue.

[0052] Furthermore, in at least one example, the third module is also configured to: for reading a target exit task in the exit task queue, lock the selected state element in the state flag array to operate on the selected state element, and in response to the selected state element indicating that the task unit corresponding to the selected state element has not been processed, process the target exit task written in the task unit corresponding to the selected state element.

[0053] Furthermore, in at least one example, the object processor includes a read pointer, and the third module is further configured to: process the target exit task written in the task unit corresponding to the selected state element, and after processing the target exit task written in the corresponding task unit, update the read pointer to point to the task unit that has not been processed in the exit task queue.

[0054] Furthermore, in at least one example, the object processor includes a read pointer, and the third module is further configured to: process the target exit task written to the task unit corresponding to the selected state element, and in response to the selected state element indicating that the task unit corresponding to the selected state element has been previously processed, skip the read operation to update the read pointer to point to the task unit that has not been processed in the exit task queue.

[0055] Furthermore, in at least one example, the third module is also configured to: for a selected state element of the locked state flag array, operate on the selected state element in an atomic manner.

[0056] Furthermore, in at least one example, the multiple processors include at least one of a central processing unit, a graphics processing unit, and a coprocessor. For example, the coprocessor can be an ISP, a TPU, etc.

[0057] For example, the various modules mentioned above can be implemented through software, hardware, firmware, or any combination thereof.

[0058] Some embodiments of this disclosure also provide a processor system including a plurality of processors and a memory. The plurality of processors includes an object processor; the memory stores executable instructions (e.g., one or more computer program modules); when executed by the object processor, the executable instructions implement the task exit processing method described in any embodiment of this disclosure as above.

[0059] Some embodiments of this disclosure also provide a non-transitory readable storage medium, wherein computer-executable instructions are stored on the non-transitory readable storage medium, wherein when the computer-executable instructions are executed by a processor, they implement the task exit processing method of any embodiment of this disclosure as described above.

[0060] For example, the aforementioned non-transiently readable storage medium is implemented as a memory, such as volatile memory and / or non-volatile memory. In the above embodiments, the memory can be volatile memory, for example, it may include random access memory (RAM) and / or cache, etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. The memory can also store various applications (code, instructions) and data, as well as various data used and / or generated by the applications.

[0061] Some embodiments of this disclosure also provide an electronic device that includes a processor system of any of the above embodiments or a processing method capable of executing any of the above embodiments.

[0062] Figure 6 This is a schematic diagram of an electronic device provided for at least one embodiment of the present disclosure. The electronic device in the embodiments of the present disclosure may include, but is not limited to, mobile terminals such as laptops, PDAs (personal digital assistants), and PADs (tablet computers), as well as fixed terminals such as desktop computers.

[0063] Figure 6 The illustrated electronic device 1000 is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein. For example, such as Figure 6 As shown, in some examples, electronic device 1000 includes a processor system according to at least one embodiment of the present disclosure. This processor system can perform various appropriate actions and processes based on a program stored in read-only memory (ROM) 1002 or a program loaded from storage device 1008 into random access memory (RAM) 1003, such as the computer program processing method of the present disclosure embodiments. Various programs and data required for the operation of the processor system are also stored in RAM 1003. Processor 1001, ROM 1002, and RAM 1003 are connected via bus 1004. Input / output (I / O) interface 1005 is also connected to bus 1004.

[0064] For example, the following components can be connected to I / O interface 1005: input devices 1006 including, for example, touch screens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 1007 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1008 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009, such as network interface cards like LAN cards and modems, etc. Communication device 1009 allows electronic device 1000 to communicate wirelessly or wiredly with other devices to exchange data and perform communication processing via networks such as the Internet. Drive 1010 is also connected to I / O interface 1005 as needed. Removable storage media 1011, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on drive 1010 as needed so that computer programs read from them can be installed into storage device 1008 as needed.

[0065] Although Figure 6 An electronic device 1000 including various devices is shown; however, it should be understood that implementation or inclusion of all shown devices is not required. More or fewer devices may be implemented or included alternatively.

[0066] For example, the electronic device 1000 may further include a peripheral interface (not shown in the figure). This peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 1009 can communicate wirelessly with a network and other devices, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0067] The processor system and corresponding exit task processing method of at least one embodiment of this disclosure realize the merging of exit tasks of an on-chip interconnect system including multiple bare dies, establish a synchronization mechanism between multiple processors, avoid functional errors caused by operation conflicts and resource preemption, and greatly improve the efficiency of exit task execution, save hardware and software resources, and significantly improve the overall performance of the MCM chip.

[0068] The following points should be noted regarding this disclosure:

[0069] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0070] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0071] The above are merely exemplary embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A method for handling task exit, used to select an object processor from a plurality of processors included in a processor system, the method comprising: An exit task queue is provided, wherein the exit task queue includes multiple task units, each task unit is used to store the exit tasks of the multiple processors, and each exit task is created by a processor that completes its own task first and executed by a processor that completes its own task later. A status marker array is provided, wherein the status marker array includes multiple status elements, each of the multiple status elements corresponds one-to-one with a multiple of the task units, and each status element is used to mark the exit status of the corresponding task unit. The status of the corresponding exit task is recorded through the status flag array, and the corresponding exit task is processed through the exit task queue.

2. The processing method according to claim 1, wherein, The processor system also includes system memory, wherein, The exit task queue is provided in the system memory, as is the status flag array.

3. The processing method according to claim 1, wherein, The status of the corresponding exit task is recorded using the status flag array, and the corresponding exit task is processed using the exit task queue, including: Write the target exit task into the exit task queue; Read the target exit task from the exit task queue.

4. The processing method according to claim 3, wherein, Writing the target exit task to the exit task queue includes: Lock the selected state element in the state flag array to operate on the selected state element; In response to the selected state element indicating that the task unit corresponding to the selected state element has not been written, the target exit task is written into the task unit corresponding to the selected state element.

5. The processing method according to claim 4, wherein, The object processor includes a write pointer. Writing the target exit task into the task unit corresponding to the selected state element includes: After writing the target exit task into the corresponding task unit, update the write pointer to point to an unoccupied task unit in the exit task queue.

6. The processing method according to claim 4, wherein, The object processor includes a write pointer. Writing the target exit task into the task unit corresponding to the selected state element includes: In response to the selected state element indicating that the task unit corresponding to the selected state element has been previously written, the write operation is skipped to update the write pointer to point to an unoccupied task unit in the exit task queue.

7. The processing method according to claim 3, wherein, Reading the target exit task from the exit task queue includes: Lock the selected state element in the state flag array to operate on the selected state element; In response to the selected state element indicating that the task unit corresponding to the selected state element has not been processed, the target exit task written in the task unit corresponding to the selected state element is processed.

8. The processing method according to claim 7, wherein, The object processor includes a read pointer. Processing the target exit task written in the task unit corresponding to the selected state element includes: After processing the target exit task written in the corresponding task unit, the read pointer is updated to point to the unprocessed task unit in the exit task queue.

9. The processing method according to claim 7, wherein, The object processor includes a read pointer. Processing the target exit task written in the task unit corresponding to the selected state element includes: In response to the selected state element indicating that the task unit corresponding to the selected state element has been previously processed, the read operation is skipped to update the read pointer to point to the task unit that has not been processed in the exit task queue.

10. The processing method according to claim 4 or 7, wherein, Locking a selected state element of the state flag array includes: The selected state element is operated on in an atomic manner.

11. A processor system, comprising: Multiple processors, wherein the multiple processors include an object processor; The first module is configured to provide an exit task queue, wherein the exit task queue includes multiple task units, each task unit is used to store the exit tasks of the multiple processors, and each exit task is created by the processor that completes its own task first and executed by the processor that completes its own task later. The second module is configured to provide a status marker array, wherein the status marker array includes multiple status elements, each of the multiple status elements corresponds one-to-one with a multiple of the task units, and each status element is used to mark the exit status of the corresponding task unit. The third module is configured so that the object processor records the status of the corresponding exit task through the status flag array, and processes the corresponding exit task through the exit task queue.

12. The processor system according to claim 11, wherein, The plurality of processors includes at least one of the following: a central processing unit, a graphics processing unit, and a coprocessor.

13. A processor system, comprising: Multiple processors, wherein the multiple processors include an object processor; A memory, wherein executable instructions are stored in the memory, and when executed by the plurality of processors, the executable instructions implement the following method: An exit task queue is provided, wherein the exit task queue includes multiple task units, each task unit is used to store the exit tasks of the multiple processors, and each exit task is created by a processor that completes its own task first and executed by a processor that completes its own task later. A status marker array is provided, wherein the status marker array includes multiple status elements, each of the multiple status elements corresponds one-to-one with a multiple of the task units, and each status element is used to mark the exit status of the corresponding task unit. The status of the corresponding exit task is recorded through the status flag array, and the corresponding exit task is processed through the exit task queue.

14. A non-transient storage medium, wherein, The non-transient storage medium stores executable instructions, which, when executed by a processor, implement the method described in any one of claims 1-10.

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