Data processing method and related apparatus

Abstract

Embodiments of the present application provide a data processing method and related device, and relate to the field of embedded systems. According to the data size and data type of to-be-processed data, it is determined whether a cache memory satisfies a preset data storage condition; the to-be-processed data includes external data and / or stored data stored in a large-capacity dynamic random access memory; if the cache memory satisfies the preset data storage condition, the to-be-processed data is stored in the cache memory, so that a CPU obtains the to-be-processed data from the cache memory and performs data processing on the to-be-processed data; if the cache memory does not satisfy the preset data storage condition, the to-be-processed data is stored in the large-capacity dynamic random access memory. Through the method, the efficiency of the CPU in obtaining data can be improved, and thus the performance of the embedded system is improved.

Description

Technical Field

[0001] This application relates to the field of embedded systems, and more specifically, to a data processing method and related apparatus. Background Technology

[0002] Currently in embedded systems, when the CPU (Central Processing Unit) interacts with external devices, it often needs to receive external data through a DMA (Direct Memory Access) controller and store the external data at a specified address in a large-capacity dynamic random access memory. The CPU then retrieves the external data from the large-capacity dynamic random access memory for processing.

[0003] However, as the amount of data exchanged between the CPU and external devices increases, this method leads to lower efficiency in CPU data acquisition, thus affecting the performance of the embedded system. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a data processing method and related apparatus to solve the problem of how to improve the efficiency of CPU data acquisition, thereby improving the performance of embedded systems.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0006] In a first aspect, this application provides a data processing method applied to a DMA controller in an embedded system. The embedded system further includes a CPU, a cache memory, and a large-capacity dynamic random access memory (DRAM). The DMA controller is connected to the CPU, the cache memory, and the DRAM via a bus. The method includes:

[0007] Based on the size and data type of the data to be processed, determine whether the cache memory meets the preset data storage conditions; the data to be processed includes external data and / or stored data in a large-capacity dynamic random access memory.

[0008] If the cache memory meets the preset data storage conditions, the data to be processed is stored in the cache memory so that the CPU can obtain the data to be processed from the cache memory and perform data processing on the data to be processed.

[0009] If the cache memory does not meet the preset data storage conditions, the data to be processed will be stored in the large-capacity dynamic random access memory.

[0010] In an optional implementation, multiple data channels are provided between the DMA controller and the large-capacity dynamic random access memory and the high-speed cache memory, wherein each data channel corresponds to a data type;

[0011] The high-speed cache memory has a contiguous storage space for each data channel according to a first preset capacity, and the large-capacity dynamic random access memory has a contiguous storage space for each data channel according to a second preset capacity.

[0012] The DMA controller has a corresponding channel register for each data channel, which is used to store read and write pointers; the read and write pointers are used to indicate the storage status of the storage space corresponding to the data to be processed.

[0013] In an optional implementation, the embedded system further includes an input interface module, and the DMA controller is electrically connected to the input interface module. The input interface module is used to acquire the external data. The read / write pointers include a cache memory write pointer, a processing completion write pointer, and a large-capacity dynamic random access memory write pointer. The data storage conditions include a first data storage condition.

[0014] The first data storage conditions include that the remaining capacity of the storage space corresponding to the external data in the cache memory is greater than or equal to the data size of the external data, and that the large-capacity dynamic random access memory does not store storage data corresponding to the data type of the external data.

[0015] The remaining capacity of the storage space corresponding to the external data in the cache memory is determined based on the total capacity of the storage space corresponding to the external data in the cache memory, the cache memory write pointer corresponding to the external data, and the processing completion write pointer; whether the large-capacity dynamic random access memory stores storage data corresponding to the data type of the external data is determined based on the cache memory write pointer corresponding to the external data and the large-capacity dynamic random access memory write pointer.

[0016] If the cache memory meets the preset data storage conditions, then storing the data to be processed in the cache memory includes:

[0017] If the cache memory meets the first data storage condition, the external data is stored in the corresponding storage space of the cache memory through the data channel corresponding to the external data.

[0018] Update the cache write pointer corresponding to the external data.

[0019] In an optional implementation, the step of storing the data to be processed in the large-capacity dynamic random access memory if the cache memory does not meet the preset data storage conditions includes:

[0020] If the high-speed cache does not meet the first data storage condition, the external data is stored in the corresponding storage space of the large-capacity dynamic random access memory through the data channel corresponding to the external data.

[0021] Update the write pointer of the large-capacity dynamic random access memory corresponding to the external data.

[0022] In an optional implementation, the data storage conditions include a second data storage condition, and the read / write pointers include a save-as-a-book read pointer and a cache memory write pointer;

[0023] The second data storage condition includes that the remaining capacity of the storage space corresponding to the stored data in the cache memory is greater than or equal to the data size of the stored data; wherein the stored data is determined according to the save-as-a-book pointer in each channel register;

[0024] If the cache memory meets the preset data storage conditions, then storing the data to be processed in the cache memory includes:

[0025] If the cache memory meets the second data storage condition, the stored data is retrieved from the large-capacity dynamic random access memory and stored in the corresponding storage space of the cache memory through the data channel corresponding to the stored data.

[0026] Update the save read pointer and the cache write pointer corresponding to the stored data.

[0027] In an optional implementation, the embedded system further includes an output interface module, the DMA controller is electrically connected to the output interface module, and the DMA controller is provided with a buffer; the read / write pointers include a CPU read pointer and a processing completion write pointer, and after storing the data to be processed in the cache memory, the method further includes:

[0028] Obtain the processing completion information sent by the CPU, and determine whether the processed data is forwarded data based on the processing completion information; wherein, the processed data is the data obtained by the CPU after processing the data to be processed;

[0029] If the processed data is forwarded data, then the CPU read pointer corresponding to the processed data is updated, and the processed data is obtained according to the storage location information in the processed information;

[0030] The processed data is stored in the buffer, and the processing completion write pointer corresponding to the processed data is updated.

[0031] The processed data in the buffer is sent to an external device through the output interface module;

[0032] If the processed data is non-forwarded data, then the CPU read pointer and the processing completion write pointer corresponding to the processed data are updated.

[0033] In an optional implementation, the method further includes:

[0034] The CPU sends spontaneous data information, and the CPU retrieves the spontaneous data based on the storage location information in the spontaneous data information; the spontaneous data is data spontaneously generated by the CPU.

[0035] The spontaneous data is stored in the buffer;

[0036] The spontaneous data in the buffer is sent to an external device through the output interface module.

[0037] In an optional implementation, a monitoring module is provided at the interface between the CPU and the bus, and the method further includes:

[0038] The system receives operation information sent by the monitoring module and determines the current operation status of the CPU based on the operation information.

[0039] Secondly, this application provides a data processing apparatus for use in a DMA controller within an embedded system. The embedded system further includes a CPU, a cache memory, and a large-capacity dynamic random access memory (DRAM). The DMA controller is connected to the CPU, the cache memory, and the DRAM via a bus. The apparatus includes:

[0040] The determination module is used to determine whether the high-speed cache memory meets the preset data storage conditions based on the data size and data type of the data to be processed; the data to be processed includes external data and / or stored data stored in a large-capacity dynamic random access memory;

[0041] The storage module is used to store the data to be processed in the cache memory if the cache memory meets the preset data storage conditions, so that the CPU can obtain the data to be processed from the cache memory and perform data processing on the data to be processed.

[0042] The storage module is further configured to store the data to be processed in the large-capacity dynamic random access memory if the high-speed cache memory does not meet the preset data storage conditions.

[0043] Thirdly, this application provides a DMA controller, including a processor and a memory, wherein the memory stores a computer program executable by the processor, and the processor can execute the computer program to implement the method described in any of the foregoing embodiments.

[0044] Fourthly, this application provides an embedded system including the DMA controller described in the foregoing embodiments.

[0045] Fifthly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described in any of the foregoing embodiments.

[0046] The data processing method and related apparatus provided in this application embodiment include external data and / or stored data in a large-capacity dynamic random access memory (DRAM). The DMA controller can determine whether the cache memory meets preset data storage conditions based on the size and data type of the data to be processed. If the conditions are met, the data to be processed is stored in the cache memory so that the CPU can retrieve the data from the cache memory and process it. If the conditions are not met, the data to be processed is stored in the DRAM. Through this method, the DMA can store external data and / or stored data in the DRAM in the cache memory when the cache memory meets the preset data storage conditions. The CPU can then directly retrieve the data to be processed from the cache memory for data processing without needing to retrieve external data from the DRAM, thus improving the efficiency of CPU data retrieval and thereby enhancing the performance of the embedded system.

[0047] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0048] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 A block diagram of an embedded system provided in an embodiment of this application is shown;

[0050] Figure 2 A block diagram of a DMA controller provided in an embodiment of this application is shown;

[0051] Figure 3 This paper illustrates a flowchart of a data processing method provided in an embodiment of this application.

[0052] Figure 4 A schematic diagram of initializing the read / write pointers is shown;

[0053] Figure 5 This diagram illustrates the read / write pointer operation after the DMA controller receives data.

[0054] Figure 6 This invention illustrates a functional block diagram of a data processing apparatus provided in an embodiment of this application;

[0055] Figure 7 Another functional block diagram of the data processing apparatus provided in the embodiments of this application is shown.

[0056] Icons: 10 - Embedded System; 20 - Bus; 100 - DMA Controller; 110 - Memory; 120 - Processor; 130 - Communication Module; 200 - CPU; 300 - Cache Memory; 400 - Large Capacity Dynamic Random Access Memory; 500 - Input Interface Module; 600 - Output Interface Module; 700 - Monitoring Module; 800 - Deterministic Module; 810 - Storage Module; 820 - Transmitting Module. Detailed Implementation

[0057] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can be arranged and designed in various different configurations.

[0058] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0059] It should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0060] Currently, as the amount of data exchanged between the CPU and external devices increases, the performance of embedded systems is experiencing a certain decline. Generally speaking, the main factors affecting the performance of embedded systems are the following three: first, the CPU's data processing capability; second, the DMA controller's data processing capability; and third, the CPU's performance in reading and writing to memory.

[0061] Regarding the factors mentioned above, the data processing capabilities of both the CPU and DMA are fundamentally dependent on the hardware architecture and operating speed. The data processing capability of the DMA controller is generally much higher than that of the CPU. Therefore, the performance bottleneck of an embedded system primarily depends on the CPU's data processing capability. Optimizing the CPU architecture requires a complete redesign of the CPU. Since redesigning a CPU is extremely time-consuming and labor-intensive, most integrated designs currently use existing CPUs. This means that the CPU architecture cannot be easily updated, making it difficult to improve the CPU's data processing capabilities. Understandably, in this case, optimizing the CPU's memory read / write performance, such as improving the CPU's data acquisition efficiency, can help optimize the performance of the embedded system.

[0062] In existing technologies, when a CPU interacts with external devices, it often needs to receive external data through a DMA controller and write the received data to a specified address in a large-capacity dynamic random access memory (DRAM). The CPU can then read and process the data from that address in the DRAM. However, because DRAMs themselves have long response times and low throughput, this method results in low efficiency for the CPU in acquiring data, leading to poor CPU read / write performance and consequently impacting the performance of the embedded system.

[0063] Based on this, embodiments of this application provide a data processing method that improves the CPU's read / write performance by increasing the efficiency of CPU data acquisition, thereby optimizing the performance of the embedded system. Specifically, Figure 1 For a block diagram of the embedded system 10 provided in the embodiments of this application, please refer to [link / reference]. Figure 1 The embedded system 10 includes a DMA controller 100, a CPU 200, a cache memory 300, and a large-capacity dynamic random access memory 400. The DMA controller 100 is connected to the CPU 200, the cache memory 300, and the large-capacity dynamic random access memory via a bus 20.

[0064] Optionally, the CPU can be an ARM Cortex-A55 small-core CPU. The A55 has one or two sets of bus access output interfaces with cache coherency, and an ACP interface that can partially implement cache write operations. The CPU can control the DMA controller's operation and check its status via the bus. The DMA controller can also perform cache write operations via the ACP interface. Simultaneously, a large-capacity dynamic random access memory (DRAM) is connected to the bus, allowing read and write operations between the CPU and the DMA controller.

[0065] Optionally, the cache memory 300 can be a cache or an on-chip SRAM (Static Random-Access Memory), depending on the CPU's functional limitations. For example, if the CPU does not support interfaces like ACP or does not support cache write operations, then on-chip SRAM can be selected as the cache memory 300.

[0066] Optionally, the large-capacity dynamic random access memory 400 may be a DDR (Double Data Rate) memory.

[0067] Optionally, the embedded system may also include an input interface module 500, an output interface module 600, and a monitoring module 700, wherein the input interface module 500 and the output interface module 600 are electrically connected to the DMA controller 100, and the monitoring module 700 is located at the interface between the CPU and the bus.

[0068] Optionally, Figure 2 For a block diagram of the DMA controller 100, please refer to [link / reference]. Figure 2 The DMA controller 100 includes a memory 110, a processor 120, and a communication module 130. The memory 110, processor 120, and communication module 130 are electrically connected directly or indirectly to enable data transmission or interaction. For example, these components can be electrically connected to each other via one or more communication buses or signal lines.

[0069] The memory 110 is used to store programs or data. The memory 110 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0070] The processor 120 is used to read / write data or programs stored in memory and to perform corresponding functions.

[0071] The communication module 130 is used to establish a communication connection between the server and other communication terminals via the network, and to send and receive data via the network.

[0072] It should be understood that, Figure 2 The structure shown is only a schematic diagram of the DMA controller 100. The DMA controller 100 may also include a ratio Figure 2 The more or fewer components shown, or having the same Figure 2 The different configurations shown. Figure 2 The components shown can be implemented using hardware, software, or a combination thereof.

[0073] The following is based on the above. Figure 1 The DMA controller 100 in this document is the execution entity. The data processing method provided in this application embodiment is illustrated with reference to the flowchart. Specifically, Figure 3Please refer to the flowchart of a data processing method provided in the embodiments of this application. Figure 3 The method includes:

[0074] Step S20: Determine whether the cache memory meets the preset data storage conditions based on the data size and data type of the data to be processed.

[0075] The data to be processed includes external data and / or stored data in a large-capacity dynamic random access memory;

[0076] Optionally, the external data is data sent by an external device, which can be sent to the DMA controller through the aforementioned input interface module; the stored data is data stored in a large-capacity dynamic random access memory that needs to be processed.

[0077] In this embodiment, the embedded system may simultaneously contain received external data and stored data in a large-capacity dynamic random access memory (DRAM), or it may contain only external data without stored data in the DRAM, or it may contain only stored data in the DRAM without external data.

[0078] Step S21: If the cache memory meets the preset data storage conditions, the data to be processed is stored in the cache memory so that the CPU can obtain the data to be processed from the cache memory and perform data processing on the data to be processed.

[0079] Step S22: If the cache memory does not meet the preset data storage conditions, the data to be processed is stored in a large-capacity dynamic random access memory.

[0080] Optionally, the data storage conditions can be pre-stored in the DMA controller to determine whether to store the data to be processed in the cache memory.

[0081] Optionally, if the data to be processed is external data, then if it is determined that the cache memory does not meet the preset data storage conditions, the data to be processed is stored in a large-capacity dynamic random access memory; if it is determined that the cache memory meets the preset data storage conditions, the data to be processed is stored in the cache memory.

[0082] Optionally, if the data to be processed is stored data, then if it is determined that the cache memory does not meet the preset data storage conditions, the storage location of the data to be processed will not be updated, and it will continue to be stored in the mass dynamic random access memory; if it is determined that the cache memory meets the preset data storage conditions, the data to be processed will be retrieved from the mass dynamic random access memory and stored in the cache memory.

[0083] In one possible implementation, the DMA controller can also include a status register. After storing the data to be processed in the cache, the DMA controller can update the status in the status register so that the CPU can determine whether the data to be processed is currently stored in the cache by querying the status register, and then process the data to be processed.

[0084] In another possible implementation, the DMA controller can generate an interrupt signal and send it to the CPU after storing the data to be processed in the cache. The CPU can then determine whether the data to be processed is currently stored in the cache based on the received interrupt signal, and thus process the data to be processed.

[0085] Understandably, in this embodiment, whether it is external data or stored data, DMA will eventually store the data to be processed that the CPU needs to process in the cache memory. This ensures that the CPU hits the cache memory every time it retrieves the data to be processed, thus avoiding the CPU from retrieving the data to be processed from the large-capacity dynamic random access memory, thereby improving the efficiency of the CPU in retrieving data and improving the CPU's read and write performance.

[0086] The data processing method provided in this application embodiment includes external data and / or stored data in a large-capacity dynamic random access memory (DRAM). The DMA controller determines whether the cache memory meets preset data storage conditions based on the size and data type of the data to be processed. If the conditions are met, the data to be processed is stored in the cache memory so that the CPU can retrieve the data from the cache memory and process it. If the conditions are not met, the data to be processed is stored in the DRAM. Through this method, the DMA can store external data and / or stored data in the DRAM in the cache memory when the cache memory meets the preset data storage conditions. This allows the CPU to directly retrieve the data to be processed from the cache memory for data processing without needing to retrieve external data from the DRAM, thus improving the efficiency of CPU data retrieval and thereby enhancing the performance of the embedded system.

[0087] Optionally, in order to ensure that the DMA controller can receive, store, and send data, the CPU can perform initialization operations on the DMA controller before the DMA controller enters the working state.

[0088] Specifically, during initialization, the CPU can establish multiple data channels between the DMA controller and the large-capacity dynamic random access memory and cache memory, based on the data type. In one possible implementation, the CPU can set up at least one data channel for each data type to receive and send the data to be processed corresponding to that data type.

[0089] Optionally, during initialization, the CPU can also set up contiguous storage spaces in the cache memory and the mass dynamic random access memory for each data channel, so as to store the data to be processed sent through the channel in the cache memory and the mass dynamic random access memory.

[0090] In one possible implementation, the storage space for each data channel in the cache memory can be a first preset capacity, and the storage space for each data channel in the large-capacity dynamic random access memory can be a second preset capacity. The first and second preset capacities can be set in advance according to the actual application requirements.

[0091] Optionally, to facilitate the DMA controller's monitoring of the storage status of each storage space, the CPU can also set a corresponding channel register in the DMA controller for each data channel during the initialization process, and each channel register can store read and write pointers.

[0092] Optionally, the CPU may set the read and write pointers in each channel register to default values ​​during initialization; in one possible implementation, the default value may be 0.

[0093] Furthermore, to facilitate the CPU's determination of whether data to be processed is stored in the cache memory, and to facilitate the DMA controller's determination of whether data to be sent exists, the CPU can also set control registers and status registers for each data channel in the DMA controller during initialization. The status register stores status information indicating whether data to be processed is stored in the cache memory, and the control register stores status information indicating whether data to be sent exists.

[0094] Understandably, the DMA controller can determine the corresponding data channel based on the data type of the data to be processed, and then store the data to be processed in the corresponding storage space in the cache memory through the data channel. It modifies the read / write pointer in the channel register corresponding to the data channel, and then modifies the status register corresponding to the data channel so that the CPU can retrieve the data to be processed from the corresponding storage space in the cache memory for processing. In one possible implementation, if there are multiple data channels corresponding to the data type, a data channel can be randomly selected for data storage, or a data channel can be determined from the multiple data channels corresponding to the data type based on other data information; this application does not limit this approach.

[0095] Understandably, after initialization, the DMA controller establishes multiple data channels with the mass dynamic random access memory (MRAM) and the cache memory, with each data channel corresponding to a data type. The cache memory has contiguous storage space for each data channel according to a first preset capacity, and the MRAM has contiguous storage space for each data channel according to a second preset capacity. The DMA controller has a corresponding channel register for each data channel, which stores read and write pointers. The read and write pointers are used to indicate the storage status of the storage space corresponding to the data to be processed.

[0096] Understandably, after initialization, each data type can correspond to at least one data channel, each data channel can correspond to a storage space in a high-speed cache memory and a storage space in a large-capacity dynamic random access memory. In addition, each data channel can also correspond to a channel register in DMA, and each channel register is set with a corresponding read / write pointer.

[0097] Optionally, after initialization, the CPU can control the receive data enable switch in the DMA controller to turn on, so that the DMA controller can receive external data.

[0098] Optionally, to facilitate the DMA controller's monitoring of write data in the cache memory, write data in the mass dynamic random access memory (MRAM), and CPU processing data, the read / write pointer may include a cache memory write pointer, a processing completion write pointer, and a MRAM write pointer. The cache memory write pointer is used to record the DMA controller's write data in the cache memory, the processing completion write pointer is used to record the CPU's data processing status, and the MRAM write pointer is used to record the DMA controller's write data in the MRAM.

[0099] Optionally, the data storage conditions include a first data storage condition, which includes that the remaining capacity of the storage space corresponding to the external data in the cache memory is greater than or equal to the size of the external data, and that the data type corresponding to the external data is not stored in the large-capacity dynamic random access memory.

[0100] Understandably, the remaining capacity of the storage space corresponding to the external data in the cache memory can be determined based on the total capacity of the storage space corresponding to the external data in the cache memory, the cache memory write pointer corresponding to the external data, and the processing completion write pointer; whether the large-capacity dynamic random access memory stores the data corresponding to the data type of the external data can be determined based on the cache memory write pointer corresponding to the external data and the large-capacity dynamic random access memory write pointer.

[0101] That is, if the write pointer of the cache memory corresponding to the external data is the same as the write pointer of the large-capacity dynamic random access memory, it means that the large-capacity dynamic random access memory does not store the data corresponding to the data type of the external data. All the data corresponding to the data type of the external data are stored in the cache memory. At this time, if the remaining capacity of the storage space corresponding to the external data in the cache memory is sufficient to store the external data, it can be determined that the cache memory meets the first data storage condition.

[0102] Optionally, the remaining capacity of the storage space refers to the capacity of the storage space that can be used to store the data to be processed. Understandably, the used capacity of the storage space corresponding to the external data in the cache can be determined by the write pointer of the cache corresponding to the external data and the write pointer of the processing completion. Then, based on the total capacity of the storage space corresponding to the external data in the cache and the used capacity, the remaining capacity of the storage space corresponding to the external data in the cache can be determined.

[0103] In this embodiment, since the CPU needs to process the data to be processed according to the receiving order of the DMA controller, if the large-capacity dynamic random access memory stores the data corresponding to the data type of the external data, it means that there is data to be processed before the external data, but it has not yet been stored in the cache memory. Therefore, the external data should be stored in the large-capacity dynamic random access memory first to wait for processing.

[0104] Based on this, if the cache memory meets the preset data storage conditions in step S21 above, the data to be processed is stored in the cache memory, which can be achieved through the following steps:

[0105] If the cache memory meets the first data storage condition, the external data is stored in the corresponding storage space of the cache memory through the data channel corresponding to the external data; and the cache memory write pointer corresponding to the external data is updated.

[0106] Optionally, if the cache memory meets the first data storage condition, the DMA controller can determine the corresponding data channel based on the data type of the external data, and store the external data in the corresponding storage space of the cache memory through the data channel.

[0107] Understandably, at this point, it is also necessary to synchronously modify the cache write pointer in the channel register corresponding to the external data so that the cache write pointer points to the next available address.

[0108] In addition, step S22 above can also be implemented by the following steps: if the cache memory does not meet the first data storage condition, the external data is stored in the corresponding storage space of the large-capacity dynamic random access memory through the data channel corresponding to the external data; the write pointer of the large-capacity dynamic random access memory corresponding to the external data is updated.

[0109] Optionally, if the cache memory does not meet the first data condition, the corresponding data channel can be determined by the data type of the external data, and the external data can be stored in the corresponding storage space of the mass dynamic random access memory (MRAM) through the data channel. Understandably, at this time, it is also necessary to synchronously modify the MRAM write pointer in the channel register corresponding to the external data so that the MRAM write pointer points to the next available address.

[0110] In this embodiment, in order to ensure that the CPU can hit the cache memory every time it acquires data to be processed, the DMA controller also needs to re-store the data to be processed from the large-capacity dynamic random access memory to the cache memory.

[0111] Based on this, the read / write pointer also includes a save-as-a-data pointer, the data storage condition including a second data storage condition, wherein the remaining capacity of the storage space corresponding to the stored data in the cache memory is greater than or equal to the size of the stored data; wherein the stored data is determined according to the save-as-a-data pointer in each channel register; optionally, the save-as-a-data pointer is used to characterize the stored data that needs to be stored in the cache memory.

[0112] In one possible implementation, the DMA controller can periodically determine whether the cache meets the second data storage condition for different types of stored data. In another possible implementation, the DMA controller can determine whether the cache meets the second data storage condition in real time for different types of stored data.

[0113] Understandably, if the second data storage condition is met, the DMA controller can retrieve the stored data from the mass dynamic random access memory and store it again in the cache memory.

[0114] Based on this, if the cache memory meets the preset data storage conditions in step S21 above, the data to be processed is stored in the cache memory, which can be achieved through the following steps:

[0115] If the cache memory meets the second data storage condition, the stored data is retrieved from the large-capacity dynamic random access memory and stored in the corresponding storage space in the cache memory through the data channel corresponding to the stored data; the save-as-a-data read pointer and the cache memory write pointer corresponding to the stored data are updated.

[0116] Optionally, the DMA controller can obtain the stored data via the bus according to the save read pointer, and then write the stored data into the corresponding storage space in the cache memory through the corresponding data channel.

[0117] In this embodiment, it is understood that the DMA controller also needs to update the separate read pointer and the separate write pointer of the stored data after writing the stored data to the cache memory, so that the updated separate read pointer points to the next stored data to be stored in the cache memory, and the updated separate write pointer points to the next available address in the storage space.

[0118] Optionally, considering that the CPU can generate processed data after processing the data to be processed, and that the processed data may or may not need to be sent to an external device, the DMA controller can send the processed data that needs to be sent to an external device. In order to improve the DMA read bandwidth, read efficiency, and send performance, a buffer of a certain depth can be set in the DMA controller to store the data that needs to be sent.

[0119] Optionally, the CPU can set parameters for the buffer during initialization.

[0120] Understandably, the read / write pointer can also include a CPU read pointer, used to characterize data stored in the cache that the CPU has not yet processed.

[0121] Understandably, after step S21 above, the method further includes:

[0122] Obtain the processing completion information sent by the CPU, and determine whether the processed data is forwarded data based on the processing completion information;

[0123] The processed data refers to the data obtained by the CPU after processing the data to be processed.

[0124] Optionally, after processing the data to be processed, the CPU can notify the DMA controller whether the data to be processed is forwarding data.

[0125] Optionally, the processing completion information can be information in the control register or information sent directly to the DMA controller.

[0126] In one possible implementation, if the processed data is forwarded data, the CPU can set processing completion information in the control register corresponding to the processed data. This allows the DMA controller to determine if there is data to be sent when it finds processing completion information in the control register. In another possible implementation, if the processed data is not forwarded data, the CPU can directly send processing completion information to the DMA controller upon receipt, indicating that the data to be processed has been completed and does not need to be sent. In this case, the DMA controller can modify the corresponding CPU read pointer and processing completion write pointer.

[0127] Optionally, if the processed data is forwarded data, the processing completion information should also include information such as the storage location and size of the processed data.

[0128] If the processed data is forwarded data, the CPU read pointer corresponding to the processed data is updated, and the processed data is obtained according to the storage location information in the processed data information; the processed data is stored in the buffer, and the processed data write pointer corresponding to the processed data is updated; the processed data in the buffer is sent to the external device through the output interface module.

[0129] Optionally, since the CPU may need to perform multiple reads while continuing data processing, the DMA controller can modify the CPU read pointer only after determining that the CPU has finished processing the data to be processed.

[0130] Optionally, in order to improve the efficiency of DMA in acquiring processed data, the CPU may, if it determines that the processed data is forwarding data, store the processed data back to the original address, that is, store the processed data at the address where the corresponding data to be processed was previously stored.

[0131] Optionally, considering that the size of the processed data may be larger than that of the data to be processed, the DMA controller can allocate a larger storage space for the data to be processed than its actual size according to a preset expansion method when storing the data to be processed.

[0132] For example, if the actual size of the data to be processed is 10, the DMA controller can generate a virtual data size, such as 12, for the data to be processed according to a preset expansion method. In this case, when determining whether the cache memory meets the preset data storage conditions for the data to be processed, the cache memory can be determined based on the virtual data size, thereby storing the data to be processed in the cache memory.

[0133] Understandably, since the completed data will be stored at the address of its corresponding pending data, in order to avoid the completed data being overwritten before it is sent, the completed write pointer can be left unchanged for the time being.

[0134] Optionally, when sending processed data, the DMA controller can first store the processed data in a buffer according to the storage location information in the processed data completion information, and then send the processed data in the buffer to an external device through the output interface module.

[0135] Optionally, after storing the processed data in the buffer, the DMA controller can update the processing completion write pointer corresponding to the processed data, so that it points to the next data that is currently being processed.

[0136] Understandably, since the DMA controller can retrieve processed data from the cache memory for transmission instead of from the large-capacity dynamic random access memory, it can improve the efficiency of the DMA controller in retrieving processed data to a certain extent, thereby improving its transmission performance.

[0137] If the processed data is non-forwarded data, then the CPU read pointer and the processing completion write pointer corresponding to the processed data are updated.

[0138] Optionally, if the processed data is non-forwarded data, the DMA controller can directly update the CPU read pointer and the processed write pointer corresponding to the processed data.

[0139] In this embodiment, it can be understood that the CPU read pointer, processing completion write pointer, cache memory write pointer, and large-capacity dynamic random access memory write pointer can collectively reflect the data reception status of the DMA controller. Specifically, Figure 4 For a diagram illustrating the initialization of the read / write pointers, please refer to [link / reference]. Figure 4 During CPU initialization, the CPU read pointer, processing completion write pointer, cache write pointer, and mass dynamic random access memory write pointer can all be set to 0. It can be seen that at this time, neither the cache nor the mass dynamic random access memory stores any data to be processed, the CPU does not read data for processing, and there is no data that has been processed.

[0140] Optionally, Figure 5 For a diagram illustrating the read / write pointer operation after the DMA controller receives data, please refer to [link / reference]. Figure 5 The data between the write pointer and the CPU read pointer represents the data that the CPU is currently processing in the cache memory. The data between the CPU read pointer and the cache write pointer represents the data that the CPU has not yet processed. The data between the cache write pointer and the mass dynamic random access memory (MRAM) write pointer represents the data that has not yet been processed and is stored in the MRAM. The data between the write pointer and the MRAM write pointer represents the data that the DMA controller has written to the MRAM or cache memory, but which the CPU has not yet finished processing.

[0141] according to Figure 5 Obviously, if the write pointer of the cache memory and the write pointer of the mass dynamic random access memory are at the same location, it means that there is no unprocessed data in the mass dynamic random access memory that has not been stored in the cache memory.

[0142] Optionally, the CPU may also spontaneously generate some data during operation, and this spontaneous data may also need to be sent to external devices. In this case, when the CPU generates spontaneous data that needs to be sent to external devices, it can send spontaneous data information to the CPU so that the DMA can determine that there is data that needs to be sent based on the spontaneous data information, and thus obtain the corresponding spontaneous data for sending.

[0143] Optionally, the spontaneous data information may include information characterizing the attributes of spontaneous data, such as storage location information and data size information.

[0144] Understandably, the DMA controller can obtain spontaneous data information sent by the CPU and retrieve the spontaneous data based on the storage location information in the spontaneous data information; the spontaneous data is data generated spontaneously by the CPU; the spontaneous data is stored in a buffer; and the spontaneous data in the buffer is sent to an external device through the output interface module.

[0145] Optionally, the spontaneous data may be stored in a large-capacity dynamic random access memory or in a cache memory.

[0146] Optionally, since the latency of reading data in a large-capacity dynamic random access memory is relatively long, in order to improve the bandwidth of the DMA controller's data reading, the read data can be stored in a buffer. Based on this, the DMA controller can continuously initiate data reading operations without waiting for the result of the previous read operation.

[0147] In this embodiment, the DMA controller can store the acquired spontaneous data in a buffer, and then send the spontaneous data in the buffer to an external device through the corresponding output interface module.

[0148] Optionally, in order to improve the overall processing efficiency of the embedded system, the DMA controller can determine the CPU's operating state in advance. Specifically, the DMA controller can receive the operation information sent by the monitoring module and determine the current operating state of the CPU based on the operation information.

[0149] Optionally, the CPU can also set processing parameters for the monitoring module during initialization. After the embedded system starts working, the monitoring module can monitor the CPU's operating status in real time and send operation information to the DMA controller.

[0150] Optionally, this operation information can be key interface signals connecting the CPU to the bus, such as read / write valid flags, read / write addresses, data lengths, etc. The DMA controller can then parse this operation information based on the configuration information of its internal registers, such as the channel-assigned address, to determine the CPU's current operating state. For example, parsing the operation information can determine which registers the CPU is currently reading or writing.

[0151] Understandably, through this method, the DMA controller does not need to wait for the CPU operation to complete before obtaining the CPU operation information, but can judge the CPU operation status in advance. Based on this operation, the overall data processing efficiency of the embedded system can be improved.

[0152] Optionally, the monitoring module can also obtain the operation information of the DMA controller and send it to the CPU so that the CPU can determine the operation status of the DMA controller.

[0153] To perform the corresponding steps in the above embodiments and various possible methods, an implementation of a data processing apparatus is given below. Further, please refer to... Figure 6 , Figure 6 This is a functional block diagram of a data processing apparatus provided in an embodiment of this application. It should be noted that the basic principle and technical effects of the data processing apparatus provided in this embodiment are the same as those in the above embodiments. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the above embodiments. The data processing apparatus includes: a determining module 800 and a storage module 810.

[0154] The determining module 800 is used to determine whether the cache memory meets the preset data storage conditions based on the data size and data type of the data to be processed; the data to be processed includes external data and / or stored data in a large-capacity dynamic random access memory.

[0155] Understandably, the determining module 800 can also be used to perform the above step S20;

[0156] The storage module 810 is used to store the data to be processed in the cache memory if the cache memory meets the preset data storage conditions, so that the CPU can obtain the data to be processed from the cache memory and perform data processing on the data to be processed.

[0157] Understandably, the storage module 810 can also be used to perform the above step S21;

[0158] The storage module 810 is also used to store the data to be processed in a large-capacity dynamic random access memory if the cache memory does not meet the preset data storage conditions.

[0159] Understandably, the storage module 810 can also be used to perform the above step S22.

[0160] Optionally, the storage module 810 is further configured to, if the cache memory meets the first data storage condition, store the external data into the corresponding storage space in the cache memory through the data channel corresponding to the external data; and update the cache memory write pointer corresponding to the external data.

[0161] Optionally, the storage module 810 is further configured to, if the cache memory does not meet the first data storage condition, store the external data into the corresponding storage space in the large-capacity dynamic random access memory through the data channel corresponding to the external data; and update the write pointer of the large-capacity dynamic random access memory corresponding to the external data.

[0162] Optionally, the storage module 810 is further configured to, if the cache memory meets the second data storage condition, retrieve the stored data from the large-capacity dynamic random access memory and store the stored data in the corresponding storage space in the cache memory through the data channel corresponding to the stored data; and update the save-as-a-data read pointer and the cache memory write pointer corresponding to the stored data.

[0163] Optionally, in Figure 6 On this basis, Figure 7 This is another functional block diagram of the data processing apparatus provided in the embodiments of this application, which further includes a sending module 820.

[0164] The sending module 820 is used to obtain processing completion information sent by the CPU, and determine whether the processed data is forwarded data based on the processing completion information. The processed data is the data obtained by the CPU after processing the data to be processed. If the processed data is forwarded data, the CPU read pointer corresponding to the processed data is updated, and the processed data is obtained according to the storage location information in the processing completion information. The processed data is stored in a buffer, and the processing completion write pointer corresponding to the processed data is updated. The processed data in the buffer is sent to an external device through the output interface module. If the processed data is not forwarded data, the CPU read pointer and processing completion write pointer corresponding to the processed data are updated.

[0165] Optionally, the sending module 820 is further configured to acquire spontaneous data information sent by the CPU, and acquire spontaneous data according to the storage location information in the spontaneous data information; the spontaneous data is data spontaneously generated by the CPU; store the spontaneous data in a buffer; and send the spontaneous data in the buffer to an external device through the output interface module.

[0166] Optionally, the determining module 800 is also used to receive operation information sent by the monitoring module and determine the current operation status of the CPU based on the operation information.

[0167] The data processing apparatus provided in this application embodiment determines, through a determining module, whether a cache memory meets preset data storage conditions based on the data size and data type of the data to be processed. The data to be processed includes external data and / or stored data in a large-capacity dynamic random access memory (DRAM). If the cache memory meets the preset data storage conditions, the storage module stores the data to be processed in the cache memory, allowing the CPU to retrieve the data from the cache memory and perform data processing. If the cache memory does not meet the preset data storage conditions, the data to be processed is stored in the large-capacity DRAM. This apparatus allows DMA to store external data and / or stored data in the large-capacity DRAM in the cache memory when the cache memory meets the preset data storage conditions. This allows the CPU to directly retrieve the data to be processed from the cache memory for data processing without needing to retrieve external data from the large-capacity DRAM, thus improving the efficiency of CPU data retrieval and thereby enhancing the performance of the embedded system.

[0168] Optionally, the above modules can be stored in the form of software or firmware. Figure 2 The memory shown may be stored in or embedded in the operating system (OS) of the DMA controller, and may be controlled by... Figure 2 The processor executes the commands. Meanwhile, the data and program code required to execute these modules can be stored in memory.

[0169] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, can implement the data processing method provided in this application.

[0170] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0171] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0172] If a function is implemented as a software module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0173] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A data processing method, characterized in that, A DMA controller is used in an embedded system, wherein the embedded system further includes a CPU, a cache memory, and a large-capacity dynamic random access memory, and the DMA controller is connected to the CPU, the cache memory, and the large-capacity dynamic random access memory respectively via a bus. The method includes: Based on the size and data type of the data to be processed, determine whether the cache memory meets the preset data storage conditions; the data to be processed includes external data and / or stored data in a large-capacity dynamic random access memory. If the cache memory meets the preset data storage conditions, the data to be processed is stored in the cache memory so that the CPU can obtain the data to be processed from the cache memory and perform data processing on the data to be processed. If the high-speed cache does not meet the preset data storage conditions, the data to be processed is stored in the large-capacity dynamic random access memory. Multiple data channels are provided between the DMA controller, the large-capacity dynamic random access memory, and the high-speed cache memory, wherein each data channel corresponds to a data type; The high-speed cache memory has a contiguous storage space for each data channel according to a first preset capacity, and the large-capacity dynamic random access memory has a contiguous storage space for each data channel according to a second preset capacity. The DMA controller has a corresponding channel register for each data channel, which is used to store read and write pointers; the read and write pointers are used to indicate the storage status of the storage space corresponding to the data to be processed.

2. The method according to claim 1, characterized in that, The embedded system further includes an input interface module, and the DMA controller is also electrically connected to the input interface module. The input interface module is used to acquire the external data. The read / write pointers include a cache memory write pointer, a processing completion write pointer, and a large-capacity dynamic random access memory write pointer. The data storage conditions include a first data storage condition. The first data storage conditions include that the remaining capacity of the storage space corresponding to the external data in the cache memory is greater than or equal to the data size of the external data, and that the large-capacity dynamic random access memory does not store storage data corresponding to the data type of the external data. The remaining capacity of the storage space corresponding to the external data in the cache memory is determined based on the total capacity of the storage space corresponding to the external data in the cache memory, the cache memory write pointer corresponding to the external data, and the processing completion write pointer; whether the large-capacity dynamic random access memory stores storage data corresponding to the data type of the external data is determined based on the cache memory write pointer corresponding to the external data and the large-capacity dynamic random access memory write pointer. If the cache memory meets the preset data storage conditions, then storing the data to be processed in the cache memory includes: If the cache memory meets the first data storage condition, the external data is stored in the corresponding storage space of the cache memory through the data channel corresponding to the external data. Update the cache write pointer corresponding to the external data.

3. The method according to claim 2, characterized in that, If the cache memory does not meet the preset data storage conditions, then storing the data to be processed in the large-capacity dynamic random access memory includes: If the high-speed cache does not meet the first data storage condition, the external data is stored in the corresponding storage space of the large-capacity dynamic random access memory through the data channel corresponding to the external data. Update the write pointer of the large-capacity dynamic random access memory corresponding to the external data.

4. The method according to claim 1, characterized in that, The data storage conditions include a second data storage condition, and the read / write pointers include a save-to-other read pointer and a cache memory write pointer. The second data storage condition includes that the remaining capacity of the storage space corresponding to the stored data in the cache memory is greater than or equal to the data size of the stored data; wherein the stored data is determined according to the save-as-a-book pointer in each channel register; If the cache memory meets the preset data storage conditions, then storing the data to be processed in the cache memory includes: If the cache memory meets the second data storage condition, the stored data is retrieved from the large-capacity dynamic random access memory and stored in the corresponding storage space of the cache memory through the data channel corresponding to the stored data. Update the save read pointer and the cache write pointer corresponding to the stored data.

5. The method according to claim 1, characterized in that, The embedded system further includes an output interface module, and the DMA controller is electrically connected to the output interface module, and the DMA controller is provided with a buffer; the read / write pointers include a CPU read pointer and a processing completion write pointer, and after storing the data to be processed in the cache memory, the method further includes: Obtain the processing completion information sent by the CPU, and determine whether the processed data is forwarded data based on the processing completion information; wherein, the processed data is the data obtained by the CPU after processing the data to be processed; If the processed data is forwarded data, then the CPU read pointer corresponding to the processed data is updated, and the processed data is obtained according to the storage location information in the processed data. The processed data is stored in the buffer, and the processing completion write pointer corresponding to the processed data is updated. The processed data in the buffer is sent to an external device through the output interface module; If the processed data is non-forwarded data, then the CPU read pointer and the processing completion write pointer corresponding to the processed data are updated.

6. The method according to claim 5, characterized in that, The method further includes: The CPU sends spontaneous data information, and the CPU retrieves the spontaneous data based on the storage location information in the spontaneous data information; the spontaneous data is data spontaneously generated by the CPU. The spontaneous data is stored in the buffer; The spontaneous data in the buffer is sent to an external device through the output interface module.

7. The method according to claim 1, characterized in that, A monitoring module is provided at the interface between the CPU and the bus, and the method further includes: The system receives operation information sent by the monitoring module and determines the current operation status of the CPU based on the operation information.

8. A data processing apparatus, characterized in that, A DMA controller for use in an embedded system, the embedded system further including a CPU, a cache memory, and a large-capacity dynamic random access memory, wherein the DMA controller is connected to the CPU, the cache memory, and the large-capacity dynamic random access memory respectively via a bus, the device comprising: The determination module is used to determine whether the high-speed cache memory meets the preset data storage conditions based on the data size and data type of the data to be processed; the data to be processed includes external data and / or stored data stored in a large-capacity dynamic random access memory; The storage module is used to store the data to be processed in the cache memory if the cache memory meets the preset data storage conditions, so that the CPU can obtain the data to be processed from the cache memory and perform data processing on the data to be processed. The storage module is further configured to store the data to be processed in the large-capacity dynamic random access memory if the high-speed cache memory does not meet the preset data storage conditions. Multiple data channels are provided between the DMA controller, the large-capacity dynamic random access memory, and the high-speed cache memory, wherein each data channel corresponds to a data type; The high-speed cache memory has a contiguous storage space for each data channel according to a first preset capacity, and the large-capacity dynamic random access memory has a contiguous storage space for each data channel according to a second preset capacity. The DMA controller has a corresponding channel register for each data channel, which is used to store read and write pointers; the read and write pointers are used to indicate the storage status of the storage space corresponding to the data to be processed.

9. A DMA controller, characterized in that, It includes a processor and a memory, the memory storing a computer program executable by the processor, the processor being able to execute the computer program to implement the method of any one of claims 1-7.

10. An embedded system, characterized in that, Includes the DMA controller as described in claim 9.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1-7.

Images