Display panel and display device

Abstract

This application discloses a display panel and a display device, wherein the display panel includes pixel circuits and light-emitting elements, and the pixel circuits are used to provide driving current to the light-emitting elements; the frame refresh frequency of the pixel circuit located in the first display area is F1, and the frame refresh frequency of the pixel circuit located in the second display area is F2, wherein F1>F2. This application can reduce display power consumption when the display panel is at a higher refresh frequency.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a display panel and a display device. Background Technology

[0002] With technological advancements, the demands on display panels are gradually increasing. To enhance the user's visual experience, panels supporting high refresh rates such as 90Hz and 120Hz have emerged. However, the application of high-frequency display technologies inevitably leads to a significant increase in the power consumption of display panels. Summary of the Invention

[0003] This application provides a display panel and a display device that can reduce the power consumption of the display panel when the display panel is at a high refresh rate.

[0004] On the one hand, a display panel is provided, which may include:

[0005] Pixel circuitry and light-emitting element; the pixel circuitry is used to provide driving current to the light-emitting element.

[0006] The frame refresh rate of the pixel circuit located in the first display area is F1, and the frame refresh rate of the pixel circuit located in the second display area is F2.

[0007] Among them, F1>F2.

[0008] Optionally, the pixel circuit includes a driving transistor, the gate of which is connected to the source driving circuit.

[0009] A frame includes a data write frame or a hold frame; in a data write frame, the source drive circuit writes a data signal to the gate of the drive transistor; in a hold frame, the source drive circuit does not write a data signal to the gate of the drive transistor.

[0010] A data refresh cycle of the display panel includes a first data refresh cycle corresponding to the first display area and a second data refresh cycle corresponding to the second display area;

[0011] The first data refresh cycle corresponding to the first display area includes m1 data write frames and r1 hold frames;

[0012] The second data refresh cycle corresponding to the second display area includes m2 data write frames and r2 hold frames;

[0013] Where m1+r1=m2+r2, and m1>m2>0, r2>r1≥0.

[0014] Optionally, the second data refresh cycle corresponding to the second display area includes n sequentially set data refresh sub-cycles, each data refresh sub-cycle including m3 data write frames and r3 hold frames.

[0015] Where m2 = n * m3, r2 = n * r3, n ≥ 2.

[0016] Optionally, the second data refresh cycle corresponding to the second display area includes a data writing phase and a holding phase set sequentially.

[0017] The data writing phase consists of m2 data writing frames, and the holding phase consists of r2 holding frames.

[0018] Optionally, the display panel may also include:

[0019] The first switch has its input terminal electrically connected to the source drive circuit, and the second switch has its output terminal electrically connected to the gate of the drive transistor.

[0020] The second switch has a high-impedance signal connected to its input terminal and its output terminal electrically connected to the gate of the driving transistor.

[0021] When the pixel circuit is working in the data writing frame, the control terminal of the first switch is connected to a valid signal, and the control terminal of the second switch is connected to a non-valid signal.

[0022] When the pixel circuit is operating in hold frame mode, the control terminal of the first switch is connected to an invalid signal, and the control terminal of the second switch is connected to an valid signal.

[0023] Preferably, the high-impedance signal is replaced with a VGMP signal or a VGSP signal.

[0024] Optionally, the display panel may also include:

[0025] Gate driving circuit, used to provide scanning signals to pixel circuit;

[0026] The first type of clock signal line is used to provide the first type of clock signal to the gate drive circuit;

[0027] When the pixel circuit is operating in hold frame mode, the first type of clock signal is the first level signal.

[0028] Optionally, the first type of clock signal line includes a first clock signal line and a second clock signal line.

[0029] When the pixel circuit is operating in the data write frame, the output timing of the first clock signal line is at least partially opposite to the output timing of the second clock signal line.

[0030] When the pixel circuit is operating in hold frame mode, the first level signals output by the first clock signal line and the second clock signal line are both high level signals.

[0031] Optionally, the display panel may also include:

[0032] The light-emitting driving circuit is used to provide light-emitting control signals to the pixel circuit;

[0033] The second type of clock signal line is used to provide the second type of clock signal to the light-emitting driver circuit;

[0034] When the pixel circuit is operating in hold frame mode, the second type of clock signal is a second level signal.

[0035] Optionally, the second type of clock signal lines includes a third clock signal line and a fourth clock signal line.

[0036] When the pixel circuit is operating in the data writing frame, at least a portion of the output timing of the third clock signal line and the output timing of the fourth clock signal line are at opposite potentials.

[0037] When the pixel circuit is operating in hold frame mode, the second level signals output by the third clock signal line and the fourth clock signal line are both low level signals.

[0038] On the other hand, a display device is also provided, which may include the display panel described above.

[0039] Compared with the prior art, the display panel and display device provided in this application embodiment are provided with pixel circuits and light-emitting elements, wherein the pixel circuits are used to provide driving current to the light-emitting elements. The frame refresh frequency of the pixel circuit located in the first display area is F1, and the frame refresh frequency of the pixel circuit located in the second display area is F2, where F1>F2. Therefore, when the display panel is displaying, the frame refresh frequencies of the pixel circuits in different display areas are designed differently, thereby achieving a high refresh rate in the first display area while using a lower frame refresh rate in the second display area. Thus, while ensuring that the display panel is at a high refresh rate, display power consumption is reduced. Attached Figure Description

[0040] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of the optional circuit structure of the pixel circuit and light-emitting element involved in the display panel of an embodiment of this application.

[0042] Figure 2 This is a schematic diagram of an optional arrangement structure of the display area involved in a display panel according to an embodiment of this application.

[0043] Figure 3 This is a schematic diagram showing the frame refresh frequency settings of pixel circuits in different display areas of a display panel according to an embodiment of this application.

[0044] Figure 4 This is a schematic diagram of an optional timing within a data refresh cycle of the display panel in an embodiment of this application.

[0045] Figure 5 This is another optional timing diagram within a data refresh cycle of the display panel in an embodiment of this application.

[0046] Figure 6 This is another optional timing diagram within a data refresh cycle of the display panel in an embodiment of this application.

[0047] Figure 7 This is another optional timing diagram within a data refresh cycle of the display panel in an embodiment of this application.

[0048] Figure 8 This is a frame count comparison table of data writing frames in the first display area and the second display area when the frame refresh frequency of the first display area in the display panel of this application embodiment is 60Hz.

[0049] Figure 9 This is a schematic diagram of the driving architecture of the source driving circuit in the display panel according to an embodiment of this application.

[0050] Figure 10 This is a schematic diagram of another driving architecture for the source driving circuit in the display panel of this application embodiment.

[0051] Figure 11 This is a schematic diagram of the circuit structure of multiple cascaded gate driving circuits in the display panel of an embodiment of this application.

[0052] Figure 12 This is a schematic diagram of an optional circuit structure for a single gate driving circuit in a display panel according to an embodiment of this application.

[0053] Figure 13 This is an optional driving timing diagram of the gate driving circuit in the display panel of this application embodiment.

[0054] Figure 14 This is a schematic diagram of the circuit structure of multiple cascaded light-emitting driving circuits in the display panel of this application embodiment.

[0055] Figure 15 This is a schematic diagram of an optional circuit structure for a single light-emitting driving circuit in a display panel according to an embodiment of this application.

[0056] Figure 16 This is an optional driving timing diagram of the light-emitting driving circuit in the display panel of this application embodiment. Attached image description:

[0058] Pixel circuit 10, threshold compensation module 11, first initialization module 12, light-emitting element 20, data refresh cycle T1, data refresh sub-cycle T2, data write stage T3, hold stage T4, first switch K1, second switch K2, third switch K3, driving transistor M5, gate driving circuit VSR1, light-emitting driving circuit VSR2, data signal Vdata, scan signal line SCAN, light-emitting control signal line EM, first type clock signal line SCK, first clock signal line SCK1, second clock signal line SCK2, second type clock signal line ECK, third clock signal line ECK1, fourth clock signal line ECK2, frame F, high impedance signal NC, digital-to-analog converter unit DAC. Detailed Implementation

[0059] The features and exemplary embodiments of various aspects of this application will now be described in detail. Numerous specific details are set forth in the following detailed description in order to provide a comprehensive understanding of this application. However, it will be apparent to those skilled in the art that this application can be implemented without some of these specific details. The following description of embodiments is merely intended to provide a better understanding of this application by illustrating examples thereof.

[0060] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The embodiments will now be described in detail with reference to the accompanying drawings.

[0061] Display panels in related technologies generally support low refresh rates, but low refresh rate displays can only support normal video and application display, and suffer from problems such as choppy video quality and poor visual experience. With the development of display technology, in order to meet users' demands for better video display effects, electronic devices such as computers and mobile phones have gradually supported high refresh rates. At high refresh rates, display panels can display high-definition movies and games. However, the application of high refresh rates inevitably leads to a significant increase in the power consumption of the display panel.

[0062] To address the aforementioned technical problems, this application provides a display panel and a display device. The display panel of this application embodiment will be described below with reference to the accompanying drawings.

[0063] See Figures 1 to 3 In an optional example of the display panel in this application embodiment, the display panel may include pixel circuitry 10 and light-emitting elements 20.

[0064] It should be noted that the above-mentioned display panel may also include multiple pixel units (not shown in the figure) arranged in an array, and the pixel circuit 10 and the light-emitting element 20 may be disposed in these pixel units.

[0065] The aforementioned light-emitting element 20 can be a light-emitting diode (LED), an organic light-emitting diode (OLED), or others.

[0066] The pixel circuit 10 described above can be used to provide driving current to the light-emitting element 20. The pixel circuit 10 can be a 7T1C circuit, an 8T1C circuit, an 8T2C circuit, a 9T2C circuit, etc., and can even be a basic 2T1C circuit. For example, please refer to... Figure 1 , Figure 1 The diagram shows an optional circuit structure of the pixel circuit 10 and the light-emitting element 20 involved in this application. In the pixel circuit 10, the threshold compensation module 11 can be composed of two thin-film transistors, M2 and M8, and the first initialization module 12 for initializing the gate of the driving transistor M5 can be composed of two thin-film transistors, M4 and M6.

[0067] The display panel may include at least two display areas; see some optional examples. Figure 2 At least two display areas may include a first display area and a second display area. For example, the first display area and the second display area may extend along the row direction or be arranged sequentially along the column direction.

[0068] For example, when the display panel is a flexible display (e.g., a foldable OLED screen), the boundary between the first and second display areas can be bent in certain situations.

[0069] Please continue reading. Figures 1 to 3 The frame refresh frequency of the pixel circuit 10 located in the first display area is F1, and the frame refresh frequency of the pixel circuit 10 located in the second display area is F2, where F1>F2.

[0070] The frames mentioned above in the frame refresh rate are calculated based on the minimum cycle of one light-emitting phase. By setting different frame refresh rates for different display areas of the display panel, the display panel can display images with higher resolution requirements in some areas and images with lower resolution requirements in others when displaying the same image, thereby reducing the power consumption of the display panel.

[0071] For example, the display panel can be a foldable screen. On one side of the foldable screen, folded area A (i.e., the first display area) can display dynamic display scenes with high refresh rates, such as games, while on the other side of the foldable screen, folded area B (i.e., the second display area) can display static images with low frame refresh rates, such as keyboard operation images.

[0072] In this embodiment, the display device includes a pixel circuit 10 and a light-emitting element 20, wherein the pixel circuit 10 provides driving current to the light-emitting element 20. The frame refresh rate of the pixel circuit 10 located in the first display area is F1, and the frame refresh rate of the pixel circuit 10 located in the second display area is F2, where F1 > F2. Therefore, when the display panel is displaying, the frame refresh rates of the pixel circuit 10 in different display areas are designed differently. This allows for a high refresh rate in the first display area while using a lower frame refresh rate in the second display area, thus reducing display power consumption while ensuring a high refresh rate for the display panel.

[0073] In some optional examples, please see Figures 4 to 5 Please refer to the following as well. Figures 1 to 3 The pixel circuit 10 described above may include a driving transistor M5, the gate of which is connected to a source driving circuit (not shown). For example, the driving transistor M5 may be connected to a data signal line, and the source driving circuit may provide a data signal Vdata to each pixel circuit 10 via the data signal line.

[0074] Furthermore, the frame F involved in the minimum period of the aforementioned light-emitting stage may include a data write frame and / or a hold frame. In the data write frame, the source drive circuit can write the data signal Vdata to the gate of the drive transistor M5 via the data signal line, at which time the drive transistor M5, threshold compensation module 11, etc., can be turned on. In the hold frame, the source drive circuit may not write the data signal Vdata to the gate of the drive transistor M5.

[0075] The data refresh cycle T1 of the display panel includes a first data refresh cycle corresponding to the first display area and a second data refresh cycle corresponding to the second display area.

[0076] The first data refresh cycle may include m1 data write frames and r1 hold frames. The second data refresh cycle may include m2 data write frames and r2 hold frames, where m1 + r1 = m2 + r2, and m1 > m2 > 0, r2 > r1 ≥ 0.

[0077] It should be noted that the data refresh in the aforementioned data refresh cycle T1 is calculated based on the minimum cycle of writing the data signal Vdata. In actual display, a portion of the image in the first display area and a portion of the image in the second display area constitute a complete frame. Therefore, when writing data corresponding to this image frame, the total number of data frames F in the first and second display areas is the same, i.e., m1 + r1 = m2 + r2. To achieve a relatively low frame refresh rate in the second display area and a relatively high frame refresh rate in the first display area, a relatively larger number of hold frames can be set in the second display area, i.e., r2 > r1. This results in a relatively smaller number of data signals Vdata being written within the second data refresh cycle corresponding to the second display area, thereby enabling the display panel to support a high refresh rate while reducing display power consumption.

[0078] For example, please see Figure 4 Please refer to the following as well. Figures 1 to 3 In the first data refresh cycle, only the data write frame can be set, i.e., r1=0. Regardless of whether the pixel circuit 10 of the second display area is working in the data write frame or the hold frame, the pixel circuit 10 of the first display area is always in the data write frame. This setting can maximize the display effect of the first display area and improve the high-definition experience of the display panel.

[0079] For example, please see Figure 5 Please refer to the following as well. Figures 1 to 3 In the second data refresh cycle, only one data write frame can be set, and the rest are hold frames, i.e., the case where m2=1. This can reduce the display power consumption of the second display area as much as possible.

[0080] It should also be noted that the order in which data is written to frames and held frames are arranged within a single data refresh cycle T1 of a single display area can be adjusted according to actual needs.

[0081] In some optional examples, please continue reading. Figure 6 Please refer to the following as well. Figures 1 to 5 Within the second data refresh cycle corresponding to the second display area, n data refresh sub-cycles T2 can be set sequentially. Each data refresh sub-cycle T2 includes m3 data write frames and r3 hold frames, where m2 = n * m3, r2 = n * r3, and n ≥ 2.

[0082] In this example, a single second data refresh cycle within the second display area is further divided into several data refresh sub-cycles T2. Each data refresh sub-cycle T2 includes several data write frames and several hold frames. Therefore, within the second data refresh cycle, the data write frames and hold frames alternate, which enables the on / off state of each transistor in the pixel circuit 10 to change at regular intervals, maintaining the stability of the display effect. At the same time, it can display high refresh rate images while reducing power consumption.

[0083] Taking a display panel with a frame refresh rate of 60Hz as an example, within the second display area, a single data refresh cycle can include 60 data frames F. A second data refresh cycle of the pixel circuit 10 located in the second display area can include 10 data refresh sub-cycles T2, i.e., n=10. Therefore, m3 can be set to 1 and r3 to 5. Within one data refresh sub-cycle T2, the pixel circuit 10 in the second display area can operate by writing one data frame, then not writing the data signal Vdata for 5 hold frames, and then continuing into a new data refresh sub-cycle T2 to write another data signal Vdata, and then not writing the data signal Vdata for 5 hold frames, remaining in a hold state.

[0084] Continuing with the above example, if the first data refresh cycle does not include a holding frame, the pixel circuit 10 of the first display area refreshes 6 frames of data writing, and the second display area operates once a data writing frame.

[0085] In some other optional examples, please see Figure 7 Please refer to the following as well. Figures 1 to 6 The second data refresh cycle includes a data writing phase T3 and a holding phase T4 set sequentially. The data writing phase T3 includes m² data writing frames, and the holding phase T4 includes r² holding frames. By sequentially setting the data writing phase T3 and the holding phase T4 within a single cycle, the pixel circuit 10 operates in different frame phases, thereby reducing the frame refresh rate of the second display area and lowering the power consumption of the display panel.

[0086] Taking a display panel with a frame refresh rate of 60Hz, m2=10, and r2=50 as an example, under this refresh method, when the pixel circuit 10 in the second display area is working, the data write frame and the hold frame do not alternate. Instead, within a second data refresh cycle, it first works in the data write frame to write the data signal Vdata until 10 data write frames are refreshed. Then, it continuously holds the data signal Vdata within 50 hold frames without writing the data signal Vdata.

[0087] If the first data refresh cycle does not include a hold frame, i.e., m1 = 60 and r1 = 0, the pixel circuit 10 of the first display area and the pixel circuit 10 of the second display area can sequentially refresh 10 data write frames during the data refresh cycle T1. Then, the pixel circuit 10 of the first display area continues to write the data signal Vdata, while the pixel circuit 10 of the second display area is in the hold phase T4 and only holds the data signal Vdata.

[0088] It should also be noted that, see Figure 8 Please refer to the following as well. Figures 1 to 7 ,in Figure 8 Taking a frame refresh rate of 60Hz for both the display panel and the first display area as an example, the number of data frames written when the pixel circuit 10 of the first and second display areas is working is shown, and the frame refresh rate of the second display area is calculated accordingly.

[0089] The ratio between the frame refresh rate of the pixel circuit 10 in the first display area and the frame refresh rate of the pixel circuit 10 in the second display area can be an integer or a non-integer. The larger the ratio, the lower the frame refresh rate of the second display area, and the more significant the power consumption reduction effect.

[0090] The number of data frames written in the first and second data refresh cycles can be set according to actual needs, but overall it still needs to satisfy m1+r1=m2+r2, and m1>m2>0, r2>r1≥0.

[0091] Please refer to some of the additional optional examples. Figures 1 to 9 In this optional example, the display panel may further include a first switch K1 and a second switch K2. Both the first switch K1 and the second switch K2 may be thin-film transistors.

[0092] The input terminal of the first switch K1 can be electrically connected to the source drive circuit, and the output terminal of the first switch K1 is electrically connected to the gate of the drive transistor M5. The input terminal of the second switch K2 can be connected to a high-impedance signal NC, and the output terminal of the second switch K2 can be electrically connected to the gate of the drive transistor M5.

[0093] When the pixel circuit 10 is operating in the data write frame mode, the control terminal of the first switch K1 receives a valid signal, and the control terminal of the second switch K2 receives a invalid signal. When the pixel circuit 10 is operating in the hold frame mode, the control terminal of the first switch K1 receives a invalid signal, and the control terminal of the second switch K2 receives a valid signal.

[0094] Alternatively, the input terminal of the first switch K1 can be connected to the digital-to-analog converter (DAC) in the source drive circuit, and the output terminal of the first switch K1 can pass through a buffer, such as a signal amplifier, and finally be connected to the gate of the drive transistor M5 via a data signal line.

[0095] In this example, the original driving architecture was optimized by adding a first switch K1 and a second switch K2, which enables the control signals accessed by the first switch K1 and the second switch K2 to control whether the gate of the driving transistor M5 in the pixel circuit 10 is connected to the data signal Vdata, providing an optional implementation scheme for inter-frame switching of data frames.

[0096] The types of the first switch K1 and the second switch K2 mentioned above can be different. For example, the first switch K1 can be an N-type thin-film transistor, and the second switch K2 can be a P-type thin-film transistor. The input terminal of the first switch K1 can be connected to a high-impedance signal, or it can also be connected to a VGMP (peak voltage output of the gamma power supply) signal or a VGSP (valley voltage output of the gamma power supply) signal, and can also refer to... Figure 10 Three third switches K3 are set in the middle. By outputting a valid signal to the control terminal of any third switch K3, different signals can be selectively connected to the input terminal of the first switch K1, thereby maintaining the pixel circuit 10 in a holding state.

[0097] The following example illustrates data refresh in the order of the first and second display areas. When both the pixel circuits 10 in the first and second display areas need to write data, the display area of ​​the display panel can achieve normal full-screen refresh display. That is, the pixel circuits 10 in the first and second display areas write data sequentially. At this time, the control terminal of the first switch K1 receives a valid signal, and the first switch K1 remains in the on state. The control terminal of the second switch K2 receives a non-valid signal, and the second switch K2 is turned off.

[0098] When the pixel circuit 10 in the first display area is operating in a data write frame, a valid signal is received at the control terminal of the first switch K1, the first switch K1 is turned on, and the second switch K2 is turned off. When the pixel circuit 10 in the first or second display area is operating in a hold frame, a valid signal is received at the control terminal of the second switch K2, the second switch K2 is turned on, and the first switch K1 is turned off.

[0099] In this example, by adding a first switch K1 and a second switch K2, the data signal Vdata is no longer continuously connected to the display area. Data is written only at regular intervals of a certain number of frames. This provides an optional implementation scheme for different display areas to achieve different frame refresh frequencies. Furthermore, since data is not written in real time, the driving power consumption of the source drive circuit is reduced.

[0100] In some additional optional examples, please see Figure 11 , Figure 12 as well as Figure 13 Please refer to the following as well. Figures 1 to 10 In this example, the display panel may also include a gate drive circuit VSR1 and a first-type clock signal line SCK.

[0101] The gate drive circuit VSR1 can be used to provide the scan signal SCAN to the pixel circuit 10. The first type clock signal line SCK can be used to provide the first type clock signal to the gate drive circuit VSR1. When the pixel circuit 10 is operating in hold frame mode, the first type clock signal is a first level signal.

[0102] It should be noted that the first level signal is a fixed level signal, such as a stable high level signal or a stable low level signal. When the pixel circuit 10 of the first display area or the second display area is in the holding frame of the stop writing data signal Vdata, the first type of clock signal provided to the gate drive circuit VSR1 is set to a fixed level state. This allows the gate drive circuit VSR1 to stop outputting the scan signal SCAN during the holding frame, thereby reducing the gate drive power consumption of the corresponding display area when in the holding frame. Based on reducing display power consumption by utilizing the frame refresh rate, the power consumption of the display panel is further reduced.

[0103] It should be noted that when the driving transistor M5 of the pixel circuit 10 is writing the data signal Vdata normally, the scan signal SCAN needs to switch different output states. Therefore, when setting the first type of clock signal line SCK, the first type of clock signal line SCK can include the first clock signal line SCK1 and the second clock signal line SCK2.

[0104] When pixel circuit 10 is operating in data write frame mode, the output timing of the first clock signal line SCK1 is at least partially opposite in potential to the output timing of the second clock signal line SCK2. For example, please refer to... Figure 12 and Figure 13 ,in Figure 13 During the control output phase of SCANm, the output timing potentials of the first clock signal line SCK1 and the second clock signal line SCK2 are opposite, thereby ensuring the stable output of the gate drive when the pixel circuit 10 is working in the data writing frame.

[0105] When the pixel circuit 10 is operating in hold frame mode, the first type of clock signal output by the first clock signal line SCK1 and the second clock signal line SCK2 can be a high-level signal.

[0106] by Figures 11 to 13 For example, combined with Figures 1 to 10 Provide an example, where Figure 11A schematic diagram of an optional structure with multiple gate drive circuits VSR1 cascaded is shown. Figure 12 A schematic diagram of an optional circuit structure for a single gate drive circuit VSR1 is shown. Figure 13 The diagram shows the output timing of the scan signal line SCANm, which is closest to the second display area in the first display area, and the scan signal line SCANm+1, which is closest to the first display area in the second display area, when the first display area and the second display area are arranged sequentially along the column direction. It also shows the output timing of the first clock signal line SCK1 and the second clock signal line SCK2, which send control signals to the gate drive circuit VSR1.

[0107] As can be seen, the scan signal lines from row 1 to row m are arranged within the projection area of ​​the first display area, while the scan signal lines from row m+1 onwards are located within the projection area of ​​the second display area. When the pixel circuits 10 in the first display area are all operating in data writing frame mode, frame refresh can be performed in a top-to-bottom order. At this time, the gate drive circuit VSR1 can normally receive the first type of clock signal output from the first clock signal line SCK1 and the second clock signal line SCK2, realizing gate drive control. When the process reaches row m+1, the switching between the high and low potentials of the first clock signal line SCK1 and the second clock signal line SCK2 stops, and a fixed level is maintained. This prevents the output of the scan signal SCAN to the pixel circuit 10 after row m, keeping the row closed. Therefore, the second display area after row m cannot perform data refresh and retains the image from the previous frame.

[0108] In these examples, by setting the first clock signal line SCK1 and the second clock signal line SCK2, the pixel circuit 10 can achieve normal gate drive control when operating in a data write frame. When the pixel circuit 10 operates in a hold frame, by maintaining the first type of clock signal output from the first clock signal line SCK1 and the second clock signal line SCK2 at a fixed level, such as a high level, the power consumption of the gate control circuit can be reduced.

[0109] In some additional optional examples, please see Figures 14 to 16 Please refer to the following as well. Figures 1 to 13 The aforementioned display panel may also include a light-emitting driving circuit VSR2 and a second-type clock signal line ECK.

[0110] The light-emitting driving circuit VSR2 can be used to provide the light-emitting control signal EM to the pixel circuit 10. The second type clock signal line ECK can be used to provide the second type clock signal to the light-emitting driving circuit VSR2. When the pixel circuit 10 is operating in hold frame mode, the second type clock signal is a second level signal.

[0111] It should be noted that the aforementioned light-emitting driving circuit VSR2 can provide a light-emitting control signal EM to the pixel circuit 10 via the light-emitting control signal line, allowing the light-emitting element 20 to selectively enter the light-emitting stage. The aforementioned second-level signal may or may not be the same as the first-level signal. The second-level signal can also be a fixed-level signal, such as a stable low-level signal or a stable high-level signal.

[0112] When the pixel circuit 10 of the first or second display area is in the holding frame of the stop writing data signal Vdata, the second type of clock signal provided to the light-emitting drive circuit VSR2 at this time is set to a fixed level. This enables the light-emitting drive circuit VSR2 to stop outputting the light-emitting control signal EM during the holding frame, thereby reducing the light-emitting control power consumption of the corresponding display area when in the holding frame. Based on reducing display power consumption by utilizing the frame refresh rate, the power consumption of the display panel is further reduced.

[0113] It should be noted that when the driving transistor M5 of the pixel circuit 10 is writing the data signal Vdata normally, the light emission control signal EM needs to switch between different states. Therefore, when setting the second type of clock signal line ECK, the second type of clock signal line ECK can include the third clock signal line ECK1 and the fourth clock signal line ECK2.

[0114] When pixel circuit 10 is operating in data write frame mode, at least a portion of the output timing of the third clock signal line ECK1 and the output timing of the fourth clock signal line ECK2 are at opposite potentials. For example, see... Figure 16 ,in Figure 16 During the control output phase of EMm, the output timing potentials of the third clock signal line ECK1 and the fourth clock signal line ECK2 are opposite, thereby ensuring the stable output of the light emission control signal EM when the pixel circuit 10 is working in the data writing frame.

[0115] When the pixel circuit 10 is operating in hold frame mode, the second type of clock signals output by the third clock signal line ECK1 and the fourth clock signal line ECK2 can both be second level signals, for example, the second level signals can both be low level signals.

[0116] by Figures 14 to 16 , combined Figures 1 to 13 Provide an example, where Figure 14 A schematic diagram showing an optional cascade of multiple LED driver circuits VSR2 is provided. Figure 15 A schematic diagram of an optional circuit structure for a single light-emitting driver circuit VSR2 is shown. Figure 16The diagram shows the output timing of the light-emitting control signal line EMm, which is closest to the second display area in the first display area, and the light-emitting control signal line EMm+1, which is closest to the first display area in the second display area, when the first display area and the second display area are arranged sequentially along the column direction. It also shows the output timing of the third clock signal line ECK1 and the fourth clock signal line ECK2, which send control signals to the light-emitting drive circuit VSR2 at this time.

[0117] As can be seen, the light emission control signal lines from row 1 to row m are arranged within the projection range of the first display area, while the light emission control signal lines from row m+1 onwards are located within the projection range of the second display area. When the pixel circuits 10 in the first display area are all operating in data writing frame mode, frame refresh can be performed in a top-to-bottom order. At this time, the light emission driving circuit VSR2 can normally receive the second type of clock signals output from the third clock signal line ECK1 and the fourth clock signal line ECK2, realizing light emission driving control. However, when the process reaches row m+1, the switching between the high and low potentials of the third clock signal line ECK1 and the fourth clock signal line ECK2 stops, and a fixed level is maintained. This prevents the output of the light emission control signal EM to the pixel circuit 10 after row m, keeping the row in a closed state. Consequently, the second display area after row m cannot perform data refresh and retains the image from the previous frame.

[0118] In these examples, by setting the third clock signal line ECK1 and the fourth clock signal line ECK2, the pixel circuit 10 can achieve normal light emission drive control when operating in a data write frame. When the pixel circuit 10 operates in a hold frame, by maintaining the second type of clock signal output from the third clock signal line ECK1 and the fourth clock signal line ECK2 at a fixed level, such as a high level or a low level, the power consumption of the light-emitting gate control circuit can be reduced.

[0119] The above text combines Figures 1 to 16 The present invention describes in detail the display panel of the embodiments of the present invention. Based on this, the present application also protects a display device, which may be at least one of wearable devices, cameras, mobile phones, tablet computers, displays, televisions, and vehicle-mounted display terminals. This display device includes the display panel provided in the above embodiments, and therefore possesses all the beneficial effects of the aforementioned display panel.

[0120] Furthermore, the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0121] It should be understood that in the embodiments of this application, "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0122] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display panel, characterized by, include: A pixel circuit and a light-emitting element, wherein the pixel circuit is used to provide a driving current to the light-emitting element; The frame refresh rate of the pixel circuit located in the first display area is F1, and the frame refresh rate of the pixel circuit located in the second display area is F2. Where F1>F2 The pixel circuit includes a driving transistor; The display panel also includes: a first switch, a second switch, and three third switches. The input terminal of the first switch is electrically connected to the source drive circuit, and the output terminal of the first switch is electrically connected to the gate of the drive transistor through a data signal line. The input terminal of the second switch is electrically connected to the output terminals of the three third switches, and the output terminal of the second switch is electrically connected to the gate of the driving transistor through the data signal line; The input terminals of the three third switches are respectively connected to a high-impedance signal, a VGMP signal, and a VGSP signal; When the pixel circuit is working in the data writing frame, the control terminal of the first switch is connected to a valid signal, and the control terminal of the second switch is connected to a non-valid signal. When the pixel circuit is operating in hold frame mode, the control terminal of the first switch is connected to an invalid signal, while the control terminal of the second switch and the control terminal of one of the three third switches are connected to an valid signal.

2. The display panel according to claim 1, characterized in that, The frame includes a data write frame or a hold frame; in the data write frame, the source drive circuit writes a data signal to the gate of the drive transistor; in the hold frame, the source drive circuit does not write a data signal to the gate of the drive transistor. A data refresh cycle of the display panel includes a first data refresh cycle corresponding to the first display area and a second data refresh cycle corresponding to the second display area; The first data refresh cycle corresponding to the first display area includes m1 data write frames and r1 hold frames; The second data refresh cycle corresponding to the second display area includes m2 data write frames and r2 hold frames; Where m1+r1=m2+r2, and m1>m2>0, r2>r1≥0.

3. The display panel according to claim 2, characterized in that, The second data refresh cycle corresponding to the second display area includes n sequentially set data refresh sub-cycles, each sub-cycle comprising m³ data write frames and r³ hold frames. Where m2=n*m3, r2=n*r3, n≥2.

4. The display panel according to claim 2, characterized in that, The second data refresh cycle corresponding to the second display area includes a data writing phase and a holding phase set sequentially. The data writing phase includes m2 data writing frames, and the holding phase includes r2 holding frames.

5. The display panel according to claim 1, characterized in that, The frame includes a data write frame or a hold frame; The display panel also includes: A gate driving circuit is used to provide a scanning signal to the pixel circuit; The first type of clock signal line is used to provide the first type of clock signal to the gate drive circuit; When the pixel circuit operates in the holding frame, the first type of clock signal is a first level signal.

6. The display panel according to claim 5, characterized in that, The first type of clock signal line includes a first clock signal line and a second clock signal line. When the pixel circuit is operating in the data write frame, the output timing of the first clock signal line is at least partially opposite in potential to the output timing of the second clock signal line; When the pixel circuit is operating in the holding frame, the first level signals output by the first clock signal line and the second clock signal line are both high level signals.

7. The display panel according to claim 1, characterized in that, The frame includes a data write frame or a hold frame; The display panel also includes: A light-emitting driving circuit is used to provide light-emitting control signals to the pixel circuit; The second type of clock signal line is used to provide a second type of clock signal for the light-emitting driving circuit; When the pixel circuit is operating in the holding frame, the second type of clock signal is a second level signal.

8. The display panel according to claim 7, characterized in that, The second type of clock signal lines includes a third clock signal line and a fourth clock signal line. When the pixel circuit is operating in the data write frame, at least a portion of the output timing of the third clock signal line and the output timing of the fourth clock signal line are at opposite potentials. When the pixel circuit is operating in the holding frame, the second level signal output by the third clock signal line and the fourth clock signal line is a low level signal.

9. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1-8.

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