Display panel and display device

Abstract

The application discloses a display panel and a display device, the display panel comprising: a display area; the display area comprising a plurality of pixel circuits arranged in an array; the pixel circuit comprising a driving transistor and a reset module; the reset module being electrically connected to a first node at a gate of the driving transistor; the reset module comprising a first reset transistor and a second reset transistor; the first reset transistor and the second reset transistor being connected in series between a reset signal end and the first node; a gate of the first reset transistor being electrically connected to a first scan end, and a gate of the second reset transistor being electrically connected to a second scan end; wherein the first reset transistor and the second reset transistor are different in channel type; and a time of an effective pulse of a first scan signal of the first scan end overlapping with times of at least two effective pulses of a second scan signal of the second scan end. The technical scheme of the application can improve display lag and improve the display effect of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] Self-emissive display panels typically contain light-emitting elements, eliminating the need for a backlight module to provide a light source. This results in self-emissive display panels being thinner, lighter, and simpler in structure, making them a current research focus in the display field.

[0003] The light emission of the light-emitting elements in the display panel requires the corresponding driving transistors to drive them. Typically, a data signal is provided to the gate of the driving transistor, which then converts the data signal into a driving current and provides it to the light-emitting element to drive it to emit light.

[0004] However, when the light-emitting element emits light, the driving transistor is in a biased state. Especially in low-frequency display mode, the driving transistor is in a biased state for a long time, which causes the threshold voltage of the driving transistor to drift. This results in hysteresis in the driving transistor, which in turn causes display ghosting and affects the display effect of the display panel. Summary of the Invention

[0005] The present invention provides a display panel and a display device to improve display ghosting and enhance the display effect of the display panel.

[0006] According to one aspect of the present invention, a display panel is provided, comprising: a display area; the display area comprising a plurality of pixel circuits arranged in an array; the pixel circuits comprising driving transistors and a reset module;

[0007] The reset module is electrically connected to the gate of the driving transistor at the first node;

[0008] The reset module includes a first reset transistor and a second reset transistor; the first reset transistor and the second reset transistor are connected in series between the reset signal terminal and the first node; the gate of the first reset transistor is electrically connected to the first scan terminal, and the gate of the second reset transistor is electrically connected to the second scan terminal.

[0009] The first reset transistor and the second reset transistor have different channel types; the effective pulse time of the first scan signal at the first scan terminal overlaps with the time of at least two effective pulses of the second scan signal at the second scan terminal.

[0010] According to another aspect of the present invention, a display device is provided, comprising: the above-described display panel.

[0011] The technical solution of this invention connects a first reset transistor and a second reset transistor of different channel types in series between a reset signal terminal and a first node. When both the first and second reset transistors are simultaneously turned on, the reset signal at the reset signal terminal is written to the first node to reset the gate of the driving transistor electrically connected to the first node. Simultaneously, the timing of the effective pulse of the first scan signal received by the gate of the first reset transistor overlaps with the timing of at least two effective pulses of the second scan signal received by the gate of the second reset transistor. This ensures that the reset signal at the reset signal terminal resets the gate of the driving transistor at least twice within the overlap time of the effective pulses of the first and second scan signals, thereby placing the driving transistor in a stable reset state. This guarantees that the data signal of the current driving cycle can be accurately written to the gate of the driving transistor, enabling the driving transistor to provide accurate driving current based on the accurate data signal, driving the light-emitting element to emit light accurately. This, in turn, improves display ghosting and enhances the display effect of the display panel.

[0012] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0015] Figure 2 This is a schematic diagram of the pixel circuit in a display panel provided by an embodiment of the present invention;

[0016] Figure 3 This is a schematic diagram of the pixel circuit structure in another display panel provided by an embodiment of the present invention;

[0017] Figure 4 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention;

[0018] Figure 5 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0019] Figure 6This is a driving timing diagram of each pixel circuit in a display panel provided by an embodiment of the present invention;

[0020] Figure 7 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0021] Figure 8 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0022] Figure 9 This is a driving timing diagram of each pixel circuit in another display panel provided by an embodiment of the present invention;

[0023] Figure 10 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0024] Figure 11 This is a driving timing diagram of each pixel circuit in a display panel provided by an embodiment of the present invention;

[0025] Figure 12 This is a schematic diagram of the structure of a pixel circuit in a display panel provided in another embodiment of the present invention;

[0026] Figure 13 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0027] Figure 14 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0028] Figure 15 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0029] Figure 16 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0030] Figure 17 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0031] Figure 18 This is a driving timing diagram of each pixel circuit in a display panel provided by an embodiment of the present invention;

[0032] Figure 19 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present invention;

[0033] Figure 20 This is a schematic diagram of the pixel circuit structure of another display panel provided in an embodiment of the present invention;

[0034] Figure 21 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0035] Figure 22 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0036] Figure 23 This is a driving timing diagram of each pixel circuit in a display panel provided by an embodiment of the present invention;

[0037] Figure 24 This is a schematic diagram of the structure of a pixel circuit in a display panel provided in another embodiment of the present invention;

[0038] Figure 25 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0039] Figure 26 This is a schematic diagram of the structure of a pixel circuit in a display panel provided in another embodiment of the present invention;

[0040] Figure 27 This is a schematic diagram of the structure of a pixel circuit in a display panel provided in another embodiment of the present invention;

[0041] Figure 28 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0042] Figure 29 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0043] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0044] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0045] As described in the background section, when the driving transistor in the pixel circuit remains in a biased state for a long time, the driving transistor exhibits a hysteresis effect. This makes it impossible to accurately write the data signal of the screen to be switched to the gate of the driving transistor during screen switching. Consequently, the driving transistor cannot generate an accurate driving current, resulting in screen ghosting and affecting the display effect of the display panel.

[0046] To address the aforementioned technical problems, embodiments of the present invention provide a display panel comprising: a display area; the display area including a plurality of pixel circuits arranged in an array; each pixel circuit including a driving transistor and a reset module; the reset module being electrically connected to the gate of the driving transistor at a first node; the reset module including a first reset transistor and a second reset transistor; the first reset transistor and the second reset transistor being connected in series between a reset signal terminal and the first node; the gate of the first reset transistor being electrically connected to a first scan terminal, and the gate of the second reset transistor being electrically connected to a second scan terminal; wherein the first reset transistor and the second reset transistor have different channel types; the effective pulse time of the first scan signal at the first scan terminal overlaps with the time of at least two effective pulses of the second scan signal at the second scan terminal.

[0047] By employing the above technical solution, a first reset transistor and a second reset transistor with different channel types are connected in series between the reset signal terminal and the first node. When both the first and second reset transistors are turned on simultaneously, the reset signal at the control reset signal terminal is written to the first node to reset the gate of the driving transistor electrically connected to the first node. Simultaneously, the time of the effective pulse of the first scan signal received by the gate of the first reset transistor overlaps with the time of at least two effective pulses of the second scan signal received by the gate of the second reset transistor. This ensures that the reset signal at the reset signal terminal resets the gate of the driving transistor at least twice within the overlap time of the effective pulses of the first and second scan signals, thereby keeping the driving transistor in a stable reset state. This guarantees that the data signal of the current driving cycle can be accurately written to the gate of the driving transistor, enabling the driving transistor to provide accurate driving current according to the accurate data signal, driving the light-emitting element to emit light accurately, thereby improving display ghosting and enhancing the display effect of the display panel.

[0048] The above is the core idea of ​​this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings.

[0049] Figure 1This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the pixel circuit structure in a display panel provided by an embodiment of the present invention. Figure 3 This is a schematic diagram of the pixel circuit structure in another display panel provided by an embodiment of the present invention, as shown below. Figure 1 As shown, the display panel 100 includes a display area AA, which includes multiple pixel circuits P arranged in an array. Among them, as... Figure 2 As shown in Figure 3, the pixel circuit P includes at least a driving transistor T and a reset module 10. The reset module 10 is electrically connected to the gate of the driving transistor T at the first node N1. The reset module 10 includes a first reset transistor M11 and a second reset transistor M12. The first reset transistor M11 and the second reset transistor M12 are connected in series between the reset signal terminal VREF and the first node N1. The gate of the first reset transistor M11 is electrically connected to the first scan terminal SN, and the gate of the second reset transistor M12 is electrically connected to the second scan terminal S2.

[0050] The first reset transistor M11 and the second reset transistor M12 are connected in series between the reset signal terminal VREF and the first node N1, which can be understood as follows: Figure 2 As shown, the first terminal of the first reset transistor M11 is electrically connected to the reset signal terminal VREF, the second terminal of the first reset transistor M11 is electrically connected to the first terminal of the second reset transistor M12, and the second terminal of the second reset transistor M12 is electrically connected to the first node N1; or, as shown... Figure 3 As shown, the first terminal of the second reset transistor M12 is electrically connected to the reset signal terminal VREF, the second terminal of the second reset transistor M12 is electrically connected to the first terminal of the first reset transistor M11, and the second terminal of the first reset transistor M11 is electrically connected to the first node N1.

[0051] Continue to refer to Figure 2 or Figure 3 The first reset transistor M11 and the second reset transistor M12 have different channel types. The gate of the first reset transistor M11 is electrically connected to the first scan terminal S1, and the gate of the second reset transistor M12 is electrically connected to the second scan terminal S2. The effective pulse time of the first scan signal s1 of the first scan terminal S1 overlaps with the time of at least two effective pulses of the second scan signal s2 of the second scan terminal S2.

[0052] Specifically, the first reset transistor M11 and the second reset transistor M12 have different channel types. Specifically, when the first reset transistor M11 is an N-channel transistor, the second reset transistor M12 can be a P-channel transistor. In this case, when the first scan signal s1 at the first scan terminal S1 is high, the first reset transistor M11 is turned on, and when the first scan signal s1 at the first scan terminal S1 is low, the first reset transistor M11 is turned off. Correspondingly, when the second scan signal s2 at the second scan terminal S2 is high, the second reset transistor M12 is turned off, and when the second scan signal s2 at the second scan terminal S2 is low, the second reset transistor M12 is turned on. Thus, the effective pulse time of the first scan signal s1 is the time when the first scan signal s1 is high, and the effective pulse time of the second scan signal s2 is the time when the second scan signal s2 is low.

[0053] In other alternative embodiments, the first reset transistor can also be a P-channel transistor, and the second reset transistor can also be an N-channel transistor. In this case, when the first scan signal at the first scan terminal is low, the first reset transistor is turned on, and when the first scan signal at the first scan terminal is high, the first reset transistor is turned off. Similarly, when the second scan signal at the second scan terminal is high, the second reset transistor is turned on, and when the second scan signal at the second scan terminal is low, the second reset transistor is turned off. Thus, the effective pulse time of the first scan signal is the time when the first scan signal is low, and the effective pulse time of the second scan signal is the time when the second scan signal is high.

[0054] It is understood that high level and low level are relative level signals and do not represent the polarity of the signal. Under the premise of being able to grasp the core inventive point of the present invention, the present invention does not limit the polarity and specific value of high level and low level.

[0055] For ease of description, unless otherwise specified, the embodiments of the present invention use the first reset transistor M11 as an N-channel transistor and the second reset transistor M12 as a P-channel transistor as examples to illustrate the technical solutions of the embodiments of the present invention.

[0056] In this context, the active layer material of the N-channel transistor can include, but is not limited to, oxide semiconductor materials, such as indium gallium zinc oxide (IGZO), while the active layer material of the P-channel transistor can include, but is not limited to, low-temperature polycrystalline silicon (LTPS). This results in the P-channel transistor exhibiting higher mobility, while the N-channel transistor exhibits lower off-state leakage current. Thus, as... Figure 3As shown, when the first reset transistor M11 is an N-channel transistor and the second reset transistor M12 is a P-channel transistor, the first terminal of the second reset transistor M12 can be electrically connected to the reset signal terminal VREF, and the second terminal of the second reset transistor M12 can be electrically connected to the first terminal of the first reset transistor M11. The second terminal of the first reset transistor M11 is electrically connected to the first node N1. At this time, the first reset transistor of the N-channel transistor is directly electrically connected to the first node N1, that is, the first reset transistor M11 of the N-channel transistor is directly electrically connected to the gate of the driving transistor T. This allows for a situation where the driving transistor T does not need to be reset, and both the first reset transistor M11 and the second reset transistor M12 are in the off state. This reduces the leakage current between the node connecting the first reset transistor M11 and the second reset transistor M12 and the gate of the driving transistor, thereby ensuring the stability of the gate potential of the driving transistor T. Simultaneously, even if the P-channel second reset transistor M12 has a large leakage current, resulting in a large leakage current between the reset signal Vref at the reset signal terminal VREF and the node connecting the second reset transistor M12 and the first reset transistor M11 when the second reset transistor M12 is in the off state, the presence of the first reset transistor M11 will not affect the gate potential of the driving transistor T, thus ensuring the stability of the gate potential of the driving transistor T.

[0057] For example, Figure 4 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 3 and Figure 4As shown, when both the first reset transistor M11 and the second reset transistor M12 are in the ON state, the reset signal Vref at the reset signal terminal VREF can be transmitted to the first node N1 sequentially through the first reset transistor M11 and the second reset transistor. However, when at least one of the first reset transistor M11 and the second reset transistor M12 is in the OFF state, the reset signal Vref at the reset signal terminal VREF cannot be transmitted to the first node N1. At this time, by making the first scan signal s1 at the first scan terminal S1 an effective pulse and the second scan signal s1 at the second scan terminal S2 also an effective pulse, the first reset transistor M11 and the second reset transistor M12 can be in the ON state simultaneously. The reset signal Vref at the reset signal terminal VREF can be transmitted to the first node N1 sequentially through the first reset transistor M11 and the second reset transistor, that is, the reset signal Vref at the reset signal terminal VREF can be transmitted to the gate of the driving transistor T to reset the gate of the driving transistor T, so that the driving transistor T recovers from the bias state in the previous driving cycle to the reset state. The bias state can be understood as the state when the driving transistor T provides driving current according to its gate potential, and the reset state can be understood as the state when the gate potential of the driving transistor T no longer contains data signal, and the gate potential of the driving transistor T can maintain the driving transistor T in the on state during the subsequent data signal writing process.

[0058] Furthermore, when the effective pulse time of the first scan signal s1 of the first scan terminal S1 overlaps with the effective pulse time of at least two effective pulse times of the second scan signal s2 of the second scan terminal S2, the gate of the driving transistor T can be reset once during the overlap time of each effective pulse of the first scan signal s1 and the second scan signal s2. This allows the gate of the driving transistor T to be reset at least twice during the effective pulse time of the first scan signal s1, so that when the gate of the driving transistor T is reset, the data signal contained in the gate potential of the driving transistor T can be completely cleared, allowing the driving transistor T to be in a stable reset state, which is beneficial for the accurate writing of subsequent data signals.

[0059] In this embodiment of the invention, a first reset transistor and a second reset transistor with different channel types are connected in series between the reset signal terminal and the first node. When both the first and second reset transistors are turned on simultaneously, the reset signal at the control reset signal terminal is written to the first node to reset the gate of the driving transistor electrically connected to the first node. Simultaneously, the time of the effective pulse of the first scan signal received by the gate of the first reset transistor overlaps with the time of at least two effective pulses of the second scan signal received by the gate of the second reset transistor. This allows the reset signal at the reset signal terminal to reset the gate of the driving transistor at least twice during the overlap time of the effective pulses of the first and second scan signals. This ensures that the driving transistor is in a stable reset state, guaranteeing that the data signal of the current driving cycle can be accurately written to the gate of the driving transistor. This enables the driving transistor to provide accurate driving current according to the accurate data signal, driving the light-emitting element to emit light accurately, thereby improving display ghosting and enhancing the display effect of the display panel.

[0060] It should be noted that, Figure 4 The example only illustrates, by way of example, the overlap of the effective pulse time of the first scan signal s1 of the first scanning end S1 with the two effective pulse times of the second scan signal s2 of the second scanning end S2 in the same pixel circuit P. However, in this embodiment of the invention, the effective pulse time of the first scan signal s1 of the first scanning end S1 can also overlap with the effective pulse times of two or more (e.g., three, four, or five) effective pulse times of the second scan signal s2 of the second scanning end S2 in the same pixel circuit. Provided that the core inventive point of this embodiment of the invention can be achieved, this embodiment of the invention does not specifically limit this. For ease of description, unless otherwise specified, this embodiment of the invention uses the overlap of the effective pulse time of the first scan signal of the first scanning end with the two effective pulse times of the second scan signal of the second scanning end in the same pixel circuit as an example to illustrate the technical solution of this embodiment of the invention.

[0061] Optional, continue to refer to the references Figure 3 and Figure 4 In the same pixel circuit P, the start time t1 of the effective pulse of the first scan signal s1 is before the start time t2 of the first effective pulse of the second scan signal s2, and the end time t4 of the effective pulse of the first scan signal s1 is after the end time t3' of the last effective pulse of the second scan signal s2.

[0062] It is understandable that the time it takes for the display panel to display one frame is equivalent to one driving cycle of a pixel circuit P. Within one driving cycle of the pixel circuit P, the first scan signal s1 of the first scan terminal S1 may include one valid pulse, and the start time t2 of the valid pulse of the first scan signal s1 is the moment when the first scan signal s1 changes from low to high level, and the end time t4 of the valid pulse of the first scan signal s1 is the moment when the first scan signal s1 changes from high to low level. Similarly, within one driving cycle of the pixel circuit P, the second scan signal s2 of the second scan terminal S2 may include at least two valid pulses, and the first valid pulse of the second scan signal s2... The start time t2 of the second scan signal s2 is the moment when the second scan signal s2 first transitions from high level to low level. The end time t3 of the first valid pulse of the second scan signal s2 is the moment when the second scan signal s2 first transitions from low level to high level. The start time t2' of the last valid pulse of the second scan signal s2 is the moment when the second scan signal s2 last transitions from high level to low level. The end time t3' of the last valid pulse of the second scan signal s2 is the moment when the second scan signal s2 last transitions from low level to high level.

[0063] Specifically, in the same pixel circuit P, by setting the start time t1 of the effective pulse of the first scan signal s1 before the start time t2 of the first effective pulse of the second scan signal s2, the conduction time of the first reset transistor M11 controlled by the first scan signal s1 is before the first conduction time of the second reset transistor M12 controlled by the second scan signal s2; and by setting the end time t4 of the effective pulse of the first scan signal s1 after the end time t3' of the last effective pulse of the second scan signal s2, the off time of the first reset transistor M11 controlled by the first scan signal s1 is after the off time of the second reset transistor M12 controlled by the second scan signal s2. Thus, during the conduction time of the second reset transistor M12, the first reset transistor M11 can be ensured to be in the conduction state, so that the reset signal Vref at the reset signal terminal VREF can be written to the first node N1 through the first reset transistor M11 and the second reset transistor M12. This allows the time for the reset signal Vref to be written to the first node N1 to be controlled by the effective pulse time of the second scan signal s2, ensuring that at least two reset signals Vref can be provided to the first node N1 when the first scan signal s1 is an effective pulse, so as to reset the gate of the driving transistor T at least twice.

[0064] It is understandable that, since the effective pulse width and number of the first scan signal s1 and the effective pulse of the second scan signal s2 are different, different scan circuits need to be set up to provide the first scan signal s1 and the second scan signal s2 to each pixel circuit P respectively.

[0065] Optional, Figure 5 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, in conjunction with reference to the reference. Figure 3 and Figure 5 The display area AA also includes multiple first scan lines 141 and second scan lines 142; at least some of the pixel circuits P in the same row have their first scan terminals S1 electrically connected to the same first scan line 141; at least some of the pixel circuits P in the same row have their second scan terminals S2 electrically connected to the same second scan line 142; at this time, the first scan line 141 can transmit a first scan signal s1 to the first scan terminal S1 of each pixel circuit P electrically connected to it, so that the first scan signal s1 controls the conduction or disconnection of the first reset transistor M11 in each pixel circuit P; the second scan line 142 can transmit a second scan signal s2 to the second scan terminal S2 of each pixel circuit P electrically connected to it, so that the second scan signal s2 controls the conduction or disconnection of the second reset transistor M12 in each pixel circuit P.

[0066] In this embodiment, at least some pixel circuits P located in the same row have their first scanning terminals S1 electrically connected to the same first scanning line 141, meaning that some or all of the pixel circuits P located in the same row have their first scanning terminals S1 electrically connected to the same first scanning line 141. Correspondingly, at least some pixel circuits P located in the same row have their second scanning terminals S2 electrically connected to the same second scanning line 142, meaning that some or all of the pixel circuits P located in the same row have their second scanning terminals S2 electrically connected to the same second scanning line 142. While ensuring the core inventive points of this embodiment are achieved, this embodiment does not specifically limit the case where pixel circuits P located in the same row share the first scanning line 141 and the second scanning line 142. For ease of description, unless otherwise specified, this embodiment uses the example of all pixel circuits P located in the same row being electrically connected to both the same first scanning line 141 and the same second scanning line 142 to illustrate the technical solution of this embodiment.

[0067] refer to Figure 2 , Figure 4 and Figure 5The display panel 100 also includes a non-display area NA surrounding the display area AA; the non-display area NA includes a first scanning circuit 110 and a second scanning circuit 120; the first scanning circuit 110 includes a plurality of cascaded first scanning units 111, and the second scanning circuit 120 includes a plurality of cascaded second scanning units 121; each level of the first scanning unit 111 is electrically connected to N adjacent first scanning lines 141; each level of the first scanning unit 111 is used to provide a first scanning signal s1 to each first scanning line 141; the effective pulses of the first scanning signal s1 output by each level of the first scanning unit 111 are shifted sequentially, and the shift amount of the effective pulses of the first scanning signal s1 at each level is less than the width of the effective pulse of the first scanning signal s1; each level of the second scanning unit 121 is electrically connected to each corresponding second scanning line 142; the effective pulses of the second scanning signal s2 output by each level of the second scanning unit 121 are shifted sequentially, and the shift amount of the effective pulses of the second scanning signal s2 output by each level of the second scanning unit 121 is greater than or equal to the width of the effective pulse of the second scanning signal s2; wherein, N is a positive integer greater than or equal to 2.

[0068] It is understood that the first scanning unit 111 may include a signal input terminal and a signal output terminal. In this case, the signal input terminal of the first-level first scanning unit 111 receives a start pulse signal, and the signal input terminals of other levels of the first scanning unit 111 are electrically connected to the signal output terminals of their respective preceding levels. For example, the signal input terminal of the second-level first scanning unit 111 is electrically connected to the signal output terminal of the first-level first scanning unit 111, and the signal input terminal of the third-level first scanning unit 111 is electrically connected to the signal output terminal of the second-level first scanning unit 111. Similarly, the second scanning unit 121 may include a signal input terminal and a signal output terminal. In this case, the signal input terminal of the first-level second scanning unit 121 receives a start pulse signal, and the signal input terminals of other levels of the second scanning unit 121 are electrically connected to the signal output terminals of their respective preceding levels. For example, the signal input terminal of the second-level second scanning unit 121 is electrically connected to the signal input terminal of the first-level second scanning unit 121, and the signal input terminal of the third-level second scanning unit 121 is electrically connected to the signal input terminal of the second-level second scanning unit 121. Among them, the signal output terminal of the first scanning unit 111 at each level is used to output the first scanning signal s1, and the signal output terminal of the second scanning unit 121 at each level is used to output the second scanning signal s2.

[0069] Each first scanning unit 111 is electrically connected to N adjacent first scanning lines 141, so that the pixel circuit P electrically connected to the N adjacent first scanning lines 141 shares the same first scanning unit 111. Therefore, it is not necessary to set a separate first scanning unit 111 for each pixel level P electrically connected to each first scanning line 141, which helps to reduce the number of first scanning units 111 set in the first scanning circuit 110. Furthermore, since the first scanning circuit 110 is set in the non-display area NA of the display panel 100, when the number of first scanning units 111 set in the first scanning circuit 110 is small, the structure of the display panel 100 can be simplified, which helps to reduce the size of the non-display area NA, thereby helping to achieve a narrow bezel of the display panel 100. Simultaneously, the effective pulses of the first scan signal s1 output by each stage of the first scan unit 111 are shifted sequentially, and the shift amount of the effective pulses of each stage of the first scan signal 111 is less than the width of the effective pulse of the first scan signal s1. That is, the time overlaps of the effective pulses of the first scan signal s1 output by two or more adjacent and cascaded first scan units 111. Compared with the case where the time overlaps of the effective pulses of the first scan signal s1 output by two or more adjacent and cascaded first scan units 111, this can effectively shorten the time between the start time of the effective pulse of the first scan signal s1 output by the first stage first scan unit 111 and the last stage first scan unit 111. The time between the termination of the effective pulse of the first scan signal s1 is shortened, which helps to shorten the reset time of the driving transistor T in each pixel circuit P. In addition, when the driving cycle of the pixel circuit P is fixed, shortening the reset time of each driving transistor T helps to extend the light-emitting stage time of each pixel circuit P. Furthermore, since the display brightness of the display panel 100 is related to the integral of time by the human eye, the longer the time, the larger the integral value, and the stronger the display brightness of the display panel 100 perceived by the human eye. Therefore, by extending the light-emitting stage time, it is beneficial to improve the display brightness of the display panel 100 and improve the display effect of the display panel 100.

[0070] It should be noted that, Figure 5 The example shown is only exemplarily illustrated when each first scanning unit 111 is electrically connected to two second scanning lines 142, i.e., N equals 2. In the embodiments of the present invention, the value of N can be any positive integer greater than or equal to 2, i.e., the number of second scanning lines 142 electrically connected to each second scanning unit 121 can be two, three or more, which can be set according to actual needs. The embodiments of the present invention do not make specific limitations in this regard.

[0071] Furthermore, each level of the second scanning unit 121 is electrically connected to a second scanning line 142, such that each pixel circuit P that is electrically connected to the same second scanning line 142 and located in the same row shares the same second scanning unit 121. At the same time, the effective pulses of the second scanning signal s2 output by each level of the second scanning unit 121 are shifted sequentially, and the shift amount of the effective pulses of the second scanning signal s2 output by each level of the second scanning unit 121 is greater than or equal to the width of the effective pulse of the second scanning signal s2. At this time, the time of the effective pulses of the second scanning signal s2 output by any adjacent N levels of the second scanning unit 121 can be non-overlapping, so that the second reset transistors M12 in the pixel circuits P that are electrically connected to the consecutive N levels of the second scanning unit 121 and located in different rows will not be turned on simultaneously. Thus, although the first scan signal s1 output by each first scan unit 111 can control the first reset transistor M11 in each pixel circuit P electrically connected by N first scan lines 142 to be turned on simultaneously, the reset signal Vref of the reset signal terminal VREF can only be written to the first node N1 when the first reset transistor M11 and the second reset transistor M12 are turned on simultaneously. Therefore, when the second reset transistor M12 of the pixel circuit P located in different rows is not turned on at the same time, the time-division reset of the driving transistor T in each pixel circuit P located in different rows can still be achieved.

[0072] It should be noted that, Figure 5 The illustration only shows the first scanning circuit 110 and the second scanning circuit 120 located on opposite sides of the display area AA, so that the size of the non-display area NA on opposite sides of the display area AA remains consistent, thereby improving the overall aesthetics of the display panel. In other embodiments of the present invention, the first scanning circuit 110 and the second scanning circuit 120 may also be located on the same side of the display area AA, or the first scanning circuit 110 and the second scanning circuit 120 may also be located on adjacent sides of the display area AA. Provided that the core inventive points of the embodiments of the present invention are achieved, the specific arrangement of the first scanning circuit 110 and the second scanning circuit 120 is not limited in the embodiments of the present invention.

[0073] In an alternative embodiment, Figure 6 This is a driving timing diagram of each pixel circuit in a display panel provided by an embodiment of the present invention, in conjunction with reference to... Figure 3 , Figure 5 and Figure 6The time interval between the start times of the effective pulses of the first scan signal s1 output by two adjacent first scan units 111 is the first time t11; in the continuous N-level second scan units 121, the effective pulses of the second scan signal s2 output by each level of the second scan unit 121 are shifted sequentially, and the time t20 of the effective pulses of the second scan signal s2 output by each level of the second scan unit 121 does not overlap; the total time of the first effective pulse of the second scan signal s2 output by each level of the second scan unit 121 in the continuous N-level second scan units 121 is the second time N*t20; wherein, the first time t11 is greater than or equal to the second time N*t20.

[0074] For example, taking N=2 as an example, the first scanning unit 111 is electrically connected to the first scanning terminal S1 of the two adjacent rows of pixel circuits P through two adjacent first scanning lines 141. The second scanning terminals S2 of the two rows of pixel circuits P are also electrically connected to two second scanning units 121 through two second scanning lines 142. For example, the first scanning terminals S1 of each pixel circuit P located in the first and second rows are electrically connected to the first-level first scanning unit 111 through two first scanning lines 141. The first scanning terminals S1 of each pixel circuit P located in the third and fourth rows are electrically connected to the second-level first scanning unit 111 through another two first scanning lines 141. Each pixel in the first row... The second scanning terminal S2 of circuit P is electrically connected to the first-level second scanning unit 121 through a second scanning line 142. The second scanning terminal S2 of each pixel circuit P located in the second row is electrically connected to the second-level second scanning unit 121 through another second scanning line 142. At this time, the effective pulses of the first scanning signal s11 output by the first-level first scanning unit 111 and the first scanning signal s12 output by the second-level first scanning unit 111 have a certain shift amount, which is the first time t11. This ensures that when the effective pulse of the first scanning signal s11 output by the first-level first scanning unit 111 reaches t11, the second-level first scanning unit 111 begins to output the first... The effective pulse of the scanning signal s12; the time for each effective pulse of the second scanning signal s2 output by the second scanning unit 121 is t20. At this time, the sum of the time t20 for the first effective pulse of the second scanning signal s21 output by the first-level second scanning unit 121 and the time t20 for the first effective pulse of the second scanning signal s22 output by the second-level second scanning unit 121 is the second time 2*t20. By making the first time t11 greater than or equal to the second time 2*t20, the driving of each pixel circuit P electrically connected to the first-level first scanning unit 111 can be achieved before the effective pulse of the first scanning signal s12 output by the second-level first scanning unit 111 begins. Transistor T is reset at least once, thereby enabling each pixel circuit P electrically connected to different first scanning units 111 to be reset at different time periods. At the same time, since the effective pulses of the second scanning signal s2 output by each level of the N-level second scanning units 121 are shifted sequentially and the time of the effective pulses of the second scanning signal s2 output by each level of the second scanning units 121 does not overlap, the driving transistors T of pixel circuits P in different rows can be reset at different time periods. This prevents the driving transistors T of pixel circuits P in different rows from being reset simultaneously, which would affect the normal operation of the display panel and thus ensure that the display panel displays and emits light normally.

[0075] Optional, continue to refer to Figure 3The pixel circuit P also includes a data writing transistor M2 and a first compensation transistor M31; the gate of the first compensation transistor M31 is electrically connected to the third scan terminal S3, the first terminal of the first compensation transistor M31 is coupled to the second terminal of the driving transistor T at the third node N3, and the second terminal of the first compensation transistor M31 is coupled to the gate of the driving transistor T at the first node N1; the gate of the data writing transistor M2 is electrically connected to the fourth scan terminal S4, the first terminal of the data writing transistor M2 is connected to the data signal terminal DATA, and the second terminal of the data writing transistor M2 is electrically connected to the first terminal of the driving transistor T at the second node N2; in the same pixel circuit P, the effective pulse time of the third scan signal s3 of the third scan terminal S3 overlaps with the effective pulse time of the fourth scan signal s4 of the fourth scan terminal S4.

[0076] The channel type of the data writing transistor M2 may be the same as or different from the channel type of the first compensation transistor M31, and this embodiment of the invention does not specifically limit this. In an optional embodiment, the channel type of the data writing transistor M2 may be different from the channel type of the first compensation transistor M31; that is, when the data writing transistor M2 is a P-channel transistor, the first compensation transistor M31 is an N-channel transistor, or, when the data writing transistor M2 is an N-channel transistor, the first compensation transistor M31 is a P-channel transistor.

[0077] It is understandable that when the first compensation transistor M31 is an N-channel transistor, the third scan signal s3 at the third scan terminal S3 is at a low level, the first compensation transistor M31 is off, the third scan signal s3 at the third scan terminal S is at a high level, and the first compensation transistor M31 is on. At this time, the time when the third scan signal s3 is at a high level is the effective pulse time of the third scan signal s3. When the first compensation transistor M31 is a P-channel transistor, the first compensation transistor M31 is on under the control of the low level of the third scan signal s3 and off under the control of the high level of the third scan signal s3. At this time, the time when the third scan signal s3 is at a low level is the effective pulse time of the third scan signal s3.

[0078] Correspondingly, when the data writing transistor M2 is a P-channel transistor, the fourth scan signal s4 at the fourth scan terminal S4 is high, and the data writing transistor M2 is off; when the fourth scan signal s4 at the fourth scan terminal S4 is low, the data writing transistor M2 is on. At this time, the time when the fourth scan signal s4 is low is the effective pulse time of the fourth scan signal s4. When the data writing transistor M2 is an N-channel transistor, the data writing transistor M2 is on under the control of the high level of the fourth scan signal s4 and off under the control of the low level of the fourth scan signal s4. At this time, the time when the fourth scan signal s4 is high is the effective pulse time of the fourth scan signal s4.

[0079] In this process, the effective pulse time of the third scan signal s3 at the third scan terminal S3 overlaps with the effective pulse time of the fourth scan signal s4 at the fourth scan terminal S4. During this overlap, the data writing transistor M2 and the first compensation transistor M31 are simultaneously in the conducting state. At this time, the data signal Vdata at the data signal terminal DATA can be transmitted to the second node N2 through the conducting data writing transistor M2. If the driving transistor T is also in the conducting state at this time, the driving transistor T can continue to transmit the data signal Vdata to the third node N3, and then transmit it to the gate of the driving transistor T through the conducting first compensation transistor M31.

[0080] Understandably, since the driving transistor T needs to be in a conducting state when the data signal Vdata is written to the gate of the driving transistor T at the data signal terminal DATA, the gate of the driving transistor T can be reset by the reset signal Vref at the reset signal terminal VREF before writing the data signal to the gate of the driving transistor T. This ensures that the difference between the gate potential and the first electrode potential of the driving transistor T is sufficient to ensure that the driving transistor T is in a conducting state when the data signal Vdata is written to the gate of the driving transistor T. Thus, the reset phase of resetting the gate of the driving transistor T by using the reset signal Vref at the reset signal terminal VREF should be before the writing phase of writing the data signal to the gate of the driving transistor T. At this time, the time of at least one valid pulse of the second scan signal s2 used to control the second reset transistor M12 to be on or off should be before the overlap time of the valid pulse of the third scan signal s3 and the valid pulse of the fourth scan signal s4. In an optional embodiment, the times of at least two valid pulses of the second scan signal s2 are all before the overlap time of the valid pulses of the third scan signal s3 and the fourth scan signal s4, so that the data signal Vdata can be written after the gate of the driving transistor T is reset at least twice. This ensures that the gate potential of the driving transistor T can maintain the driving transistor T in the on state during the writing stage of the data signal Vdata, thereby ensuring the accurate writing of the data signal Vdata at the data signal terminal DATA.

[0081] Furthermore, since the gate of the driving transistor T is reset before writing the data signal Vdata to its gate, the gate potential of the driving transistor T is consistent with the reset signal Vref at the reset signal terminal VREF. As the data signal Vdata is written, the gate potential of the driving transistor T gradually changes until the potential between the gate potential and its first electrode potential equals the threshold voltage Vth of the driving transistor T. At this point, the critical conduction condition of the driving transistor T is reached, so that at the end of the data signal Vdata writing phase, the gate potential of the driving transistor T is Vdata + Vth. Thus, after the data signal Vdata writing phase ends, the driving current provided by the driving transistor T based on its gate potential is independent of its own threshold voltage.

[0082] In an alternative embodiment, reference continues. Figure 3The pixel circuit P may also include a light-emitting control module 40 and a light-emitting element D; in the same pixel circuit P, the light-emitting control module 40 is connected in series with the driving transistor T and the light-emitting element D between the positive power supply terminal PVDD and the negative power supply terminal PVEE; the light-emitting control module 40 can control the time when the positive power supply terminal PVDD and the negative power supply terminal PVEE form a current path, that is, the driving transistor T provides a driving current to the light-emitting element D according to its gate potential, so as to control the time when the light-emitting element D emits light.

[0083] In an exemplary embodiment, the light emission control module 40 may include a first light emission control transistor M41 and a second light emission control transistor M42. In the same pixel circuit P, when the channel types of the first light emission control transistor M41 and the second light emission control transistor M42 are the same, the gates of the first light emission control transistor M41 and the second light emission control transistor M42 may both be electrically connected to the same light emission control terminal EM. The first electrode of the first light emission control transistor M41 is electrically connected to the positive power supply terminal PVDD, the second electrode of the first light emission control transistor M41 is electrically connected to the first electrode of the driving transistor T at the second node N2, the second light emission control transistor M42 is electrically connected to the second electrode of the driving transistor T at the third node N3, and the second light emission control transistor M42 is electrically connected to the anode of the light emission element D. The cathode of the light emission element D is electrically connected to the negative power supply terminal PVEE. The effective pulse time of the light emission control signal Em of the light emission control terminal EM does not overlap with the effective pulse time of the first scan signal s1, the effective pulse time of the second scan signal s2, the effective pulse time of the third scan signal s2, and the effective pulse time of the fourth scan signal s4.

[0084] It is understood that the first light-emitting control transistor M41 and the second light-emitting control transistor M42 have the same channel type, that is, both the first light-emitting control transistor M41 and the second light-emitting control transistor M42 are either N-channel transistors or both are P-channel transistors. When both the first light-emitting control transistor M41 and the second light-emitting control transistor M42 are N-channel transistors, when the light-emitting control signal Em at the light-emitting control terminal EM is high, the first light-emitting control transistor M41 and the second light-emitting control transistor M42 are simultaneously turned on; and when the light-emitting control signal Em at the light-emitting control terminal EM is low, the first light-emitting control transistor M41 and the second light-emitting control transistor M42 are simultaneously turned off. In this case, the effective pulse duration of the light-emitting control signal Em is the same as the duration when Em is high. Conversely, when both the first light-emitting control transistor M41 and the second light-emitting control transistor M42 are P-channel transistors, when the light-emitting control signal Em at the light-emitting control terminal EM is low, both the first light-emitting control transistor M41 and the second light-emitting control transistor M42 are simultaneously turned on, and when the light-emitting control signal Em at the light-emitting control terminal EM is high, both the first light-emitting control transistor M41 and the second light-emitting control transistor M42 are simultaneously turned off. In this case, the effective pulse duration of the light-emitting control signal Em is the same as the duration when Em is low. Under the premise of achieving the core inventive points of this embodiment, this embodiment does not specifically limit the channel type of the first light-emitting control transistor M41 and the second light-emitting control transistor M42.

[0085] For example, taking the first reset transistor M11 and the first compensation transistor M31 as N-channel transistors, and the second reset transistor M12, the data writing transistor M2, the first light-emitting control transistor M41, the second light-emitting control transistor M42, and the driving transistor T as P-channel transistors, Figure 7 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention, in conjunction with reference to the reference. Figure 3 and Figure 7 Each pixel circuit P's driving cycle includes two reset phases t21 and t22, a write phase t30, and a light emission phase t40. After the previous driving cycle of pixel circuit P ends, the light emission control signal Em changes from a low-level active pulse to a high-level active pulse, and the first scan signal s1 changes from a low-level active pulse to a high-level active pulse.

[0086] When entering the first reset phase t21 of the current driving cycle, the first scan signal s1 is a high-level valid pulse and the second scan signal s2 is a low-level valid pulse, causing the first reset transistor M11 and the second reset transistor M12 to be turned on simultaneously. The reset signal at the reset signal terminal VREF is transmitted to the first node N1 through the turned-on first reset transistor M11 and the second reset transistor M12 to perform the first reset on the gate of the driving transistor T electrically connected to the first node N1. After the first reset phase t21 of the pixel circuit P ends, the first scan signal s1 of the pixel circuit P remains a high-level valid pulse, while the second scan signal s2 jumps to a high level, causing the second reset transistor M12 of the pixel circuit P to be turned off.

[0087] When entering the second reset stage t22, the first scan signal s1 remains a high-level valid pulse, and the second scan signal s2 jumps to a low-level valid pulse again. The first reset transistor M11 and the second reset transistor M12 are turned on simultaneously, thereby resetting the gate of the driving transistor T again and providing a reset signal Verf to the gate of the driving transistor T, so that the driving transistor T returns to the reset state. This is to prevent the driving transistor T from failing to return to the reset state from the bias state of the previous driving cycle after the first reset. After resetting the gate of the driving transistor T twice, the potential of the first node N1 will be consistent with the reset signal Vref, so that the potential difference between the gate potential of the driving transistor T and the data signal corresponding to any display brightness can meet the condition for the driving transistor T to conduct accurately.

[0088] When entering the write phase t30, the first scan signal s1 is low, the second scan signal s2 is high, the first reset transistor M11 and the second reset transistor M12 are off, the third scan signal s3 is a valid high-level pulse, the fourth scan signal s4 is a valid low-level pulse, the data write transistor M2 and the first compensation transistor M31 are turned on, and the data signal Vdata at the data signal terminal DATA is transmitted to the second node N2 through the turned-on data write transistor M2, making the first terminal potential of the driving transistor T equivalent to the voltage of the data signal Vdata. Since after the second reset phase t22, the gate potential of the driving transistor T is equal to the reset voltage... When the voltage of the signal Vref is equal, the potential difference between the gate of the driving transistor T and its first electrode becomes Vdata-Vref. The driving transistor T is in the on state, and the data signal Vdata continues to be transmitted to the third node N3 through the on driving transistor T, and then to the gate of the driving transistor T through the first compensation transistor M31 electrically connected between the third node N3 and the first node N1, until the gate potential of the driving transistor T becomes Vdata+Vth, and the potential difference between the gate of the driving transistor and its first electrode becomes Vth, reaching the critical on condition of the driving transistor T, and the gate potential of the driving transistor T no longer changes.

[0089] After the writing phase t30 ends, the light-emitting phase t40 begins. At this time, the third scan signal s3 jumps to a low level, and the fourth scan signal s4 jumps to a high level, causing both the data writing transistor M2 and the first compensation transistor M31 to turn off. The light-emitting control signal Em jumps to a low-level valid pulse, and the first light-emitting control transistor M41 and the second light-emitting control transistor M42 turn on. Due to the conduction of the first light-emitting control transistor M41, the positive power supply signal Pvdd of the positive power supply terminal PVDD is transmitted to the first terminal of the driving transistor T. At this time, the potential difference between the gate of the driving transistor T and its first terminal is Vdata + Vth - Pvdd, making the driving current generated by the driving transistor T Id = K * (Vdata - Pvdd). 2 K is a coefficient related to the size and material of the driving transistor T. Thus, the driving current generated by the driving transistor T is independent of its own threshold voltage Vth. This driving current is transmitted to the anode of the light-emitting element D through the conducting second light-emitting control transistor M42, causing the light-emitting element D to emit light.

[0090] In addition, continue to refer to Figure 3The pixel circuit P may also include a storage capacitor Cst, which is connected between a fixed power supply terminal (e.g., a positive power supply terminal PVDD or a negative power supply terminal PVEE) and the first node N1. The storage capacitor C1 is used to store the potential of the first node N1 (i.e., the gate potential of the driving transistor T) to ensure that the driving transistor T can continuously provide driving current to the light-emitting element 20 during the light-emitting phase.

[0091] Accordingly, continue to refer to Figure 3 The pixel circuit P may also include an initialization transistor M5. The gate of the initialization transistor M5 is electrically connected to the initialization control terminal SE. The first terminal of the initialization transistor M5 is connected to the initialization signal terminal VINI. The second terminal of the initialization transistor M5 is electrically connected to the anode of the light-emitting element D. Thus, when the initialization control signal Se of the initialization control terminal SE controls the initialization transistor M5 to be turned on, the initialization signal Vini of the initialization signal terminal VINI can be transmitted to the anode of the light-emitting element D to initialize the anode of the light-emitting element D and prevent the driving current provided to the anode of the light-emitting element D in the previous driving cycle from affecting the display brightness of the light-emitting element D in the next driving cycle.

[0092] In this embodiment, the initialization transistor M5 can be an N-channel transistor or a P-channel transistor. When the initialization transistor M5 is an N-channel transistor, it is turned on when the initialization control signal Se at the initialization control terminal SE is high, and turned off when the initialization control signal Se at the initialization control terminal SE is low. Conversely, when the initialization transistor M5 is a P-channel transistor, it is turned on when the initialization control signal Se at the initialization control terminal SE is low, and turned off when the initialization control signal Se at the initialization control terminal SE is high. This embodiment of the invention does not specifically limit the type of the initialization transistor M5.

[0093] In an optional embodiment, the channel type of the initialization transistor M5 can be the same as that of the data writing transistor M2. In this case, since the data writing transistor M2 controls the writing of the data signal Vdata before the light-emitting element D emits light, and the initialization transistor M5 also initializes the anode of the light-emitting element D before the light-emitting element 20 emits light, the fourth scan terminal S4 can be multiplexed as the initialization control terminal SE, so that the initialization transistor M5 and the data writing transistor M2 can be turned on or off simultaneously.

[0094] In other alternative embodiments, the channel type of the initialization transistor M5 can be the same as that of the second reset transistor M12. In this case, the second scan terminal S2 can be multiplexed with the initialization control terminal SE, so that the initialization transistor M5 and the second reset transistor M12 can be turned on or off simultaneously.

[0095] It is understood that the above description only illustrates the types of transistors in the pixel circuit P and the corresponding driving process. In the embodiments of the present invention, when the types of transistors in the pixel circuit P change, the driving process can be similar to that described above by changing the signal received by the gate of each transistor, which will not be repeated here.

[0096] In an alternative embodiment, Figure 8 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, in conjunction with reference to the reference. Figure 3 and Figure 8 When the channel type of the first compensation transistor M31 is the same as that of the first reset transistor M11, both the first compensation transistor M31 and the first reset transistor M11 can be N-channel transistors or both can be P-channel transistors. At this time, the display area AA also includes multiple first scan lines 141 and multiple third scan lines 143. The first scan terminal S1 of at least a portion of the pixel circuits P located in the same row is electrically connected to the same first scan line 141, and the third scan terminal S3 of at least a portion of the pixel circuits P located in the same row is electrically connected to the same third scan line 143.

[0097] In this embodiment, at least some pixel circuits P located in the same row have their first scanning terminals S1 electrically connected to the same first scanning line 141, meaning that some or all of the pixel circuits P located in the same row have their first scanning terminals S1 electrically connected to the same first scanning line 141. Correspondingly, at least some pixel circuits P located in the same row have their third scanning terminals S3 electrically connected to the same third scanning line 143, meaning that some or all of the pixel circuits P located in the same row have their third scanning terminals S3 electrically connected to the same third scanning line 143. For ease of description, unless otherwise specified, the embodiments of this invention use the example of all pixel circuits P located in the same row being electrically connected to both the same first scanning line 141 and the same third scanning line 143 to illustrate the technical solutions of the embodiments of this invention.

[0098] like Figure 8As shown, the non-display area NA of the display panel 100 includes a first scanning circuit 110; the first scanning circuit 110 includes a plurality of cascaded first scanning units 111; The first scan line 141 and the third scan line 143, which are electrically connected to the same pixel circuit P, are respectively electrically connected to the two adjacent first scan units 111. The first scan unit 111 of the previous level is electrically connected to the first scan line 141, and the first scan unit 111 of the next level is electrically connected to the third scan line 143. The first scan unit 111 of the first level is electrically connected to N first scan lines 141, and the last scan unit 111 of the last level is electrically connected to N third scan lines 143. In each level of first scan unit 111 between the first scan unit 111 of the first level and the last scan unit 111, each level of first scan unit 111 is electrically connected to N adjacent first scan lines 141 and N adjacent third scan lines 143. Wherein, N is a positive integer greater than or equal to 2. The effective pulses of the first scan signal s1 output by each first scan unit 111 are shifted sequentially, and the shift amount of the effective pulse of each first scan signal s1 is less than the width of the effective pulse of the first scan signal s1.

[0099] Specifically, when the first scan line 141 and the third scan line 143 electrically connected to the same pixel circuit P are electrically connected to the two adjacent first scan units 111 respectively, the first scan circuit 110 that provides the first scan signal s1 to the pixel circuit P can be multiplexed into a scan circuit that provides the third scan signal s3 to the pixel circuit P. This reduces the number of scan circuits set in the non-display area NA, thereby reducing the space occupied by the scan circuits in the non-display area NA, which is beneficial to the narrow bezel of the display panel 100. Simultaneously, the first-level first scanning unit 111 is electrically connected to N first scanning lines 141, so that the N rows of pixel circuits P, which are electrically connected to the N first scanning lines 141 respectively, share the same first scanning unit 111; the last-level first scanning unit 111 is electrically connected to N third scanning lines 143, so that the N rows of pixel circuits P, which are electrically connected to the N third scanning lines 143 respectively, share the same first scanning unit 111; in each level of first scanning unit 111 between the first-level first scanning unit 111 and the last-level first scanning unit 111, each level of first scanning unit 111 is electrically connected to N first scanning lines 141 and N third scanning lines 143 respectively, so that the N rows of pixel circuits P, which are electrically connected to the N first scanning lines 141 respectively, and the N rows of pixel circuits P, which are electrically connected to the N third scanning lines 143 respectively, share the first scanning unit 111, thereby reducing the number of first scanning units set in the first scanning circuit 110, and further reducing the size occupied by the first scanning circuit 110.

[0100] Furthermore, since the first scan line 141 and the third scan line 143, which are electrically connected in the same pixel circuit P, are electrically connected, the first scan line 141 is electrically connected to the previous first scan unit 111, and the third scan line 143 is electrically connected to the next first scan unit 111. Moreover, the first scan signal s1 output by each first scan unit 111 is shifted sequentially, so that in the same pixel circuit, the time when the first reset transistor M11 starts to conduct is before the time when the first compensation transistor M31 starts to conduct. This ensures that at least part of the time for resetting the gate of the driving transistor T is before the time for providing the data signal Vdata to the gate of the driving transistor T. This ensures that the data signal Vdata is accurately written to the gate of the driving transistor T after the gate of the driving transistor T is reset.

[0101] In an alternative embodiment, Figure 9 This is a driving timing diagram of each pixel circuit in another display panel provided by an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 8 and Figure 9 In each pixel circuit P electrically connected to the same first scanning unit 111, the termination time (t5, t5') of the first valid pulse of the second scanning signal s2 is located before the start time (t7, t7') of the valid pulse of the fourth scanning signal s4.

[0102] Specifically, the gate of the driving transistor T of the row pixel circuit P can only be reset when the first reset transistor M11 and the second reset transistor M12 are both turned on, for example, when the first scan signal s11 and the second scan signal s21 provided to the first row pixel circuit P are both valid pulses. Furthermore, the data signal Vdat can only be transmitted to the gate of the driving transistor T of the row pixel circuit P when the data writing transistor M2 and the first compensation transistor M13 are both turned on, for example, when the third scan signal s31 and the fourth scan signal s41 provided to the first row pixel circuit P are both valid pulses. Therefore, by setting the termination time (t5, t5') of the first valid pulse of the second scan signal s2 in each pixel circuit P electrically connected to the same first scan unit 111 to be before the start time (t7, t7') of the valid pulse of the fourth scan signal s4, for example, with the first stage first... The scanning unit 111 is electrically connected to the pixel circuits P in the first row and the second row. The first valid pulse of the second scan signal s21 received by each pixel circuit P in the first row ends at t5, the first valid pulse of the second scan signal s22 received by each pixel circuit P in the second row ends at t5', the start time of the valid pulse of the fourth scan signal s41 received by each pixel circuit P in the first row is t7, and the start time of the valid pulse of the fourth scan signal s41 received by each pixel circuit P in the second row is t7'. At this time, t5 and t5' are both before t7 and t7'. Thus, after resetting the gate of the driving transistor T at least once, the driving transistor T can be turned on during the writing phase of the data signal Vdata, ensuring that the data signal Vdata can be written to the gate of the driving transistor T in each pixel circuit P.

[0103] In an alternative embodiment, the reference continues... Figure 3 , Figure 8 and Figure 9 In each pixel circuit P electrically connected to the same first scanning unit 111, the start time (t7 and t7') of the effective pulse of the fourth scanning signal s4 is located after the end time t6 of the effective pulse of the first scanning signal s1.

[0104] Specifically, during the period when the first scan signal s1 is an effective pulse, the first reset transistor M11 is in the on state. At this time, the state of the second reset transistor M12 is controlled by the second scan signal s2, thereby controlling the transmission path of the reset signal Vref from the reset signal terminal VREF to the first node N1. Since the second scan signal s2 includes at least two effective pulses during the period when the first scan signal s1 is an effective pulse, the gate of the driving transistor T is reset at least twice after the end time t6 of the effective pulse of the first scan signal s1, so that the gate potential of the driving transistor T is sufficient to support the subsequent writing process of the data signal Vdata. Thus, by making the start time (t7 and t7') of the effective pulse of the fourth scan signal s4 after the end time t6 of the effective pulse of the first scan signal s1, the data writing transistor M2 can be turned on after the gate of the driving transistor T is reset at least twice, and the writing stage can be entered. In the writing stage, the data signal Vdata is accurately written to the gate of the driving transistor T, so that in the light-emitting stage, the driving transistor T generates an accurate driving current according to its gate, thereby accurately driving the light-emitting element D to emit light.

[0105] It is understood that the above only exemplifies that pixel circuits P located in different rows are electrically connected to different second scan lines 142, and different second scan lines 142 are electrically connected to different second scan units 121, so that the driving transistors of pixel circuits P located in different rows are reset at different time periods. However, in the embodiments of the present invention, the connection method between the second scan line 142 and the second scan unit 121 is not limited to this.

[0106] Optional, Figure 10 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 11 This is another driving timing diagram of the pixel circuits in a display panel provided by an embodiment of the present invention, combined with... Figure 3 , Figure 10 and Figure 11 The display area AA also includes multiple second scan lines 142 and multiple fourth scan lines 144; at least a portion of the pixel circuits P in the same row have their second scan terminals electrically connected to the same second scan line 142, and at least a portion of the pixel circuits P in the same row have their fourth scan terminals electrically connected to the same fourth scan line 144; the non-display area NA also includes a second scan circuit 120 and a third scan circuit 130; the second scan circuit 120 includes multiple cascaded second scan units 121; the third scan circuit 130 includes multiple cascaded third scan units 130.

[0107] Each level of the second scanning unit 121 is electrically connected to the adjacent N second scanning lines 142. That is, when pixel circuits P located in the same row share a second scanning line 142, each level of the second scanning unit 121 provides a second scanning signal to the adjacent N rows of pixel circuits P, so that the second reset transistors M12 in the N rows of pixel circuits P are simultaneously turned on or off. The effective pulses of the second scanning signal s2 output by each second scanning unit 121 are shifted sequentially, and the shift amount of the second scanning signal s2 is greater than or equal to the width of the effective pulse of the second scanning signal. For example, the termination time of the effective pulse of the second scanning signal s21 output by the first level of the second scanning unit 121 is located after the start time of the effective pulse of the second scanning signal s22 output by the second level of the second scanning unit 121, so that the effective pulses of the second scanning signal s22 output by the two levels of the second scanning unit 121 do not overlap. Thus, by ensuring that the second scanning terminals S2 of adjacent N rows of pixel circuits P receive the same second scanning signal s2, these adjacent N rows of pixel circuits P can be reset simultaneously. This helps to shorten the reset time of each pixel circuit P in the display panel 100, thereby relatively increasing the light-emitting time of the light-emitting element D, and ultimately improving the display effect of the display panel 100. Furthermore, since the reset signal Vref provided to each row of pixel circuits P is usually the same, even if the N rows of pixel circuits P are reset simultaneously, the reset accuracy of each pixel circuit P will not be affected.

[0108] Correspondingly, each level of the third scanning unit 131 is electrically connected to each of the fourth scanning lines 144. For example, each level of the third scanning unit 131 is electrically connected to one fourth scanning line 144. When the pixel circuits P located in the same row share the fourth scanning line 144, each level of the third scanning unit 131 provides a third scanning signal to each pixel circuit P located in the same row. Different levels of the third scanning unit 131 provide third scanning signals to pixel circuits P in different rows. For example, the first level of the third scanning unit 131 provides a fourth scanning signal s41 to the data writing transistor M2 of the pixel circuit P located in the first row, and the second level of the third scanning unit 131 provides a fourth scanning signal S42 to the data writing transistor M2 of the pixel circuit P located in the second row. The effective pulses of the fourth scan signal s4 output by the three scanning units 131 are shifted sequentially, and the shift amount of the effective pulses of the fourth scan signal s4 is greater than or equal to the width of the effective pulses of the fourth scan signal s4. For example, the termination time of the effective pulse of the fourth scan signal s41 output by the first-level third scanning unit 131 is before the start time of the fourth scan signal s42 output by the second-level third scanning unit 131. This allows the pixel circuits P located in different rows to write data signals at different times, preventing crosstalk between the data signals written by the pixel circuits P in different rows due to the simultaneous writing of data signals by the pixel circuits P in different rows. This helps to improve the accuracy of the data signals written by each pixel circuit P.

[0109] In an alternative embodiment, the reference continues... Figure 3 , Figure 10 and Figure 11 The width t20 of the effective pulse of the second scan signal s2 is greater than or equal to N times the width t30 of the effective pulse of the fourth scan signal s4, and in the same pixel circuit P, the time of the effective pulse of the second scan signal s2 and the time of the effective pulse of the fourth scan signal s4 do not overlap.

[0110] Specifically, since each level of the second scanning unit 121 is electrically connected to N second scanning lines 142, the gates of the driving transistors T of the N rows of pixel circuits P, which are electrically connected to the N second scanning lines 142 respectively, can be reset simultaneously. After the reset of the driving transistors T of the N rows of pixel circuits P is completed, data signals Vdata need to be provided to each pixel circuit P in each row. At this time, it is necessary to control the writing of data signals Vdata of each row of pixel circuits P in a time-division manner. Therefore, by making the width t20 of the effective pulse of the second scanning signal s2 greater than or equal to N times the width t30 of the effective pulse of the fourth scanning signal s4, the writing of data signals Vdata of the N rows of pixel circuits P can be completed within the time of one effective pulse of the second scanning signal s2, which helps to shorten the writing time of data signals Vdata and ensures that each row of pixel circuits P can be accurately written. Meanwhile, by ensuring that the effective pulse times of the second scan signal s2 and the fourth scan signal s4 in the same pixel circuit P do not overlap, the reset and write phases of the same pixel circuit P can be performed in a time-division manner. This avoids the write of the data signal Vdata affecting the gate reset of the driving transistor T, and prevents the reset signal Vref from affecting the write of the data signal Vdata. As a result, the accuracy of the gate reset of the driving transistor T can be improved, while ensuring that the data signal Vdata can be accurately written to the gate of the driving transistor T.

[0111] In an alternative embodiment, Figure 12 This is a schematic diagram of the pixel circuit structure in another display panel provided by an embodiment of the present invention, as shown below. Figure 12 As shown, the pixel circuit P also includes a bias adjustment transistor M6; the gate of the bias adjustment transistor M6 is electrically connected to the fifth scan terminal S5, the first terminal of the bias adjustment transistor M6 is electrically connected to the bias adjustment terminal DVH, and the second terminal of the bias adjustment transistor M6 is electrically connected to the first terminal of the driving transistor T; in the same pixel circuit P, the time of at least a portion of the effective pulses of the fifth scan signal s5 at the fifth scan terminal S5 does not overlap with the time of the effective pulses of the third scan signal s3, and the time of the effective pulses of the fifth scan signal s5 does not overlap with the time of the effective pulses of the fourth scan signal s4.

[0112] It is understandable that the bias adjustment transistor M6 can be an N-channel transistor or a P-channel transistor. When the bias adjustment transistor M6 is an N-channel transistor, it is turned on when the fifth scan signal s5 at the fifth scan terminal S5 is high, and turned off when the fifth scan signal s5 is low. The duration of the high level of the fifth scan signal s5 is the duration of the effective pulse of the fifth scan signal s5. When the bias adjustment transistor M6 is a P-channel transistor, it is turned on when the fifth scan signal s5 is low, and turned off when the fifth scan signal s5 is high. The duration of the low level of the fifth scan signal s5 is the duration of the effective pulse of the fifth scan signal s5.

[0113] When the driving transistor T is in the on state, there is a certain potential difference between its gate and its first electrode, causing the driving transistor T to be in a biased state. This results in a shift in the IV curve of the driving transistor, causing the threshold voltage of the driving transistor T to drift. Consequently, it cannot accurately provide driving current to the light-emitting element D, affecting the display effect. By setting a bias adjustment transistor M6 in the pixel circuit P, when the bias adjustment transistor M6 is on, the bias adjustment signal Vpark at the bias adjustment terminal DVH can be written to the first electrode of the driving transistor T through the on-state bias adjustment transistor M6. This ensures that the potential of the first electrode of the driving transistor T is consistent with the bias adjustment signal Vpark, improving the potential difference between the gate and its first electrode of the driving transistor T. This achieves bias adjustment of the driving transistor T, balances the shift in the IV curve of the driving transistor T, improves the threshold voltage drift of the driving transistor T, and ensures the display uniformity of the display panel.

[0114] For example, taking the bias adjustment transistor M6 as a P-channel transistor, Figure 13 This is another driving timing diagram of a pixel circuit provided in an embodiment of the present invention, wherein, Figure 13 and Figure 7 The similarities can be found in the text above. Figure 7 The description will not be repeated here; only the description of the previous section will be provided. Figure 13 and Figure 7 The differences are illustrated by example. (Refer to the reference.) Figure 12 and Figure 13Each driving cycle of the pixel circuit P also includes a bias adjustment stage t50, which is located after the write stage t30 and before the light emission stage t40. In the light emission stage of the previous driving cycle, the driving transistor T provides driving current to the light-emitting element D, causing the driving transistor T to be in a conducting state. In this conducting state, the driving transistor T remains in a biased state for a long time, causing an IV offset in the driving transistor T. In the write stage t30, the writing of the data signal Vdata causes the driving transistor T to be in a conducting state, resulting in a biased state and affecting the characteristics of the driving transistor. In the bias adjustment structure t50, the fifth scan signal s5 is an effective pulse, and the bias adjustment transistor M6 is turned on, causing the bias adjustment signal Vpark to be written to the first terminal of the driving transistor T. This adjusts the potential difference between the gate and the first terminal of the driving transistor T, adjusting the bias of the driving transistor T and mitigating the phenomenon where the IV curve offset of the driving transistor T affects the driving current supplied to the light-emitting element D in the subsequent light emission stage t40. This is beneficial for improving the display light emission accuracy of the light-emitting element D. This ensures accuracy and improves the display effect of the display panel. Simultaneously, during the writing stage t30, the data writing transistor M2 provides a data signal Vdata to the first electrode of the driving transistor T, making the voltage of the first electrode of the driving transistor T equivalent to the voltage of the data signal Vdata. However, due to differences in the data signals Vdata written by different pixel circuits P, the first electrode potentials of the driving transistors T of different pixel circuits P are different, resulting in different bias states for different pixel circuits P. This affects the display uniformity of the display panel during the subsequent light-emitting stage t40. By entering the bias adjustment stage t50 after the writing stage t30, the same bias adjustment signal Vprk can be provided to the first electrode of the driving transistors T of different pixel circuits P. This ensures that the first electrode potentials of the driving transistors T of each pixel circuit P remain consistent before the start of the light-emitting stage t40, thus improving the display uniformity of the display panel during the subsequent light-emitting stage t40.

[0115] In another alternative embodiment, combined with participation Figure 12 and Figure 14The bias adjustment stage t50 can also be located before the write stage t30. For example, the bias adjustment stage t50 is located between the reset stage t21 and the reset stage t22. After the gate of the driving transistor T is reset once, the driving transistor T will be in the conducting state and continue to provide the bias adjustment signal Vpark to the first terminal of the driving transistor T. The bias adjustment signal Vpark will be transmitted to its second terminal through the first terminal of the driving transistor so that the potential of the first terminal of the driving transistor T is consistent with the potential of its second terminal. This improves the phenomenon of threshold voltage drift caused by the large potential difference between the gate, the first terminal and the second terminal of the driving transistor T, thereby helping to accurately write the data signal Vdata in the write stage t30.

[0116] In yet another alternative embodiment, in conjunction with reference to Figure 13 and Figure 15 One driving cycle of the pixel circuit P can include multiple light-emitting stages t40, and the bias adjustment stage t50 can be located between two adjacent light-emitting stages t40. Thus, after a light-emitting stage t40 ends, the bias adjustment stage t50 begins, where the bias adjustment signal Vpark is written to the first electrode of the driving transistor T to improve the potential difference between the gate of the driving transistor T and its first electrode, balancing the offset of the IV curve of the driving transistor T. This allows the driving transistor T to provide accurate driving current to the light-emitting element D in subsequent light-emitting stages t40, enabling the light-emitting element D to emit light accurately and improving the display effect of the display panel.

[0117] It is understood that the above only exemplifies the conduction time of the bias adjustment transistor M6. Under the premise that the bias adjustment of the driving transistor T can be realized, the present invention does not specifically limit the conduction time of the bias adjustment transistor M6.

[0118] It should be noted that, Figures 13-15 This is merely an example showing that the fifth scan signal s5, which controls the bias adjustment transistor M6 to be turned on or off, includes only one valid pulse in one driving cycle. However, in this embodiment of the invention, the number of valid pulses of the fifth scan signal s5 in each driving cycle can be set as needed, and this embodiment of the invention does not specifically limit this.

[0119] Optional, Figure 16 This is another driving timing diagram of a pixel circuit provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 12 and Figure 16The effective pulse of the fifth scan signal s5 is part of the first effective pulse; in the same pixel circuit P, the time t51 of the first effective pulse of the fifth scan signal s5 overlaps with the time t30' of the effective pulse of the third scan signal s3, and the time t51 of the first effective pulse of the fifth scan signal s5 is located between the times (t21 and t22) of the effective pulses of the two adjacent second scan signals s2.

[0120] Specifically, during the effective pulse time (t21, t22) of the second scan signal s2, the reset signal Vref can be written to the first node N1 to reset the driving transistor T, clear the data signal written to the gate of the driving transistor T in the previous driving cycle, and enable the driving transistor T to be in the on state. By setting the time t51 of the first effective pulse of the fifth scan signal s5 between the effective pulse times (t21 and t22) of the two adjacent second scan signals s2, the bias of the driving transistor T can be adjusted after the gate of the driving transistor T is reset at least once, so that the bias adjustment signal Vpark can be transmitted to the first terminal of the driving transistor T through the bias adjustment transistor M6, and then transmitted to its second terminal by the driving transistor T, thereby making the potential of the first terminal and the second terminal of the driving transistor T consistent. Furthermore, by overlapping the effective pulse time t51 of the fifth scan signal s5 with the effective pulse time t30' of the third scan signal s3 in the same pixel circuit P, the bias transistor M6 and the first compensation transistor M31 are simultaneously turned on during the overlapping time. This allows the bias adjustment signal Vpark to be transmitted sequentially through the bias adjustment transistor M6, the driving transistor T, and the first compensation transistor M31 to the gate of the driving transistor T. This ensures that the potentials of the first electrode, the second electrode, and the gate of the driving transistor T are kept consistent, thereby balancing the offset phenomenon of the IV curve of the driving transistor T, improving the threshold drift phenomenon of the driving transistor T, and thus improving the display uniformity of the display panel.

[0121] In an alternative embodiment, the reference continues... Figure 12 and Figure 16 The fifth scan signal s5 may also include at least one second effective pulse. The time t52 of the second effective pulse may be located after the time t30 of the effective pulse of the fourth scan signal s4. At this time, it is also possible to keep the first pole potential of the driving transistor T in each pixel circuit P consistent before each pixel circuit P enters the light-emitting stage t40, thereby further improving the display uniformity of the display panel.

[0122] Understandably, it is advisable to continue using references. Figure 12 and Figure 16The number of effective pulses of the fifth scan signal s5 can be the same as the number of effective pulses of the second scan signal s2. In this case, when the width of the effective pulse of the fifth scan signal s5 is also the same as the width of the effective pulse of the second scan signal s2, the same scanning circuit can be used to provide the fifth scan signal s5 and the second scan signal s2 to the pixel circuit P respectively.

[0123] Optional, Figure 17 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, in conjunction with reference to the reference. Figure 12 and Figure 17 The display area AA also includes a second scan line 142 and a fifth scan line 145; the second scan terminal S2 of at least a portion of the pixel circuits P in the same row is electrically connected to the same second scan line 142; the fifth scan terminal S5 of at least a portion of the pixel circuits P in the same row is electrically connected to the same fifth scan line 145; thus, the second scan terminal S2 of at least a portion of the pixel circuits P in the same row receives the same second scan signal s2, and the fifth scan terminal S5 of at least a portion of the pixel circuits P in the same row receives the same fifth scan signal s5, thereby realizing row-by-row scanning of each pixel circuit P in the display panel 100. For ease of description, the embodiments of the present invention are illustrated by the example of the second scan terminal S2 of the pixel circuits P in the same row being electrically connected to the same second scan line 142, and the fifth scan terminal S5 of the pixel circuits P in the same row being electrically connected to the same fifth scan line 145.

[0124] Continue to refer to Figure 12 and Figure 17 The display panel 100 also includes a non-display area NA; the non-display area NA also includes a second scanning circuit 120; the second scanning circuit 120 includes a plurality of cascaded second scanning units 121; the second scanning line 142 and the fifth scanning line 145 electrically connected to the same pixel circuit P are respectively electrically connected to two adjacent odd-level second scanning units 121 or two adjacent even-level second scanning units 121, and the previous level second scanning unit 121 is electrically connected to the second scanning line 142, and the next level second scanning unit 121 is electrically connected to the fifth scanning line 145; the effective pulses of the second scanning signal s2 output by each second scanning unit 121 are shifted sequentially, and the shift amount of the effective pulses of the second scanning signal s2 is greater than or equal to the width of the effective pulses of the second scanning signal s2. Thus, in each pixel circuit P, the reset stage for resetting the gate of the driving transistor T is located before the bias adjustment stage for writing the bias adjustment signal Vpark to the first pole of the driving transistor T. The reset stage and the bias adjustment stage are performed in a time-sharing manner and do not affect each other, thereby ensuring the accuracy of resetting and bias adjustment of each driving transistor T.

[0125] Optional, continue to refer to Figure 17When the second scanning circuit 120 includes M levels of second scanning units, the first level second scanning unit 121 and the second level second scanning unit 121 are electrically connected to the adjacent N second scanning lines 142, respectively. The (M-1)th level second scanning unit 121 and the Mth level second scanning unit 121 are electrically connected to the adjacent N fifth scanning lines 145, respectively. In each level of second scanning unit 121 between the second level second scanning unit 121 and the (M-1)th level second scanning unit 121, each level second scanning unit 121 is electrically connected to the adjacent N second scanning lines 142 and the adjacent N fifth scanning lines 145. Here, M is an even number greater than or equal to 4, and N is a positive integer greater than or equal to 2.

[0126] For example, Figure 18 This is a driving timing diagram of each pixel circuit in a display panel provided by an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 12 , Figure 17 and Figure 18Taking N=2 and M=6 as an example, the first-level second scanning unit 121 is electrically connected to the two second scanning lines 142 corresponding to the first row pixel circuit P and the second row pixel circuit P, respectively, so that the first-level second scanning unit 121 can simultaneously provide the second scanning signal s21 to the second scanning terminals S2 of the first row pixel circuit P and the second row pixel circuit P; the second-level second scanning unit 121 is electrically connected to the two second scanning lines 142 corresponding to the third row pixel circuit P and the fourth row pixel circuit P, respectively, so that the second-level second scanning unit 121 can simultaneously provide the second scanning signal s21 to the second scanning terminals S2 of the third row pixel circuit P and the fourth row pixel circuit P. The scanning terminal S2 provides a second scan signal s22; the third-level second scanning unit 121 is electrically connected to two fifth scan lines 145 corresponding to the first row pixel circuit P and the second row pixel circuit P, respectively. Simultaneously, the third-level second scanning unit 121 is also electrically connected to two second scan lines 142 corresponding to the fifth row pixel circuit P and the sixth row pixel circuit P, respectively. This allows the third-level second scanning unit 121 to simultaneously provide a fifth scan signal s51 to the fifth scan terminals S5 of the first row pixel circuit P and the second row pixel circuit P, and simultaneously provide a second scan signal s22 to the second scan terminals S2 of the fifth row pixel circuit P and the sixth row pixel circuit P. The fourth-level second scanning unit 121 is electrically connected to two fifth scan lines 145 corresponding to the third row pixel circuit P and the fourth row pixel circuit P, respectively. Simultaneously, the fourth-level second scanning unit 121 is also electrically connected to two second scan lines 142 corresponding to the seventh row pixel circuit P and the eighth row pixel circuit P, respectively. This allows the fourth-level second scanning unit 121 to simultaneously provide fifth scan signals s52 to the fifth scan terminals S5 of the third row pixel circuit P and the fourth row pixel circuit P, and simultaneously provide second scan signals s24 to the second scan terminals S2 of the seventh row pixel circuit P and the eighth row pixel circuit P. The second scanning unit 121 of the fifth level is electrically connected to two fifth scanning lines 145 corresponding to the fifth row pixel circuit P and the sixth row pixel circuit P, respectively, so that the second scanning unit 121 of the fifth level can simultaneously provide the fifth scanning signal s53 to the second scanning terminals S2 of the fifth row pixel circuit P and the sixth row pixel circuit P; the second scanning unit 121 of the sixth level is electrically connected to two fifth scanning lines 145 corresponding to the seventh row pixel circuit P and the eighth row pixel circuit P, respectively, so that the second scanning unit 121 of the sixth level can simultaneously provide the fifth scanning signal s54 to the second scanning terminals S2 of the seventh row pixel circuit P and the eighth row pixel circuit P.

[0127] Thus, by electrically connecting the second scanning terminal S2 of the adjacent N-row pixel circuit P to the same second scanning unit 121, and electrically connecting the fifth scanning terminal S5 of the adjacent N-row pixel circuit P to the same second scanning unit 121, the number of second scanning units 121 provided in the non-display area NA of the display panel 100 can be reduced, thereby simplifying the circuit structure of the non-display area NA in the display panel 100 and reducing the size of the non-display area NA, which is beneficial to the narrow bezel of the display panel 100.

[0128] It is understood that the above is only an example of each second scanning unit 121 being electrically connected to two second scanning lines 142 and / or two fifth scanning lines 145 respectively, i.e., N is equal to 1. In the embodiments of the present invention, the value of N can be set as needed, and the embodiments of the present invention do not make specific limitations on this.

[0129] In one exemplary embodiment, Figure 19 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 20 This is a schematic diagram of the pixel circuit structure of another display panel provided in an embodiment of the present invention, in conjunction with reference to the reference. Figure 12 , Figure 19 and Figure 20Taking N equal to 2 as an example, when the display panel 100 simultaneously includes a first scanning circuit 110, a second scanning circuit 120, a third scanning circuit 130, and a light-emitting control circuit 140, each first scanning unit 111 in the first scanning circuit 110 is electrically connected to two first scanning lines 141 and / or two third scanning lines 143; each second scanning unit 121 in the second scanning circuit 120 is electrically connected to two second scanning lines 142 and / or two fifth scanning lines 145; each third scanning unit 131 in the third scanning circuit 130 is electrically connected to each fourth scanning line 144; and each light-emitting control unit in the light-emitting control circuit 140 is electrically connected to two light-emitting control lines 147. At this time, the driving process of the two adjacent rows of pixel circuits P can be as follows: In the first reset stage t21, the first reset transistor M11 and the second reset transistor M12 of the two rows of pixel circuits P are simultaneously turned on, thereby simultaneously resetting the gates of the driving transistors T of the two rows of pixel circuits P; In the first bias adjustment stage t51, the bias adjustment transistor M6 and the first compensation transistor M31 of the two rows of pixel circuits P are simultaneously turned on, thereby simultaneously adjusting the bias of the driving transistors T of the two rows of pixel circuits P; In the second reset stage t22, the first reset transistor M11 and the second reset transistor M12 of the two rows of pixel circuits P are turned on again to further reset the gates of the driving transistors T of the two rows of pixel circuits P; In the writing stage t31 of the preceding row of pixel circuits P, the data writing transistor M2 and the first compensation transistor M31 of the row of pixel circuits P are turned on, so that the data writing transistor M2 of the preceding row of pixel circuits P is turned on, thereby adjusting the bias of the driving transistors T of the preceding row of pixel circuits P; The data signal Vdata of each pixel circuit P can be written one-to-one to the gate of the driving transistor T of each pixel circuit P in that row of pixel circuits; in the writing stage t32 of the latter row of pixel circuits P, the data writing transistor M2 and the first compensation transistor M31 of that row of pixel circuits P are turned on, so that the data signal Vdata of each pixel circuit P in that row of pixel circuits can be written one-to-one to the gate of the driving transistor T of each pixel circuit P in that row of pixel circuits; in the second bias adjustment stage t52, the bias adjustment transistor M6 and the first compensation transistor M31 of the two rows of pixel circuits P are turned on again, so that the bias adjustment of the driving transistor T of the two rows of pixel circuits P can be performed simultaneously; in the light emission stage t40, the first light emission control transistor M41 and the second light emission control transistor M42 of the two rows of pixel circuits P are turned on simultaneously, so that the light emission element D of the two rows of pixel circuits P can emit light simultaneously. In this way, while the data signal Vdata of each pixel circuit P can be written one-to-one into the gate of the driving transistor T of each pixel circuit P, the number of scanning circuits set in the non-display area NA of the display panel 100 and the number of scanning units in each scanning circuit can be reduced, which is beneficial to the narrow bezel of the display panel.

[0130] It is understood that the above example only exemplifies that each driving cycle of the pixel circuit P includes two bias adjustment stages to adjust the bias of the driving transistor T. In the embodiments of the present invention, the bias adjustment of the driving transistor T can also be achieved in other ways.

[0131] Optional, Figure 21 This is another driving timing diagram of a pixel circuit provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 3 and Figure 21 In the same pixel circuit P, the effective pulse time t30´ of the third scan signal s3 of the third scan terminal S3 overlaps with the time (t41, t42) of at least two effective pulses of the fourth scan signal s4 of the fourth scan terminal S4.

[0132] Specifically, the effective pulse of the third scan signal s3 can control the first compensation transistor M31 to turn on, so that the first compensation transistor M31 will remain in the conducting state during the effective pulse time t30' of the third scan signal s3; the effective pulse of the fourth scan signal s4 can control the data writing transistor M2 to turn on; thus, during the overlap time (t41, t42) of the effective pulses of the third scan signal s3 and the fourth scan signal s4, the data writing transistor M2 and the first compensation transistor M31 will be in the conducting state simultaneously, so that the data signal Vdata at the data signal terminal DATA can be transmitted to the gate of the driving transistor T. During the transmission of the data signal Vdata, the data signal Vdata will pass through the first and second terminals of the driving transistor T in sequence before reaching its gate, so that the potentials of the first terminal, the second terminal and the gate of the driving transistor T are kept consistent. Simultaneously, because the effective pulse time t30' of the third scan signal s3 overlaps with the times (t41, t42) of at least two effective pulses of the fourth scan signal s4, for example, the effective pulse time t30' of the third scan signal s3 overlaps with the times (t41, t42) of two effective pulses of the fourth scan signal s4, during the first effective pulse overlap time of the third scan signal s3 and the fourth scan signal s4, the data signal Vdata is sequentially transmitted to the gate of the driving transistor T through the data writing transistor M2, the driving transistor T, and the first compensation transistor M31, so that the first electrode, the second electrode, and the gate potential of the driving transistor T are kept consistent, thereby enabling the driving... The bias adjustment of transistor T balances the offset phenomenon of the IV curve of driving transistor T and improves the threshold drift phenomenon of driving transistor T. During the overlap time of the next effective pulse of the third scan signal s3 and the fourth scan signal s4, due to the bias adjustment effect of the driving transistor T during the overlap time of the previous effective pulse, the driving transistor T moves closer to the unbiased state. At this time, the data signal Vdata is written to the gate of the driving transistor T again, which can ensure the accurate writing of the data signal Vdata. Thus, when the driving transistor T provides driving current to the light-emitting element D according to its gate potential, it can drive the light-emitting element D to emit light accurately, thereby improving the display uniformity of the display panel.

[0133] It is understood that the above example only illustrates the overlap between the effective pulse time of the third scan signal s3 and the times of two effective pulses of the fourth scan signal s4. However, in the embodiments of the present invention, in the same pixel circuit, the effective pulse time of the third scan signal s3 can also overlap with the times of two or more (e.g., three, four, or five) effective pulses of the fourth scan signal s4. Provided that the core inventive points of the embodiments of the present invention can be achieved, the embodiments of the present invention do not specifically limit this. For ease of description, unless otherwise specified, the embodiments of the present invention will use the overlap between the effective pulse time of the third scan signal and the times of two effective pulses of the fourth scan signal in the same pixel circuit as an example to illustrate the technical solutions of the embodiments of the present invention.

[0134] Optional, continue to refer to the references Figure 3 and Figure 21 In the same pixel circuit P, the time (t21) of a portion of the effective pulses of the fourth scan signal s4 is located between the times (t21 and t22) of two adjacent effective pulses of the second scan signal s2.

[0135] Specifically, the effective pulse time of the fourth scan signal s4 falls between the times of two adjacent effective pulses of the second scan signal s2. This can be understood as: the effective pulse time of the fourth scan signal s4 falls between the times of two adjacent effective pulses of the second scan signal s2, and the effective pulse time of the fourth scan signal s4 does not fall between the times of two adjacent effective pulses of the second scan signal s2. In an optional embodiment, the effective pulse time of the fourth scan signal s4 may also fall after the effective pulse time of the second scan signal s2 or the first scan signal s1.

[0136] For example, in each driving cycle of pixel circuit P, both the second scan signal s2 and the fourth scan signal s4 have two valid pulses, and the times (t21, t22) of each valid pulse of the second scan signal s2 overlap with the time t10 of the valid pulse of the first scan signal s1, and the times (t41, t42) of each valid pulse of the fourth scan signal s4 overlap with the time t30' of the valid pulse of the third scan signal s3. In this case, the time t41 of the first valid pulse of the fourth scan signal s4 is located between the times t21 and t22 of the two valid pulses of the second scan signal s2. During the time t21 of the first valid pulse of the second scan signal s2, the gate of the driving transistor T can be reset, causing the driving transistor T to conduct, so that the first valid pulse of the fourth scan signal s4... During the effective pulse time period t41, the data signal Vdata is ensured to be transmitted sequentially to the first terminal, second terminal, and gate of the driving transistor T, so that the potentials between the first terminal, second terminal, and gate of the driving transistor T are kept consistent, thereby achieving bias adjustment of the driving transistor T. After the first effective pulse time t41 of the fourth scan signal s4, the second effective pulse time period t22 of the second scan signal s2 is entered, which can reset the gate of the driving transistor T again to clear the gate potential of the driving transistor T, so as to ensure that the data signal Vdata can be accurately transmitted to the gate of the driving transistor T within the second effective pulse time t42 of the fourth scan signal s4, so that in the subsequent light emission stage t40, the driving transistor T can accurately drive the light-emitting element D to emit light according to its gate potential.

[0137] Optional, Figure 22 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, in conjunction with reference to the reference. Figure 3 and Figure 22 When the channel type of the data writing transistor M2 is the same as the channel type of the second reset transistor M12, the display area AA may include multiple first scan lines 141, multiple second scan lines 142, and multiple fourth scan lines 144; the first scan terminal S1 of at least a portion of the pixel circuits P located in the same row is electrically connected to the same first scan line 141, the second scan terminal S2 of at least a portion of the pixel circuits P located in the same row is electrically connected to the same second scan line 142, and the fourth scan terminal S4 of at least a portion of the pixel circuits P located in the same row is electrically connected to the same fourth scan line 144; correspondingly, the non-display area NA of the display panel 100 includes a first scan circuit 110 and a second scan circuit 120; the first scan circuit 110 includes multiple cascaded first scan units 111; the second scan circuit 120 includes multiple cascaded second scan units 121.

[0138] Each first scanning unit 111 is electrically connected to N adjacent first scanning lines 141, where N is a positive integer greater than or equal to 2. This reduces the number of first scanning units 111, which is beneficial for narrow bezels of the display panel 100. Each first scanning unit 111 provides a first scanning signal s1 to each first scanning line 141. The effective pulses of the first scanning signal s1 output by each first scanning unit 111 are shifted sequentially, and the shift amount of the effective pulse of each first scanning signal s1 is less than the width of the effective pulse of the first scanning signal s1. In this way, while achieving line-by-line scanning of each pixel circuit P, it is beneficial to shorten the scanning time of the first scanning circuit 110 for each pixel circuit P.

[0139] In an optional embodiment, the display area AA of the display panel 100 may further include multiple third scan lines 143. At least some of the pixel circuits P located in the same row have their third scan terminals S3 electrically connected to the same third scan line 143. The first scan unit 111 may also be electrically connected to the adjacent N third scan lines 143, and the first scan terminal S1 and the third scan terminal S3 of the same pixel circuit P are respectively electrically connected to the two adjacent first scan units 111, so that the first scan unit 11 can also provide a third scan signal s3 to each pixel circuit P. At this time, the first scan circuit 110 that provides the first scan signal s1 to the pixel circuit P can be multiplexed into a scan circuit that provides the third scan signal s3 to the pixel circuit P. This is beneficial to reducing the number of scan circuits set in the non-display area NA, thereby benefiting the narrow bezel of the display panel 100.

[0140] Continue to refer to Figure 3 and Figure 22 Each level of the second scanning unit 121 is electrically connected to each second scanning line 142 and each fourth scanning line 144 respectively. The two levels of second scanning units 121 corresponding to the second scanning line 142 and the fourth scanning line 144 electrically connected to the same pixel circuit P are the i-th level second scanning unit 121 and the (i+N)-th level second scanning unit 121 respectively. The effective pulses of the second scanning signal s2 and / or the fourth scanning signal s4 output by each level of the second scanning unit 121 are shifted sequentially, and the shift amount of the effective pulses of the second scanning signal s2 and / or the fourth scanning signal s4 is greater than or equal to the width of the effective pulse of the second scanning signal s2.

[0141] For example, Figure 23 This is another driving timing diagram of the pixel circuits in a display panel provided by an embodiment of the present invention, taking N equal to 2 as an example, in conjunction with reference. Figure 3 , Figure 22 and Figure 23When each pixel circuit P located in the same row is electrically connected to the same first scan line 141, second scan line 142, third scan line 143, and fourth scan line 144, the first-level first scan unit 111 is electrically connected to the first scan terminal S1 of each pixel circuit P located in the first and second rows through two first scan lines 141, the second-level first scan unit 111 is electrically connected to the first scan terminal S1 of each pixel circuit P located in the third and fourth rows through two first scan lines 141, and the second-level first scan unit 111 is also electrically connected to the third scan terminal S3 of each pixel circuit P located in the first and second rows through two third scan lines 143, and so on, until the last-level first scan unit 111 is electrically connected to the first scan terminal S1 of each pixel circuit P located in the last two rows through two first scan lines 141; the pixels in the first row The second scanning terminal S2 of circuit P is electrically connected to the first-level second scanning unit 121 via a second scanning line 142. The second scanning terminal S2 of pixel circuit P located in the second row is electrically connected to the second-level second scanning unit 121 via a second scanning line 142, and so on. The second scanning terminal S2 of pixel circuit P located in the last row is electrically connected to the penultimate-level second scanning unit 121 via a second scanning line 142. The pixel circuit P located in the first row and the fourth scanning terminal S4 are electrically connected to the third-level second scanning unit 121 via a fourth scanning line 144. The pixel circuit P located in the second row and the fourth scanning terminal S4 are electrically connected to the fourth-level second scanning unit 121 via a fourth scanning line 144, and so on. The fourth scanning terminal S4 of pixel circuit P located in the last row is electrically connected to the last-level second scanning unit 121 via a fourth scanning line 144.

[0142] The driving process of the first and second row pixel circuits P is illustrated using an example. During the overlap time t211 between the effective pulse of the first scan signal s11 output by the first-level first scan unit 111 and the first effective pulse of the second scan signal s21 output by the first-level second scan unit 121, the first reset transistor M11 and the second reset transistor M12 of each pixel circuit P in the first row are simultaneously turned on, resetting the driving transistor T of each pixel circuit P in the first row. During the overlap time t212 between the effective pulse of the first scan signal s11 output by the first-level first scan unit 111 and the first effective pulse of the second scan signal s22 output by the second-level second scan unit 121, the first reset transistor M11 and the second reset transistor M12 of each pixel circuit P in the second row are simultaneously turned on, resetting the driving transistor T of each pixel circuit P in the first row. A reset transistor M11 and a second reset transistor M12 are simultaneously turned on, enabling the reset of the driving transistors T of each pixel circuit P located in the second row; within the overlap time t411 between the effective pulse of the third scan signal s31 output by the second-stage first scan unit 111 and the first effective pulse of the fourth scan signal s41 output by the third-stage second scan unit 121, the data writing transistor M2 and the first reset compensation transistor M31 of each pixel circuit P located in the first row are simultaneously turned on, enabling the provision of data signals Vdata to the first terminal, second terminal, and gate of the driving transistors T of each pixel circuit P located in the first row, thereby realizing the bias adjustment of the driving transistors T; in the... During the overlap time t412 between the effective pulse of the third scan signal s31 output by the second-level first scan unit 111 and the first effective pulse of the fourth scan signal s42 output by the fourth-level second scan unit 121, the data writing transistor M2 and the first reset compensation transistor M31 of each pixel circuit P in the second row are simultaneously turned on, providing data signals Vdata to the first, second, and gate terminals of the driving transistors T of each pixel circuit P in the second row, thereby adjusting the bias of the driving transistors T; the effective pulse of the first scan signal s11 output by the first-level first scan unit 111 and the first effective pulse of the second scan signal s21 output by the first-level second scan unit 121 are... During the overlap time t221 of the second valid pulse, the first reset transistor M11 and the second reset transistor M12 of each pixel circuit P in the first row are turned on again, which can reset the driving transistor T of each pixel circuit P in the first row again; during the overlap time t222 of the valid pulse of the first scan signal s11 output by the first stage first scan unit 111 and the second valid pulse of the second scan signal s22 output by the second stage second scan unit 121, the first reset transistor M11 and the second reset transistor M12 of each pixel circuit P in the second row are turned on again, which can reset the driving transistor T of each pixel circuit P in the second row again.During the overlap time t421 between the effective pulse of the third scan signal s31 output by the second-level first scan unit 111 and the second effective pulse of the fourth scan signal s41 output by the third-level second scan unit 121, the data writing transistor M2 and the first reset compensation transistor M31 of each pixel circuit P in the first row are turned on again, which can accurately write the data signal Vdata corresponding to each pixel circuit P in the first row to the gate of the driving transistor T in each pixel circuit P; during ...-level second scan unit 121, the data writing transistor M2 and the first reset compensation transistor M31 of each pixel circuit P in the first row are turned on again, which can accurately write the data signal Vdata corresponding to each pixel circuit P in the first row to the gate of the driving transistor T in each pixel circuit P; during the overlap time t421 between the effective pulse of the third scan signal s31 output by the second-level first scan unit 111 and the second effective pulse of the fourth-level second scan unit 121, the data writing transistor M2 and the first reset compensation transistor M31 of each pixel circuit P in the first row are turned on again, which can accurately write the data signal Vdata corresponding to each pixel circuit P in the first row to the gate of the driving transistor T in each pixel circuit P; during the overlap time t421 between the effective pulse of the third scan signal s31 output by the second-level first scan unit During the overlap time t422 of the second valid pulse of the fourth scan signal s42 output by 21, the data writing transistor M2 and the first reset compensation transistor M31 of each pixel circuit P in the second row are turned on again, which can accurately write the data signal Vdata corresponding to each pixel circuit P in the second row to the gate of the driving transistor T in each pixel circuit P; after completing the two resets and two data signal Vdata writings of each pixel circuit in the first and second rows, the light-emitting stage t40 of the two rows of pixel circuits P can be entered simultaneously, driving the light-emitting element D of the two rows of pixel circuits P to emit light.

[0143] In this way, the reset and write phases of each row pixel circuit P can be performed in time without affecting each other. This is beneficial for the accurate writing of data signals of each pixel circuit P, while also reducing the number of scanning circuits and scanning units set in the display panel 100, and thus contributing to the narrow bezel of the display panel 100.

[0144] Optional, Figure 24 This is a schematic diagram of the pixel circuit structure in another display panel provided by an embodiment of the present invention, as shown below. Figure 24 As shown, the pixel circuit P further includes a second compensation transistor M32; the gate of the second compensation transistor M32 is electrically connected to the sixth scan terminal S6; the second compensation transistor M32 is electrically connected between the gate of the driving transistor T and the first terminal of the first compensation transistor M31; in the same pixel circuit P, the time of at least a portion of the effective pulse of the sixth scan signal s6 of the sixth scan terminal S6 overlaps with the time of the effective pulse of the third scan signal s3 of the third scan terminal S3, and the time of at least a portion of the effective pulse of the sixth scan signal s6 overlaps with the time of at least a portion of the effective pulse of the fourth scan signal s4.

[0145] Since the second compensation transistor M32 is electrically connected between the gate of the first compensation transistor M31 and the gate of the driving transistor T, the signal at the third node N3 can only be transmitted to the gate of the driving transistor T when both the second compensation transistor M32 and the first compensation transistor M31 are in the on state. Thus, during the writing stage of the data signal Vdata, the data writing transistor M2, the first compensation transistor M31 and the second compensation transistor M32 can be controlled to be turned on simultaneously, so that the data signal Vdata at the data signal terminal DATA can be transmitted to the gate of the driving transistor T in sequence through the on-state data writing transistor M2, driving transistor T, first compensation transistor M31 and second compensation transistor M32.

[0146] In an alternative embodiment, Figure 25 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 24 and Figure 25 In each driving cycle of the pixel circuit P, both the fourth scan signal s4 and the sixth scan signal s6 can include at least two valid pulses. Taking the example that both the fourth scan signal s4 and the sixth scan signal s6 have two pulses, during the overlap between the effective pulse time t30' of the third scan signal s3 and the effective pulse times (t41 and t42) of the fourth scan signal s4 and the sixth scan signal s6, at least two write operations of the data signal Vdata can be completed, thereby improving the accuracy of the written data signal Vdata. Thus, when the effective pulse time of the third scan signal s3 is long, the write time of the data signal Vdata can be controlled by separately controlling the effective pulse times of the fourth scan signal s4 and the sixth scan signal s6.

[0147] It is understandable that the second compensation transistor M32 is electrically connected between the driving transistor T and the first compensation transistor M31. That is, the first terminal of the first compensation transistor M31 is electrically connected to the second terminal of the driving transistor T at the third node N3, the second terminal of the first compensation transistor M31 is electrically connected to the first terminal of the second compensation transistor M32, and the second terminal of the second compensation transistor M32 is electrically connected to the gate of the driving transistor T. In this way, the first compensation transistor M31 and the second compensation transistor M32 can be connected in series.

[0148] In other alternative embodiments, such as Figure 26As shown, the second compensation transistor M32 can also be electrically connected between the second terminal of the first compensation transistor M31 and the second terminal of the driving transistor T. In this case, the first terminal of the second compensation transistor M32 and the second terminal of the driving transistor T are electrically connected to the third node N3, the second terminal of the second compensation transistor M32 is electrically connected to the first terminal of the first compensation transistor M31, and the second terminal of the first compensation transistor M31 is electrically connected to the gate of the driving transistor T. In this case, the first compensation transistor M31 and the second compensation transistor M32 can also be connected in series.

[0149] It should be noted that, Figure 24 and Figure 26 The connection methods described are merely two exemplary connection methods in this embodiment of the invention. The driving processes corresponding to these two connection methods are similar, and both can realize the writing of the data signal Vdata by controlling the conduction time of the first compensation transistor M31, the second compensation transistor M32, and the data writing transistor M2. For ease of description, the following will all refer to... Figure 25 The following example illustrates the situation.

[0150] It is understandable that the channel types of the first compensation transistor M31 and the second compensation transistor M32 can be the same or different. When the channel types of the first compensation transistor M31 and the second compensation transistor M32 are the same, for example, both the first compensation transistor M31 and the second compensation transistor M32 are N-channel transistors or both are P-channel transistors; when the channel types of the first compensation transistor M31 and the second compensation transistor M32 are different, the first compensation transistor M31 is an N-channel transistor and the second compensation transistor M32 is a P-channel transistor, and vice versa.

[0151] For example, taking the first compensation transistor M31 as an N-channel transistor and the second compensation transistor M32 as a P-channel transistor, when the third scan signal s3 is high and the sixth scan signal s6 is low, the first compensation transistor M31 and the second compensation transistor M32 are simultaneously turned on; conversely, when the third scan signal s3 is low, the first compensation transistor M31 is turned off, and when the sixth scan signal s6 is high, the second compensation transistor M32 is turned off; thus, the time when the third scan signal s3 is high is the effective pulse time of the third scan signal, and the time when the sixth scan signal s6 is low is the effective pulse time of the sixth scan signal s6.

[0152] In an alternative embodiment, in conjunction with reference to Figure 25 and Figure 26When the channel type of the data writing transistor M2 is the same as the channel type of the second compensation transistor M32, the fourth scan terminal S4 can be reused as the sixth scan terminal S6.

[0153] Specifically, when the fourth scanning terminal S4 is multiplexed as the sixth scanning terminal S6, the fourth scanning signal s4 provided to the fourth scanning terminal S4 can control the data writing transistor M2 and the second compensation transistor M32 to be turned on or off simultaneously. When the data writing transistor M2 and the second compensation transistor M32 are turned on simultaneously, a path can be provided for writing the data signal Vdata. At the same time, by multiplexing the fourth scanning terminal S4 as the sixth scanning terminal S6, the number of scanning terminals set in the pixel circuit P can be reduced, the structure of the pixel circuit P can be simplified, and the size occupied by the pixel circuit P and its corresponding scan lines in the display area can be reduced, which is beneficial to the high resolution of the display panel. In addition, by multiplexing the fourth scanning terminal S4 as the sixth scanning terminal S6, it is not necessary to provide the fourth scanning signal s4 and the sixth scanning signal s6 to the pixel circuit P separately, so as to realize the control of the data writing transistor M2 and the second compensation transistor M32 in the pixel circuit P. This can reduce the number of scanning signals provided to the pixel circuit P and the number of scanning circuits set in the non-display area, which is beneficial to the narrow bezel of the display panel.

[0154] In an alternative embodiment, Figure 27 This is a schematic diagram of the pixel circuit structure in another display panel provided by an embodiment of the present invention, as shown below. Figure 27 As shown, when the pixel circuit P includes the second compensation transistor M32, the pixel circuit P may also include a bias adjustment transistor M6 electrically connected to the first pole of the driving transistor T.

[0155] For example, Figure 28 This is another driving timing diagram of a pixel circuit provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 27 and Figure 28 As shown, when the pixel circuit P includes both a bias adjustment transistor M6 and a second compensation transistor M32, the bias adjustment transistor M6 can enter the bias adjustment stage t50 after the writing stage (t42) of the data signal Vdata, so that the bias adjustment signal Vpark is written to the first pole (i.e., the second node N2) of the driving transistor T to adjust the bias of the driving transistor T. This ensures that the bias of the driving transistor T of each pixel circuit P is consistent before entering the light emission stage t40, which is beneficial to improving the display uniformity of the display panel.

[0156] It is understood that the above examples only exemplify that the bias adjustment stage t50 is located before the light emission stage t40 and after the writing stage t42 of the last data signal Vdata. Without affecting the core inventive point of the present invention, the present invention does not limit the specific time of the bias adjustment stage t50.

[0157] Based on the same inventive concept, embodiments of the present invention also provide a display device, which includes the display panel provided in the embodiments of the present invention. Therefore, this display device possesses the technical features of the display panel and its driving method provided in the embodiments of the present invention, and can achieve the beneficial effects of the display panel provided in the embodiments of the present invention. Similarities can be found in the above description of the display panel provided in the embodiments of the present invention, and will not be repeated here.

[0158] For example, Figure 29 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 29 As shown, the display device 200 includes the display panel 100 provided in this embodiment of the invention. The display device 200 provided in this embodiment of the invention can be any electronic product with display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc., and this embodiment of the invention does not make any special limitations on these categories.

[0159] It should be understood that the working process of the various forms of pixel circuits shown above can be used to reorder, add, or delete stages. For example, the stages in the working process of the pixel circuits described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and no limitation is made herein.

[0160] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: Display area; The display area includes multiple pixel circuits arranged in an array; The pixel circuit includes a driving transistor and a reset module; The reset module is electrically connected to the gate of the driving transistor at the first node; The reset module includes a first reset transistor and a second reset transistor; the first reset transistor and the second reset transistor are connected in series between the reset signal terminal and the first node; the gate of the first reset transistor is electrically connected to the first scan terminal, and the gate of the second reset transistor is electrically connected to the second scan terminal. The first reset transistor and the second reset transistor have different channel types; the effective pulse time of the first scan signal at the first scan terminal overlaps with the time of at least two effective pulses of the second scan signal at the second scan terminal. The display area also includes multiple first scan lines and second scan lines; at least a portion of the first scan terminals of the pixel circuits in the same row are electrically connected to the same first scan line; at least a portion of the second scan terminals of the pixel circuits in the same row are electrically connected to the same second scan line. The display panel also includes a non-display area surrounding the display area; the non-display area includes a first scanning circuit and a second scanning circuit; the first scanning circuit includes a plurality of cascaded first scanning units, and the second scanning circuit includes a plurality of cascaded second scanning units; Each level of the first scanning unit is electrically connected to the adjacent N first scanning lines; each level of the first scanning unit is used to provide a first scanning signal to each of the first scanning lines; the effective pulses of the first scanning signals output by each level of the first scanning unit are shifted sequentially, and the shift amount of the effective pulses of the first scanning signals at each level is less than the width of the effective pulses of the first scanning signals; where N is a positive integer greater than or equal to 2; Each level of the second scanning unit is electrically connected to each of the second scanning lines; the effective pulses of the second scanning signals output by each level of the second scanning unit are shifted sequentially, and the shift amount of the effective pulses of the second scanning signals output by each level of the second scanning unit is greater than or equal to the width of the effective pulses of the second scanning signal; The time interval between the start times of the effective pulses of the first scan signal output by two adjacent first scan units is the first time; in the N consecutive second scan units, the effective pulses of the second scan signal output by each second scan unit are shifted sequentially, and the times of the effective pulses of the second scan signal output by each second scan unit do not overlap; the total time of the first effective pulse of the second scan signal output by each second scan unit in the N consecutive second scan units is the second time; wherein, the first time is greater than or equal to the second time.

2. The display panel according to claim 1, characterized in that, In the same pixel circuit, the start time of the effective pulse of the first scan signal is before the start time of the first effective pulse of the second scan signal, and the end time of the effective pulse of the first scan signal is after the end time of the last effective pulse of the second scan signal.

3. The display panel according to claim 1, characterized in that, The first terminal of the second reset transistor is electrically connected to the reset signal terminal, and the second terminal of the second reset transistor is electrically connected to the first terminal of the first reset transistor; the second terminal of the first reset transistor is electrically connected to the first node; the first reset transistor is an N-channel transistor, and the second reset transistor is a P-channel transistor.

4. The display panel according to claim 1, characterized in that, The pixel circuit also includes a data writing transistor and a first compensation transistor; The gate of the first compensation transistor is electrically connected to the third scan terminal, the first terminal of the first compensation transistor is coupled to the second terminal of the driving transistor at the third node, and the second terminal of the first compensation transistor is coupled to the gate of the driving transistor at the first node. The gate of the data writing transistor is electrically connected to the fourth scan terminal, the first terminal of the data writing transistor is connected to the data signal terminal, and the second terminal of the data writing transistor is electrically connected to the first terminal of the driving transistor at the second node. In the same pixel circuit, the effective pulse time of the third scan signal of the third scan end overlaps with the effective pulse time of the fourth scan signal of the fourth scan end.

5. The display panel according to claim 4, characterized in that, The channel type of the first compensation transistor is the same as that of the first reset transistor; The display area further includes multiple first scan lines and multiple third scan lines; at least a portion of the pixel circuits located in the same row have their first scan terminals electrically connected to the same first scan line, and at least a portion of the pixel circuits located in the same row have their third scan terminals electrically connected to the same third scan line. The display panel further includes a non-display area; the non-display area includes a first scanning circuit; the first scanning circuit includes a plurality of cascaded first scanning units; the first scanning line and the third scanning line electrically connected to the same pixel circuit are respectively electrically connected to the two adjacent levels of the first scanning units, and the first scanning unit of the previous level is electrically connected to the first scanning line, and the first scanning unit of the next level is electrically connected to the third scanning line. The first-level first scanning unit is electrically connected to N first scanning lines, and the last-level first scanning unit is electrically connected to N third scanning lines; in each level of the first scanning unit between the first-level and last-level first scanning units, each level of the first scanning unit is electrically connected to N adjacent first scanning lines and N adjacent third scanning lines; where N is a positive integer greater than or equal to 2; The effective pulses of the first scan signal output by each of the first scan units are shifted sequentially, and the shift amount of the effective pulses of each of the first scan signals is less than the width of the effective pulses of the first scan signal.

6. The display panel according to claim 5, characterized in that, In each of the pixel circuits electrically connected to the same first scanning unit, the termination time of the first valid pulse of the second scanning signal is all located before the start time of the valid pulse of the fourth scanning signal.

7. The display panel according to claim 5, characterized in that, In each of the pixel circuits electrically connected to the same first scanning unit, the start time of the effective pulse of the fourth scanning signal is located after the end time of the effective pulse of the first scanning signal.

8. The display panel according to claim 5, characterized in that, The display area also includes multiple second scan lines and multiple fourth scan lines; at least a portion of the second scan terminals of the pixel circuits in the same row are electrically connected to the same second scan line, and at least a portion of the fourth scan terminals of the pixel circuits in the same row are electrically connected to the same fourth scan line. The non-display area further includes a second scanning circuit and a third scanning circuit; the second scanning circuit includes a plurality of cascaded second scanning units; the third scanning circuit includes a plurality of cascaded third scanning units; Each second scanning unit is electrically connected to the adjacent N second scanning lines; the effective pulses of the second scanning signal output by each second scanning unit are shifted sequentially, and the shift amount of the effective pulses of the second scanning signal is greater than or equal to the width of the effective pulses of the second scanning signal; Each of the third scanning units is electrically connected to each of the fourth scanning lines; the effective pulses of the fourth scanning signal output by each of the third scanning units are shifted sequentially, and the shift amount of the effective pulses of the fourth scanning signal is greater than or equal to the width of the effective pulses of the fourth scanning signal.

9. The display panel according to claim 8, characterized in that, The width of the effective pulse of the second scan signal is greater than or equal to N times the width of the effective pulse of the fourth scan signal; In the same pixel circuit, the effective pulse time of the second scan signal does not overlap with the effective pulse time of the fourth scan signal.

10. The display panel according to claim 4, characterized in that, In the same pixel circuit, the time of the effective pulse of the third scan signal of the third scan end overlaps with the time of at least two effective pulses of the fourth scan signal of the fourth scan end.

11. The display panel according to claim 10, characterized in that, In the same pixel circuit, the timing of a portion of the effective pulses of the fourth scan signal lies between the timings of two adjacent effective pulses of the second scan signal.

12. The display panel according to claim 10, characterized in that, The channel type of the data writing transistor is the same as the channel type of the second reset transistor; The display area further includes multiple first scan lines, multiple second scan lines, and multiple fourth scan lines; at least a portion of the pixel circuits located in the same row have their first scan terminals electrically connected to the same first scan line, at least a portion of the pixel circuits located in the same row have their second scan terminals electrically connected to the same second scan line, and at least a portion of the pixel circuits located in the same row have their fourth scan terminals electrically connected to the same fourth scan line. The display panel also includes a non-display area; the non-display area includes a first scanning circuit and a second scanning circuit; the first scanning circuit includes a plurality of cascaded first scanning units; the second scanning circuit includes a plurality of cascaded second scanning units; Each first scanning unit is electrically connected to N adjacent first scanning lines; each first scanning unit is used to provide a first scanning signal to each first scanning line; the effective pulse of the first scanning signal output by each first scanning unit is shifted sequentially, and the shift amount of the effective pulse of each first scanning signal is less than the width of the effective pulse of the first scanning signal; where N is a positive integer greater than or equal to 2. Each level of the second scanning unit is electrically connected to each of the second scanning lines and each of the fourth scanning lines, and the two levels of the second scanning units corresponding to the second scanning lines and the fourth scanning lines electrically connected to the same pixel circuit are respectively the i-th level second scanning unit and the (i+N)-th level second scanning unit; the effective pulses of the second scanning signal and / or the fourth scanning signal output by each level of the second scanning unit are shifted sequentially, and the shift amount of the effective pulses of the second scanning signal and / or the fourth scanning signal is greater than or equal to the width of the effective pulse of the second scanning signal.

13. The display panel according to claim 4, characterized in that, The pixel circuit further includes a bias adjustment transistor; the gate of the bias adjustment transistor is electrically connected to the fifth scan terminal, the first terminal of the bias adjustment transistor is electrically connected to the bias adjustment terminal, and the second terminal of the bias adjustment transistor is electrically connected to the first terminal of the driving transistor. In the same pixel circuit, the time of at least a portion of the effective pulses of the fifth scan signal at the fifth scan end does not overlap with the time of the effective pulses of the third scan signal, and the time of the effective pulses of the fifth scan signal does not overlap with the time of the effective pulses of the fourth scan signal.

14. The display panel according to claim 13, characterized in that, The effective pulse of the fifth scan signal is part of the first effective pulse; In the same pixel circuit, the time of the first valid pulse of the fifth scan signal overlaps with the time of the valid pulse of the third scan signal, and the time of the first valid pulse of the fifth scan signal is located between the times of the valid pulses of two adjacent second scan signals.

15. The display panel according to claim 14, characterized in that, The display area further includes a second scan line and a fifth scan line; at least a portion of the second scan terminals of the pixel circuits in the same row are electrically connected to the same second scan line; at least a portion of the fifth scan terminals of the pixel circuits in the same row are electrically connected to the same fifth scan line; The display panel also includes a non-display area; the non-display area also includes a second scanning circuit; the second scanning circuit includes a plurality of cascaded second scanning units; the second scanning line and the fifth scanning line electrically connected to the same pixel circuit are respectively electrically connected to two adjacent odd-numbered level second scanning units or two adjacent even-numbered level second scanning units, and the previous level second scanning unit is electrically connected to the second scanning line, and the next level second scanning unit is electrically connected to the fifth scanning line; The effective pulses of the second scan signal output by each of the second scan units are shifted sequentially, and the shift amount of the effective pulses of the second scan signal is greater than or equal to the width of the effective pulses of the second scan signal.

16. The display panel according to claim 15, characterized in that, The second scanning circuit includes M-level second scanning units; the first-level second scanning unit and the second-level second scanning unit are electrically connected to the adjacent N second scanning lines respectively, and the (M-1)-level second scanning unit and the M-level second scanning unit are electrically connected to the adjacent N fifth scanning lines respectively; wherein, M is an even number greater than or equal to 4, and N is a positive integer greater than or equal to 2; In each level of the second scanning unit between the second level of the second scanning unit and the (M-1)th level of the second scanning unit, each level of the second scanning unit is electrically connected to the adjacent N second scanning lines and the adjacent N fifth scanning lines.

17. The display panel according to claim 4, characterized in that, The pixel circuit further includes a second compensation transistor; the gate of the second compensation transistor is electrically connected to the sixth scan terminal; The second compensation transistor is electrically connected between the second terminal of the driving transistor and the first terminal of the first compensation transistor, or the second compensation transistor is electrically connected between the second terminal of the first compensation transistor and the gate of the driving transistor; In the same pixel circuit, the time of at least a portion of the effective pulses of the sixth scan signal of the sixth scan end overlaps with the time of the effective pulses of the third scan signal of the third scan end, and the time of at least a portion of the effective pulses of the sixth scan signal overlaps with the time of at least a portion of the effective pulses of the fourth scan signal.

18. The display panel according to claim 17, characterized in that, The channel type of the first compensation transistor is different from that of the second compensation transistor.

19. The display panel according to claim 17, characterized in that, The channel type of the data writing transistor is the same as that of the second compensation transistor. The fourth scanning end is multiplexed as the sixth scanning end.

20. A display device, characterized in that, include: The display panel according to any one of claims 1-19.

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