Capacitance measurement and apparatus for resistive switching memory devices

Abstract

A semiconductor device comprising: a two-terminal memory device characterized by a programming voltage range and a first capacitance, wherein the two-terminal memory device is coupled in parallel between a ground and a first common node; a first capacitor having a second capacitance coupled between the ground and a second common node; a voltage source configured to provide an input voltage lower than the programming voltage range; a first operational amplifier comprising an inverting input, a non-inverting input, and an output, wherein the non-inverting input is coupled to the first voltage source, wherein the inverting input is coupled to a third common node, and wherein the output is coupled to a fourth common node; a first resistive device coupled between the third common node and the fourth common node, and wherein the first common node is coupled to the second common node and the third common node.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims the benefit of U.S. Provisional Application No. 62 / 888000, filed August 16, 2019, entitled “RERAM CAPACITANCE MEASUREMENT AND APPARATUS”, the entire contents of which are incorporated herein by reference and used for all purposes.

[0003] By citing the incorporated literature

[0004] U.S. Patent Application No. 14 / 588185, filed December 31, 2014, entitled "SELECTOR DEVICE FOR TWO-TERMINAL MEMORY"; U.S. Patent Application No. 14 / 717185, filed May 20, 2015, entitled "NON-VOLATILE MEMORY CELLUTILIZING VOLATILE SWITCHING TWO TERMINAL DEVICE AND A MOS TRANSISTOR"; U.S. Patent Application No. 15 / 066504, filed March 10, 2016, entitled "SELECTOR-BASED NON-VOLATILE CELL UTILIZING IC-FOUNDRY COMPATIBLE PROCESS"; and U.S. Patent Application No. 15 / 066504, filed June 30, 2015, entitled "SENSING A NON-VOLATILE MEMORY DEVICE UTILIZING SELECTORDEVICE HOLDING". U.S. Patent Application No. 14 / 755998 entitled “CHARACTERISTICS” and U.S. Patent Application No. 15 / 469179 entitled “SWITCHING BLOCK CONFIGURATION BIT COMPRISING ANON-VOLATILE MEMORYCELL”, filed March 24, 2017, are incorporated herein by reference in their entirety and for all purposes. Technical Field

[0005] Embodiments of this disclosure relate to electronic memory structures; for example, various embodiments disclose apparatus and methods for measuring the capacitance of electronic memory devices. background

[0006] The inventors recognized the various solid-state memory architectures used in modern electronic memory and computing devices. Strict control over the processes used to manufacture modern solid-state memory architectures is crucial for creating correctly functioning memory structures and achieving tight consistency across multiple devices.

[0007] In various embodiments, the inventors of this disclosure aim to minimize the impact of variations in semiconductor manufacturing processes. Process variations can differ between multiple semiconductor wafers produced by a single process, between dies within a single wafer, or both. These process variations can, in turn, cause performance variations in the memory structure on a given die. Performance variations exceeding acceptable manufacturing limits are typically considered defective parts and are discarded. This reduction in acceptable yield increases the indirect costs of the entire process. While some performance variations are small enough to remain within target operating specifications, they can still adversely affect memory performance over time.

[0008] In view of the above, the inventors hope to have a new mechanism to overcome the current challenges in dealing with existing memory structures in the art and to mitigate the impact of process changes. Summary of the Invention

[0009] The following is a simplified summary of this disclosure to provide a basic understanding of some of the aspects described herein. This summary is not a comprehensive overview of the disclosed subject matter. It is neither intended to identify key or critical elements disclosed, nor to describe the scope of this innovation. Its sole purpose is to present some concepts of the disclosed subject matter in a simplified form as a prelude to a more detailed description that follows.

[0010] Various embodiments of the present invention relate to the manufacture of semiconductor two-terminal memory devices, including arrays of non-volatile ReRAM memories currently developed by the assignee of this application, Crossbar, Inc. Further embodiments relate to the manufacture of semiconductor memory devices including volatile two-terminal resistive switching devices, such as selector devices (e.g. The selector device was also developed by Crossbar, Inc. Further embodiments relate to the fabrication of semiconductor memory devices comprising one or more arrays of very high-speed non-volatile memory devices, which accordingly include transistors, selector devices, and optional capacitors. Other embodiments relate to the fabrication of other two-terminal memory devices, such as filamentary memory devices, magnetoresistive memory devices, phase-change memory devices, carbon nanotube memory devices, conductive bridged memory devices, silicon suboxide memory devices, metal oxide memory devices, etc.

[0011] In various types of two-terminal memory devices, and for more advanced semiconductor processing nodes, variations in memory layer thickness affect the operation of the memory device and its peripheral circuitry. Due to process variations, the memory layer thickness may differ between two-terminal memory devices within the same die, and may also differ between different dies across a wafer. These varying memory layer thicknesses affect the characteristics of two-terminal memories, such as programming, reading, and erasing voltages; programming, reading, and erasing speeds; and programming, reading, and erasing characteristics.

[0012] In some cases, variations in memory layer thickness can be compensated for by setting trim values ​​and other parameters during programming, read, or erase cycles. In other cases, the memory layer thickness may exceed specifications too much to be compensated for by trim values, and such devices may be considered defective dies. In either case, the ability to accurately measure these memory layer thickness variations during manufacturing can significantly improve quality control in the manufacturing process, identify devices operating within acceptable limits, identify appropriate trim values ​​to aid in proper operation from wafer to wafer and die to die, and optimize manufacturing costs overall.

[0013] Because the electrical characteristics of memory layers (e.g., programming, reading, and erasing conditions) can vary depending on the thickness of the memory layer, various embodiments involve efficient and effective mechanisms for determining the thickness of memory layers in a two-terminal memory device. In some embodiments, the thickness can be measured directly from a cross-sectional image of the device. However, this technique is expensive and impractical on a production line. In other embodiments, the thickness can be determined indirectly by measuring the parasitic capacitance of these layers. In some embodiments, the parasitic capacitance can be measured by connecting external electronic equipment to electrical connection points on the die / wafer surface. These embodiments can be cumbersome and error-prone if the contact points on the die / wafer surface are small, or they can consume excessive die / wafer surface area if the contact is large. These are also impractical on a production line. Furthermore, different portions of one or more memory layers may not be selectively accessible via external contact points. Therefore, there is a need for indirect measurement of the thickness of memory layers within a semiconductor die or wafer, particularly in modern high-volume manufacturing environments, to facilitate accurate and repeatable indirect measurements.

[0014] Some disclosed embodiments provide an on-die circuit that can be selectively connected to different groups of two-terminal resistive switching devices to measure the parasitic capacitance of the resistive switching devices from within the die itself. In some embodiments, this circuit can be integrated into a control of an array of resistive switching devices (e.g., see below). Figure 12The peripheral circuitry accessing the memory array may be fabricated, at least partially, on the substrate of the die, at least partially within the memory layer of the die, or within other portions of the die, or a suitable combination thereof. In one or more embodiments, the circuitry may be a resistor-capacitor (RC) circuit with an output frequency that varies according to the parasitic capacitance of a resistive switching device coupled to the RC circuitry. In another embodiment, this disclosure may provide multiple on-die circuits to measure different portions of the memory array. In still other embodiments, this disclosure may provide multiple circuits on different dies of the wafer to test the uniformity of the memory layer across different portions of the wafer.

[0015] In embodiments, this disclosure provides a semiconductor device. The semiconductor device may include a first plurality of two-terminal memory devices, wherein each of the two-terminal memory devices is characterized by a programming voltage within a programming voltage range, wherein the first plurality of two-terminal memory devices are associated with a first capacitor, and wherein the first plurality of two-terminal memory devices are selectively coupled in parallel between ground and a first common node. Furthermore, the semiconductor device may include: a first capacitor coupled between ground and a second common node, wherein the first capacitor is characterized by a second capacitor; and a first voltage source configured to provide a first input voltage, wherein the first input voltage is smaller than the programming voltage range. Additionally, the semiconductor device may include a first operational amplifier including an inverting input, a non-inverting input, and an output, wherein the non-inverting input is coupled to the first voltage source, wherein the inverting input is coupled to a third common node, and wherein the output is coupled to a fourth common node. Furthermore, the semiconductor device may include a first resistive device coupled between the third and fourth common nodes, wherein the first common node is coupled to both the second and third common nodes.

[0016] Another embodiment of this disclosure provides a method for operating a semiconductor device. The method may include closing a first switch and coupling a first plurality of two-terminal memory devices to an inverting input of a first operational amplifier, wherein each of the first plurality of two-terminal memory devices is characterized by a programming voltage within a first programming voltage range, wherein a first capacitor is coupled between the inverting input of the first operational amplifier and ground, and wherein a first resistor is coupled between the inverting input of the first operational amplifier and the output of the first operational amplifier. In addition to the above, the method may include providing a first input voltage to a non-inverting input of the first operational amplifier using a first voltage source, wherein the first input voltage is less than a minimum programming voltage within the first programming voltage range. The method may further include outputting a first signal using the first operational amplifier, wherein the first signal is characterized by a first oscillation frequency, wherein the first oscillation frequency is responsive to a first capacitor associated with the first plurality of two-terminal memory devices. Additionally, the method may include measuring a frequency value of the first oscillation frequency and storing an indicator associated with the measurement of the first oscillation frequency in a memory.

[0017] The following description and accompanying drawings illustrate certain illustrative aspects of the specification. However, these aspects indicate only a few of the various ways in which the principles of this specification can be employed. Other advantages and novel features of the specification will become apparent from the following detailed description when considered in conjunction with the accompanying drawings. Attached Figure Description

[0018] Many aspects, embodiments, objects, and advantages of the invention will become apparent upon consideration of the following detailed description taken in conjunction with the accompanying drawings, in which like reference numerals refer to like parts throughout. Numerous specific details are set forth in this specification to provide a thorough understanding of the present disclosure. However, it should be understood that certain aspects of the present disclosure may be practiced without these specific details, or implemented with other methods, components, materials, etc. In other instances, well-known structures and apparatuses are shown in block diagram form to facilitate the description of the present disclosure;

[0019] Figure 1 A schematic diagram of an example circuit for determining the capacitance of one or more resistive switching devices (RSDs) in the disclosed embodiment is depicted.

[0020] Figure 2 A schematic diagram of an example circuit is shown for providing a frequency output proportional to the capacitance of a switching device coupled to the circuit.

[0021] Figure 3 A public implementation of a capacitor for determining nonvolatile RSD is described;

[0022] Figure 4A public embodiment of a capacitor for determining volatile RSD is shown;

[0023] Figure 5 An implementation for determining the capacitance of a memory cell having a volatile RSD in series with a non-volatile RSD is described.

[0024] Figure 6 An implementation of a capacitor for determining a plurality of RSDs or a capacitor for a memory cell consisting of volatile and non-volatile RSDs is shown;

[0025] Figure 7 An implementation method for determining the relationship between the frequency of an RC circuit and the average capacitance of the RSD group coupled to the RC circuit is described.

[0026] Figure 8 A flowchart illustrating an example method for determining the capacitance of multiple two-terminal memory devices in a memory array is shown.

[0027] Figure 9 A flowchart is shown illustrating an example method for adjusting trim values ​​of a memory array by determining the capacitance on the die of the memory device.

[0028] Figure 10 A flowchart is depicted in some disclosed embodiments of an example method for determining the uniformity of memory layers across multiple dies on a wafer.

[0029] Figure 11 A flowchart of an example method for determining the range of memory layer characteristics across a single die, in another embodiment, is shown.

[0030] Figure 12 A block diagram depicts an example electronic operating environment according to certain embodiments of the present disclosure;

[0031] Figure 13 A block diagram of an example computing environment for implementing one or more of the disclosed embodiments presented herein is shown. Detailed Implementation

[0032] As the name suggests, a two-terminal resistive switching device has two terminals or electrodes. Here, the terms "electrode" and "terminal" are used interchangeably; furthermore, two-terminal resistive switching devices include both non-volatile two-terminal memory devices and volatile two-terminal switching devices. Typically, the first electrode of a two-terminal resistive switching device is referred to as the "top electrode" (TE), and the second electrode as the "bottom electrode" (BE). However, it should be understood that the electrodes of a two-terminal resistive switching device can be arranged in any suitable manner, including a horizontal arrangement, where the components of the memory cells are (substantially) side-by-side rather than overlapping each other. Between the TE and BE of a two-terminal resistive switching device is typically an interface layer, sometimes also referred to as a switching layer, resistive switching medium (RSM), or resistive switching layer (RSL); however, such devices are not limited to these layers. One or more barrier layers, adhesion layers, ion-conducting layers, seed layers, etc., as disclosed herein, disclosed in any publication incorporated herein by reference, or as commonly understood and used in the art, may be included between or near one or more of the TE, BE, or interface layers consistent with the proper operation of such devices. Various embodiments of this disclosure provide an array of memory devices including circuitry fabricated on a die, for determining the capacitance of one or more two-terminal resistive switching devices in the array. An architecture for controlling and operating the array of memory devices is also provided.

[0033] Generally, the composition of memory cells varies depending on the device, which has different components selected to achieve desired characteristics (e.g., volatile / non-volatile, on / off current ratio, switching time, read time, memory endurance, program / erase cycle time, etc.). An example of a filament-based device may include: a conductive layer, such as a metal, metal alloy, or metal nitride (e.g., including TiN, TaN, TiW, or other suitable metal compounds); an optional interface layer (e.g., a doped p-type (or n-type) silicon (Si) carrier layer (e.g., p-type or n-type Si carrier layer, p-type or n-type polycrystalline silicon, p-type or n-type polycrystalline SiGe, etc.)); a resistive switching layer (RSL); and an active metallized layer capable of being ionized. Under suitable conditions, the active metallized layer can provide ions formed by the filament to the RSL. In such embodiments, the conductive filament (e.g., formed by ions) can promote conductivity through at least a subset of the RSL, and, as an example, the resistance of the filament-based device can be determined by the tunneling resistance between the filament and the conductive layer. Memory cells with these characteristics can be described as filament-based devices.

[0034] The RSL (which may also be referred to in the art as a resistive switching medium (RSM)) may include, for example: an undoped amorphous Si-containing layer, a semiconductor layer with intrinsic properties, or silicon nitride (such as SiN, Si3N4, SiN...). x (etc.), silicon oxides (e.g., SiO2) x (where x has a value between 0.1 and 2), silicon subnitride, metal oxides, metal nitrides, non-stoichiometric silicon compounds, etc. Other examples of materials suitable for RSL may include Si. X Ge Y O Z (where x, y, and z are the corresponding appropriate positive numbers), silicon dioxide (e.g., SiO2). N (where N is an appropriate positive number), silicon oxynitride, undoped amorphous silicon (a-Si), amorphous SiGe (a-SiGe), TaO B (where B is a suitable positive number), HfO C (where C is a suitable positive number), TiO D (where D is an appropriate number), Al2O E (where E is an appropriate positive number) etc., nitrides (e.g., AlN, SiN), or appropriate combinations thereof.

[0035] In some embodiments, an RSL used as part of a non-volatile memory device (non-volatile RSL) may include a relatively large number (e.g., compared to a volatile selector device) of material voids or defects to trap neutral metal particles within the RSL (at least at low voltages). A large number of voids or defects can facilitate the formation of a thick, stable neutral metal particle structure. In such a structure, these trapped particles can maintain the non-volatile memory device in a low-resistance state without external stimuli (e.g., electricity), thereby enabling non-volatile operation. In other embodiments, an RSL for a volatile selector device (volatile RSL) may have very few material voids or defects for trapping particles. Because the voids / defects trapping the particles are few, the conductive filaments formed in such an RSL can be very thin (e.g., one to several particle widths, depending on the field strength, particle material, or RSL material, or a suitable combination of the foregoing), and unstable without a sufficiently high external stimuli (e.g., electric field, voltage, current, Joule heating, or a suitable combination thereof). Furthermore, the particles can be selected to have high surface energy and good diffusivity within the RSL. This yields conductive filaments that can rapidly form in response to appropriate stimuli, but are also readily deformable, for example, in response to external stimuli that decrease to a deformation amplitude (which can be lower than the formation amplitude associated with, for example, the formation of volatile conductive filaments in response to current flowing through a selector device; see U.S. Patent Application No. 14 / 755998, incorporated above by reference). Note that the volatile RSL and conductive filaments used for selector devices can have different electrical properties than the conductive filaments and non-volatile RSLs used for non-volatile memory devices. For example, the selector device RSL can have a higher material resistance and can have a higher on / off current ratio, etc.

[0036] Active metal-containing layers for filament-based memory cells may include the following: silver (Ag), gold (Au), titanium (Ti), titanium nitride (TiN) or other suitable titanium compounds, nickel (Ni), copper (Cu), aluminum (Al), chromium (Cr), tantalum (Ta), iron (Fe), manganese (Mn), tungsten (W), vanadium (V), cobalt (Co), platinum (Pt), hafnium (Hf), and palladium (Pd). In some aspects of this disclosure, other suitable conductive materials and combinations of compounds, nitrides, oxides, alloys, or the foregoing or similar materials may be used in the active metal-containing layer. Furthermore, in at least one embodiment, non-stoichiometric compounds such as non-stoichiometric metal oxides or metal nitrides (e.g., AlO) may be used. x AlNx, CuOx, CuNx, AgOx, AgNx, etc., where x is an appropriate positive number 0 < x < 2 (which can have different values ​​for different non-stoichiometric compounds) or other appropriate metal compounds can be used for active metal-containing layers.

[0037] In one or more embodiments, the disclosed filamentary resistive switching device may include an active metal layer comprising a metal nitride selected from the group consisting of TiNx, TaNx, AlNx, CuNx, WNx, and AgNx, where x is a positive number. In another embodiment, the active metal layer may include a metal oxide selected from the group consisting of TiOx, TaOx, AlOx, CuOx, WOx, and AgOx. In yet another embodiment, the active metal layer may include a metal nitride selected from the group consisting of TiOaNb, AlOaNb, CuOaNb, WOaNb, and AgOaNb, where a and b are positive numbers. The disclosed filamentary resistive switching device may further include a switching layer comprising a switching material selected from the group consisting of: SiOy, AlNy, TiOy, TaOy, AlOy, CuOy, TiNx, TiNy, TaNx, TaNy, SiOx, SiNy, AlNx, CuNx, CuNy, AgNx, AgNy, TiOx, TaOx, AlOx, CuOx, AgOx, and AgOy, wherein x and y are positive numbers, and y is greater than x. Various combinations thereof are contemplated and considered to be within the scope of embodiments of the present invention.

[0038] In one example, the disclosed filamentary resistive switching device includes a particle donor layer (e.g., an active metal layer) comprising a metal compound and a resistive switching layer. In an alternative embodiment of this example, the particle donor layer comprises a metal nitride: MNx, such as AgNx, TiNx, AlNx, etc., and the resistive switching layer comprises a metal nitride: MNy, such as AgOy, TiOy, AlOy, etc., where y and x are positive numbers, and in some cases y is greater than x. In an alternative embodiment of this example, the particle donor layer comprises a metal oxide: MOx, such as AgOx, TiOx, AlOx, etc., and the resistive switching layer comprises a metal oxide: MOy, such as AgOy, TiOy, AlOy, etc., where y and x are positive numbers, and in some cases y is greater than x. In another alternative, the metal compound of the particle donor layer is MNx (e.g., AgNx, TiNx, AlNx, etc.), and the resistive switching layer is selected from the group consisting of MOy (e.g., AgOx, TiOx, AlOx, etc.) and SiOy, where x and y are typically non-stoichiometric values, or in another embodiment, the reverse is true.

[0039] As used herein, variables x, a, b, etc., representing the value or ratio of one element relative to another (or other) element in a compound may have different values ​​applicable to the respective compound and are not intended to represent the same or similar values ​​or ratios in the compound. Some details relating to embodiments of this disclosure similar to the examples above can be found in the following U.S. patent applications assigned to the assignee of this patent application: Application No. 11 / 875541, filed October 19, 2007, and Application No. 12 / 575921, filed October 8, 2009; each of the foregoing patent applications is incorporated herein by reference in its entirety and for all purposes, except for those patent applications which are incorporated herein by reference elsewhere.

[0040] It should be understood that the various embodiments described herein can utilize a variety of memory cell technologies with different physical characteristics. For example, different resistive switching memory cell technologies can have different discrete programmable resistors, different associated programming / erasing voltages, and other differentiated characteristics. For example, various embodiments of this disclosure can employ a bipolar switching device that exhibits a first switching response (e.g., programming to one of a set of programming states) to an electrical signal of a first polarity and a second switching response (e.g., erasing to an erase state) to an electrical signal of a second polarity. For example, a bipolar switching device contrasts with a unipolar device that exhibits both a first switching response (e.g., programming) and a second switching response (e.g., erasing) in response to electrical signals of the same polarity but different amplitudes.

[0041] In various embodiments, filament-based resistive switching devices can operate in a bipolar manner, thus exhibiting different behaviors in response to external stimuli of different polarities (or directions, energy flows, energy source orientations, etc.). For a volatile filament-based selector device, as an illustrative example, in response to a first polarity stimulus exceeding a first threshold voltage (or voltage group), the filament selector device can change from a first resistive state to a second resistive state. Furthermore, in response to a second polarity stimulus exceeding a second threshold voltage, the filament selector device can change from a first state to a third state. In some embodiments, the third state can be substantially the same as the first state, having the same or similar measurably different characteristics (e.g., conductivity, etc.), having the same or similar threshold stimulus amplitudes (although opposite in polarity or direction), etc. In other embodiments, the third state can differ from the second state in terms of measurable characteristics (e.g., a different conductivity value in response to an opposite polarity compared to a positive polarity) or in terms of threshold stimuli that are excessively associated with the first state (e.g., a different positive voltage amplitude required to transition to the second state compared to the amplitude of the negative voltage required to transition to the third state).

[0042] For bipolar operation of non-volatile filament-based memory cells, conductive paths or filaments are formed through a non-volatile RSL in response to an appropriate programming voltage applied across the memory cell. Specifically, upon application of the programming voltage, metal ions are generated from an active metal-containing layer and migrate into the non-volatile RSL layer. The metal ions can occupy void or defect sites within the non-volatile RSL layer. In some embodiments, after the bias voltage is removed, the metal ions become neutral metal particles and remain trapped in the voids or defects of the non-volatile RSL layer. When a sufficient number of particles are trapped, a filament is formed and the memory cell switches from a relatively high resistance state to a relatively low resistance state. More specifically, the trapped metal particles provide conductive paths or filaments through the non-volatile RSL layer, and the resistance is typically determined by the tunneling resistance through the non-volatile RSL layer. In some resistive switching devices, an erase process can be implemented to deform the conductive filaments, thereby at least partially returning the memory cell from a low-resistance state to a high-resistance state. More specifically, when an erase bias voltage is applied, metal particles trapped in the gaps or defects of the non-volatile RSL become mobile ions and migrate back towards the active metal layer. In the context of memory, this state change can be associated with the corresponding state of a binary bit. For an array of multiple memory cells, one or more words, one or more bytes, one or more pages, one or more blocks, etc., of the memory cells can be programmed or erased to represent zeros or ones in binary information, and binary information is efficiently stored by retaining these states over time. In various implementations, multi-level information (e.g., multiple bits) can be stored in such memory cells.

[0043] Where no particular memory cell technology or programming / erasing voltage is specified for any aspect and implementation herein, these aspects and implementations are intended to be combined with any suitable memory cell technology and operated by a programming / erasing voltage suitable for that technology, as would be known to a person of ordinary skill in the art, or as would be known to a person of ordinary skill in the art through the context provided herein. It should also be understood that implementations including the replaced memory cell technology or changes in signal levels known to a person of ordinary skill in the art are considered within the scope of this disclosure where replacing a different memory cell technology would require circuit modifications known to a person of ordinary skill in the art or changes in operating signal levels known to such a person.

[0044] As described above, applying a programming voltage (also known as a “programming pulse”) to one of the electrodes of a two-terminal memory can cause a conductive filament to form in the interface layer (e.g., RSL). Conventionally, and as generally described herein, the TE receives the programming pulse and the BE is grounded (or maintained at a lower voltage or opposite polarity than the programming pulse), but this is not intended to limit all implementations. Conversely, applying an “erase pulse” to one of the electrodes (typically a pulse with the opposite polarity to the programming pulse or an electrode opposite to the programming pulse) can disrupt the continuity of the filament, for example, by driving the metal particles or other material forming the filament back to the active metal source. The characteristics of this conductive filament, and its presence or absence, affect the electrical characteristics of the two-terminal memory cell, such as, for example, reducing the resistance between the terminals and / or increasing the conductance between the terminals when the conductive filament is present compared to when it is absent.

[0045] Following a programming or erasing pulse, a read pulse is typically applied. The amplitude of this read pulse is usually lower than that of the programming or erasing pulse and is generally insufficient to affect the conductive filament and / or alter the state of the two-terminal memory cell. By applying a read pulse to one of the electrodes of the two-terminal memory, a measured current (e.g., Ion) can indicate the conductive state of the two-terminal memory cell when compared to a predetermined threshold current. The threshold current can be preset based on expected current values ​​for a two-terminal memory device suitable for a given two-terminal memory technology in different states (e.g., high-resistance state current; corresponding currents for one or more low-resistance states, etc.). For example, when a conductive filament has been formed (e.g., in response to the application of a programming pulse), the cell's conductance is greater than in other cases, and the measured current (e.g., Ion) reading in response to the read pulse will be larger. On the other hand, when the conductive filament is removed (e.g., in response to the application of an erasing pulse), the cell's resistance is higher because the interface layer has a relatively high resistance, so the cell's conductance is lower, and the measured current (e.g., Ioff) reading in response to the read pulse will be smaller. Conventionally, a memory cell is referred to as being in a "conducting state" with high conductivity when a conductive filament is formed. When the conductive filament is absent, the memory cell is referred to as being in a "turn-off state." Memory cells in the conducting or turning-off states can be logically mapped to binary values ​​such as, for example, "1" and "0". It should be understood that the conventions associated with the states of cells or the associated logical binary mappings used herein are not intended to be limiting, as other conventions, including the opposite conventions, can be used in conjunction with the disclosed subject matter. The techniques detailed herein are described and illustrated in conjunction with single-level cell (SLC) memory, but it should be understood that the disclosed techniques can also be used with multi-level cell (MLC) memory, in which a single memory cell can retain a set of measurably distinct states representing multiple bits of information.

[0046] Digital information can be stored in such devices by mapping it to the non-volatile resistive states of two-terminal memory cells. Electronic devices comprising many of these two-terminal memory cells can also store large amounts of data. High-density arrays are configured to include as many memory cells as possible for a given chip space, thereby maximizing the data storage capacity of the memory chip or system-on-a-chip device.

[0047] For two-terminal memories (e.g., cross-arrays) formed at the intersections of metal lines within a wafer, the inventors of this disclosure recognize two general conventions for arranging memory cells. The first convention is a 1T1R memory array, where each memory cell is isolated from the electrical effects (e.g., current, including leakage path current) of surrounding circuitry by an associated transistor. The second convention is a 1TnR memory array (where n is a positive number greater than 1), where multiple groups of memory cells are isolated from the electrical effects of surrounding circuitry by one (or more) transistors. In the 1T1R context, individual memory cells can be configured to have high current suppression between memory cells, thereby significantly reducing the leakage path current of the 1T1R memory array.

[0048] An example mechanism for connecting a 1T1R memory array includes a first terminal of a two-terminal resistive memory device connected to the drain of a transistor. The second terminal of the two-terminal resistive memory device can be connected to a bit line of the 1T1R memory array. Depending on the erase / programming conditions of the memory array, the source of the transistor is grounded or used as a source of erase or program signals. Another example mechanism involves a three-terminal memory including a transistor coupled to a volatile two-terminal resistive switching device (RSD). The first terminal of the volatile RSD is connected to the gate of the transistor, while the second terminal of the volatile RSD is connected to a voltage source. When activated, the volatile RSD allows charge to accumulate at the gate of the transistor, and when deactivated, the accumulated charge can be captured at the gate of the transistor. Other resistive switching device (RSD) circuits can be used within the scope of this disclosure.

[0049] Figure 1Examples of circuits 100 according to various embodiments of the present invention are shown. Such circuits, or suitable variations thereof, can be included in a semiconductor die incorporating two-terminal memory cells. In some embodiments, such circuits can be included in one die, multiple dies, or all dies on a semiconductor wafer. Circuit 100 can be configured to selectively connect to one or more resistive switching devices (RSDs) 114 on a given die to determine the capacitance of the RSDs. Based on the capacitance determination, the characteristics of the memory layer in which the RSDs are formed can be estimated or inferred. Typically, the RSD 114 is a two-terminal resistive switching device, but a three-terminal RSD 114 incorporating a volatile selector RSD and a transistor (and optional capacitor) can also be well utilized.

[0050] Figure 1 An operational amplifier 104 (OPAMP) is shown, having an inverting input 102A (-), a non-inverting input 102B (+), and an output 106 (out). A resistor R1 110 is connected between the output 106 and the inverting input 102A of the operational amplifier 104. Furthermore, a capacitor C1116 is connected between the inverting input 102A and ground. In one embodiment, the terminals of capacitor 116 and resistor 110 are connected to corresponding nodes, which in turn are connected to the inverting input 102A. In at least one embodiment, these corresponding nodes can be a single common node 112, as shown.

[0051] The inverting input 102A can also be connected to RSD114 at its first terminal. In one embodiment, the two-terminal RSD114 may include multiple RSDs connected in parallel between the common node 112 and ground. In another embodiment, the (two-terminal) RSD114 may be selectively connected to and disconnected from the common node 112 and circuit 100 (e.g., via a switch, multiplexer, or other suitable electrical connection; see below). Figure 2 Additionally, the non-inverting input 102B can be connected to a voltage source Vref, which can be configured to provide the non-inverting input 102B with a selected voltage, voltage amplitude, voltage waveform, etc. Output 106, if the operational amplifier 104 is additionally coupled to a (frequency) divider, such as through an N-way divider circuit (-:- / N; where N is an appropriate positive number).

[0052] As described above, RSD114 is coupled to the inverting input 102A at one (or more) terminals (e.g., via common node 112). RSD114 is coupled to the inverting input 102A to mimic the capacitor C. RSDIt can be in a non-conductive state. For nanoscale RSD technology, the capacitance of a single RSD can be very small. In order to have reasonable accuracy in determining the capacitance value of RSD114, the capacitance of RSD114 should be on the order of C1116 (or any suitable value or range therebetween), and preferably on the range of about 1 / 3 to about 3 times the value of C1116, or any suitable range or value therebetween. However, variations in the specified value within a range of one-tenth to a fraction of a specified voltage (e.g., the range of 0.1 volt, 0.2 volt, 0.3 volt, 0.1 volt to 0.5 volt, or suitable values ​​in both) or a fraction of a specified value (e.g., 1% to 25%, 5 to 20%, 1 to 15%, 5 to 15%, or any suitable value or any suitable percentage range therebetween) (or any specified value disclosed herein, unless the context clearly indicates otherwise) are considered to be within the meaning of the term “about” as used herein. It should be understood that the terms “about,” “approximately,” or other degree terms used herein are intended to refer to variations, ranges, or values ​​specified herein, or variations, ranges, or values ​​that would be reasonably understood by one of ordinary skill in the art, to provide the same or similar function and operation as a given component, part or element of the described apparatus, or its method or steps. Therefore, degree terms generally refer to values ​​or ranges that one of ordinary skill in the art would understand to facilitate the operation of the various embodiments described.

[0053] To achieve the desired capacitance C within the desired range RSD Multiple RSD114s can be connected in parallel to add their respective capacitances to a larger combined C. RSD In the case of a two-terminal RSD 114 comprising multiple resistive switching devices, these devices can be connected in parallel at their respective first terminals (e.g., at a common node 112) and grounded at their second terminals. In the case of a three-terminal RSD 114 comprising a volatile selector and a transistor (and optional capacitor), the first terminal of the volatile selector is selectively connected to the inverting input 102A, and its second terminal is connected to the gate of the transistor. Multiple such three-terminal RSDs 114 can be connected in parallel at their respective volatile selector first terminals.

[0054] In various implementations, any suitable number of RSD 114s, such as 10,000 to 20,000; 20,000 to 60,000, or any suitable range of values ​​between, can be used in parallel combination. Since each resistive switching device has a small capacitor, by coupling a large number of devices in parallel, the small capacitors add up to a total capacitance, up to which it is shown as C. RSD A large RSD capacitor.

[0055] During operation, the voltage source provides a voltage Vref lower than the programming voltage of RSD114 (or a range below the programming voltage). Thus, the voltage applied to the two-terminal memory device should not affect the programming state of the resistive switching device. In some embodiments, the programming voltage of the non-volatile two-terminal memory device is approximately 1 volt; therefore, the applied Vref should be less than 1 volt, such as 0.2 volts, 0.4 volts, 0.6 volts, 0.8 volts, etc., or any suitable value or range thereof. Furthermore, Vref is not limited to this example and other voltages lower than the switching voltage of RSD114 can be used. Therefore, Vref can have: a value or range of values ​​for a non-volatile two-terminal resistive random access memory (ReRAM) (e.g., 0.2V to 1.0V or any suitable value or range therebetween); different values / ranges of values ​​for a non-volatile phase-change, magnetoresistive, conductive bridge, or other suitable non-volatile memory; another value / range of values ​​for a volatile two-terminal selector device (e.g., 0.1V to 1.0V or any suitable value or range therebetween); and another value / range of values ​​for a non-volatile three-terminal RSD including a volatile two-terminal selector device (and optional capacitor) coupled to the gate of a transistor.

[0056] In response to the application of Vref, circuit 100 will begin to oscillate or "ring," and the output of operational amplifier 104 at output node 106 will oscillate at a detectable frequency. This oscillation is a result of the time delay of the voltage rise between the non-inverting input 102B and the inverting input 102A, and the R*(capacitor C1116+C) of RC circuit 100 (resistor 110). RSD The output of operational amplifier 104 is proportional to the voltage Vref at the non-inverting input 102B. When the voltage Vref at the non-inverting input 102B is higher than that at the inverting input 102A, the output of operational amplifier 104 increases; when the voltage at the inverting input 102A is higher than that at the non-inverting input 102B, the output of operational amplifier is toggled and decreases. The RC circuit 100 provides a delay that promotes the output of operational amplifier to be proportional to the sum of the capacitances: C1 and C2. RSD Proportional detectable frequency oscillations.

[0057] In some implementations, the voltage source can adjust Vref to different voltages below the minimum programming voltage within the appropriate programming voltage range associated with RSD 114. For example, where the programming voltage range of RSD 114 is between about 1.2 volts and about 1.5 volts, Vref can be set to different voltages at least below 1.2 volts or lower. In some implementations, different values ​​of Vref can cause operational amplifier 104 to oscillate at different frequencies. In other implementations, operational amplifier 104 can oscillate around the same oscillation frequency by applying different Vref voltages.

[0058] In other embodiments, a frequency divider 107 is provided. In at least one example, the frequency divider 107 may be a counter circuit, but this disclosure is not limited to that particular example. The frequency divider 7 may be configured to reduce the output of the operational amplifier 104 to a smaller frequency. In some embodiments, the frequency divider 7 may be configured (e.g., pre-manufactured) for a fixed frequency reduction factor (e.g., 20x, 50x, 100x, 1000x reduction, etc.) or may be programmed (e.g., post-manufactured) to one of a set of programmable frequency reduction values. Thus, as an example, the frequency divider 7 may be configured to provide a reduced frequency in MHz at the frequency divider output 108 in response to the original output of the operational amplifier 104 in GHz at output 106. As another example, the frequency divider 7 may receive a signal at a frequency in MHz at output 106 and output a signal at a frequency in kHz at output 108, etc.

[0059] Based on the measured or otherwise determined oscillation frequency, trim values ​​for the memory array can be adjusted for appropriate operation. Such trim values ​​can relate to programming, reading, or erasing: voltage, current, cycle period, cycle step size, voltage or current ramp value or ramp / increase rate, etc., or suitable combinations of the foregoing. For example, programming, reading, and erasing cycles may include applying one or more voltage pulses with different amplitudes, different pulse widths, different pulse-to-pulse relationships (e.g., ramp-up, ramp-down, ramp-up rate, ramp-down rate, etc.), different total cycle timing, different current limits, etc. In at least some of the disclosed embodiments, one, more, or all of these parameters can be modified by the aforementioned trim values. As a non-limiting illustrative example, a higher C can be inferred in response to a lower relative oscillation frequency. RSD This indicates a relatively thick memory layer. Therefore, a trim value associated with the programming time of RSD114 can be increased to compensate for the thicker memory layer. Conversely, for higher relative oscillation frequencies, the opposite is true, indicating a relatively thinner memory layer.

[0060] The trim value and circuitry for adjusting the trim value are typically included in on-die memory (non-volatile, volatile, etc.). In some embodiments, the die incorporating embodiments of this disclosure may be placed on a test apparatus, etc., and the oscillation frequency is determined by the test apparatus. The trim value can then be programmed using the test apparatus via a register embedded in the die. In other embodiments, the die may include additional circuitry (not depicted) that can automatically determine an appropriate trim value based on the oscillation frequency measured at output 108 and a programming capacitor value associated with the measured oscillation frequency. The measured oscillation frequency is related to C... RSD The correlation between capacitance values ​​can be stored in memory (not depicted, but see below). Figure 12and 13 It can be used as a lookup table, database, or other appropriate data management structure.

[0061] In various implementations, the relationship between the oscillation frequency at output 108 and the thickness of the memory layer, along with appropriate trimming values, can be determined at least in part from experimental data. Then, in some implementations, these relationships can be stored on the die, or in others on a test apparatus, and accessed in response to determining the oscillation frequency. These relationships can then be used during production, for example, at a manufacturing plant or test facility, to set the trimming value for RSD114.

[0062] In other embodiments, circuitry 100 can be replicated in a die subset on a semiconductor wafer. In such embodiments, the oscillation frequency of the RSD at a die, for example, at the 12 o'clock position on the wafer, can be compared with the oscillation frequencies determined for other dies on the wafer, for example, at the 6 o'clock, 3 o'clock, 9 o'clock, etc. positions. If the oscillation frequencies are substantially similar, this may indicate uniform memory layer thickness across the wafer. Conversely, if the oscillation frequencies are different, this may indicate non-uniform memory layer thickness across the wafer. In some cases, non-uniformity can be compensated for by setting a trim value on dies with memory layer thicknesses determined to be outside the target value or range, to achieve the target RSD performance. However, in other cases, the difference may exceed an acceptable correction range, and such dies can be identified as defective. Large differences in memory layer thickness can be used to indicate problems in the manufacturing process (e.g., non-uniform material deposition), and thus can be used for diagnosis and when process correction is needed.

[0063] Figure 2 An embodiment of an RC circuit 200 for determining the capacitance of one or more resistive switching devices within the die of a semiconductor device is shown in another implementation. The RC circuit 200 may include inputs with inverting and non-inverting inputs (e.g., as described above). Figure 1Operational amplifier 104 (described) and output 106. Output 106 can be input to an optional frequency divider circuit 107, but frequency divider circuit 107 is not required in all embodiments. Resistor 110 is coupled between output 106 of operational amplifier 104 and common node 224 connected to the inverting input of operational amplifier 104. In addition, capacitor can be connected to second common node 222 and ground, as shown. In embodiments, second common node 222 and common node 224 can be the same electrical node. One or more RSDs can be selectively connected to second common node 222, common node 224, or both by switching circuit 230. Switching circuit 230 can be embodied by a switch, multiplexer, or other suitable mechanism for selectively connecting a first plurality of RSDs 114 to a node (e.g., common node 224, second common node 222, ...), selectively disconnecting a first plurality of RSDs 114 from a node, and selectively connecting or disconnecting a second plurality of RSDs (not depicted) from a node.

[0064] As is known to those skilled in the art, although Figure 2 A single capacitor C coupled to the third common node 220 is shown. RSD However, capacitor C RSD It can be the sum of multiple (first) RSD 114 connected in parallel. It should be understood that the capacitor C... RSD The value can vary as different plurality of RSDs (not depicted) are connected to the third common node 220, including different RSDs, different numbers of RSDs, etc. Furthermore, in some embodiments, the connections to the third common node 220 can be fixed within the memory array at manufacturing time (e.g., the first plurality of RSDs can all be coupled to common bit lines, word lines, source lines, etc. at manufacturing time). However, in alternative embodiments, the (first) plurality of RSDs 114 connected to the third common node 220 can instead be selectively provided by a multiplexer or other switching circuitry configured to selectively connect subsets of the RSDs of the memory array to the third common node 220. Other embodiments not specifically shown or described herein but known to those skilled in the art or reasonably conveyed by the context provided herein are considered to be within the scope of this disclosure.

[0065] An output is generated at output node 108 in response to a voltage Vref applied to the non-inverting input of operational amplifier 104 in RC circuit 104. The output oscillates with an amplitude 210 and has a period 212 that defines the oscillation frequency. The amplitude 210 can be controlled by the voltage value of Vref. Because the output (e.g., output 106) is provided by resistor 110 at node 224, Vref is selected to keep the amplitude 210 at a voltage smaller than (or smaller than the minimum programming voltage in the programming voltage range) the programming voltage associated with the plurality of RSDs 114. This prevents bit interference of the memory devices associated with the plurality of RSDs 114 (e.g., see below). Figure 3 and 4 In some implementations, Vref can be selected as the capacitance of a two-terminal non-volatile memory component measuring RSD, which includes a two-terminal volatile selector device electrically connected in series with the two-terminal non-volatile memory component (see, for example, below). Figure 5 In such implementations, Vref can be selected to have a sufficiently large amplitude to activate the selector device components of (multiple) RSD 114, but small enough to prevent programming or erasing of the two-terminal non-volatile memory components of (multiple) RSD 114.

[0066] like Figure 2 As shown, the output frequency generated at output node 108 is equal to 1 / period 212 and is related to (C RSD +C1) is directly proportional. Therefore, C RSD It is proportional to the output frequency - C1. Therefore, C can be determined by measuring the frequency and subtracting the (known) capacitance value of C1. RSD In the case where a single RSD114 is coupled to a third common node 220, C RSD This is the capacitance value of a single RSD114. When multiple RSD114s are coupled to a third common node 220, C... RSD This represents the total capacitance of multiple RSDs 114. The average capacitance of each RSD can be determined by dividing by the number of RSDs in the multiple RSDs 114.

[0067] Figure 3A schematic diagram of an example circuit 300, in another disclosed embodiment, is shown. The parallel capacitor includes a fixed capacitor 116 having a known capacitance C1, electrically connected in parallel with one or more two-terminal non-volatile RSDs 302. The one or more two-terminal non-volatile RSDs 302 may include a single RSD having a first terminal connected to node 220 and a second terminal connected to ground. Alternatively, the two-terminal non-volatile RSDs 302 may include a plurality of two-terminal non-volatile resistive switching memory devices having respective first terminals connected in parallel at a common node 220 and second terminals connected to ground. A switching device 230 may electrically couple the first terminal to node 222 in parallel with capacitor C1116.

[0068] The current-voltage response 320 of the two-terminal non-volatile RSD 302 is also shown (but not necessarily scaled). To measure the capacitance of the two-terminal non-volatile RSD 302, the device should be in an erase (high resistance) state. To prevent the RSD 302 from being programmed to a low resistance state, the voltage across the RSD 302 should be kept at a level smaller than the programming voltage amplitude (or smaller than the minimum programming voltage amplitude (e.g., <1.2 V) of the possible programming voltage amplitude range associated with the RSD 302, which is likely 1.2 to 1.7 V). P An example programmed voltage amplitude is shown that is associated with changing RSD 302 from a high-resistance state (mimicking a capacitor) to a low-resistance state (mimicking a resistor). For example, by maintaining the voltage across RSD 302 at V... P The (average) capacitance of RSD 302 can be determined as described herein.

[0069] Figure 4 A schematic diagram of an example circuit 400 including parallel capacitors is shown in other disclosed embodiments. The parallel capacitors include a fixed capacitor 116 having a known capacitance C1, which is electrically connected in parallel with one or more two-terminal volatile RSDs 402. In embodiments, one or more two-terminal volatile RSDs 402 may be two-terminal volatile selector devices. In some embodiments, RSD 402 may be a single RSD having a first terminal connected to node 220 and a second terminal connected to ground. Alternatively, RSD 402 may include multiple two-terminal volatile RSDs having respective first terminals connected in parallel at a common node 220 and second terminals connected to ground. Switching device 230 may electrically couple the first terminal to node 222 in parallel with capacitor C1116.

[0070] The current-voltage response 420 of the two-terminal volatile RSD 402 is shown. The depicted current-voltage response 420 corresponds to (but is not necessarily to scale) the one developed by the assignee of this patent application. Selector device. To measure the capacitance of the two-terminal volatile RSD 402, the device should be in an inactive (high resistance) state, corresponding to the positive switching voltage shown in the figure: V S Negative switching voltage: -V S The voltage values ​​between [variable values]. Start at 0 volts and increase the applied voltage to less than V. S (or -V) S The voltage across RSD 302 should be maintained at a level smaller than the switching voltage amplitude (e.g., <~1.0 volts) or smaller than the minimum switching voltage amplitude (e.g., <0.8 volts) of the possible switching voltage amplitude range (e.g., 0.8 to 1.2 volts) associated with the volatile RSD 402. This is achieved by maintaining the voltage across the volatile RSD 402 at -V... S To V S Between these parameters, the (average) capacitance of RSD 402 can be determined as described in this article.

[0071] Figure 5 A diagram of an example circuit 500 including parallel capacitors is shown in other disclosed embodiments. The parallel capacitors include a fixed capacitor 116 having a known capacitance C1, electrically connected in parallel with one or more memory cells 502, 504. The first memory cell 502 may include a two-terminal memory cell 502 including a two-terminal volatile switching device electrically connected in series with a two-terminal non-volatile memory device. A current-voltage response (but not necessarily proportional) of the two-terminal memory cell 502 is provided at 520. In another embodiment, the second memory cell 502 may include a three-terminal memory cell 504, which may include a two-terminal volatile switching device connected at one terminal to the gate of a CMOS transistor. In either embodiment, memory cells 502, 504 may be a single two-terminal memory cell 502 having a first terminal connected to node 220 and a second terminal connected to ground, or a single three-terminal memory cell 504 having a two-terminal selector device having a first selector terminal connected to node 220 and a second selector terminal connected to the gate of a CMOS transistor. Alternatively, RSD 502 may include a plurality of memory cells 502, 504, each memory cell having a corresponding first terminal connected in parallel at a common node 220 and a second terminal connected to ground or to the corresponding gate of a corresponding CMOS transistor.

[0072] For memory cell 502, in some embodiments, the capacitance of the combination of volatile selector and non-volatile memory device of memory cell 502 can be measured, or the capacitance of a two-terminal non-volatile memory device excluding the two-terminal volatile selector device can be measured. In the first case, Vref remains below the switching voltage amplitude V. S or -V S This keeps the selector device in a high-resistance state. In this way, the capacitance of the series combination of the volatile selector device and the non-volatile memory device can be measured as described herein. In other embodiments, Vref can be increased to V... S Above and maintained at the programming voltage V of the two-terminal non-volatile memory device P The capacitance of a memory device excluding the selector device is measured below. For memory cell 504, the capacitance of the volatile selector device of memory cell 504 can be maintained by keeping Vref at the switching voltage amplitude V S or -V S The following simple measurement will keep the selector device in a high resistance state.

[0073] Figure 6 Embodiment 600 is illustrated, in which a plurality of resistive switching devices 610 are electrically coupled in parallel to measure the combined capacitance of the plurality of resistive switching devices 610. As shown, each two-terminal RSD 602 ​​is connected in parallel with each other and connected to capacitor C1116. In various embodiments, the number of resistive switching devices 610 can be: about 10, about 100, about 1000, about 10000, about 20000, about 60000 or more; it can be in the range of about 10 to about 100, about 100 to about 1000, about 1000 to about 10000, about 10000 to about 20000, about 20000 to about 60000 or greater; or it can be any suitable number between those explicitly identified, or it can be a range of any suitable values ​​between those explicitly identified.

[0074] Figure 7 An alternative implementation 700 for characterizing the capacitance of an array of memory devices is shown. A set of Vref voltages can be applied to multiple memory devices, generating a range of capacitance measurements according to the RC measurement circuit described herein. Figure 7 The figure shows capacitance 704 and frequency 702 used for such measurements. The best-fit frequency versus capacitance relationship 706 can be plotted to characterize the array of memory devices.

[0075] The schematic diagrams included herein are depictions of interactions between various memory devices, memory device components, memory arrays, or electronic circuits. It should be understood that such schematic diagrams may include those memory devices, components, arrays, and circuits specified therein, some of the specified memory devices / components / arrays / circuits, or suitable alternatives or additional memory devices / components / arrays / circuits. Where appropriate, sub-components of circuits or memory devices may also be implemented as electrically connected to other sub-components rather than being included in a parent circuit. Similarly, according to other embodiments, individual components may be implemented in a combined architecture. Furthermore, where appropriate, some disclosed embodiments may be implemented as part of other disclosed embodiments.

[0076] Furthermore, one or more disclosed processes can be combined into a single process that provides aggregate functionality. For example, a programming or erasing process may include a read / verify process, or vice versa, to facilitate programming / erasing memory cells and verifying the completion of programming / erasing through a single process. Additionally, it should be understood that rows of multiple memory device architectures can be erased in groups (e.g., multiple rows erased simultaneously) or individually. Furthermore, it should be understood that multiple memory cells can be read or programmed in groups (e.g., multiple memory cells read / programmed simultaneously) or individually read or programmed on a particular row. Components of the disclosed architecture can also interact with one or more other components not specifically described herein but known to those skilled in the art or reasonably apparent to those skilled in the art from the context provided herein.

[0077] refer to Figure 8 An example flowchart of a method 800 for characterizing a memory array of a semiconductor die, according to an additional disclosed embodiment, is depicted. At 802, method 800 may include closing a first switch and coupling a first plurality of two-terminal memory devices to the inverting input of a first operational amplifier, wherein each of the first plurality of two-terminal memory devices is characterized by a programming voltage within a first programming voltage range. In an embodiment, a first capacitor may be coupled between the inverting input of the first operational amplifier and ground, and a first resistor may be coupled between the inverting input of the first operational amplifier and the output of the first operational amplifier. In response to closing the first switch, the first capacitor and the first resistor may be electrically connected in parallel with the first plurality of two-terminal memory devices.

[0078] At 804, method 800 may include providing a first input voltage to the non-inverting input of a first operational amplifier using a first voltage source, wherein the first input voltage is less than a minimum programming voltage in a first voltage range. At 806, method 800 may include outputting a first signal using the first operational amplifier, wherein the first signal is characterized by a first oscillation frequency, wherein the first oscillation frequency is responsive to a first capacitor associated with a first plurality of two-terminal memory devices.

[0079] At 808, method 800 may include measuring a frequency value of a first oscillation frequency. At 810, method 800 may include storing an indicator associated with the measurement of the first oscillation frequency in a memory.

[0080] In one embodiment, a first plurality of two-terminal memory devices, a first switch, a first operational amplifier, a first capacitor, a first resistor, and a first voltage source are formed within a first die of a plurality of dies formed on a semiconductor device. In another embodiment, a second die of the plurality of dies includes a second plurality of two-terminal memory devices, a second switch, a second operational amplifier, a second capacitor, a second resistor, and a second voltage source. In such embodiments, method 800 may further include closing a second switch and coupling the second plurality of two-terminal memory devices to an inverting input of a second operational amplifier, wherein each of the second plurality of two-terminal memory devices is characterized by a second programming voltage within a second programming voltage range. Furthermore, in various embodiments, a second capacitor may be coupled between the inverting input of the second operational amplifier and ground, and a second resistor may be coupled between the inverting input of the second operational amplifier and the output of the second operational amplifier. In another embodiment, method 800 may include providing a second input voltage to a non-inverting input of the second operational amplifier using a second voltage source, wherein the second input voltage is less than a minimum programming voltage within the second programming voltage range. Furthermore, method 800 may include outputting a second signal using a second operational amplifier, wherein the second signal is characterized by a second oscillation frequency, wherein the second oscillation frequency is responsive to a second capacitor associated with a second plurality of two-terminal memory devices. Further, method 800 may include measuring a second frequency value of the second oscillation frequency and storing a second indicator associated with the second oscillation frequency in a second memory. In another embodiment, method 800 may include determining a semiconductor wafer passage condition when the difference between a first oscillation frequency value and a second oscillation frequency value is within a predetermined frequency range.

[0081] In alternative or additional embodiments, method 800 may include providing a second input voltage to the non-inverting input of a first operational amplifier using a first voltage source, wherein the second input voltage is less than the minimum programming voltage in a first programming voltage range. Furthermore, method 800 may include outputting a second signal using the first operational amplifier, wherein the second signal is characterized by a second oscillation frequency, wherein the second oscillation frequency is responsive to a first capacitor associated with a first plurality of two-terminal memory devices. In various embodiments, method 800 may also include measuring a second frequency value of the second oscillation frequency and storing a second indicator associated with the second oscillation frequency in memory.

[0082] In an implementation, method 800 may further include determining a pass condition for the first plurality of two-terminal memory devices when the difference between the first oscillation frequency and the second oscillation frequency is within a predetermined frequency range. For example, the difference between the first input voltage and the second input voltage may be less than 0.5 volts.

[0083] According to other embodiments, method 800 may include modifying a trim value in response to an indicator associated with a first oscillation frequency and storing the trim value in memory. In at least one such embodiment, the trim value may be associated with a parameter associated with a first plurality of two-terminal memory devices, wherein the parameter is selected from the group consisting of read parameters, write parameters, and erase parameters. In at least one embodiment, the number of two-terminal memory devices in the first plurality of two-terminal memory devices is in the range of 20,000 to 60,000. In other embodiments, outputting a first signal using a first operational amplifier may additionally include outputting a second signal using the first operational amplifier, wherein the second signal is characterized by a second oscillation frequency, and the second oscillation frequency is divided by a frequency divider to determine the first oscillation frequency.

[0084] refer to Figure 9 The document describes a method 900 for characterizing a resistive switching device for a memory array in various embodiments. At 902, method 900 may include selectively connecting one or more two-terminal resistive switching devices of the memory array to an RC oscillator circuit formed on the same die as the memory array. At 904, method 900 may include providing a first voltage to the input of the RC oscillator circuit that is smaller than a minimum switching voltage associated with the two-terminal resistive switching device. Furthermore, at 906, method 900 may include measuring a first oscillation frequency output from the RC oscillator circuit, and at 908, method 900 may include determining the average capacitance of one or more two-terminal resistive switching devices based on the oscillation frequency output. At 910, method 900 may include determining a trimmed value for trimmed parameters of the memory array, at least in part, based on the average capacitance.

[0085] Figure 10 A method 1000 for measuring characteristics of a memory device according to an alternative or additional embodiment of the present disclosure is described. At 1002, method 1000 may include selectively connecting a first plurality of two-terminal resistive switching devices of a memory array to an RC oscillator circuit formed together with the memory array in a first die of a semiconductor wafer. At 1004, method 1000 may include providing a first voltage to the input of the RC oscillator circuit that is smaller than a minimum switching voltage associated with the first set of devices. In addition to the above, at 1006, method 1000 may include measuring a first oscillation frequency output from the RC oscillator circuit.

[0086] At 1008, method 1000 may include selectively connecting a second plurality of two-terminal resistive switching devices of the memory array to a second RC oscillator circuit formed in the first die. Furthermore, at 1010, method 1000 may include providing a second voltage to the input of the second RC oscillator circuit that is smaller than the minimum switching voltage of the second plurality of devices. At 1012, method 1000 may include measuring a second oscillation frequency output from the second RC oscillator circuit, and at 1014, method 1000 may include determining the difference between the first oscillation frequency and the second oscillation frequency. Further, at 1016, method 1000 may include determining whether a pass condition is met. In an embodiment, the pass condition may be that the difference between the first oscillation frequency and the second oscillation frequency is less than a target value (or a range of values). The target value may be set based on the characteristics of the first plurality of devices and the second plurality of devices, the characteristics of the first die and the second die, the characteristics of the semiconductor wafer, etc., or a suitable combination thereof. In response to the pass condition being met, method 1000 may proceed to 1018 and allow the wafer to pass. In response to the failure of the pass condition, method 1000 proceeds to 1020 and the chip is rejected.

[0087] Figure 11 A flowchart of an example method 1100 according to an alternative or additional embodiment of the present disclosure is shown. At 1102, method 1100 may include selectively connecting a first plurality of two-terminal resistive switching devices of a memory array to an RC oscillator circuit formed together with the memory array in a single die of a semiconductor device. At 1104, method 1100 may include providing a first voltage to the input of the RC oscillator circuit that is less than a minimum switching voltage associated with the first set of devices. At 1106, method 1100 may include measuring a first oscillation frequency output from the RC oscillator circuit, and at 1108, method 1100 may include providing a second voltage to the input of the RC oscillator circuit that is less than the minimum switching voltage.

[0088] At 1110, method 1100 may include measuring a second oscillation frequency output from the RC oscillator circuit. Furthermore, at 1114, method 1100 may include determining the difference between a first oscillation frequency and a second oscillation frequency. At 1116, method 1100 may include determining whether a die pass condition has been met. In an embodiment, the pass condition may be whether the difference between the first oscillation frequency and the second oscillation frequency is less than a target value. In response to the pass condition being met, method 1100 may proceed to 1118 and the die may pass. In response to the pass condition failing, method 1100 may proceed to 1120 and the die may be rejected.

[0089] Example operating environment

[0090] In order to provide background on various aspects of the open topic, Figure 12 The following discussion is intended to provide a brief, general description of a suitable environment in which the various aspects of the disclosed subject matter can be implemented or processed. While the subject matter has been described above in the general context of semiconductor architectures and process methods for manufacturing, operating, or characterizing arrays of two-terminal memory devices, those skilled in the art will recognize that this disclosure can also be implemented in combination with other architectures or process methods. Furthermore, those skilled in the art will understand that the disclosed processes can be practiced using a processing system or computer processor, either alone or in conjunction with a host, which can include: single-processor or multi-processor computer systems, microcomputing devices, mainframe computers and personal computers, handheld computing devices (e.g., PDAs, telephones, watches), microprocessor-based or programmable consumer or industrial electronics, etc. The aspects shown can also be practiced in a distributed computing environment, where tasks are performed by remote processing devices linked via a communication network. However, some (if not all) aspects of the claimed innovation can be practiced on standalone electronic devices, such as memory cards, flash memory modules, removable storage devices (e.g., CF cards, USB memory sticks, SD cards, microSD cards), etc. In a distributed computing environment, programming modules can reside in both local and remote memory storage modules or devices.

[0091] Figure 12A block diagram of an example operating and control environment 1200 for a memory array 1202 of a multi-memory cell array according to aspects of this disclosure is shown. In at least one aspect of this disclosure, the memory array 1202 may include a memory selected from a variety of memory cell technologies. In at least one embodiment, the memory array 1202 may include a two-terminal memory technology arranged in a compact two-dimensional or three-dimensional architecture. Suitable two-terminal memory technologies may include resistive switching memory, conductive bridged memory, phase-change memory, organic memory, magnetoresistive memory, etc., or suitable combinations thereof. In yet another embodiment, as described herein, the memory array 1202 may be configured to characterize the thickness of the memory layers in which the memory array 1202 is formed.

[0092] Column controller 1206 and sense amplifier 1208 may be formed adjacent to memory array 1202. Furthermore, column controller 1206 may be configured to activate (or identify to activate) a subset of bit lines of memory array 1202. Column controller 1206 may utilize control signals provided by reference and control signal generator 1218 to activate and operate on corresponding subsets of bit lines, applying appropriate programming, erasing, or read voltages to those bit lines. Inactive bit lines may be maintained at a suppression voltage (also applied by reference and control signal generator 1218) to mitigate or avoid bit interference effects on these inactive bit lines.

[0093] Furthermore, the operating and control environment 1200 may include a row controller 1204. The row controller 1204 may be formed adjacent to and electrically connected to the word lines (and in some embodiments, source lines) of the memory array 1202. Furthermore, using control signals from the reference and control signal generator 1218, the row controller 1204 can select specific rows with appropriate selection voltages for memory cells. Additionally, the row controller 1204 can facilitate programming, erasing, or reading operations by applying appropriate voltages at the selected word lines (and source lines). Similar to the column controller 1206, the row controller 1204 may apply suppression voltages to inactive word lines (source lines) to mitigate or avoid bit interference effects on inactive word lines (source lines).

[0094] The sensing amplifier 1208 can read data from or write data to an active memory cell of the memory array 1202 selected by column control 1206 and row control 1204. Data read from the memory array 1202 can be provided to the input and input / output buffer 1212. Similarly, data to be written to the memory array 1202 can be received from the input and input / output buffer 1212 and written to the active memory cell of the memory array 1202.

[0095] Clock source 1210 can provide corresponding clock pulses to facilitate the timing of read, write, and programming operations of row controller 1204 and column controller 1206. Clock source 1210 can also facilitate word line or bit line selection in response to external or internal commands received by operating and control environment 1200. Input and input / output buffer 1212 can include command and address inputs, as well as bidirectional data inputs and outputs. Instructions are provided via command and address inputs, and data to be written to memory array 1202 and data to be read from memory array 1202 are transferred on bidirectional data inputs and outputs, thereby facilitating communication to external host devices such as computers or other processing devices (not depicted, but see, for example, below). Figure 13 The connection to computer 1302).

[0096] The input and input / output buffer 1212 can be configured to receive write data, receive erase commands, receive status or maintenance commands, output read data, output status information, and receive address data, command data, and address data for corresponding commands. Address data can be transmitted to the row controller 1204 and column controller 1206 via the address register 1214. Furthermore, input data is transmitted to the memory array 1202 via the signal input lines between the sense amplifier 1208 and the input and input / output buffer 1212, and output data is received from the memory array 1202 via the signal output lines from the sense amplifier 1208 to the input and input / output buffer 1212. Input data can be received from the host device, and output data can be transmitted to the host device via the I / O bus.

[0097] In one embodiment, an RC circuit 100 is provided for determining the capacitance of a subset of the memory array 1202. The RC circuit 100 is formed on a die having an operating and control environment 1200. In various embodiments, the RC circuit 100 may be fabricated within or in an input / output buffer 1212, an address register 1214, a column control 1206, a row control 1204, a sense amplifier 1208, or a reference and control signal generator 1218, or other suitable components or suitable combinations thereof. In another embodiment, as shown, the RC circuit 100 may be fabricated separately from the aforementioned components, having independent connections to the memory array 1202 and the input / output buffer 1212 for receiving and responding to commands.

[0098] Commands received from the host device can be provided to command interface 1216. Command interface 1216 can be configured to receive external control signals from the host device and determine whether the data input to input and input / output buffer 1212 is write data, a command, or an address. Input commands can be transmitted to state machine 1220.

[0099] State machine 1220 can be configured to manage the programming and reprogramming of memory array 1202 (and other memory banks of the multi-bank memory array). Instructions provided to state machine 1220 are implemented according to control logic configuration, enabling state machine 1220 to manage read, write, erase, data input, data output, and other functions associated with memory array 1202. In some aspects, state machine 1220 can send and receive acknowledgments and negative acknowledgments regarding the successful reception or execution of various commands. In other embodiments, state machine 1220 can decode and execute state-related commands, decode and execute configuration commands, etc.

[0100] To implement functions such as read, write, erase, input, and output, state machine 1220 can control clock source 1210 or reference and control signal generator 1218. Control of clock source 1210 can cause output pulses to be configured to prompt row controller 1204 and column controller 1206 to perform specific functions. Output pulses can be sent to selected bit lines, such as those adjacent to column controller 1206, or word lines, such as those adjacent to row controller 1204.

[0101] refer to Figure 13 The appropriate environment 1300 for implementing the various aspects of the claimed subject matter includes a computer 1302. The computer 1302 includes a processing unit 1304, system memory 1310, a codec 1314, and a system bus 1308. The system bus 1308 couples system components to the processing unit 1304, including but not limited to the system memory 1310. The processing unit 1304 can be any of a variety of available processors. Dual microprocessors and other multiprocessor architectures can also be used as the processing unit 1304.

[0102] The system bus 1308 can be any of several types of bus architectures, including memory bus or memory controller, peripheral bus or external bus and / or local bus using any of the various available bus architectures, including but not limited to: Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), PCMCIA Bus, Firewire (IEEE 1394), and Small Computer System Interface (SCSI).

[0103] System memory 1310 includes volatile memory 1310A and non-volatile memory 1310B. The Basic Input / Output System (BIOS), including basic routines for transferring information between components within computer 1302, such as during startup, is stored in non-volatile memory 1310B. Furthermore, according to this invention, codec 1314 may include at least one of an encoder or a decoder, wherein the encoder or decoder may be composed of hardware, software, or a combination of hardware and software. Although codec 1314 is depicted as a separate component, codec 1314 may be included within non-volatile memory 1310B. By way of illustration and not limitation, non-volatile memory 1310B may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, two-terminal memory, etc. Volatile memory 1310A includes random access memory (RAM), which acts as an external cache memory. According to this aspect, volatile memory can store write operation retry logic ( Figure 13 (not shown in the image). As an illustration and not a limitation, RAM comes in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), and enhanced SDRAM (ESDRAM).

[0104] Computer 1302 may also include removable / non-removable, volatile / non-volatile computer storage media. For example, Figure 13Disk storage device 1306 is shown. Disk storage device 1306 includes, but is not limited to, devices such as disk drives, solid-state drives (SSDs), floppy disk drives, magnetic tape drives, Jaz drives, Zip drives, LS-100 drives, flash memory cards, or memory sticks. Furthermore, disk storage device 1306 may include storage media, either alone or in combination with other storage media, including, but not limited to, optical disc drives such as optical disc ROM devices (CD-ROM), CD recordable drives (CD-R drives), CD rewritable drives (CD-RW drives), or digital versatile ROM drives (DVD-ROM). To facilitate connection of disk storage device 1306 to system bus 1308, a removable or non-removable interface, such as storage interface 1312, is typically used. It is understood that storage device 1306 may store user-related information. Such information may be stored on or provided to a server or an application running on a user device. In one embodiment, the user may be notified (e.g., via output device 1332) of the type of information stored in disk storage device 1306 or transmitted to a server or application. Users may be given the opportunity to opt in or opt out of using the server or application to collect and / or share such information (e.g., through input from input device 1342).

[0105] It should be understood that Figure 13 Software that acts as an intermediary between the user and the basic computer resources described in the appropriate operating environment 1300 is described. This software includes an operating system 1306A. The operating system 1306A, which may be stored on disk storage 1306, is used to control and allocate the resources of the computer system 1302. Application 1306C utilizes the management of resources through the operating system 1306A via a programming module 1306D and programming data 1306D stored in system memory 1310 or on disk storage 1306, such as start / stop transaction tables. It should be understood that the claimed subject matter can be implemented using various operating systems or combinations of operating systems.

[0106] Users input commands or information into computer 1302 via input device 1342. Input device 1342 includes, but is not limited to, pointing devices such as mouse, trackball, stylus, touchpad, keyboard, microphone, joystick, gamepad, satellite dish, scanner, TV tuner card, digital camera, digital camcorder, webcam, etc. These and other input devices are connected to processing unit 1304 via input port 1340 through system bus 1308. Input port 1340 includes, for example, serial port, parallel port, game port, and Universal Serial Bus (USB). Output device 1332 uses some of the same type of port as input device 1342. Thus, for example, a USB port can be used to provide input to computer 1302 and output information from computer 1302 to output device 1332. Output adapter 1330 is provided to account for the presence of other output devices 1332 that require special adapters, such as monitors, speakers, and printers. By way of illustration and not limitation, output adapter 1330 includes a graphics card and a sound card that provide a connection between output device 1332 and system bus 1308. It should be noted that other devices and / or device systems provide input and output capabilities, such as remote computer 1338.

[0107] Computer 1302 can operate in a networked environment using a logical connection to one or more remote computers, such as remote computer 1324. Remote computer 1324 can be a personal computer, server, router, network PC, workstation, microprocessor-based device, peer-to-peer device, smartphone, tablet, or other network node, and typically includes many components associated with computer 1302. For simplicity, only remote computer 1324 is shown as storage device 1326. Remote computer 1324 is logically connected to computer 1302 via network 1322 and then connected via communication interface 1320. Network 1322 includes wired or wireless communication networks, such as local area networks (LANs) and wide area networks (WANs), as well as cellular networks. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Wire Distributed Data Interface (CDDI), Ethernet, Token Ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks such as Integrated Services Digital Network (ISDN) and its variants, packet-switched networks, and Digital Subscriber Line (DSL).

[0108] Communication interface 1320 refers to the hardware / software used to connect network 1322 to bus 1308. Although for clarity, communication interface 1320 is shown inside computer 1302, it may also be outside computer 1302. For illustrative purposes only, the hardware / software required to connect to network 1322 includes internal and external technologies such as: modems, including conventional telephone-grade modems, cable modems, and DSL modems; ISDN adapters; wired and wireless Ethernet cards; hubs; and routers.

[0109] The aspects shown in this disclosure can also be practiced in a distributed computing environment, where certain tasks are performed by a remote processing device linked via a communication network. In a distributed computing environment, programming modules or stored information, instructions, etc., can reside in local or remote memory storage devices.

[0110] Furthermore, it should be understood that the various components described herein may include circuits, which may include components and circuit elements of suitable value for implementing embodiments of this disclosure. Additionally, it is understood that many different components may be implemented on one or more IC chips. For example, in one embodiment, a set of components may be implemented on a single IC chip. In other embodiments, one or more corresponding components are manufactured or implemented on separate IC chips.

[0111] Regarding the various functions performed by the aforementioned components, architectures, circuits, processes, etc., unless otherwise stated, the terminology used to describe such components (including references to "device") is intended to correspond to any component (e.g., a functional equivalent) that performs the specified function of the described component, even if it is not structurally equivalent to the disclosed structure that performs the function in the exemplary aspects of the embodiments shown herein. In this regard, it will also be appreciated that the embodiments include systems having computer-executable instructions for performing actions and / or events of various processes, as well as computer-readable media.

[0112] Furthermore, while a particular feature may be disclosed only for one of several embodiments, it may be combined with one or more other features of other implementations, which may be desirable and advantageous for any given or particular application. Moreover, with regard to the use of the terms "include," "including," and variations thereof in the detailed description or claims, these terms are intended to be encompassed in a manner similar to the term "comprising."

[0113] As used herein, the term “or” is intended to mean inclusive “or” rather than exclusive “or.” That is, unless otherwise stated or clear from the context, “X uses A or B” is intended to mean any naturally inclusive permutation. That is, if X uses A; X uses B; or X uses both A and B, then “X uses A or B” is satisfied in any of the foregoing cases. Furthermore, unless otherwise specified or clearly indicated from the context to the singular form, the articles “a” and “an” used herein and in the appended claims should generally be interpreted as meaning “one or more”.

[0114] Other implementations will be conceived by those skilled in the art upon reading this disclosure. For example, in various implementations, erase operations can be initiated simultaneously on multiple ReRAM devices (e.g., 16, 32, etc.).

[0115] In other embodiments, combinations or sub-combinations of the disclosed embodiments can be advantageously performed. For ease of understanding, the block diagrams and flowcharts of the architecture have been grouped. However, it should be understood that alternative embodiments of this disclosure consider combinations of blocks, additions of new blocks, rearrangements of blocks, etc.

[0116] It should also be understood that the examples and embodiments described herein are for illustrative purposes only, and various modifications or variations thereof will be suggested to those skilled in the art and are included within the spirit and scope of this application and the appended claims.

Claims

1. A semiconductor device, comprising: The first plurality of two-terminal memory devices, wherein each of the two-terminal memory devices is characterized by a programming voltage within a programming voltage range, wherein the first plurality of two-terminal memory devices are associated with a first capacitor, and wherein the first plurality of two-terminal memory devices are selectively coupled in parallel between ground and a first common node. A first capacitor is coupled between ground and a second common node, wherein the first capacitor is characterized by the second capacitor. A first voltage source is configured to provide a first input voltage, wherein the first input voltage is lower than the programming voltage range; A first operational amplifier includes an inverting input, a non-inverting input, and an output, wherein the non-inverting input is coupled to a first voltage source, the inverting input is coupled to a third common node, and the output is coupled to a fourth common node. The first operational amplifier is configured to output a first signal, wherein the first signal is characterized by a first oscillation frequency, wherein the first oscillation frequency is responsive to a first capacitor associated with the first plurality of two-terminal memory devices. A first resistive device is coupled between the third common node and the fourth common node; and wherein the first common node is coupled to the second common node and the third common node.

2. The apparatus according to claim 1, wherein, The capacitance value associated with the second capacitance of the first capacitor is larger than the capacitance value associated with the first capacitance of the first plurality of dual-terminal memory devices.

3. The apparatus according to claim 1 further includes an inverter having an input and an output, wherein, The input of the inverter is coupled to the fourth common node.

4. The apparatus of claim 1, further comprising at least one of the following: A first switcher is configured between the first common node and the third common node, wherein... The first switcher is configured to couple and decouple the first common node from the third common node; or A first multiplexer is used to selectively couple and decouple a corresponding first terminal of the plurality of dual-terminal memory devices from the first common node.

5. The apparatus according to claim 1, wherein, The first voltage source is also configured to provide a second input voltage to a non-inverting input, wherein the second input voltage is below the programming voltage range.

6. The apparatus according to claim 5, wherein, The number of dual-terminal memory devices in the first plurality of dual-terminal memory devices is in the range of 20,000 to 60,000.

7. The apparatus according to claim 1, wherein, The dual-terminal memory devices in the first plurality of dual-terminal memory devices are selected from the group consisting of: filamentary memory devices; Non-volatile filamentary resistor switching device; Volatile filamentary resistor switching device; A non-volatile memory comprising a transistor, an optional capacitor, and a two-terminal resistive selector, the two-terminal resistive selector being coupled to the gate of the transistor at a first selector terminal and to the optional capacitor at a second selector terminal. Magnetoresistive memory devices; Phase-change memory devices; Carbon nanotube memory devices; Conductive bridged memory device; Silicon suboxide memory devices and metal oxide memory devices.

8. The apparatus according to claim 1, further comprising: The second plurality of dual-terminal memory devices, wherein each of the second plurality of dual-terminal memory devices is characterized by a second programming voltage within a second programming voltage range, wherein the second plurality of dual-terminal memory devices are associated with a third capacitor, and wherein the second plurality of dual-terminal memory devices are selectively coupled in parallel between ground and a fifth common node. The second capacitor is coupled between ground and the sixth common node; A second voltage source is configured to provide a second input voltage, wherein the second input voltage is smaller than the range of the second programming voltage; The second operational amplifier includes a second inverting input, a second non-inverting input, and a second output, wherein the second non-inverting input of the second operational amplifier is coupled to the second voltage source, the second inverting input of the second operational amplifier is coupled to a seventh common node, and the output of the second operational amplifier is coupled to an eighth common node. A second resistor is coupled between the seventh common node and the eighth common node; and wherein the fifth common node is coupled to the sixth common node and the seventh common node; wherein the first plurality of dual-terminal memory devices are disposed on a first portion of a semiconductor wafer; The second plurality of dual-terminal memory devices are disposed on a second portion of the semiconductor wafer; and the first portion is not adjacent to the second portion.

9. The apparatus according to claim 1, wherein, The first operational amplifier is configured to oscillate at a first frequency in response to the first capacitor, the second capacitor, and the first resistor.

10. The apparatus of claim 9, further comprising a memory configured to store an indicator of the first frequency.

11. A method comprising: Close the first switch and couple the first plurality of two-terminal memory devices to the inverting input of the first operational amplifier, wherein each of the first plurality of two-terminal memory devices is characterized by a programming voltage within a first programming voltage range, wherein a first capacitor is coupled between the inverting input of the first operational amplifier and ground, and wherein a first resistor is coupled between the inverting input of the first operational amplifier and the output of the first operational amplifier. A first input voltage is provided to the non-inverting input of the first operational amplifier using a first voltage source, wherein the first input voltage is smaller than the minimum programming voltage in the first programming voltage range; The first signal is output using the first operational amplifier, wherein the first signal is characterized by a first oscillation frequency, wherein the first oscillation frequency is responsive to a first capacitor associated with the first plurality of two-terminal memory devices; Measure the frequency value of the first oscillation frequency; and The indicator associated with the first oscillation frequency measurement is stored in memory.

12. The method according to claim 11, wherein, The first plurality of dual-terminal memory devices, the first switch, the first operational amplifier, the first capacitor, the first resistor device, and the first voltage source are formed within the first die of a plurality of dies formed on a semiconductor wafer.

13. The method according to claim 12, in, The second die among the plurality of dies includes a second plurality of two-terminal memory devices, a second switch, a second operational amplifier, a second capacitor, a second resistor device, and a second voltage source; and The method further includes: Close the second switch and couple the second plurality of two-terminal memory devices to the inverting input of the second operational amplifier, wherein each of the second plurality of two-terminal memory devices is characterized by a second programming voltage within a second programming voltage range, wherein the second capacitor is coupled between the inverting input of the second operational amplifier and ground, and wherein the second resistor is coupled between the inverting input of the second operational amplifier and the output of the second operational amplifier; Using the second voltage source, a second input voltage is provided to the non-inverting input of the second operational amplifier, wherein the second input voltage is smaller than the minimum programming voltage in the second programming voltage range; The second signal is output using the second operational amplifier, wherein the second signal is characterized by a second oscillation frequency, wherein the second oscillation frequency is responsive to a second capacitor associated with the second plurality of two-terminal memory devices; Measure the second frequency value of the second oscillation frequency; and A second indicator associated with the second oscillation frequency is stored in a second memory.

14. The method of claim 13, further comprising: When the difference between the first oscillation frequency and the second oscillation frequency is within a predetermined frequency range, the pass condition of the semiconductor wafer is determined.

15. The method of claim 11, further comprising: Using the first voltage source, a second input voltage is provided to the non-inverting input of the first operational amplifier, wherein the second input voltage is smaller than the minimum programming voltage in the first programming voltage range; and The first operational amplifier outputs a second signal, wherein the second signal is characterized by a second oscillation frequency, wherein the second oscillation frequency is responsive to a first capacitor associated with the first plurality of two-terminal memory devices; Measure the second frequency value of the second oscillation frequency; and The second indicator associated with the second oscillation frequency is stored in memory.

16. The method of claim 15, further comprising: When the difference between the first oscillation frequency and the second oscillation frequency is within a predetermined frequency range, the pass condition of the first plurality of dual-terminal memory devices is determined.

17. The method according to claim 15, wherein, The difference between the first input voltage and the second input voltage is less than 0.5 volts.

18. The method of claim 11, further comprising: The trim value is modified in response to an indicator associated with the first oscillation frequency; And store the adjusted value in memory; The trim value is associated with parameters related to the first plurality of dual-terminal memory devices, wherein the parameters are selected from the group consisting of read parameters, write parameters, and erase parameters.

19. The method according to claim 11, wherein, The number of dual-terminal memory devices in the first plurality of dual-terminal memory devices is in the range of 20,000 to 60,000.

20. The method according to claim 11, wherein, Outputting the first signal using the first operational amplifier includes: The first operational amplifier outputs a second signal, wherein the second signal is characterized by a second oscillation frequency; and The second oscillation frequency is divided using a frequency divider to determine the first oscillation frequency.

Images