A chip wafer testing method

Abstract

The application provides a chip wafer testing method, comprising the following steps: a collection control system judges whether the parameter difference between sampling data and full testing data of the same core particle in a last to-be-tested chip wafer is greater than a set range, and generates a prompt signal; the prompt signal comprises a correction signal of the parameter difference greater than the set range and a testing signal of the parameter difference not greater than the set range; and a testing machine receives the prompt signal; wherein, the testing machine prompts an operator to manually correct the testing machine according to the correction signal; or the testing machine tests the current to-be-tested chip wafer according to the testing signal. When testing the to-be-tested chip wafer, the testing machine does not need to be manually corrected every time, but only needs to be manually corrected when the parameter difference is large, thereby improving the testing efficiency of the testing machine and the production efficiency; meanwhile, the operation of the operator is simplified, and the number of the operator operating the testing machine is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a chip wafer testing method. Background Technology

[0002] Testing machines are an indispensable piece of equipment in the back-end manufacturing process of LED (light-emitting diode) chips, used for testing photoelectric parameters. They effectively detect and eliminate defects in the product. Currently, based on different manufacturing processes, they are mainly divided into positive polarity chip testing machines and reverse polarity chip testing machines. Furthermore, based on process requirements, they are mainly divided into sampling testing (selecting samples from all chips on the LED chip wafer) and full testing (selecting all chips on the LED chip wafer). During full testing, the photoelectric characteristics of the machine are confirmed to be normal through monitoring and calibration before mass production can begin. If an operator simultaneously monitors multiple full testing machines, the machine needs to be calibrated before testing each LED chip wafer, reducing testing efficiency and overall production efficiency. Summary of the Invention

[0003] In view of this, the present invention provides a chip wafer testing method that effectively solves the existing technical problems, improves the testing efficiency of the testing machine, and improves production efficiency; at the same time, it simplifies the operation of the operator and increases the number of testing machines that the operator can control.

[0004] To achieve the above objectives, the technical solution provided by the present invention is as follows:

[0005] A chip wafer testing method, comprising:

[0006] S1. The test machine is interconnected with the integrated control system. The integrated control system stores the test data of the test machine on the chip wafer under test. The test data includes sampling test data of a preset chip in the chip wafer under test and full test data of all chips in the chip wafer under test.

[0007] S2. Transmit the batch number of the chip wafer currently under test to the collection control system;

[0008] S3. The collection control system determines whether the parameter difference between the sampled data and the full test data of the same chip in the previous test wafer is greater than a set range, and generates a prompt signal. The prompt signal includes a correction signal if the parameter difference is greater than the set range, and a test signal if the parameter difference is not greater than the set range.

[0009] S4. The testing machine receives the prompt signal, wherein the testing machine prompts the operator to manually calibrate the testing machine according to the calibration signal; or the testing machine tests the current chip wafer under test according to the test signal.

[0010] Optionally, after step S2 and before step S3, the method further includes:

[0011] The integrated control system determines whether the current chip wafer under test matches the test machine. If it does, it proceeds to the next step; otherwise, it generates a matching failure signal.

[0012] The testing machine receives the matching failure signal and issues an alarm.

[0013] Optionally, after step S2 and before step S3, the method further includes:

[0014] The collection control system determines whether it can query the corresponding test data of the previous chip wafer under test. If yes, it proceeds to the next step; otherwise, it generates a no data signal.

[0015] The testing machine receives the no-data signal and prompts the operator to manually calibrate the testing machine.

[0016] Optionally, after step S2 and before step S3, the method further includes:

[0017] The collection control system determines whether the time interval between the time when the test data of the previous chip wafer under test was stored and the current time is greater than the set time. If not, it proceeds to the next step; if so, it generates a long standby signal.

[0018] The test machine receives the long standby signal and prompts the operator to manually calibrate the test machine.

[0019] Optionally, the set time is not less than 8 hours.

[0020] Optionally, after step S2 and before step S3, the method further includes:

[0021] The collection control system determines whether the test data of the previous chip wafer under test has been processed. If yes, it proceeds to the next step; otherwise, it generates a data processing signal.

[0022] The testing machine receives the data processing signal and issues a waiting alarm.

[0023] Optionally, the parameters of the sampled data and the full measurement data include at least one of voltage, brightness, and wavelength.

[0024] Optionally, step S3 includes:

[0025] The integrated control system determines that the voltage difference between the sampled data and the full test data of the same chip in the previous test wafer is greater than the voltage setting range, and generates a voltage correction signal; wherein, the test machine prompts the operator for voltage abnormality based on the voltage correction signal, so that the test machine can be manually calibrated.

[0026] And / or, the collection control system determines that the difference in brightness between the sampled data and the full test data of the same chip in the previous test wafer is greater than the brightness set range, and generates a brightness correction signal; wherein, the test machine prompts the operator for abnormal brightness based on the brightness correction signal, so as to manually correct the test machine;

[0027] And / or, the collection control system determines that the wavelength difference between the sampled data and the full test data of the same chip in the previous test wafer is greater than the wavelength setting range, and generates a wavelength correction signal; wherein, the test machine prompts the operator for wavelength abnormality based on the wavelength correction signal so as to manually correct the test machine.

[0028] Optionally, the chip wafer includes an LED chip wafer;

[0029] The integrated control system includes a MES (manufacturing execution system).

[0030] Optionally, the testing machine performs tests on the current chip wafer under test based on the test signal, including:

[0031] The testing machine performs random sampling tests on preset chips of the current chip wafer under test according to the test signal;

[0032] After the sampling is completed, all chips of the current chip wafer to be tested are fully tested.

[0033] Compared with the prior art, the technical solution provided by the present invention has at least the following advantages:

[0034] This invention provides a method for testing chip wafers, comprising the following steps: the collection control system determines whether the parameter difference between the sampled test data and the full test data of the same die in the previous chip wafer under test is greater than a set range, and generates a prompt signal, the prompt signal including a correction signal if the parameter difference is greater than the set range, and a test signal if the parameter difference is not greater than the set range; the testing machine receives the prompt signal, wherein the testing machine prompts the operator to manually calibrate the testing machine according to the correction signal; or the testing machine tests the current chip wafer under test according to the test signal.

[0035] As can be seen from the above, the technical solution provided by the present invention eliminates the need for manual calibration of the testing machine every time the chip wafer under test is tested. Manual calibration is only required when there are significant parameter differences, thereby improving the testing efficiency of the testing machine and increasing production efficiency. At the same time, it simplifies the operation for operators and increases the number of testing machines that operators can control. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0037] Figure 1 This is a flowchart of a chip wafer testing method provided in an embodiment of the present invention.

[0038] Figure 2 A flowchart of another chip wafer testing method is provided for embodiments of the present invention; Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] As described in the background section, testing machines are currently mainly classified into two categories based on different manufacturing processes: positive polarity chip testing machines and reverse polarity chip testing machines. Furthermore, based on the needs of the manufacturing process, they are mainly divided into two categories: sampling testing (selecting samples from all chips on the LED chip wafer) and full testing (selecting all chips on the LED chip wafer). During full testing, the machine's photoelectric characteristics are confirmed to be normal through monitoring and calibration before mass production can begin. If one operator simultaneously monitors multiple full testing machines, the machine needs to be calibrated before testing each LED chip wafer, reducing testing efficiency and consequently, production efficiency.

[0041] Based on this, the present invention provides a chip wafer testing method that effectively solves existing technical problems, improves the testing efficiency of the testing machine, and increases production efficiency; at the same time, it simplifies the operation of operators and increases the number of testing machines that operators can control.

[0042] To achieve the above objectives, the technical solutions provided by the embodiments of the present invention are as follows, in detail... Figures 1 to 2 The technical solutions provided in the embodiments of the present invention will be described in detail.

[0043] refer to Figure 1 The diagram shows a flowchart of a chip wafer testing method provided in an embodiment of the present invention, wherein the chip wafer testing method includes:

[0044] S1. The test machine is interconnected with the integrated control system. The integrated control system stores the test data of the test machine on the chip wafer under test. The test data includes sampling test data of a preset chip in the chip wafer under test and full test data of all chips in the chip wafer under test.

[0045] S2. Transmit the batch number of the chip wafer currently under test to the collection control system.

[0046] S3. The collection control system determines whether the parameter difference between the sampled data and the full test data of the same chip in the previous test wafer is greater than a set range, and generates a prompt signal. The prompt signal includes a correction signal if the parameter difference is greater than the set range, and a test signal if the parameter difference is not greater than the set range.

[0047] S4. The testing machine receives the prompt signal, wherein the testing machine prompts the operator to manually calibrate the testing machine according to the calibration signal; or the testing machine tests the current chip wafer under test according to the test signal.

[0048] It is understood that the technical solution provided by the embodiments of the present invention eliminates the need for manual calibration of the testing machine every time the chip wafer under test is tested. Manual calibration is only required when there are significant parameter differences, thereby improving the testing efficiency of the testing machine and increasing production efficiency. At the same time, it simplifies the operation of the operators and increases the number of testing machines that can be operated by the operators.

[0049] In one embodiment of the present invention, the present invention provides an interconnection between a test machine and a centralized control system, wherein the centralized control system can be a MES system. The interconnection between the MES system and the test machine may include:

[0050] Create an interface and initially confirm the parameters required to send the results, including status type ResponseResult, enumeration type ResultStatus, type ResponseGainData, enumeration type OperationType, type ResponseProber, etc.; at the same time, maintain MES information, including product part number, model size, site, Prober name, test calibration program name, etc.

[0051] For interface debugging, after confirming the required parameters, debug the interface via the URL and confirm the interface information. Determine whether the MES results can be returned to the test machine and confirm whether the returned results are correct. If there are any discrepancies, make adjustments accordingly.

[0052] To achieve interconnection, after the interface is debugged normally, the required parameter information is implanted into the Tester software to confirm whether the MES system and the test machine can communicate normally. After the Tester software and the MES system are debugged, the interconnection between the MES system and the test machine is achieved.

[0053] In one embodiment of the present invention, the batch number of the chip wafer under test is transmitted to the collection control system by means of barcode scanning. For example, the barcode of the chip wafer under test is scanned by a barcode scanner to obtain the batch number of the chip wafer under test, and the batch number is then input to the collection control system. The present invention does not impose specific limitations on this method.

[0054] In one embodiment of the present invention, after the integrated control system obtains the batch number of the chip wafer under test, it can determine whether the chip wafer under test matches the testing machine, thereby effectively preventing mistake-proofing. See details. Figure 2 The diagram shows another chip wafer testing method provided by an embodiment of the present invention, wherein, after step S2 and before step S3, the method further includes:

[0055] S21. The collection control system determines whether the current chip wafer under test is matched with the test machine. If so, it proceeds to the next step; if not, it generates a matching failure signal. The test machine receives the matching failure signal and issues an alarm.

[0056] Understandably, after the integrated control system obtains the batch number of the chip wafer under test, it queries relevant new information based on the batch number: whether the target testing machine is the current testing machine, and the name of the current part number. If the testing machine does not match the chip wafer under test, a mismatch signal is generated and transmitted to the testing machine, which then issues an alarm reminding the operator that "the batch number is not in process of manufacture," thus preventing the operator from mistakenly taking chip wafers associated with other testing machines and effectively preventing mistaken identification.

[0057] In one embodiment of the present invention, since it is necessary to compare the sampling test data and full test data of the previous chip wafer under test to determine whether the tester is stable, the existence of the test data can be verified before querying the corresponding test data of the previous chip wafer under test, thereby effectively preventing errors. Specifically, after step S2 and before step S3, the method further includes:

[0058] The collection control system determines whether it can query the corresponding test data of the previous chip wafer under test. If yes, it proceeds to the next step; otherwise, it generates a no data signal.

[0059] The testing machine receives the no-data signal and prompts the operator to manually calibrate the testing machine.

[0060] Understandably, the collection control system provided in this embodiment of the invention, after obtaining the batch number, checks whether the corresponding data of the previous chip wafer under test exists. If not, it generates a no data signal and transmits it to the test machine. The test machine responds to the no data signal by issuing a corresponding alarm for "no data of the previous chip wafer under test", thereby reminding the operator to perform manual calibration.

[0061] Optionally, the absence of a data signal can correspond to the absence of sampled test data from the previous chip wafer under test, and / or it can correspond to the absence of full test data from the previous chip wafer under test. This serves to remind the operator that sampled test data and / or full test data from the previous chip wafer under test may have been missed, or that the batch number of the current chip wafer under test has been entered incorrectly, thus achieving the purpose of error prevention.

[0062] In one embodiment of the present invention, if the time between the testing of the current chip wafer and the testing of the previous chip wafer is relatively long, this may lead to inconsistencies in the stability of the testing machine. Therefore, after step S2 and before step S3, the following method is further included:

[0063] The collection control system determines whether the time interval between the time when the test data of the previous chip wafer under test was stored and the current time is greater than a set time. If not, it proceeds to the next step; if so, it generates a long standby signal.

[0064] The test machine receives the long standby signal and prompts the operator to manually calibrate the test machine.

[0065] Understandably, the testing method provided in this embodiment of the invention, after the control system obtains the batch number of the chip wafer under test, generates a long standby signal and transmits it to the testing machine when it is determined that the interval between the test of the previous chip wafer under test is relatively long. The testing machine issues an alarm "Testing machine is in long standby and manual calibration is required" based on the long standby signal, prompting the operator to manually calibrate the testing machine, thereby preventing stability differences caused by the long-term pause of the testing machine in standby mode and increasing the prevention and control measures.

[0066] Optionally, the set time provided in the embodiments of the present invention is not less than 8 hours, and the present invention does not impose specific limitations on this.

[0067] In one embodiment of the present invention, when the collection control system provided by the present invention determines the test data of the previous chip wafer under test, the test data may not have been fully processed and stored. Therefore, after step S2 and before step S3, the system further includes:

[0068] The collection control system determines whether the test data of the previous chip wafer under test has been processed. If yes, it proceeds to the next step; otherwise, it generates a data processing signal.

[0069] The testing machine receives the data processing signal and issues a waiting alarm.

[0070] Understandably, after the control system obtains the batch number of the chip wafer under test, if the test data of the previous chip wafer under test has not yet been processed and stored, a data processing signal is generated and transmitted to the test machine. The test machine then issues an alarm saying "Previous test data has not been processed, please wait" to remind the operator.

[0071] In one embodiment of the present invention, the parameters of the sampled data and the full measured data provided by the present invention include at least one of voltage, brightness, and wavelength. The present invention does not impose specific limitations on this. In other embodiments of the present invention, the parameters may include more types, which need to be specifically selected according to the actual application. Optionally, step S3 provided in the embodiments of the present invention includes:

[0072] The integrated control system determines that the voltage difference between the sampled data and the full test data of the same chip in the previous test wafer is greater than the voltage setting range, and generates a voltage correction signal; wherein, the test machine prompts the operator for voltage abnormality based on the voltage correction signal, so as to manually correct the test machine.

[0073] And / or, the collection control system determines that the difference in brightness between the sampled data and the full test data of the same chip in the previous test wafer is greater than the brightness setting range, and generates a brightness correction signal; wherein, the test machine prompts the operator for abnormal brightness based on the brightness correction signal, so as to manually correct the test machine.

[0074] And / or, the collection control system determines that the wavelength difference between the sampled data and the full test data of the same chip in the previous test wafer is greater than the wavelength setting range, and generates a wavelength correction signal; wherein, the test machine prompts the operator for wavelength abnormality based on the wavelength correction signal so as to manually correct the test machine.

[0075] Understandably, the testing method provided in this embodiment of the invention will trigger an alarm through the testing machine when the control system determines that the differences in voltage, brightness, and wavelength exceed the set range, respectively, to remind the operator that "voltage exceeds the set range, the testing machine needs to be manually calibrated", "brightness exceeds the set range, the testing machine needs to be manually calibrated", and "wavelength exceeds the set range, the testing machine needs to be manually calibrated", thereby reminding the operator to manually calibrate the testing machine.

[0076] Optionally, the manual calibration testing machine provided in this embodiment of the invention may include:

[0077] The first step is to prepare a calibration chip wafer with known parameters and begin the preparatory work before calibration.

[0078] The second step is to input the batch number of the calibration chip wafer into the tester and select the corresponding test program.

[0079] The third step is to confirm that the calibration chip wafer has been tested using the testing machine, start the calibration testing machine, and save the test data after the test is completed.

[0080] In one embodiment of the present invention, the chip wafer provided by the present invention includes an LED chip wafer.

[0081] Furthermore, the aggregate control system provided by the present invention includes a MES system.

[0082] In one embodiment of the present invention, the testing machine provided in this embodiment of the present invention tests the current chip wafer under test according to the test signal, including: the testing machine performs random sampling tests on a preset die of the current chip wafer under test according to the test signal; after the random sampling tests are completed, all dies of the current chip wafer under test are fully tested.

[0083] This invention provides a method for testing chip wafers, comprising the following steps: The collection control system determines whether the parameter difference between the sampled data and the full test data of the same die in the previous chip wafer under test is greater than a set range, and generates a prompt signal. The prompt signal includes a correction signal indicating that the parameter difference is greater than the set range, and a test signal indicating that the parameter difference is not greater than the set range. The testing machine receives the prompt signal, wherein the testing machine prompts the operator to manually calibrate the testing machine based on the correction signal; or the testing machine tests the current chip wafer under test based on the test signal.

[0084] As can be seen from the above, the technical solution provided by the embodiments of the present invention eliminates the need for manual calibration of the testing machine every time the chip wafer under test is tested. Manual calibration is only required when significant parameter differences occur, thereby improving the testing efficiency of the testing machine and increasing production efficiency. Simultaneously, it simplifies operator operations and increases the number of testing machines that can be operated by a single operator. Through experimental comparison, using the technical solution provided by the embodiments of the present invention, the ratio of testing machine to operator can be increased from 1:20-1:23 to 1:55-1:60, increasing the number of testing machines that can be operated by a single operator. Furthermore, since manual calibration of the testing machine is eliminated every time, approximately 66% of calibration wafers are saved, reducing chip costs.

[0085] In the description of this invention, it should be understood that terms such as "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0086] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0087] In this invention, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between components; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0088] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0089] In this invention, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0090] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A chip wafer testing method, characterized in that, include: S1. Interconnect the test machine with the integrated control system. The integrated control system stores the test data of the test machine. The test data includes sampling test data for sampling a preset chip in the chip wafer under test and full test data for full testing of all chips in the chip wafer under test. S2. Transmit the batch number of the chip wafer currently under test to the collection control system; S3. The collection control system determines whether the parameter difference between the sampled data and the full test data of the same chip in the previous test wafer is greater than a set range, and generates a prompt signal. The prompt signal includes a correction signal if the parameter difference is greater than the set range, and a test signal if the parameter difference is not greater than the set range. S4. The testing machine receives the prompt signal, wherein the testing machine prompts the operator to manually calibrate the testing machine according to the calibration signal; or the testing machine tests the current chip wafer under test according to the test signal.

2. The chip wafer testing method according to claim 1, characterized in that, After step S2 and before step S3, the following is also included: The integrated control system determines whether the current chip wafer under test matches the test machine. If it does, it proceeds to the next step; otherwise, it generates a matching failure signal. The testing machine receives the matching failure signal and issues an alarm.

3. The chip wafer testing method according to claim 1, characterized in that, After step S2 and before step S3, the following is also included: The collection control system determines whether it can query the corresponding test data of the previous chip wafer under test. If yes, it proceeds to the next step; otherwise, it generates a no data signal. The testing machine receives the no-data signal and prompts the operator to manually calibrate the testing machine.

4. The chip wafer testing method according to claim 1, characterized in that, After step S2 and before step S3, the following is also included: The collection control system determines whether the time interval between the time when the test data of the previous chip wafer under test was stored and the current time is greater than the set time. If not, it proceeds to the next step; if so, it generates a long standby signal. The test machine receives the long standby signal and prompts the operator to manually calibrate the test machine.

5. The chip wafer testing method according to claim 4, characterized in that, The set time is no less than 8 hours.

6. The chip wafer testing method according to claim 1, characterized in that, After step S2 and before step S3, the following is also included: The collection control system determines whether the test data of the previous chip wafer under test has been processed. If yes, it proceeds to the next step; otherwise, it generates a data processing signal. The testing machine receives the data processing signal and issues a waiting alarm.

7. The chip wafer testing method according to claim 1, characterized in that, The parameters of the sampled data and the full measured data include at least one of voltage, brightness, and wavelength.

8. The chip wafer testing method according to claim 7, characterized in that, Step S3 includes: The integrated control system determines that the voltage difference between the sampled data and the full test data of the same chip in the previous test wafer is greater than the voltage setting range, and generates a voltage correction signal; wherein, the test machine prompts the operator for voltage abnormality based on the voltage correction signal, so that the test machine can be manually calibrated. And / or, the collection control system determines that the difference in brightness between the sampled data and the full test data of the same chip in the previous test wafer is greater than the brightness set range, and generates a brightness correction signal; wherein, the test machine prompts the operator for abnormal brightness based on the brightness correction signal, so as to manually correct the test machine; And / or, the collection control system determines that the wavelength difference between the sampled data and the full test data of the same chip in the previous test wafer is greater than the wavelength setting range, and generates a wavelength correction signal; wherein, the test machine prompts the operator for wavelength abnormality based on the wavelength correction signal so as to manually correct the test machine.

9. The chip wafer testing method according to claim 1, characterized in that, The chip wafer includes LED chip wafers; The integrated control system includes a MES system.

10. The chip wafer testing method according to claim 1, characterized in that, The testing machine performs tests on the current chip wafer under test based on the test signal, including: The testing machine performs random sampling tests on preset chips of the current chip wafer under test according to the test signal; After the sampling is completed, all chips of the current chip wafer to be tested are fully tested.

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