Semiconductor devices including substrates bonded together and methods for manufacturing the same

Abstract

This application relates to a semiconductor device comprising substrates bonded to each other and a method of manufacturing the same. A semiconductor device and a method of manufacturing the same are provided. The semiconductor device may include a second semiconductor substrate directly bonded to a first semiconductor substrate. The first semiconductor substrate may include a first via, a liner, and a first diffusion barrier layer. An end of the first via protrudes through a first top surface, which is a top surface of the body of the first semiconductor substrate. The liner extends to partially expose a side surface of the end of the first via. The liner may include a third top surface positioned at a height lower than a second top surface, which is the top surface of the end of the first via, and positioned substantially equal to or higher than the first top surface. Alternatively, the liner may include a third top surface positioned at a height lower than the second top surface and higher than the first top surface.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor technology, and more specifically, to semiconductor devices comprising semiconductor substrates bonded together and stacked in three dimensions, and methods for manufacturing the same. Background Technology

[0002] Semiconductor devices are used in a wide variety of electronic applications. They are found in personal computers, mobile phones, cameras, and more. Semiconductor devices are manufactured through processes that deposit semiconductor material layers, conductive layers, dielectric layers, or insulating layers on a semiconductor substrate or wafer and pattern these layers to form circuit components and elements, as well as processes that separate the semiconductor substrate or wafer into individual wafers and package the individual wafers into packages. With the increasing integration density of various electronic components and the need for smaller semiconductor devices, three-dimensional semiconductor devices have recently been developed. 3D semiconductor devices are being developed in the form of packages such as PoP (PoP) or SiP (System-in-Package). Summary of the Invention

[0003] Embodiments of this disclosure may provide a semiconductor device including a first semiconductor substrate and a second semiconductor substrate directly bonded to the first semiconductor substrate. The first semiconductor substrate may include: a first semiconductor substrate body; a first via having an end protruding through a first top surface, the first top surface being the top surface of the first semiconductor substrate body; a liner formed at the interface between the first via and the first semiconductor substrate body and extending to partially expose a side surface of the end of the first via; and a first diffusion barrier layer covering the first top surface of the semiconductor substrate body and covering the side surface of the end of the first via. The liner may include a third top surface positioned lower than a second top surface, the second top surface being the top surface of the end of the first via, and the third top surface being substantially equal to or higher than the first top surface.

[0004] Another embodiment of this disclosure provides a method of manufacturing a semiconductor device, the method comprising: forming a first through-hole surrounded by a liner in a first semiconductor substrate body; first recessing the first semiconductor substrate body to allow an end of the first through-hole to protrude from a first recessed top surface of the first semiconductor substrate body while being covered by the liner; removing a portion of the liner surrounding the end of the first through-hole to expose a portion of a side surface and a second top surface of the end of the first through-hole; second recessing the first top surface of the first semiconductor substrate body; forming a first diffusion barrier layer that covers the second recessed first top surface of the first semiconductor substrate body and exposes the second top surface of the end of the first through-hole; and directly bonding a second semiconductor substrate to the first diffusion barrier layer and the second top surface of the end of the first through-hole.

[0005] Another embodiment of this disclosure provides a semiconductor device comprising: a first semiconductor substrate; and a second semiconductor substrate directly bonded to the first semiconductor substrate, wherein the first semiconductor substrate may include a first semiconductor substrate body; a first via having an end protruding through a first top surface, the first top surface being the top surface of the first semiconductor substrate body; a liner disposed at an interface between the first via and the first semiconductor substrate body, and extending to partially expose a side surface of the end of the first via; and a first diffusion barrier layer covering the first top surface of the semiconductor substrate body and covering the side surface of the end of the first via, wherein the liner includes an inclined third top surface positioned lower than a second top surface, the second top surface being the top surface of the end of the first via, and wherein the inclined third top surface includes a first edge portion located higher than the first top surface of the first semiconductor substrate body and a second edge portion located lower than the first top surface of the first semiconductor substrate body opposite to the first edge portion. Attached Figure Description

[0006] Figure 1 This is a schematic cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure.

[0007] Figure 2 It is shown Figure 1 A schematic diagram of the direct bonding of the semiconductor substrate of the semiconductor device.

[0008] Figure 3 It is shown Figure 1 A schematic cross-sectional view of the semiconductor substrate of the semiconductor device.

[0009] Figure 4 This is a schematic cross-sectional view illustrating copper (Cu) contamination that may occur during bonding of a semiconductor substrate according to a comparative example.

[0010] Figure 5 This is a schematic cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0011] Figure 6 It is shown Figure 5 A schematic cross-sectional view of the semiconductor substrate of the semiconductor device.

[0012] Figure 7 This is a schematic cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0013] Figure 8 It is shown Figure 7 A schematic cross-sectional view of the semiconductor substrate of the semiconductor device.

[0014] Figure 9 This is a schematic cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0015] Figure 10 This is a schematic cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0016] Figure 11 This is a schematic cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0017] Figures 12 to 17 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0018] Figure 18 This is a schematic cross-sectional view showing the formation of pores in a semiconductor substrate according to a comparative example.

[0019] Figure 19 This is a schematic cross-sectional view illustrating copper (Cu) contamination that may occur during bonding of a semiconductor substrate according to a comparative example.

[0020] Figure 20 and Figure 21 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0021] Figures 22 to 24 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0022] Figure 25 and Figure 26This is a schematic cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0023] Figure 27 This is a block diagram illustrating an electronic system employing a memory card including a package according to an embodiment of the present disclosure.

[0024] Figure 28 This is a block diagram illustrating an electronic system including a package according to an embodiment of the present disclosure. Detailed Implementation

[0025] The terms used herein may correspond to words chosen in consideration of their function in the presented embodiments, and the meaning of the terms may be interpreted differently by one of ordinary skill in the art to which the embodiments pertain. If defined in detail, these terms may be interpreted according to the definition. Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments pertain.

[0026] It should be understood that although the terms “first” and “second,” “side,” “top” and “bottom or lower” may be used herein to describe various devices, these devices should not be limited by these terms. These terms are used only to distinguish one device from another, and not to indicate a particular sequence or number of devices.

[0027] Semiconductor devices can include semiconductor substrates or structures with multiple semiconductor substrates stacked together. A semiconductor device can refer to a semiconductor package structure in which a structure with stacked semiconductor substrates is encapsulated. A semiconductor substrate can refer to a semiconductor wafer, semiconductor chip, or semiconductor chip in which electronic components and devices are integrated. A semiconductor chip can refer to a memory chip that integrates memory integrated circuits such as dynamic random access memory (DRAM), static random access memory (SRAM), NAND flash memory, NOR flash memory, magnetic random access memory (MRAM), resistive random access memory (ReRAM), ferroelectric random access memory (FeRAM), or phase-change random access memory (PCRAM), logic chips or ASIC chips with logic circuitry integrated in the semiconductor substrate, or processors such as application processors (APs), graphics processing units (GPUs), central processing units (CPUs), or system-on-a-chip (SoCs). Semiconductor devices can be used in information and communication systems such as mobile phones, biotechnology or healthcare-related electronic systems, or wearable electronic systems. Semiconductor devices are suitable for the Internet of Things (IoT).

[0028] Throughout this specification, the same reference numerals refer to the same devices. Although reference numerals may not be mentioned or described in the accompanying drawings, they may be mentioned or described in another drawing. Furthermore, even if reference numerals may not be shown in the accompanying drawings, they may be shown in another drawing.

[0029] Figure 1 This is a schematic cross-sectional view showing a semiconductor device 10 according to an embodiment of the present disclosure. Figure 2 It is shown Figure 1 A schematic diagram of the direct bonding of semiconductor substrates 100 and 200 of semiconductor device 10. Figure 3 It is shown Figure 1 A schematic cross-sectional view of the first semiconductor substrate 100 of the semiconductor device 10.

[0030] Reference Figure 1 and Figure 2 The semiconductor device 10 may include a first semiconductor substrate 100 and a second semiconductor substrate 200. The second semiconductor substrate 200 may be substantially vertically stacked on the first semiconductor substrate 100. The first semiconductor substrate 100 may have the shape of a semiconductor wafer. The first semiconductor substrate 100 may have the shape of a separate wafer separated from the semiconductor wafer. The second semiconductor substrate 200 may have the shape of a separate wafer separated from the semiconductor wafer. The second semiconductor substrate 200 may have the shape of a semiconductor wafer. The second semiconductor substrate 200 may have a shape substantially the same as the first semiconductor substrate 100, or may include the same elements as the first semiconductor substrate 100. The semiconductor device 10 may have a structure in which semiconductor wafers or semiconductor substrates 100 and 200 are three-dimensionally stacked. The semiconductor device 10 may have a structure in which other semiconductor substrates are placed on a wafer-level semiconductor substrate.

[0031] The second semiconductor substrate 200 can be directly bonded to the first semiconductor substrate 100. No separate bonding or connecting members need to be introduced between the second semiconductor substrate 200 and the first semiconductor substrate 100. For example, connecting members such as solder balls or solder bumps do not need to be inserted between the second semiconductor substrate 200 and the first semiconductor substrate 100. The second semiconductor substrate 200 and the first semiconductor substrate 100 can be bonded to each other while facing surfaces that are in contact and in close contact with each other. No separate adhesive or underfill material needs to be introduced into the bonding interface where the second semiconductor substrate 200 is directly bonded to the first semiconductor substrate 100. This direct bonding of the substrates can indicate a hybrid bonding of the substrates.

[0032] Reference Figure 1 and Figure 3The first semiconductor substrate 100 may include a first semiconductor substrate body 110, a first via 120, a first substrate 130, and a first diffusion barrier layer 140. The first semiconductor substrate 100 may also include a first multi-level interconnect structure 160, a first conductive pad 150, and a third diffusion barrier layer 155.

[0033] The first semiconductor substrate body 110 may include silicon (Si) or other semiconductor materials. The first semiconductor substrate body 110 may include a first top surface 110T and a first bottom surface 110B opposite to each other. Integrated circuit elements (not shown) may be integrated on the first bottom surface 110B of the first semiconductor substrate body 110. The integrated circuit elements may include memory devices such as DRAM devices or NAND devices. The first bottom surface 110B may indicate the front side of the first semiconductor substrate body 110, and the first top surface 110T may indicate the rear side of the first semiconductor substrate body 110. The first top surface 110T of the first semiconductor substrate body 110 may be a surface without integrated circuits.

[0034] The first via 120 can be introduced as a vertical connection member that penetrates substantially perpendicularly through the first semiconductor substrate body 110. The first via 120 may include a conductive material filling a first opening 113 that penetrates substantially perpendicularly through the first semiconductor substrate body 110. The first opening 113 may be a through-hole. The first via 120 may be introduced as an element such as a through-silicon via (TSV). The first via 120 may be configured as a conductive element extending at least from a first bottom surface 110B of the first semiconductor substrate body 110 to a first top surface 110T. The first via 120 may extend further such that an end 120E protrudes from the first top surface 110T of the first semiconductor substrate body 110. The first via 120 may extend further to penetrate substantially perpendicularly through the first diffusion barrier layer 140.

[0035] The first via 120 may include copper (Cu), which has a lower resistivity than aluminum (Al) or conductive polycrystalline silicon. The first via 120 may include a first via body 121 and a first side barrier layer 122. The first via body 121 may be formed in a columnar or plug shape comprising copper (Cu).

[0036] The first side barrier layer 122 may be configured to cover the side surface of the first via body 121. The first side barrier layer 122 may be introduced to reduce or substantially block the diffusion of copper (Cu) ions from the first via body 121 in the lateral direction. The first side barrier layer 122 can prevent the diffusion of copper (Cu) ions in the lateral direction, thereby reducing or substantially preventing the diffusion of copper (Cu) or copper (Cu) ions constituting the first via body 121 into the first semiconductor substrate body 110 and contaminating the first semiconductor substrate body 110. The first side barrier layer 122 may be formed of a diffusion-blocking material that prevents the diffusion of copper (Cu) ions. The first side barrier layer 122 may include a tantalum (Ta) layer or a tantalum nitride (TaN) layer. The first side barrier layer 122 may include a double layer of tantalum (Ta) layer and tantalum nitride (TaN) layer. The tantalum (Ta) layer may be disposed between the first via body 121 and the tantalum nitride layer.

[0037] A first liner 130 may be disposed on a side surface of the first side barrier layer 122. The first liner 130 may be positioned between the first semiconductor substrate body 110 and the first side barrier layer 122. The first liner 130 may be introduced as an insulating layer electrically isolating the first side barrier layer 122 and the first semiconductor substrate body 110, or as an insulating layer electrically isolating the first via 120 and the first semiconductor substrate body 110. The first liner 130 may be introduced as a buffer layer that reduces or decreases stress that may occur between the first via 120 and the first semiconductor substrate body 110. The first liner 130 may include a silicon oxide (SiO2) layer. The silicon oxide (SiO2) layer may include silicon oxide prepared from a material such as tetraethyl orthosilicate (TEOS).

[0038] The first liner 130 may also extend between a portion of the first diffusion barrier layer 140 and the first side barrier layer 122. The first liner 130 may further extend to expose a portion of the side surface of the end portion 120E of the first via 120. The first liner 130 may extend to expose the upper side surface S1 of the end portion 120E of the first via 120 and cover the lower side surface S2 of the end portion 120E. The first liner 130 may not extend to completely cover the upper side surface S1 of the end portion 120E of the first via 120. The lower side surface S2 of the end portion 120E of the first via 120 may be a side portion that is relatively closer to the first top surface 110T of the first semiconductor substrate body 110 than the upper side surface S1.

[0039] The first diffusion barrier layer 140 may be configured to cover a first top surface 110T of the first semiconductor substrate body 110. The first diffusion barrier layer 140 may be configured to cover the upper surface S1 of the end portion 120E of the first via 120. The end portion 120E of the first via 120 may extend further to penetrate the first diffusion barrier layer 140 substantially vertically. The first diffusion barrier layer 140 may extend to cover and seal a third top surface 130T of the first bushing 130. The second top surface 120T of the end portion 120E of the first via 120 may be exposed outside the fourth top surface 140T of the first diffusion barrier layer 140. The second top surface 120T of the end portion 120E of the first via 120 and the fourth top surface 140T of the first diffusion barrier layer 140 may have the same surface height. The second top surface 120T of the end 120E of the first through hole 120 and the fourth top surface 140T of the first diffusion barrier layer 140 can form globally flat surfaces connected to each other without any step difference between the second top surface 120T and the fourth top surface 140T.

[0040] The first diffusion barrier layer 140 may be configured as a layer comprising a dielectric material or an insulating material. The first diffusion barrier layer 140 may include another diffusion barrier material having a lower copper (Cu) ion diffusion rate than the first substrate 130. The first diffusion barrier layer 140 may include a diffusion barrier material capable of reducing or substantially preventing copper (Cu) ion diffusion. The first diffusion barrier layer 140 may include a diffusion barrier material capable of reducing or substantially preventing copper (Cu) ion diffusion compared to silicon oxide. The first diffusion barrier layer 140 may include a silicon nitride (Si3N4) layer.

[0041] Reference Figure 3The third top surface 130T of the first substrate 130 may be located at a height H2 that is higher than the height H1 of the first top surface 110T of the first semiconductor substrate body 110. The third top surface 130T of the first substrate 130 may have a step difference with the first top surface 110T of the first semiconductor substrate body 110 to form a stepped shape. The third top surface 130T of the first substrate 130 may be located at a height H2 that is lower than the height H3 of the second top surface 120T of the end 120E of the first via 120. Heights H1, H2, and H3 may indicate the surface height from the first bottom surface 110B of the first semiconductor substrate body 110. The first diffusion barrier layer 140 may extend to cover the third top surface 130T of the first substrate 130. The third top surface 130T of the first liner 130 can be located at the height between the first top surface 110T of the first semiconductor substrate body 110 and the second top surface 120T of the end 120E of the first through hole 120, so that the third top surface 130T of the first liner 130 can be covered by the first diffusion barrier layer 140, thereby being in close contact with the first diffusion barrier layer 140 while being isolated from the outside.

[0042] The first semiconductor substrate 100 may further include a first multi-level interconnect structure 160. The first multi-level interconnect structure 160 may be disposed below a first bottom surface 110B of the first semiconductor substrate body 110. The first multi-level interconnect structure 160 may be electrically connected to a first via 120. The first multi-level interconnect structure 160 may include a plurality of conductive patterns 162, 163, and 164 disposed in a first dielectric layer 161. Due to the first dielectric layer 161, the plurality of conductive patterns 162, 163, and 164 may be insulated from each other. The first conductive pattern 162 and the third conductive pattern 164 may be located at different heights. A second conductive pattern 163 may substantially penetrate the first dielectric layer 161 to electrically connect the first conductive pattern 162 to the first via 120.

[0043] The first semiconductor substrate 100 may further include a first conductive pad 150 and a third diffusion barrier layer 155. The first conductive pad 150 may be introduced as a connection member for electrically connecting the first semiconductor substrate 100 to an external device or another semiconductor substrate. The first conductive pad 150 may be electrically connected to a first multilevel interconnect structure 160. The first conductive pad 150 may be electrically connected to an integrated circuit element integrated in the first semiconductor substrate 100 via the first multilevel interconnect structure 160. The first conductive pad 150 may be electrically connected to a first via 120 via the first multilevel interconnect structure 160. The first conductive pad 150 may be electrically connected to the first via 120 via a first conductive pattern 162 and a second conductive pattern 163.

[0044] The first conductive pad 150 may be configured with a conductive pattern including a metallic material such as copper (Cu). The third diffusion barrier layer 155 may be configured to cover the first multilevel interconnect structure 160 while exposing the surface of the first conductive pad 150. The third diffusion barrier layer 155 may be configured to cover and protect the passivation layer of the first multilevel interconnect structure 160. The third diffusion barrier layer 155 may include a silicon nitride (Si3N4) layer.

[0045] Reference Figure 1 and Figure 2 The second semiconductor substrate 200 can be directly bonded to the first semiconductor substrate 100 without inserting another separate layer such as an adhesive layer, connecting member, or solder layer. Surfaces 250B and 255B of the second semiconductor substrate 200 can be directly bonded to the facing surfaces 120T and 140T of the first semiconductor substrate 100. The first top surface 120T of the first via 120 of the first semiconductor substrate 100 and the second top surface 140T of the first diffusion barrier layer 140 can provide surfaces 120T and 140T for bonding to the second semiconductor substrate 200. The second semiconductor substrate 200 may include a second conductive pad 250 and a second diffusion barrier layer 255. The second conductive pad 250 and the second diffusion barrier layer 255 can provide surfaces 250B and 255B for bonding to the first semiconductor substrate 100.

[0046] The second conductive pad 250 of the second semiconductor substrate 200 can be directly bonded to the first via 120 of the first semiconductor substrate 100. The bottom surface 250B of the second conductive pad 250 of the second semiconductor substrate 200 can be directly bonded to the second top surface 120T of the first via 120 of the first semiconductor substrate 100. The second diffusion barrier layer 255 of the second semiconductor substrate 200 can be directly bonded to the fourth top surface 140T of the first diffusion barrier layer 140 of the first semiconductor substrate 100.

[0047] The second conductive pad 250 of the second semiconductor substrate 200 may include a metal material substantially the same as that of the first via 120 of the first semiconductor substrate 100. The second conductive pad 250 may include copper (Cu). Therefore, the second conductive pad 250 can be directly bonded to the first via 120, which is also formed of copper (Cu). The second diffusion barrier layer 255 of the second semiconductor substrate 200 may include a dielectric or insulating material substantially the same as that of the first diffusion barrier layer 140 of the first semiconductor substrate 100. The second diffusion barrier layer 255 of the second semiconductor substrate 200 may include silicon nitride (Si3N4). Therefore, the second diffusion barrier layer 255 can be directly bonded to the first diffusion barrier layer 140, which is also formed of silicon nitride (Si3N4).

[0048] Reference Figure 2The second semiconductor substrate 200 may further include a second semiconductor substrate body 210, a second via 220, a second substrate 230, and a fourth diffusion barrier layer 240. The second via 220 may include a conductive material filling a second opening 213 that penetrates the second semiconductor substrate body 210.

[0049] The second semiconductor substrate 200 may further include a second multilevel interconnect structure 260. The second via 220 can be electrically connected to the second conductive pad 250 through the second multilevel interconnect structure 260. The second multilevel interconnect structure 260 may include a plurality of conductive patterns 262, 263, and 264 disposed in the second dielectric layer 261. The fourth conductive pattern 262 and the sixth conductive pattern 264 may be located at different heights. The fifth conductive pattern 263 can electrically connect the fourth conductive pattern 262 to the second via 220.

[0050] Reference Figure 2 and Figure 3 The second semiconductor substrate 200 may include elements substantially the same as those of the first semiconductor substrate 100. The second semiconductor substrate body 210, the second via 220, and the second substrate 230 of the second semiconductor substrate 200 may correspond to the first semiconductor substrate body 110, the first via 102, and the first substrate 130 of the first semiconductor substrate 100. The second semiconductor substrate body 210, the second via 220, and the second substrate 230 of the second semiconductor substrate 200 may be configured to have substantially the same shape as the first semiconductor substrate body 110, the first via 120, and the first substrate 130 of the first semiconductor substrate 100, respectively.

[0051] The fourth diffusion barrier layer 240 of the second semiconductor substrate 200 may indicate the first diffusion barrier layer 140 of the first semiconductor substrate 100. The fourth diffusion barrier layer 240 of the second semiconductor substrate 200 may be configured to have a shape substantially the same as the first diffusion barrier layer 140 of the first semiconductor substrate 100. The second multilevel interconnect structure 260 of the second semiconductor substrate 200 may indicate the first multilevel interconnect structure 160 of the first semiconductor substrate 100. The second multilevel interconnect structure 260 of the second semiconductor substrate 200 may be configured to have a shape substantially the same as the first multilevel interconnect structure 160 of the first semiconductor substrate 100.

[0052] The second conductive pad 250 of the second semiconductor substrate 200 can indicate the first conductive pad 150 of the first semiconductor substrate 100. The second conductive pad 250 of the second semiconductor substrate 200 can be configured to have a shape substantially the same as the first conductive pad 150 of the first semiconductor substrate 100. The second diffusion barrier layer 255 of the second semiconductor substrate 200 can indicate the third diffusion barrier layer 155 of the first semiconductor substrate 100. The second diffusion barrier layer 255 of the second semiconductor substrate 200 can be configured to have a shape substantially the same as the third diffusion barrier layer 155 of the first semiconductor substrate 100.

[0053] Figure 4 This is a schematic cross-sectional view showing possible copper (Cu) contamination in the bonding of semiconductor substrates 10 and 20 according to a comparative example.

[0054] Reference Figure 4 The semiconductor device 10R according to the comparative example can be configured by directly bonding the second semiconductor substrate 20 to the first semiconductor substrate 10. In the process of configuring the semiconductor device 10R according to the comparative example, copper (Cu) contamination that may occur in the first semiconductor substrate 10 due to copper (Cu) diffusion may be a problem to be overcome. The first semiconductor substrate 10 may include vias 12, a substrate 13, and a diffusion barrier layer 14. The second semiconductor substrate 20 may include conductive pads 25. When the second semiconductor substrate 20 is directly bonded or directly connected to the first semiconductor substrate 10, the bottom surface 25B of the conductive pads 25 of the second semiconductor substrate 20 may be connected to the top surface 12T of the vias 12 of the first semiconductor substrate 10. The substrate 13 may extend to substantially cover the entire side surface of the end 12E of the via 12. The top surface 13T of the substrate 13 may contact the bottom surface 25B of the conductive pads 25. The substrate 13 may be connected to the conductive pads 25 such that the substrate 13 provides a path for copper (Cu) diffusion or copper (Cu) ion diffusion.

[0055] like Figure 1As shown, the third top surface 130T of the first substrate 130 according to an embodiment of the present disclosure can be covered by a portion of the first diffusion barrier layer 140. Because the third top surface 130T of the first substrate 130 is sealed by a portion of the first diffusion barrier layer 140, the third top surface 130T of the first substrate 130 can be prevented from contacting the second bottom surface 250B of the second conductive pad 250 of the second semiconductor substrate 200. The portion of the first diffusion barrier layer 140 covering the third top surface 130T of the first substrate 130 can be used to isolate the second conductive pad 250 from the first substrate 130. Therefore, the diffusion of copper (Cu) or copper (Cu) ions constituting the second conductive pad 250 into the first substrate 130 can be effectively prevented. Because the diffusion of copper (Cu) or copper (Cu) ions can be blocked in this way, it is possible to overcome the limitations of traditional methods. Figure 4 The copper (Cu) contamination problem shown.

[0056] Figure 5 This is a schematic cross-sectional view showing a semiconductor device 10-1 according to another embodiment of the present disclosure. Figure 6 It is shown Figure 5 A schematic cross-sectional view of the semiconductor substrate 100-1 of the semiconductor device 10-1. Figure 5 and Figure 6 In, with Figures 1 to 3 In the accompanying drawings, the same reference numerals can indicate the same elements. Figure 5 and Figure 6 In, with Figures 1 to 3 Elements with essentially the same or similar shapes can indicate the same element.

[0057] Reference Figure 5 and Figure 6 Semiconductor device 10-1 may include a first semiconductor substrate 100-1 and a second semiconductor substrate 200-1. The second semiconductor substrate 200-1 may be directly bonded to the first semiconductor substrate 100-1. The first semiconductor substrate 100-1 may include a first semiconductor substrate body 110, a first via 120, a first substrate 130-1, and a first diffusion barrier layer 140. The first semiconductor substrate 100-1 may also include a first multi-level interconnect structure 160, a first conductive pad 150, and a third diffusion barrier layer 155. The second semiconductor substrate 200-1 may include at least a second substrate 230-1, a second conductive pad 250, and a second diffusion barrier layer 255. The second semiconductor substrate 200-1 may include elements substantially the same as those in the first semiconductor substrate 100-1.

[0058] The first substrate 130-1 of the first semiconductor substrate 100-1 can expose the side surface S1-1 of the end 120E of the first via 120 and can extend between the first semiconductor substrate body 110 and the first side barrier layer 122. The height H2-1 of the third top surface 130T of the first substrate 130-1 can be substantially equal to the height H1 of the first top surface 110T of the first semiconductor substrate body 110. The third top surface 130T-1 of the first substrate 130-1 can be located at a height H2-1 lower than the second top surface 120T of the first via 120, such that a portion of the first diffusion barrier layer 140 can cover and shield the third top surface 130T-1 of the first substrate 130-1. Therefore, due to the first diffusion barrier layer 140, the first substrate 130-1 can be isolated from the second bottom surface 250B of the second conductive pad 250 of the second semiconductor substrate 200-1. Therefore, it can effectively prevent copper (Cu) ions or copper (Cu) components constituting the second conductive pad 250 from diffusing into the first semiconductor substrate 100-1 through the first substrate 130-1.

[0059] Figure 7 This is a schematic cross-sectional view showing a semiconductor device 10-2 according to another embodiment of the present disclosure. Figure 8 It is shown Figure 7 A schematic cross-sectional view of the semiconductor substrate 100-2 of the semiconductor device 10-2. Figure 7 and Figure 8 In, with Figures 1 to 3 In the accompanying drawings, the same reference numerals can indicate the same elements. Figure 7 and Figure 8 In, with Figures 1 to 3 Elements with essentially the same or similar shapes can indicate the same element.

[0060] Reference Figure 7 and Figure 8 Semiconductor device 10-2 may include a first semiconductor substrate 100-2 and a second semiconductor substrate 200-2. The second semiconductor substrate 200-2 may be directly bonded to the first semiconductor substrate 100-2. The first semiconductor substrate 100-2 may include a first semiconductor substrate body 110, a first via 120, a first substrate 130-2, and a first diffusion barrier layer 140. The first semiconductor substrate 100-2 may also include a first multi-level interconnect structure 160, a first conductive pad 150, and a third diffusion barrier layer 155. The second semiconductor substrate 200-2 may include at least a second substrate 230-2, a second conductive pad 250, and a second diffusion barrier layer 255. The second semiconductor substrate 200-2 may include elements substantially the same as those in the first semiconductor substrate 100-2.

[0061] The first liner 130-2 may expose the upper side S1-2 of the end portion 120E of the first via 120 and extend to cover the lower side S2-2 of the end portion 120E. The first liner 130-2 may expose the upper side S1-2 of the end portion 120E of the first via 120 and extend between the first semiconductor substrate body 110 and the first side barrier layer 122. The third top surface 130T-2 of the first liner 130-2 may have an inclined surface shape. The height H2-2 of the third top surface 130T-2 may be higher than the height H1 of the first top surface 110T of the first semiconductor substrate body 110. The third top surface 130T-2 of the first liner 130-2 may be an inclined surface, with one end extending from the first top surface 110T of the first semiconductor substrate body 110 and the other end located at a height H2-2 higher than the first top surface 110T of the first semiconductor substrate body 110.

[0062] The third top surface 130T-2 of the first substrate 130-2 is located at a height H2-2 lower than the second top surface 120T of the first via 120, such that a portion of the first diffusion barrier layer 140 can cover and shield the third top surface 130T-2 of the first substrate 130-2. Therefore, due to the first diffusion barrier layer 140, the first substrate 130-2 can be isolated from the second bottom surface 250B of the second conductive pad 250 of the second semiconductor substrate 200-2. This effectively prevents copper (Cu) ions or copper (Cu) components constituting the second conductive pad 250 from diffusing into the first semiconductor substrate 110-2 through the first substrate 130-2.

[0063] Figure 9 This is a schematic cross-sectional view showing a semiconductor device 10-3 according to another embodiment of the present disclosure. Figure 9 In, with Figures 1 to 3 In the accompanying drawings, the same reference numerals can indicate the same elements. Figure 9 In, with Figures 1 to 3 Elements with essentially the same or similar shapes can indicate the same element.

[0064] Reference Figure 9Semiconductor device 10-3 may include a first semiconductor substrate 100-3 and a second semiconductor substrate 200-3. The second semiconductor substrate 200-3 may be directly bonded to the first semiconductor substrate 100-3. The first semiconductor substrate 100-3 may include a first semiconductor substrate body 110, a first via 120, a first substrate 130, and a first diffusion barrier layer 140. The first semiconductor substrate 100-3 may also include a first multi-level interconnect structure 160, a first conductive pad 150-3, and a third diffusion barrier layer 155. The second semiconductor substrate 200-3 may include at least a second conductive pad 250-3 and a second diffusion barrier layer 255. The second semiconductor substrate 200-3 may include components substantially the same as those in the first semiconductor substrate 100-3.

[0065] The second conductive pad 250-3 of the second semiconductor substrate 200-3 may have a width W2 that is narrower than the width W1 of the first via 120 of the first semiconductor substrate 100-3. Width W1 may indicate the diameter of the first via 120, and width W2 may indicate the diameter of the second conductive pad 250-3. The width W2 of the second conductive pad 250-3 may be 1 / 2 to 1 / 6 times the width W1 of the first via 120. The second conductive pad 250-3 may have a diameter or width W2 of approximately 1.0 μm to 2.0 μm, while the first via 120 may have a diameter or width W1 of 4.0 μm to 6.0 μm. Therefore, the surface area of ​​the second bottom surface 250-3B of the second conductive pad 250-3 may be smaller than the surface area of ​​the second top surface 120T of the first via 120.

[0066] Because the second conductive pad 250-3 has a width W2 that is narrower than the width W1 of the first via 120, when the second semiconductor substrate 200-3 is directly bonded to the first semiconductor substrate 100-3, the likelihood that the second conductive pad 250-3 will be located within the range of the second top surface 120T of the first via 120 can be increased. When the second semiconductor substrate 200-3 is directly bonded to the first semiconductor substrate 100-3, the second semiconductor substrate 200-3 can be aligned with the first semiconductor substrate 100-3, and the second conductive pad 250-3 can be aligned with the first via 120. Because the width W2 of the second conductive pad 250-3 is narrower than the width W1 of the first via 120, the likelihood or alignment margin of the second conductive pad 250-3 being aligned within the range of the second top surface 120T of the first via 120 can be increased.

[0067] Refer again Figure 1The second conductive pad 250 of the second semiconductor substrate 200 may have a wider width than the first via 120. When the second conductive pad 250 is attached to the first via 120, a portion of the second conductive pad 250 may extend beyond the range of the second top surface 120T of the first via 120, thereby overlapping with a portion of the first diffusion barrier layer 140 of the underlying first semiconductor substrate 100. Conversely, Figure 9 The second conductive pad 250-3 shown can be located within the range of the second top surface 120T of the first via 120, and a portion of the second top surface 120T of the first via 120 can be covered by the second diffusion barrier layer 255 of the second semiconductor substrate 200-3. Therefore, the portion between the second conductive pad 250-3 of the second semiconductor substrate 200-3 and the first substrate 130 of the first semiconductor substrate 100-3 can be further blocked by the overlapping portion of the second diffusion barrier layer 255. The portion between the second conductive pad 250-3 and the first substrate 130 can be doubly blocked by at least the overlapping portion of the second diffusion barrier layer 255 and a portion of the first diffusion barrier layer 140. Therefore, the diffusion of the copper (Cu) component constituting the second conductive pad 250-3 into the first substrate 130 can be more effectively prevented.

[0068] Figure 10 This is a schematic cross-sectional view showing a semiconductor device 10-4 according to another embodiment of the present disclosure. Figure 10 In, with Figure 5 , Figure 6 and Figure 9 In the accompanying drawings, the same reference numerals can indicate the same elements. Figure 10 In, with Figure 5 , Figure 6 and Figure 9 Elements with essentially the same or similar shapes can indicate the same element.

[0069] Reference Figure 10 Semiconductor device 10-4 may include a first semiconductor substrate 100-4 and a second semiconductor substrate 200-4. The second semiconductor substrate 200-4 may be directly bonded to the first semiconductor substrate 100-4. The first semiconductor substrate 100-4 may include a first semiconductor substrate body 110, a first via 120, a first substrate 130-1, and a first diffusion barrier layer 140. The first semiconductor substrate 100-4 may also include a first multi-level interconnect structure 160, a first conductive pad 150-3, and a third diffusion barrier layer 155. The second semiconductor substrate 200-4 may include at least a second conductive pad 250-3 and a second diffusion barrier layer 255. The second semiconductor substrate 200-4 may include components substantially the same as those in the first semiconductor substrate 100-4.

[0070] The second conductive pad 250-3 of the second semiconductor substrate 200-3 may have a width W2 that is smaller than the width W1 of the first through hole 120 of the first semiconductor substrate 100-4. Therefore, the copper (Cu) component constituting the second conductive pad 250-3 can be more effectively prevented from diffusing into the first substrate 130-1.

[0071] Figure 11 This is a schematic cross-sectional view showing a semiconductor device 10-5 according to another embodiment of the present disclosure. Figure 11 In, with Figures 7 to 9 In the accompanying drawings, the same reference numerals can indicate the same elements. Figure 11 In, with Figures 7 to 9 Elements with essentially the same or similar shapes can indicate the same element.

[0072] Reference Figure 11 Semiconductor device 10-5 may include a first semiconductor substrate 100-5 and a second semiconductor substrate 200-5. The second semiconductor substrate 200-5 may be directly bonded to the first semiconductor substrate 100-5. The first semiconductor substrate 100-5 may include a first semiconductor substrate body 110, a first via 120, a first substrate 130-2, and a first diffusion barrier layer 140. The first semiconductor substrate 100-5 may also include a first multi-level interconnect structure 160, a first conductive pad 150-3, and a third diffusion barrier layer 155. The second semiconductor substrate 200-5 may include at least a second conductive pad 250-3 and a second diffusion barrier layer 255. The second semiconductor substrate 200-5 may include components substantially the same as those in the first semiconductor substrate 100-5.

[0073] The second conductive pad 250-3 of the second semiconductor substrate 200-5 may have a width W2 that is smaller than the width W1 of the first through hole 120 of the first semiconductor substrate 100-5. Therefore, the diffusion of the copper (Cu) component constituting the second conductive pad 250-3 into the first substrate 130-2 can be prevented more effectively.

[0074] Figures 12 to 17 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figures 12 to 17 The formation can be schematically shown Figure 3 The process steps of the first semiconductor substrate 100. Figures 12 to 17 In, with Figure 3 In the accompanying drawings, the same reference numerals can indicate the same elements. Figures 12 to 17 In, with Figure 3 Elements with essentially the same or similar shapes can indicate the same element.

[0075] Reference Figure 12 A first through-hole 120, surrounded by a first substrate 130L, can be formed in a first semiconductor substrate body 110. The first semiconductor substrate body 110 may include a semiconductor substrate having a first bottom surface 110B and an initial first top surface 110T-S opposite to each other. A first opening 113 can be formed at the first bottom surface 110B of the first semiconductor substrate body 110. Detailed process steps for integrating integrated circuit elements (not shown) on the first bottom surface 110B of the first semiconductor substrate body 110 can be performed prior to the process of forming the first opening 113.

[0076] A first insert 130L may be formed in a first opening 113 formed in the first semiconductor substrate body 110. The first insert 130L may be formed as a layer extending to conformally cover the sidewalls and bottom of the first opening 113. A first side barrier layer 122 may be formed to cover the first insert 130L. A first via body 121 may be formed to cover the first side barrier layer 122 and may substantially fill and bury the first opening 113. A first via 120 may be surrounded by the first insert 130L.

[0077] The first multilevel interconnect structure 160 may be further formed below the first bottom surface 110B of the first semiconductor substrate body 110. The first conductive pad 150 and the third diffusion barrier layer 155 may be further formed below the first multilevel interconnect structure 160.

[0078] Reference Figure 13 The first semiconductor substrate body 110 can be first recessed (301) from the initial top surface 110T-S. The first recessed first top surface 110T-M of the first semiconductor substrate body 110 can be formed by the first recess. The first recessed first top surface 110T-M of the first semiconductor substrate body 110 can be formed during the formation of... Figure 3 The intermediate first top surface 110T-M preceding the first top surface 110T can be exposed by the first recess. The first semiconductor substrate body 110 can be recessed by a dry etching process (301). The dry etching process can be performed as a process for selectively removing silicon (Si) constituting the first semiconductor substrate body 110.

[0079] A portion of the first semiconductor substrate body 110 can be removed through the first recess (301), causing the end 120E of the first through hole 120 to protrude from the first top surface 110T-M of the first recess of the first semiconductor substrate body 110. The end 120E of the first through hole 120 can protrude from the first top surface 110T-M of the first recess of the first semiconductor substrate body 110, while being covered by the first liner 130L.

[0080] Reference Figure 14 The first liner can be removed. Figure 13 The portion 130-R of the first liner 130L surrounding the end 120E of the first via 120 is removed. With the removal of the portion 130-R of the first liner 130L surrounding the end 120E of the first via 120, the first liner 130 can be confined between the first semiconductor substrate body 110 and the first via 120. Therefore, a portion S3 of the side surface of the first via 120 and the second top surface 120T-S can be exposed to the outside of the first liner 130. The first side barrier layer 122 can extend to cover the second top surface 120T-S of the first via 120.

[0081] The process of removing the portion 130-R of the first substrate 130 surrounding the end 120E of the first via 120 may include a wet etching process. The wet etching process can be performed as a process that selectively removes the silicon oxide constituting the first substrate 130. When the portion 130-R of the first substrate 130 surrounding the end 120E of the first via 120 is removed by wet etching, a recess 130-G may appear between the first semiconductor substrate body 110 and the side surface of the end 120E of the first via 120. During the complete removal of the portion 130-R of the first substrate 130 surrounding the end 120E of the first via 120 by wet etching, the first substrate 130 may be over-etched. Therefore, the recess 130-G can be generated.

[0082] Reference Figure 15 The first semiconductor substrate body 110 can be recessed a second time (303). By making the first top surface 110T-M of the first recessed first semiconductor substrate body 110 a second recess (303), the height of the first top surface 110T-M of the first recess can be reduced to the height of the first top surface 110T of the second recess. The second recess (303) can be performed such that the first top surface 110T of the second recess has a height H1 that is lower than the height H2 of the third top surface 130T of the first liner 130. Therefore, the third top surface 130T of the first liner 130 can be located at a height H2 that is lower than the second top surface 120T-S of the end 120E of the first through hole 120 and higher than the first top surface 110T of the second recess. By performing the second recess (303) in this way, the first top surface 110T of the second recess can be removed. Figure 14 The concave shape of the recess 130-G in the middle.

[0083] Reference Figure 16A first diffusion barrier layer 140L can be formed. The first diffusion barrier layer 140L can extend to cover the second recessed first top surface 110T of the first semiconductor substrate body 110, and cover the second top surface 120T-S and a portion S3 of the side surface of the end 120E of the first via 120. The first diffusion barrier layer 140L can be formed by a deposition process. The first diffusion barrier layer 140L can include multiple sublayers. The first diffusion barrier layer 140L can be formed by depositing a first sublayer 141 and depositing a second sublayer 142 on the first sublayer 141. The first sublayer 141 can include a dielectric material different from the second sublayer 142. The first sublayer 141 can include a silicon nitride layer, and the second sublayer 142 can include a silicon oxide layer. The silicon oxide layer can be used as a stress buffer to compensate for the relative fragility of the silicon nitride layer to stress. The silicon oxide layer of the second sublayer 142 can be formed on the silicon nitride layer. Therefore, due to the silicon nitride layer, the first substrate 130 and the first via 120 can not contact the silicon oxide layer.

[0084] Reference Figure 17 The first diffusion barrier layer 140L can be planarized (304). A chemical mechanical polishing (CMP) process can be performed on the first diffusion barrier layer 140L to form a planarized first diffusion barrier layer 140. The first diffusion barrier layer 140L can be chemically mechanically polished to expose the second top surface 120T of the end portion 120E of the first via 120. When the first diffusion barrier layer 140L is chemically mechanically polished, a portion of the end portion 120E of the first via 120 can be removed together. Therefore, the top surface of the first via body 122 can be exposed to the second top surface 120T of the end portion 120E of the first via 120.

[0085] Second semiconductor substrate ( Figure 1 The 200 in the figure can be directly bonded to the first semiconductor substrate 100 formed as described above, thereby forming a semiconductor device. Figure 1 10 in the middle).

[0086] Figure 18 This is a schematic cross-sectional view showing the formation of a hole 14V in a first semiconductor substrate 100R according to a comparative example. Figure 19 This is a schematic cross-sectional view showing possible copper (Cu) contamination in the bonding of semiconductor substrates 10-1 and 20-1 according to a comparative example.

[0087] Reference Figure 18 The depression 130-G remaining during the process of removing a portion of the end of the first substrate 13 surrounding the first via by wet etching can create pores 14V during the deposition of the first diffusion barrier layer 14L. The resulting pores 14V can act as a cause of copper (Cu) contamination in the semiconductor device 10R-1, such as... Figure 19 As shown. When the semiconductor device 10R-1 is constructed by directly bonding the second semiconductor substrate 20-1 to the first semiconductor substrate 10-1, the aperture 14L provides a channel through which the copper (Cu) component or copper (Cu) ions of the conductive pads 25 constituting the second semiconductor substrate 20-1 diffuse. The aperture 14L can be located on the side surface of the end 120E of the through hole 12 of the first semiconductor substrate 10-1, and can be connected to the bottom surface 25B of the conductive pad 25 connected to the through hole 12. Therefore, the copper (Cu) component of the conductive pad 25 can diffuse into the first semiconductor substrate body 110 through the aperture 14L.

[0088] Reference Figure 14 and Figure 15 During the process of making the first semiconductor substrate body 110 second recessed, as the height H1 of the second recessed first top surface 110T becomes lower than the height of the first recessed first top surface 110T-M, the recess can be removed. Figure 14 The shape of 130-G in the text. Therefore, it is possible to prevent the occurrence of such... Figure 18 The aperture shown is 14V. Therefore, as... Figure 1 As shown, when the second semiconductor substrate 200 is directly bonded to the first semiconductor substrate 100, it can prevent the diffusion of copper (Cu) components or copper (Cu) ions through the pores 14V.

[0089] Figure 20 and Figure 21 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure. Figure 20 and Figure 21 The formation can be schematically shown Figure 6 The process of the first semiconductor substrate 100-1 in the process. Figure 20 and Figure 21 In, with Figure 6 and Figure 14 In the accompanying drawings, the same reference numerals can indicate the same elements. Figure 20 and Figure 21 In, with Figure 6 and Figure 14 Elements with essentially the same or similar shapes can indicate the same element.

[0090] Reference Figure 14 and Figure 20When the portion 130-R of the first liner 130 or 130-1 surrounding the end 120E of the first through hole 120 is removed (302), a recess 130-G may be created. The first semiconductor substrate body 110 may be second recessed (303-1) to reduce the height of the first top surface 110T-M of the first recess to the height of the second top surface 110T of the second recess. In this case, the first semiconductor substrate body 110 may be second recessed (303-1) such that the height H1 of the second top surface 110T of the first semiconductor substrate body 110 becomes substantially equal to the height H2-1 of the third top surface 130T-1 of the first liner 130-1, or has substantially the same height as the third top surface 130T-1 of the first liner 130-1.

[0091] Reference Figure 21 A first diffusion barrier layer 140L can be formed. The first diffusion barrier layer 140L can extend to cover the second recessed first top surface 110T of the first semiconductor substrate body 110 and the third top surface 130T-1 of the first liner 130-1, and cover the second top surface 120T-S and a portion S3 of the side surface of the end 120E of the first via 120. Afterwards, the first diffusion barrier layer 140L can be planarized (304). Figure 5 The second semiconductor substrate 200-1 can be directly bonded to the first semiconductor substrate 100-1 formed as described above, thereby forming a semiconductor device. Figure 5 (10-1 in the middle).

[0092] Figures 22 to 24 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure. Figures 22 to 24 The formation can be schematically shown Figure 8 The process of the first semiconductor substrate 100-2 in the process. Figures 22 to 24 In, with Figure 8 , Figure 14 and Figure 20 In the accompanying drawings, the same reference numerals can indicate the same elements. Figures 22 to 24 In, with Figure 8 , Figure 14 and Figure 20 Elements with essentially the same or similar shapes can indicate the same element.

[0093] Reference Figure 22When removing the portion 130-R of the first substrate 130-2 surrounding the end 120E of the first through-hole 120 of the first semiconductor substrate 100-2, a recess 130-G may be generated. In this case, when removing the portion 130-R of the first substrate 130-2, the third top surface 130T-2 of the first substrate 130-2 can be made to have an inclined surface by adjusting the degree of anisotropic etching.

[0094] Reference Figure 23 The first semiconductor substrate body 110 may be recessed a second time (303-2) to reduce the height of the first top surface 110T-M of the first recess to the height of the first top surface 110T of the second recess. In this case, the second recess (303-2) may be performed such that the height H2-2 of the third top surface 130T-1 of the first liner 130-2 becomes higher than the height H1 of the second top surface 110T of the first semiconductor substrate body 110 or becomes lower than the height of the second top surface 120T-S of the end 120E of the first via 120.

[0095] Reference Figure 24 A first diffusion barrier layer 140L can be formed. The first diffusion barrier layer 140L can extend to cover the second recessed first top surface 110T of the first semiconductor substrate body 110 and the third top surface 130T-2 of the first substrate 130-2, and cover the second top surface 120T-S and a portion S3 of the side surface of the end 120E of the first via 120. Afterwards, the first diffusion barrier layer 140L can be planarized (304). The second semiconductor substrate ( Figure 7 200-2 in the figure can be directly bonded to the first semiconductor substrate 100-2 formed as described above, thereby forming a semiconductor device. Figure 7 (10-2 in the middle).

[0096] Figure 25 and Figure 26 This is a schematic cross-sectional view showing a semiconductor device 10-6 according to another embodiment of the present disclosure. Figure 26 It is shown Figure 25 A schematic cross-sectional view of the first semiconductor substrate 100-6 of the semiconductor device 10-6. Figure 25 and Figure 26 In, with Figure 7 and Figure 8 or Figures 1 to 3 In the accompanying drawings, the same reference numerals can indicate the same elements. Figure 25 and Figure 26 In, with Figure 7 and Figure 8 or Figures 1 to 3Elements with essentially the same or similar shapes can indicate the same element.

[0097] Reference Figure 25 and Figure 26 Semiconductor device 10-6 may include a first semiconductor substrate 100-6 and a second semiconductor substrate 200-6. The second semiconductor substrate 200-6 may be directly bonded to the first semiconductor substrate 100-6. The first semiconductor substrate 100-6 may include a first semiconductor substrate body 110, a first via 120, a first substrate 130-6, and a first diffusion barrier layer 140. The first semiconductor substrate 100-6 may also include a first multi-level interconnect structure 160, a first conductive pad 150, and a third diffusion barrier layer 155. The second semiconductor substrate 200-6 may include at least a second substrate 230-6, a second conductive pad 250, and a second diffusion barrier layer 255. The second semiconductor substrate 200-6 may include components substantially the same as those in the first semiconductor substrate 100-6.

[0098] The first liner 130-6 may extend to expose the upper side of the end portion 120E of the first through-hole 120 and cover the lower side of the end portion 120E. The first liner 130-6 may be configured to have an inclined third top surface 130T-6, which is lower than the second top surface 120T of the end portion 120E of the first through-hole 120. The inclined third top surface 130T-6 of the first liner 130-6 may be an inclined surface having a first edge portion 130E1 and an opposing second edge portion 130E2. The first edge portion 130E1 of the inclined third top surface 130T-6 of the first liner 130-6 may be located at a height H2-T that is higher than the height of the first top surface 110T of the first semiconductor substrate body 110, and the second edge portion 130E2 may be located at a height H2-B that is lower than the height of the first top surface 110T of the first semiconductor substrate body 110. The inclined third top surface 130T-6 of the first liner 130-6 can be tilted such that the first edge portion 130E1 is positioned closer to the end 120E of the first through hole 120 than the second edge portion 130E2.

[0099] Because the second edge portion 130E2 of the inclined third top surface 130T-6 of the first substrate 130-6 is located at a lower height H2-B than the first top surface 110T of the first semiconductor substrate body 110, the second edge portion 130E2 of the inclined third top surface 130T-6 can form a step difference with the first top surface 110T of the first semiconductor substrate body 110, and this step difference results in a recess 130-D being formed between the second edge portion 130E2 of the inclined third top surface 130T-6 and the first semiconductor substrate body 110. The first diffusion barrier layer 140 can extend to fill the recess 130-D. The first substrate 130-6 can have an inclined third top surface 130T-6, and the first diffusion barrier layer 140 can fill the recess 130-D without creating pores.

[0100] Some portions of the first diffusion barrier layer 140 can cover and shield the third top surface 130T-6 of the first substrate 130-6. Therefore, due to the first diffusion barrier layer 140, the first substrate 130-6 can be isolated from the second bottom surface 250B of the second conductive pad 250 of the second semiconductor substrate 200-6. This effectively prevents copper (Cu) ions or copper (Cu) components constituting the second conductive pad 250 from diffusing through the first substrate 130-6 into the first semiconductor substrate 100-6.

[0101] Figure 27 This is a block diagram illustrating an electronic system including a memory card 7800 employing at least one of the semiconductor packages according to an embodiment. The memory card 7800 includes a memory 7810, such as a non-volatile memory device, and a memory controller 7820. The memory 7810 and memory controller 7820 can store data or read out stored data. At least one of the memory 7810 and memory controller 7820 may include at least one of the semiconductor packages according to an embodiment.

[0102] The memory 7810 may include a non-volatile memory device to which the techniques of embodiments of the present disclosure are applied. The memory controller 7820 may control the memory 7810 in response to a read / write request from the host 7830, such that stored data is read or stored data is stored.

[0103] Figure 28 This is a block diagram illustrating an electronic system 8710 including at least one of the semiconductor packages according to an embodiment. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be interconnected via a bus 8715 providing the path traversed by data movement.

[0104] In an embodiment, controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. Controller 8711 or memory 8713 may include at least one semiconductor package according to embodiments of the present disclosure. Input / output device 8712 may include at least one selected from keypad, keyboard, display device, touchscreen, etc. Memory 8713 is a means for storing data. Memory 8713 may store data and / or commands to be executed based on controller 8711.

[0105] The memory 8713 may include volatile memory devices such as DRAM and / or non-volatile memory devices such as flash memory. For example, flash memory may be installed in information processing systems such as mobile terminals or desktop computers. Flash memory can form a solid-state drive (SSD). In this case, the electronic system 8710 can stably store large amounts of data in the flash memory system.

[0106] The electronic system 8710 may further include an interface 8714 configured to transmit data to and receive data from a communication network. The interface 8714 may be of wired or wireless type. For example, the interface 8714 may include an antenna or a wired or wireless transceiver.

[0107] The electronic system 8710 can be implemented as a mobile system, personal computer, industrial computer, or logic system performing various functions. For example, a mobile system can be any of a personal digital assistant (PDA), portable computer, tablet computer, mobile phone, smartphone, wireless phone, laptop computer, memory card, digital music system, and information sending / receiving system.

[0108] If the electronic system 8710 is a device capable of performing wireless communication, then the electronic system 8710 can be used in a communication system by using technologies such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution), or Wibro (Wireless Broadband Internet).

[0109] The concept of the invention has been disclosed in conjunction with some embodiments described above. Those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of this disclosure. Therefore, the embodiments disclosed in this specification should be considered from an illustrative rather than a restrictive perspective. The scope of the inventive concept is not limited to the foregoing description but is defined by the appended claims, and all distinguishing features within the equivalent scope should be interpreted as being included within the inventive concept.

[0110] Cross-references to related applications

[0111] This application claims priority to Korean Application No. 10-2021-0137913, filed on October 15, 2021, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: First semiconductor substrate; as well as The second semiconductor substrate is directly bonded to the first semiconductor substrate. The first semiconductor substrate includes: First semiconductor substrate body; A first through-hole has an end protruding through a first top surface, which is the top surface of the first semiconductor substrate body; A liner formed at the interface between the first via and the first semiconductor substrate body and extending to partially expose the side surface of the end of the first via; and A first diffusion barrier layer covers the first top surface of the first semiconductor substrate body and the side surface of the end of the first via, and The liner includes a third top surface positioned lower than a second top surface, which is the top surface of the end of the first through hole, and the third top surface is positioned at a position equal to or higher than the first top surface. The first diffusion barrier layer extends to cover the third top surface of the liner.

2. The semiconductor device according to claim 1, wherein, The third top surface has a step difference from the first top surface to form a step shape.

3. The semiconductor device according to claim 1, wherein, The third top surface is an inclined surface.

4. The semiconductor device according to claim 1, wherein, The first diffusion barrier layer extends to cover the third top surface.

5. The semiconductor device according to claim 1, wherein, The liner includes a silicon oxide (SiO2) layer, and The first diffusion barrier layer includes a silicon nitride Si3N4 layer.

6. The semiconductor device according to claim 1, wherein, The first via penetrates the first semiconductor substrate body and the first diffusion barrier layer.

7. The semiconductor device according to claim 1, wherein, The first through hole includes: The through-hole body comprises copper (Cu); and A side barrier layer, comprising a tantalum Ta layer or a tantalum nitride TaN layer, covers the side surface of the via body.

8. The semiconductor device according to claim 1, wherein, The second semiconductor substrate includes: Including a conductive pad made of copper (Cu), which is directly bonded to the first through-hole; and The second diffusion barrier layer is directly bonded to the first diffusion barrier layer.

9. The semiconductor device according to claim 8, wherein, The conductive pad has a width that is wider than the first through hole.

10. The semiconductor device according to claim 8, wherein, The conductive pad has a width narrower than the first through hole.

11. The semiconductor device according to claim 8, wherein, The second diffusion barrier layer comprises a silicon nitride (Si3N4) layer.

12. The semiconductor device according to claim 8, wherein, The second semiconductor substrate also includes a second through-hole electrically connected to the conductive pad.

13. The semiconductor device according to claim 1, wherein, The second semiconductor substrate includes the same elements as the first semiconductor substrate.

14. A method for manufacturing a semiconductor device, the method comprising the following steps: A first through-hole surrounded by a liner is formed in the first semiconductor substrate body; The first semiconductor substrate body is first recessed to allow the end of the first through hole to protrude from the first top surface of the first recess of the first semiconductor substrate body while being covered by the liner; Remove a portion of the liner surrounding the end of the first through hole to expose a portion of the side surface and the second top surface of the end of the first through hole; The first top surface of the first semiconductor substrate body is recessed in the second direction; A first diffusion barrier layer is formed, which covers the second recessed first top surface of the first semiconductor substrate body and exposes the second top surface of the end of the first via. as well as The second semiconductor substrate is directly bonded to the second top surface of the end of the first diffusion barrier layer and the first via.

15. The method according to claim 14, wherein, The first top surface of the first semiconductor substrate body is recessed to a second depth, such that the liner includes a third top surface located at a height lower than the second top surface of the end of the first through hole and higher than the second recessed first top surface of the first semiconductor substrate body.

16. The method of claim 14, wherein, The first top surface of the first semiconductor substrate body is recessed to a second depth, such that the liner includes a third top surface located at a height that is lower than the second top surface of the end of the first through hole and equal to the height of the second recessed first top surface of the first semiconductor substrate body.

17. The method of claim 14, wherein, Perform removal of the portion of the liner surrounding the end of the first through hole, such that the liner includes a third top surface having an inclined surface.

18. The method according to claim 14, wherein, Remove the portion of the liner surrounding the end of the first through hole, which is associated with the recess between the first recessed top surface of the first semiconductor substrate body and the side surface of the end of the first through hole.

19. The method of claim 14, wherein, The steps for forming the first diffusion barrier layer include the following: Forming the first diffusion barrier layer to cover the second recessed first top surface of the first semiconductor substrate body and to cover the end of the first via; and Chemical mechanical polishing (CMP) is performed on the first diffusion barrier layer to expose the second top surface of the end of the first via.

20. The method of claim 14, wherein, The second semiconductor substrate includes: Including a conductive pad made of copper (Cu), which is directly bonded to the first through-hole; and The second diffusion barrier layer is directly bonded to the first diffusion barrier layer.

21. A semiconductor device comprising: First semiconductor substrate; as well as The second semiconductor substrate is directly bonded to the first semiconductor substrate. The first semiconductor substrate includes: First semiconductor substrate body; A first through-hole has an end protruding through a first top surface, which is the top surface of the first semiconductor substrate body; A liner disposed at the interface between the first through-hole and the first semiconductor substrate body and extending to partially expose the side surface of the end of the first through-hole; and A first diffusion barrier layer covers the first top surface of the semiconductor substrate body and the side surface of the end of the first via. The liner includes an inclined third top surface positioned lower than a second top surface, which is the top surface of the end of the first through-hole. The inclined third top surface includes a first edge portion located at a position higher than the first top surface of the first semiconductor substrate body and a second edge portion located at a position lower than the first top surface of the first semiconductor substrate body, opposite to the first edge portion.

22. The semiconductor device according to claim 21, wherein, The first edge portion of the inclined third top surface is positioned closer to the end of the first through hole than the second edge portion.

23. The semiconductor device according to claim 21, wherein, The second edge portion of the inclined third top surface forms a recess based on the step difference with the first top surface, and The first diffusion barrier layer extends to fill the recessed depression.

24. The semiconductor device according to claim 23, wherein, The second semiconductor substrate includes: Including a conductive pad made of copper (Cu), which is directly bonded to the first through-hole; and The second diffusion barrier layer is directly bonded to the first diffusion barrier layer.

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