Three-dimensional circuit structures and memory circuit structures having stepped contact configurations

Abstract

The present disclosure provides a three-dimensional circuit structure and memory circuit structure having a stepped contact configuration for improving manufacturing yield of complex 3D circuits. The circuit structure includes a first stack of conductors, a second stack of conductors, and a connection circuit. The first and second stacks of conductors each have an operational region and a contact region. The conductors of the first stack have a stepped arrangement in the contact region to provide an overlap region on the conductors. The connection circuit connects the overlap region of the conductive layers of the first stack to a through-stack conductor located in a via of the second stack to connect to circuitry located below the stack. The connection circuit includes an interlayer connection that contacts the overlap region of the first stack and extends to a patterned conductor located above the first and second stacks. The patterned conductor can include a link from the interlayer connection of the first stack to the through-stack conductor of the second stack. The circuit structure can include a plurality of structural vertical posts located in the contact region of the first stack.

Description

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 254,893, filed on October 12, 2021, which is incorporated herein by reference. Technical Field

[0002] This disclosure proposes a three-dimensional circuit structure and memory circuit structure for stacked conductors (e.g., word lines in a three-dimensional (3D) memory) with a stepped contact configuration. Background Technology

[0003] Integrated circuits are being fabricated using stacks of conductors to achieve higher density and interconnectivity. For example, in 3D memory, circuit structures with stacks of word lines comprising dozens, and in some cases more than 100 layers, are being developed.

[0004] Stacked circuit structures can be fragile, especially during certain stages of manufacturing. For example, one method for manufacturing 3D structures involves forming a stack of insulating and sacrificial layers, followed by etching the stack to shape the circuit structure and adding active components while retaining the sacrificial layer. At some stage of manufacturing, the sacrificial layer is removed and replaced with a conductive material. In some types of 3D memory, the conductive material used to replace the sacrificial layer can be configured as word lines, which serve as the gates of memory cells in the forming 3D memory array. Therefore, this process is sometimes referred to as gate replacement technology. During the stages where the sacrificial layer is removed and replaced, the circuit structure is very fragile, which can affect manufacturing yield.

[0005] In addition, the critical dimensions of these types of stacked circuit structures continue to shrink, which in turn affects the etch margin and layout margin of the structures being built.

[0006] It is desirable to provide techniques that can improve etch margin and placement margin in stacked circuit structures. Additionally, it is desirable to provide techniques for improving manufacturing yield in stacked circuit structures. Summary of the Invention

[0007] This disclosure proposes techniques for circuit structures that can improve manufacturing yield in complex 3D circuits. The circuit structure includes: a first stack of conductors having an operating region and a contact region, the conductors of the first stack being arranged in a stepped manner in the contact region to provide corresponding overlap areas on the conductors; a second stack of conductors, separate from the first stack, the second stack having an operating region and a contact region adjacent to the contact region of the first stack; and a connection circuit connecting the overlap region of the conductive layers in the first stack to a through-hole conductor in a via located in the contact region of the second stack, the through-hole conductor connecting to a circuit system located below the stack.

[0008] A circuit structure can be implemented comprising: a first array of vertical pillars and a second array of vertical pillars, the first array of which passes through the operating area of ​​a first stack (e.g., a memory area including memory cells), and the second array of which passes through the operating area of ​​a second stack. The connection circuit may include: a plurality of interlayer connectors located in the contact area of ​​the first stack, wherein the interlayer connectors contact corresponding overlap areas on conductors in the first stack and extend to patterned conductors located above the first and second stacks. Additionally, the patterned conductor may include connectors extending from the interlayer connectors located in the contact area of ​​the first stack to through-stack conductors located in the contact area of ​​the second stack.

[0009] A circuit structure may be implemented, the circuit structure including a plurality of structural vertical pillars located in the contact area of ​​the first stack.

[0010] The structural vertical pillars, one of which may be disposed in a through-hole having a first layout area, and the through-stacked conductors, one of which may be disposed in a through-hole having a second layout area, the second layout area being larger than the first layout area. In an example, the circuit structure may include two structural vertical pillars located in corresponding through-holes passing through the stack in the overlap region of a specific conductor in the first stack.

[0011] In an exemplary combination of features, the circuit structure may include: a first stack of conductors having an operating area and a contact area, the conductors of the first stack having a stepped arrangement in the contact area to provide corresponding overlap areas on the conductors; a second stack of conductors, separate from the first stack, the second stack having an operating area and a contact area adjacent to the contact area of ​​the first stack; a first array and a second array of vertical pillars, the first array of vertical pillars passing through the operating area of ​​the first stack, the second array of vertical pillars passing through the operating area of ​​the second stack, the vertical pillars in the first array and the vertical pillars in the second array including memory structures located in first vias having a first layout area; a plurality of interlayer connectors located in the contact area of ​​the first stack, the interlayer connectors of the plurality of interlayer connectors contacting corresponding overlap areas on the conductors of the first stack and extending to patterned conductors located above the first stack and the second stack; and a plurality of through-stack conductors located in the contact area of ​​the second stack, the through-stack conductors of the plurality of through-stack conductors extending from the patterned conductors located above the first stack and the second stack to circuitry located below the second stack. The patterned conductor in this exemplary combination includes an interlayer connector from one of the plurality of interlayer connectors located in the contact area of ​​the first stack to a through-stack conductor from one of the plurality of through-stack conductors located in the contact area of ​​the second stack.

[0012] In a dual-outlet configuration, this exemplary combination can be extended such that the second stack has a second contact area on a second side of the operating area of ​​the second stack, and the conductors of the second stack are arranged in a stepped manner in the second contact area to provide corresponding overlap areas on the conductors; and the first stack has a second contact area on a second side of the operating area of ​​the first stack, the second contact area of ​​the first stack being adjacent to the second contact area of ​​the second stack; the circuit structure further includes: a second plurality of interlayer connectors located in the second contact area of ​​the second stack, the interlayer connectors of the second plurality of interlayer connectors contacting corresponding overlap areas on the conductors of the second stack and extending to patterned conductors located above the first stack and the second stack; and a plurality of through-stack conductors located in the second contact area of ​​the first stack, the through-stack conductors of the plurality of through-stack conductors extending from the patterned conductors located above the first stack and the second stack to circuitry located below the first stack. The patterned conductors include connections from the interlayer connectors of the plurality of interlayer connectors located in the second contact area of ​​the second stack to the through-stack conductors of the plurality of through-stack conductors located in the second contact area of ​​the first stack.

[0013] Other aspects and advantages of this disclosure can be seen in the following drawings, detailed description and the scope of the claims. Attached Figure Description

[0014] Figure 1 This is a simplified block diagram of an integrated circuit memory device, which includes through-stack vias (TSVs) in the contact area of ​​the memory array for connection to circuitry located below the stack.

[0015] Figure 2A This includes devices that can be used in memory devices (such as...) Figure 1 A view of the circuit structure of the stacked conductors in the memory device shown.

[0016] Figure 2B and Figure 2C The circuit structure is shown (e.g.) Figure 2A The storage pillars and cell structure of the circuit shown.

[0017] Figure 2D Show storage units (such as) Figure 2B and Figure 2C The operation of the storage unit shown.

[0018] Figure 2E It is used for or related to the architecture memory, such as Figures 2A to 2C The diagram shows a schematic circuit of an array of memory cells implemented therein.

[0019] Figure 3 The layout diagram shows a portion of the memory structure, including the storage cell area and the ladder area.

[0020] Figure 4 It shows a first contact area and a second contact area. Figure 3 The diagram shows an unfolded layout, in which the second contact area is complementary to the first contact area.

[0021] Figure 5 It is cut along line 5-5 (along the second contact area of ​​STACK D). Figure 4 A cross-sectional view of the structure shown.

[0022] Figure 6 It is cut along line 6-6 (crossing the second contact area of ​​STACK D and the second contact area of ​​STACK C). Figure 4 A cross-sectional view of the structure shown.

[0023] Figure 7 The layout diagram illustrates a portion of a memory structure, which includes a storage cell area containing vertical NAND gate (NAND) strings and a ladder-like area.

[0024] Explanation of reference numerals in the attached figures

[0025] 5-5, 6-6, 115, 130, 175, 185, AA: Line

[0026] 100: Memory device

[0027] 101, 510, 611: Padding

[0028] 102: Memory Structure

[0029] 103: Array-based circuitry

[0030] 104: Text Line Layer

[0031] 106, 593: Insulation layer

[0032] 107, 108: Vertical conductors

[0033] 110: Patterned conductor

[0034] 111: Bias component power supply voltage circuit

[0035] 116: Data output line / cable

[0036] 119: Input / Output Interface

[0037] 120, 193: Dielectric layer

[0038] 140: Decoder / Driver

[0039] 145. WL, WL(i)m, WL(i)(m+1), WL(i+1)m, WL(i+1)(m+1): word line

[0040] 160: 3D Storage Array

[0041] 165: Data cable

[0042] 170: Line decoder

[0043] 180: Page Buffer

[0044] 190: Cache

[0045] 191a: Additional conductor layer / Underlying conductor layer

[0046] 191b, 191c: Additional conductor layer

[0047] 200: Storage column / column

[0048] 203: Arrow

[0049] 204: First vertical conductor / vertical conductor

[0050] 205: Second vertical conductor / vertical conductor

[0051] 208: Data Storage Structure

[0052] 209: Channel Layer

[0053] 211: Insulating filler layer

[0054] 215, 216, 521: Contact plugs

[0055] 217: Position line conductor

[0056] 218: Source wire conductor

[0057] 220, 220a, 220b, 220c: Storage units

[0058] 221a, 221b: Contact element S / D

[0059] 301, 311, 520, 530, 701, 711: Interlayer connectors

[0060] 302, 312, 612, 702, 712: Through-stack conductors

[0061] 303, 610, 703, TSV: Stacked perforations

[0062] 305, 306, 315, 316: Structural columns

[0063] 350, 351, 410, 750, 751: Patterned conductor layers

[0064] 360, 361, 660, 661, 662, 760, 761: Insulating trench

[0065] 370, 371, 770, 771: Storage columns

[0066] 375, 376, 775, 776: Columns

[0067] 378: High-density bit line

[0068] 401A, 401C, 402B, 402D: Word line contact area

[0069] 401B, 401D, 402A, 402C: TSV area

[0070] 501, 502, 705, 706, 715, 716: Structural columns

[0071] 504C-1, 504C-2, 504C-4~504C-N, 591a, 591b, 591c: Conductive layer

[0072] 504C-3: Conductive layer / layer

[0073] 504D-1: First conductive layer / conductive layer / layer

[0074] 504D-2: Second conductive layer / conductive layer / layer

[0075] 504D-3: Third conductive layer / conductive layer / layer

[0076] 504D-4~504D-N: Conductive layer / layer

[0077] 511: Floor

[0078] 512: Conductive core

[0079] 522, 532: Patterned conductors

[0080] 531: Contact plug / Conductive plug

[0081] 631: Conductive plug

[0082] 650: Stacked Under-Circuit System / Patterned Conductor Layer

[0083] 651: Under-Stack Circuitry / Active Components

[0084] 652, 653: Stacked circuit systems

[0085] 780, 781, 782, 783, 784: Interlayer conductors

[0086] BLn, BL(n+1): Bit lines

[0087] DMP, DTSV: Diameter

[0088] i: First stack

[0089] i+1: Second stack

[0090] SLn, SL(n+1): Source lines

[0091] STACK A, STACK C: Stacking of conductors

[0092] STACK B, STACK D: Stacking / Stacking of conductors

[0093] STEP 1, STEP 2, STEP 3, STEP 4: Ladder

[0094] X, Y, Z: Direction Detailed Implementation

[0095] Reference Figures 1 to 7Detailed descriptions of embodiments of the proposed technology are provided.

[0096] Figure 1 This is a simplified block diagram of an integrated circuit memory device 100 including a 3D memory array 160. While the technology described herein can be applied to various types of memory arrays, examples set forth in this disclosure include 3D flash memories configured with or in relation to an architecture. The memory device 100 includes peripheral circuitry supporting the 3D memory array 160. The peripheral circuitry includes a controller 110 (which includes logic circuitry, such as a state machine, etc.) for performing operations necessary for the device, including in some instances command decoding, read, erase, and program operations, input / output operations, address generation, memory management, etc. The peripheral circuitry includes a biasing arrangement supply voltages circuit 111, which generates and distributes bias and supply voltages throughout the integrated circuit for memory operations and other operations. Additionally, the input / output I / O interface 119 receives input data from off-chip and transmits the input data to on-chip resources on line 115, and receives output data from on-chip resources on line 116 and transmits the output data to off-chip.

[0097] In this example, an address is provided by controller 110 on line 130, which is assigned to row decoder 170 coupled to data line 165 from 3D memory array 160 and, in this example, to decoder / driver 140 for columns in 3D memory array 160 coupled to word line 145. Row decoder 170 is coupled to sense amplifier and page buffer 180 via line 175. In this example, sense amplifier and page buffer 180 is coupled to cache 190 via line 185. Cache 190 is coupled to data output line 116.

[0098] In the techniques described in this disclosure, at least some of the peripheral circuitry is implemented under a 3D memory array 160. This can be achieved, for example, using an array circuitry structure under a complementary metal-oxide-semiconductor (CMOS) architecture. In this block diagram, a decoder / driver 140 is implemented under the array. The 3D memory array 160 includes a memory structure comprising multiple stacks of conductors configured as word lines in the examples described below. To connect to the circuitry located under the 3D memory array 160, multiple stacked through-hole (TSV) vias are implemented in the contact areas of the memory structure.

[0099] Figures 2A to 2EThis illustrates a 3D memory structure suitable for use with architecture flash memory devices, which can be referenced above. Figure 1 To be implemented as described above.

[0100] Figure 2A It is a cross-section of a circuit structure including a stack of conductors configured as word lines. The stack of conductors includes memory regions in which memory pillars (e.g., 200) pass through the stack. In this example, memory pillar 200 includes a data storage structure 208, a channel layer 209, and a core. The core includes a first vertical conductor 204 configured as a source / drain line, a second vertical conductor 205 configured as a source / drain line, and a dielectric filler isolating the first and second vertical conductors.

[0101] The stacking of conductors is implemented in a circuit structure comprising alternating insulating layers 106 and word line layers 104. The alternating insulating layers 106 and word line layers 104 form a stack of conductors formed on a plurality of additional conductor layers 191a, 191b, 191c, which can be used to support various functions of the memory array, including delivering bias voltages, selecting transistor gates, etc.

[0102] A plurality of dielectric layers 120 are disposed on an alternating stack of insulating layers 106 and word line layers 104. At least upper sections of vertical conductors 204, 205 extend through at least some of the dielectric layers 120. Overlay patterned conductors are used for global bit lines, source lines, and other circuitry supporting memory operation.

[0103] Dielectric layer 193 is disposed below the stack and on top of the array-under-circuit system.

[0104] The conductors are stacked in a stepped configuration within the contact area, thereby forming an overlap region on each word line layer within the stack. At the overlap region, contact can be made using a vertical conductor (e.g., 107) extending from the overlap region of the corresponding conductor to the patterned conductor 110 overlying the array. Additionally, as shown, the vertical conductor 108 may connect to the underlying conductor layer (e.g., 191a) up to the overlying patterned conductor layer. The patterned conductor 110 extends to a peripheral circuitry system, which may be disposed beneath the stack, as described in the examples of this disclosure.

[0105] The schematically illustrated circuit structure includes an array under-circuit system 103 (including transistors and one or more patterned conductor layers) located on a substrate 101, which can provide at least some of the peripheral circuitry for the array.

[0106] Now refer to Figure 2B and Figure 2C The structure of the storage post 200 is described below. As described above, the structure disposed in the through-hole for forming the storage post 200 includes a first vertical conductor 204 located inside or on a first side of the vertical opening of the post 200, and a second vertical conductor 205 located inside or on a second side of the vertical opening of the post 200. The first vertical conductor 204 and the second vertical conductor 205 extend from the top of the vertical opening of the post 200 to the bottom of the vertical opening of the post 200, and are separated from each other by an insulating filler layer 211. Contact plugs 215 and 216 connect the vertical conductors 204 and 205 to the overlying bit line conductor 217 and source line conductor 218.

[0107] like Figure 2B and Figure 2C As shown, the structure disposed in the vertical opening of pillar 200 includes a data storage structure 208, such as a dielectric charge storage structure implemented using so-called silicon oxide nitride oxide silicon (SONOS), bandgap engineered SONOS (BE-SONOS), and related technologies. The data storage structure 208 extends in the Z direction within the vertical opening of pillar 200. The data storage structure 208 may include a multilayer dielectric having a tunneling layer, a charge trapping layer, and a blocking layer. The tunneling layer may comprise silicon oxide or a silicon oxide / silicon nitride combination (e.g., oxide / nitride / oxide or ONO). The charge trapping layer may comprise silicon nitride or other materials capable of trapping charges. The blocking layer may comprise silicon oxide, aluminum oxide, and / or a combination of such materials. As described above, the data storage structure 208 (tunneling layer / charge trapping layer / blocking layer) may have any different combinations of materials. In some instances, the data storage structure 208 can be implemented using a floating gate with a polysilicon charge trapping layer.

[0108] The memory cell 220 of memory structure 102 will be described. The memory cell 220 is located at the intersection (cross point) of the vertical opening in the pillar 200 and the word line layer 104. Figure 2C Shown in Figure 2B The storage cell 220 is shown in the cross-section taken at line AA. The storage cell 220 includes a word line layer 104, a channel layer 209, a first vertical conductor 204, and a second vertical conductor 205 surrounding the data storage structure 208. An insulating filler layer 211 is filled in the gaps surrounded by the channel layer 209, and the insulating filler layer 211 is not occupied by the first vertical conductor 204 and the second vertical conductor 205.

[0109] like Figure 2B and Figure 2CAs shown, channel layer 209 is disposed on the inner surface of data storage structure 208 around the periphery of the vertical opening in pillar 200. Channel layer 209 is located between data storage structure 208 and first vertical conductor 204. Additionally, channel layer 209 is located between data storage structure 208 and second vertical conductor 205. Channel layer 209 is located in the region between insulating fill layer 211 and data storage structure 208, around the periphery of the opening between first vertical conductor 204 and second vertical conductor 205. In this example, channel layer 209 is present at least at the layer level of word line layer 104. Channel layer 209 comprises a semiconductor layer, such as polysilicon, germanium, or silicon / germanium, for charge transport during operation of the memory cell.

[0110] like Figure 2B and Figure 2C As seen, word line layer 104 constitutes the gate in memory structure 102. Channel layer 209 has contacts S / D 221a with a first vertical conductor 204 located on a first side of the vertical opening in pillar 200, and contacts S / D 221b with a second vertical conductor 205 located on a second side of the vertical opening in pillar 200. Figure 2C As shown, at the connection between the channel layer 209 and the first vertical conductor 204 and the second vertical conductor 205, the contacts located on opposite sides of the pillar 200 serve as source / drain terminals of the storage cell 220.

[0111] like Figure 2C As shown, the channel region is located within the channel layer 209 of the storage cell 220. The channel region extends around the periphery of the vertical opening in the pillar 200. Arrow 203 indicates the current flow path within the channel region between the source / drain terminals (first vertical conductor 204 / second vertical conductor 205) at contacts S / D 221a and S / D 221b. Therefore, the storage cell 220 has a horizontal channel perpendicular to the direction of the vertical conductors 204, 205. In this configuration, the storage cells are arranged in a row along the Z direction of the vertical opening of the pillar 200. The storage cells in the same vertical opening of the pillar 200 are electrically connected in parallel between the first vertical conductor 204 and the second vertical conductor 205.

[0112] Reference Figure 2D This will explain the operations on the storage units. For example, in Figure 2D Three consecutive memory cells 220a, 220b, and 220c are shown and labeled, wherein these three consecutive memory cells 220a, 220b, and 220c are coupled in parallel between vertical conductors 204 and 205. It is assumed that memory cell 220b will be read during a read operation. The channel region of the channel layer 209 of the memory cell is horizontal, as shown for... Figure 2CAs discussed above, a read voltage is applied to the word line layer 104 of the selected memory cell 220b, while the channel regions of the unselected memory cells 220a and 220c are turned off. Depending on the data stored in the memory cell 220b, current can flow from the vertical conductor 205 through the channel region of the memory cell 220b to the vertical conductor 204 (the current path is shown with thick arrows in the figure), and this current can then be sensed during the read operation.

[0113] Figure 2E It is due to and Figures 2A to 2D The circuit diagram shows a memory array constructed using a memory structure similar to the one shown. Multiple bit lines (e.g., BLn and BL(n+1)) are disposed on and connected to the corresponding vertical conductors in the memory pillars. The word lines of the first stack i are implemented as horizontal conductors penetrated by the memory pillars. The word lines of the second stack i+1 are implemented as horizontal conductors penetrated by the memory pillars. The multiple bit lines are connected to... Figure 2E The multiple word lines (e.g., WL(i)m and WL(i)(m+1)) in the stack shown in the first X direction extend in a second direction (Y direction). The first X direction is also perpendicular to the Z direction in which the vertical conductors 204 and 205 extend. The multiple source lines extend in the second direction (Y direction) orthogonal to the multiple word lines (e.g., WL(i)m and WL(i)(m+1)) in the first direction (X direction).

[0114] Vertical conductors 204 and 205 in each memory pillar are coupled to the corresponding source line SLn and bit line BLn, source line SL(n+1) and bit line BL(n+1). At each layer, a separate word line WL (e.g., word line layer 104) is provided and penetrated by the plurality of memory pillars. Memory cells are located at the intersection of word lines and memory pillars.

[0115] For example, word lines WL(i)m and WL(i)(m+1) are stacked and alternately interleaved with insulating layers (not shown). A first memory cell is formed at the intersection of word line WL(i)m, source line SLn, and bit line BLn. A second memory cell is formed at the intersection of word line WL(i)(m+1), source line SLn, and bit line BLn. The first and second memory cells are coupled in parallel. A third memory cell is formed at the intersection of word line WL(i)m, source line SL(n+1), and bit line BL(n+1). A fourth memory cell is formed at the intersection of word line WL(i)(m+1), source line SL(n+1), and bit line BL(n+1). The third and fourth memory cells are coupled in parallel. Similarly, as... Figure 2E As shown, four memory cells are formed at the intersections of WL(i+1)m and WL(i+1)(m+1) with the corresponding source line and bit line.

[0116] The array-under-circuit system and stacked via technology described in this disclosure are applicable to reference... Figures 2A to 2E The memory structure is similar to the memory structure described above. Figures 3 to 6 Showing the application to and Figures 2A to 2E The embodiments shown are similar to those in memory structures. However, the under-array circuitry and stacked via techniques described in this disclosure can also be applied to other types of memory structures (for some examples, including vertical NAND gate structures and cross-point phase-change memory structures), and to non-circuits not used as memory.

[0117] Figure 3 The diagram illustrates a portion of a memory structure, including cell areas and contact areas. The portion shown includes a stack of four conductors labeled STACK A through STACK D. The stacks are separated by insulating channels (e.g., 360, 361). The stacks may be on the order of approximately 900 nanometers wide, separated by channels on the order of approximately 150 nanometers wide.

[0118] In this example, the memory cell area includes memory pillars as described above. In the stacked memory cell areas, each stack contains two columns of memory pillars (e.g., 375 and 376 in STACK C). The columns of memory pillars are arranged to allow for a greater pattern offset in the density of the overlying bit lines and source lines.

[0119] The contact area includes a stepped structure, which in this example provides an overlap area for each conductive layer configured as a word line. Figure 3 The diagram shows four steps, STEP 1 to STEP 4, but the structure may include N steps, one step for each word line layer. The overlap area is the exposed surface of the conductive layer in the corresponding step.

[0120] In STACK A and STACK C, interlayer connectors (e.g., 301, 311 in STACK A) are provided in each corresponding step, contacting the overlap area of ​​the corresponding conductive layer exposed at the step, and extending to the overlying patterned conductive layer (e.g., 350, 351). In alternating stacks (STACK B and STACK D), stack vias (e.g., 303) are provided through each corresponding step, and include through-stack conductors (e.g., 302, 312 in STACK B) extending from the circuitry located below the stack to the overlying patterned conductive layer (e.g., 350, 351).

[0121] Storage pillars (e.g., 370, 371) are formed in first vias through the stack having a first layout area. The stack via 303 has a second layout area larger than the first layout area. Utilizing a larger second layout area for the stack via provides greater alignment margin and an expanded etching process window during manufacturing for forming through-stack conductors 302, 312 within the stack via.

[0122] In the layout shown, interlayer connectors (e.g., 301, 311) that contact the overlap pads on the conductive layer are arranged in two columns that are substantially aligned with the columns of memory pillars in the memory cell area. Thus, interlayer connector 301 is aligned with the lower column of memory pillars in the same stack, and interlayer connector 311 is aligned with the upper column of memory pillars in the same stack.

[0123] Additionally, structural columns (e.g., 305, 306 in STACK A) are arranged through the overlap area on each layer in a column that is substantially aligned with the column of memory columns in the memory cell area, and in a pattern opposite to that of the interlayer connectors 301, 311. Therefore, each overlap area in STACK A and STACK C includes an interlayer connector (e.g., 301) and two structural columns (e.g., 305, 306). Structural columns 305, 306 may have the same layout area as memory columns 370, 371. In the illustrated example, structural pillars 305 and 306 are symmetrically arranged on opposite sides of a line drawn perpendicular to the long axis of the stack from the center of the interlayer connector 301. The interlayer connector 301 on the first side of the overlap region is aligned with the lower column of the memory pillars, and structural pillars 315 and 316 are symmetrically arranged on opposite sides of a line drawn perpendicular to the long axis of the stack from the center of the interlayer connector 311. The interlayer connector 311 on the second side of the overlap region is aligned with the upper column of the memory pillars. This symmetry in the layout contributes to the stability of the structure during the gate replacement process. The proposed technique provides a symmetrical layout of structural pillars in the overlap region of a stepped contact structure with interlayer conductors as described herein. This can be applied independently of a layout using stacked vias in adjacent stacks, or in combination with a layout using stacked vias in adjacent stacks.

[0124] In gate replacement manufacturing technology, stacked vias, vias for structural pillars 305 and 306, and vias for memory pillars 370 and 371 can be fabricated when stacking alternating sacrificial and insulating layers. Furthermore, the stacked vias, vias for structural pillars 305 and 306, and vias for memory pillars 370 and 371 can be fabricated in a process that shares a step masking, etching, and filling step. After the step masking, etching, and filling, structural pillars 305 and 306 and the stacked via 303 can be filled with material to form pillars isolated from the gate replacement process and to provide structural support during the process. The formation of interlayer interconnects (e.g., 301) and through-stack conductors (e.g., 302) in the stacked vias can be performed after refilling the voids left by the removal of sacrificial material using word line material.

[0125] Therefore, after removing the sacrificial material and refilling the voids in the structure with conductive material, the stacked vias and through-holes for the structural pillars and memory pillars provide structural support. Thus, the structural features described in this disclosure, both individually and in combination, can reduce structural fragility and improve manufacturing yield during gate replacement processes.

[0126] In the illustrated layout, a first stack of conductors having a memory cell area (or other form of operating area in other embodiments) and a contact area is arranged such that the first stack has a stepped arrangement in the contact area to provide corresponding overlap areas on the conductors. A second stack of conductors is separated from the first stack and has a memory cell area (or other form of operating area) and a contact area adjacent to the contact area of ​​the first stack. A connection circuit is provided that connects the overlap area of ​​the conductive layer in the first stack to a through-hole conductor in a via located in the contact area of ​​the second stack, wherein the through-hole conductor connects to a circuit system located below the stack.

[0127] For additional structural support, the first stack includes structural pillars, and in this case, each overlap region includes two structural pillars, having the same layout area as the memory pillars. The structural pillars do not provide circuitry functionality, but rather support the first stack, for example, during manufacturing using a gate replacement process.

[0128] Figure 4 It shows a first contact area and a second contact area. Figure 3 The diagram shows an unfolded layout, where the second contact area is complementary to the first contact area. (See attached diagram.) Figure 4As seen, STACK B and STACK D have enlarged stacking vias and through-stack conductors in the overlap area of ​​the first contact area (see TSV areas 401B and 401D) for connecting the interlayer connections in the contact areas (word line contact areas 401A and 401C) of STACK A and STACK C to the circuitry located below the stack. In the second contact area, the layout is complementary, such that STACK A and STACK C have enlarged stacking vias and through-stack conductors in the overlap area of ​​the second contact area (e.g., TSV areas 402A and 402C) for connecting the interlayer connections in the contact areas (word line contact areas 402B and 402D) of STACK B and STACK D to the circuitry located below the stack. Similarly... Figure 4 As seen, the high-density bit line 378 covers the memory cell area and contacts the vertical conductor in the memory column.

[0129] Figure 4 The diagram shows that the diameter DTSV of the stacked vias used in the contact area is larger than the diameter DMP of the memory pillar vias. In this example, the diameter DTSV is approximately twice the diameter DMP, and therefore has a much larger layout area, thereby providing the increased alignment margin and the increased etching process window described above for forming through-stack conductors inside the stacked vias.

[0130] like Figure 4 As shown, word lines of adjacent stacks have exits to the surrounding circuitry on opposite sides of the array, a dual-exit layout. This dual-exit layout alleviates layout constraints on connection circuitry, including connections to through-stack conductors in adjacent stacks.

[0131] Figure 5 and Figure 6 These are cuts taken along line 5-5 (the second contact area of ​​STACK D) and line 6-6 (between the second contact area of ​​STACK D and the second contact area of ​​STACK C), respectively. Figure 4 A cross-sectional view of the structure shown.

[0132] Figure 5 This is a cross-section of a portion of the contact area of ​​STACK D. The circuit structure includes multiple conductive layers 504D-1 to 504D-N, which are configured to interact with... Figure 4The memory structure shown is similar to the word lines in a memory structure. In this example, conductive layers 591a to 591c are disposed beneath layers 504D-1 to 504D-N, which are configured as word lines. An underlying insulating layer 593 covers a patterned conductor layer 410, which is part of the circuit system located beneath the stack. Besides the patterned conductor layer 410, active components, such as transistors, may or may not be present beneath a particular stack in the array. Figure 5 In this cross-section, a first overlapping area on the first conductive layer 504D-1 is contacted by an interlayer connector 520, which extends upward to a contact plug 521 and then to an overlying patterned conductor 522. A second overlapping area on the third conductive layer 504D-3 is contacted by an interlayer connector 530, which extends upward to a contact plug 531 and then to an overlying patterned conductor 532. In this cross-section, structural pillars 501 and 502 are disposed between the overlapping areas on the first conductive layer 504D-1 and the overlapping areas on the third conductive layer 504D-3, passing through the overlapping area on the second conductive layer 504D-2. An interlayer conductor for the second conductive layer 504D-2 may be disposed on the opposite side of the memory region in the first contact area shown in this figure.

[0133] Structural pillars 501 and 502 may include pads 510 formed during the fabrication of the memory pillars, including, for example, layers of semiconductor material for forming channel layers in the memory pillars, layers of memory material for forming memory material layers in the memory pillars, or both. Additionally, structural pillars 501 and 502 may fill the space within pads 510, such that structural pillars 501 and 502 form a stable structure during gate replacement processes used to fabricate the stack. In this example, a conductive core 512 is shown within structural pillars 501 and 502, which may be formed during the fabrication of the memory pillars. However, the conductive core 512 extends into the insulating layer 593 of the circuit structure and does not perform any circuit function. Layer 511 may be a material used as an etch stop layer, deposited prior to the formation of the stack.

[0134] Figure 6 This is a cross-section spanning the second contact area of ​​STACK D and STACK C, with insulating channels 660, 661, and 662 on the stacked sides. Conductive layers 504D-1 and 504D-2 are shown with shallower boundaries to indicate that conductive layers 504D-1 and 504D-2 are recessed in this illustration, which shows a cross-section through the overlap area on the third conductive layer 504D-3. The interlayer connector 530 extends upward from the overlap area on the third conductive layer 504D-3 to the conductive plug 531 and upward to the patterned conductor 532.

[0135] The adjacent STACK C includes multiple conductive layers 504C-1 to 504C-N. A stacked via 610 is provided through the overlap region of layer 504C-3. A through-stack conductor 612 is disposed within the stacked via 610 and extends from the circuitry located below the stack, including a patterned conductor layer 650 and transistors or other active components 651. The circuitry located below the stack can be used to form the peripheral circuitry of the memory array. The stacked via 610 may be filled with a structure including a pad 611 formed during the fabrication of the memory pillar, including, for example, a layer of semiconductor material for forming a channel layer in the memory pillar, a layer of memory material for forming a memory material layer in the memory pillar, or both. Additionally, the stacked via 610 may be filled within the pad 611 such that the pad 611 forms a stable structure during fabrication (e.g., during a gate replacement process used in the fabrication of the stack). A conductive core provides a vertical through-stack conductor 612 within the stacked via 610, which can be formed after a gate replacement process within the enlarged stacked via, utilizing a larger alignment and etching process window. The through-stack conductor 612 is connected to the patterned conductor 532 via the conductive plug 631, thereby connecting the third conductive layer 504D-3 to the circuit system (650, 651, 652, 653) under the stack.

[0136] Figure 7 by Figure 3 The layout diagram shown illustrates a portion of an alternative memory structure containing NAND gate memory operation areas. Therefore, as shown, the structure includes memory cell areas with vertical NAND gate strings and contact areas. The portion shown includes a stack of four conductors labeled STACK A through STACK D. The stacks are separated by insulating channels (e.g., 760, 761).

[0137] In this example, the memory cell region includes memory pillars configured to serve as NAND gate strings, one example of which is described in U.S. Patent No. 10,644,018 ("3D Memory Having Pluginal Lower Select Gates") by Lee et al., published May 5, 2020, which is incorporated herein by reference as fully stated in this disclosure. In the illustrated NAND gate string structure, the memory pillars include vertical channels, and each pillar contacts the vertical channel to connect to a bit line. Figure 3 In the example shown, within the stacked memory cell area, there are two columns of memory pillars in each stack (e.g., 775 and 776 in STACK C). The columns of memory pillars are arranged to allow for a greater pattern offset in the density of the overlying bit lines and source lines.

[0138] The contact area includes a stepped structure, which in this example provides an overlap area for each conductive layer configured as a word line. Figure 7 The diagram shows four steps, STEP 1 to STEP 4, but the structure may include N steps, one step for each word line layer. The overlap area is the exposed surface of the conductive layer in the corresponding step.

[0139] In STACK A and STACK C, interlayer connectors (e.g., 701, 711 in STACK A) are disposed in each corresponding step, contacting the overlap area of ​​the corresponding conductive layer exposed at the step, and extending to the overlying patterned conductor layer (e.g., 750, 751). In alternating stacks (STACK B and STACK D), stack vias (e.g., 703) are disposed through each corresponding step and include through-stack conductors (e.g., 702, 712 in STACK B) extending from the circuitry located below the stack to the overlying patterned conductor layer (e.g., 750, 751). In the illustrated NAND gate structure, interlayer conductors 780, 781, 782, 783, and 784 are disposed in vias located in the slots between the stacks and connected to the underlying shared source line for the NAND gate circuitry.

[0140] Storage pillars (e.g., 770, 771) are formed in first vias through the stack having a first layout area. The stack via 703 has a second layout area larger than the first layout area. Utilizing a larger second layout area for the stack via provides greater alignment margin and an expanded etching process window during manufacturing for forming through-stack conductors 702, 712 within the stack via.

[0141] In the layout shown, interlayer connectors (e.g., 701, 711) that contact the overlap pads on the conductive layer are arranged in two columns that are substantially aligned with the columns of memory pillars in the memory cell area. Thus, interlayer connector 701 is aligned with the lower column of memory pillars in the same stack, and interlayer connector 711 is aligned with the upper column of memory pillars in the same stack.

[0142] Additionally, structural columns (e.g., 705, 706 in STACK A) are arranged through the overlap area on each layer in a column that is substantially aligned with the column of memory columns in the memory cell area, and in a pattern opposite to that of the interlayer connectors 701, 711. Therefore, each overlap area in STACK A and STACK C includes an interlayer connector (e.g., 701) and two structural columns (e.g., 705, 706). Structural columns 705, 706 may have the same layout area as memory columns 770, 771. In the illustrated example, structural pillars 705 and 706 are symmetrically arranged on opposite sides of a line drawn perpendicular to the long axis of the stack from the center of the interlayer connector 701. The interlayer connector 701 on the first side of the overlap region is aligned with the lower column of the memory pillars, and structural pillars 715 and 716 are symmetrically arranged on opposite sides of a line drawn perpendicular to the long axis of the stack from the center of the interlayer connector 711. The interlayer connector 711 on the second side of the overlap region is aligned with the upper column of the memory pillars. This symmetry in the layout contributes to the stability of the structure during the gate replacement process. The proposed technique provides a symmetrical layout of structural pillars in the overlap region of a stepped contact structure with interlayer conductors as described herein. This can be applied independently of a layout using stacked vias in adjacent stacks, or in combination with a layout using stacked vias in adjacent stacks.

[0143] In gate replacement manufacturing technology, when stacking alternating sacrificial and insulating layers, stacked vias, vias for structural pillars 705 and 706, vias for interlayer conductors 780 to 784, and vias for memory pillars 770 and 771 can be fabricated. Furthermore, the stacked vias, vias for structural pillars 705 and 706, vias for interlayer conductors 780 to 784, and vias for memory pillars 770 and 771 can be fabricated in a process that shares masking, etching, and filling of the steps. After masking, etching, and filling the steps, structural pillars 705 and 706 and the stacked via 703 can be filled with material to form pillars isolated from the gate replacement process and to provide structural support during the process. The formation of interlayer interconnects (e.g., 701) and through-stacking conductors (e.g., 702) in the stacked vias can be performed after refilling the voids left by the removal of sacrificial material using word line material.

[0144] Therefore, after removing the sacrificial material and refilling the voids in the structure with conductive material, the stacked vias and through-holes for the structural pillars and memory pillars provide structural support. Thus, the structural features described in this disclosure, both individually and in combination, can reduce structural fragility and improve manufacturing yield during gate replacement processes.

[0145] In the illustrated layout, a first stack of conductors having a memory cell area (or other form of operating area in other embodiments) and a contact area is arranged such that the first stack has a stepped arrangement in the contact area to provide corresponding overlap areas on the conductors. A second stack of conductors is separated from the first stack and has a memory cell area (or other form of operating area) and a contact area adjacent to the contact area of ​​the first stack. A connection circuit is provided that connects the overlap area of ​​the conductive layer in the first stack to a through-hole conductor in a via located in the contact area of ​​the second stack, wherein the through-hole conductor connects to a circuit system located below the stack.

[0146] For additional structural support, the first stack includes structural pillars, and in this case, each overlap region includes two structural pillars, having the same layout area as the memory pillars. The structural pillars do not provide circuitry functionality, but rather support the first stack, for example, during manufacturing using a gate replacement process.

[0147] A technique is proposed to provide a circuit structure that improves the manufacturing yield of complex circuits, such as 3D memories. The circuit structure can improve stability during processes such as gate replacement manufacturing. It can prevent [problems] in [the context of]... Figure 4 In structures similar to the one shown, STACK A through STACK D tilts after the removal of sacrificial material used in the manufacturing process. The technology provides a bridge for connecting conductors, such as word lines, in the stepped contact areas of a 3D structure to stacked vias for connecting to a circuit system located beneath the stack. The circuit structure includes enlarged stacked vias, which improves the etching process window and alignment window during manufacturing. The circuit structure includes an alternating layout of interlayer connections for contact pads and through-stack connections in the stack of adjacent conductors. This improves the layout and density of the overlay conductors required in this type of circuit.

[0148] Although the present invention has been disclosed with reference to preferred embodiments and the examples described in detail above, it should be understood that these examples are intended to be illustrative and not restrictive. Modifications and combinations will readily occur to those skilled in the art, and such modifications and combinations will fall within the spirit and scope of the invention and the claims.

Claims

1. A circuit structure, comprising: A first stack of conductors has an operating area and a contact area, wherein the conductors of the first stack are arranged in a stepped manner in the contact area to provide corresponding overlap areas on the conductors; A second stack of conductors, separate from the first stack, the second stack having an operating area and a contact area adjacent to the contact area of ​​the first stack; as well as A connection circuit is formed to connect the overlapping area of ​​the conductive layer in the first stack to a through-hole in the contact area of ​​the second stack of the conductors, and the through-hole in the second stack of the conductors is connected to a circuit system located below the first stack and the second stack.

2. The circuit structure according to claim 1, comprising: A first array of vertical pillars and a second array of vertical pillars, the first array passing through the operating area of ​​the first stack, the second array passing through the operating area of ​​the second stack, and wherein the connection circuitry includes: A plurality of interlayer connectors are located in the contact area of ​​the first stack, wherein one of the plurality of interlayer connectors contacts a corresponding overlap area on a conductor in the first stack and extends to a patterned conductor located above the first stack and the second stack; and The patterned conductor includes an interlayer connector from one of the plurality of interlayer connectors located in the contact area of ​​the first stack to a through-stack conductor located in the contact area of ​​the second stack.

3. The circuit structure according to claim 1, comprising a plurality of structural pillars, wherein the plurality of structural pillars are located in the contact area of ​​the first stack.

4. The circuit structure according to claim 3, wherein the structural pillars of the plurality of structural pillars are disposed in a through hole having a first layout area, and the through stacked conductors are disposed in a through hole having a second layout area, wherein the second layout area is greater than the first layout area.

5. The circuit structure according to claim 1, comprising two structural pillars located in corresponding through-holes of the first stack in the overlapping region of the first stack.

6. A circuit structure, comprising: A first stack of conductors has an operating area and a contact area, wherein the conductors of the first stack are arranged in a stepped manner in the contact area to provide corresponding overlap areas on the conductors; A second stack of conductors, separate from the first stack, the second stack having an operating area and a contact area adjacent to the contact area of ​​the first stack; A first array of vertical pillars and a second array of vertical pillars, the first array passing through the operating area of ​​the first stack and the second array passing through the operating area of ​​the second stack, wherein the vertical pillars in the first array and the second array include memory structures located in first vias having a first layout area; Multiple interlayer connectors are located in the contact area of ​​the first stack, and the interlayer connectors of the multiple interlayer connectors contact the corresponding overlapping area on the conductor in the first stack and extend to the patterned conductor located on the first stack and the second stack. Multiple through-stacked conductors are formed in the contact area of ​​the second stack of the conductors, and the through-stacked conductors formed in the second stack of the conductors extend from the patterned conductors located above the first stack and the second stack to the circuit located below the second stack; as well as The patterned conductor includes a connector from an interlayer connector in the contact area of ​​the first stack to a through-stack conductor in the contact area of ​​the second stack.

7. The circuit structure according to claim 6, comprising a plurality of structural pillars disposed in a second through-hole having the first layout area in the contact area of ​​the first stack.

8. The circuit structure according to claim 6, wherein the through-stacked conductor of the plurality of through-stacked conductors is disposed in a third via having a second layout area, the second layout area being larger than the first layout area.

9. The circuit structure of claim 6, wherein the second stack has a second contact area on a second side of the operating area of ​​the second stack, and the conductors of the second stack have a stepped arrangement in the second contact area to provide corresponding overlap areas on the conductors; Furthermore, the first stack has a second contact area on the second side of the operating area of ​​the first stack, and the second contact area of ​​the first stack is adjacent to the second contact area of ​​the second stack; The circuit structure also includes: The second plurality of interlayer connectors are located in the second contact area of ​​the second stack, and the interlayer connectors of the second plurality of interlayer connectors contact the corresponding overlapping area on the conductor in the second stack and extend to the patterned conductor located on the first stack and the second stack. A second plurality of through-stacked conductors are located in the second contact area of ​​the first stack, the through-stacked conductors extending from the patterned conductors located above the first stack and the second stack to the circuit located below the first stack; and The patterned conductor includes an interlayer connector from the plurality of interlayer connectors located in the second contact area of ​​the second stack to a through-stack conductor from the plurality of through-stack conductors located in the second contact area of ​​the first stack.

10. The circuit structure of claim 6, comprising two structural pillars located in corresponding second vias through the first stack in the overlapping region of the first stack, the second vias having the first layout area.

11. The circuit structure of claim 6, wherein the memory structures in the first array and the second array of vertical pillars respectively include a first vertical conductor, a second vertical conductor, and a channel structure located between the first vertical conductor and the second vertical conductor to form a memory cell, wherein the conductors in the first stack and the second stack are configured as word lines.

12. The circuit structure of claim 6, wherein the memory structures in the first array and the second array of vertical pillars respectively include a first vertical NAND gate string and a second vertical NAND gate string to form a memory cell, wherein the conductors in the first stack and the second stack are configured as word lines.

13. A memory circuit structure, comprising: A first stack of conductors has a memory area and a first word line contact area, wherein the conductors of the first stack include word line conductors having a stepped arrangement in the first word line contact area to provide corresponding overlap areas on the conductors; A second stack of conductors, separate from the first stack, the second stack having a memory region and a second through-stack contact region adjacent to the first word line contact region of the first stack, and the conductors of the second stack including word line conductors; A first array and a second array of vertical pillars, the first array passing through the memory region of the first stack, the second array passing through the memory region of the second stack, the vertical pillars in the first array and the second array comprising memory structures located in first vias having a first layout area; Multiple interlayer connectors are located in the first word line contact area of ​​the first stack, and the interlayer connectors of the multiple interlayer connectors contact the corresponding overlapping area on the word line conductor in the first stack and extend to the patterned conductor located on the first stack and the second stack. Multiple through-stack conductors are formed in the second through-stack contact area of ​​the second stack of the conductors, and the through-stack conductors formed in the second stack of the conductors extend from the patterned conductors located above the first stack and the second stack to the circuit located below the second stack; as well as The patterned conductor includes a connector from an interlayer connector in the first word line contact area of ​​the first stack to a through-stack conductor in the second through-stack contact area of ​​the second stack.

14. The memory circuit structure according to claim 13, comprising a plurality of structural pillars, wherein the plurality of structural pillars are disposed in a second via having the first layout area in the first word line contact area of ​​the first stack.

15. The memory circuit structure according to claim 13, wherein the through-stack conductor of the plurality of through-stack conductors in the second through-stack contact area is disposed in a third via having a second layout area, the second layout area being larger than the first layout area.

16. The memory circuit structure of claim 13, wherein the second stack has a second word line contact area on a second side of the memory region of the second stack, and the conductors of the second stack have a stepped arrangement in the second word line contact area to provide corresponding overlap areas on the conductors; Furthermore, the first stack has a first through-stack contact area on the second side of the memory region of the first stack, and the first through-stack contact area of ​​the first stack is adjacent to the second word line contact area of ​​the second stack; The memory circuit structure also includes: The second plurality of interlayer connectors are located in the second word line contact area of ​​the second stack, and the interlayer connectors of the second plurality of interlayer connectors contact the corresponding overlapping area on the conductor in the second stack and extend to the patterned conductor located on the first stack and the second stack. A second plurality of through-stack conductors are located in the first through-stack contact area of ​​the first stack, the through-stack conductors extending from the patterned conductors located above the first stack and the second stack to the circuit located below the first stack; and The patterned conductor includes a connector from an interlayer connector in a second plurality of interlayer connectors located in the second word line contact area of ​​the second stack to a through stack conductor in a plurality of through stack conductors located in the first through stack contact area of ​​the first stack.

17. The memory circuit structure of claim 13, comprising two structural pillars located in corresponding second vias passing through the first stack in the overlapping region of the first stack, the second vias having the first layout area.

18. The memory circuit structure of claim 13, wherein the memory structures in the first array and the second array of vertical pillars respectively include a first vertical conductor, a second vertical conductor, and a channel structure located between the first vertical conductor and the second vertical conductor to form a memory cell, wherein the conductors in the first stack and the second stack are configured as word lines.

19. The memory circuit structure of claim 13, wherein the memory structures in the first array and the second array of vertical pillars respectively include a first vertical NAND gate string and a second vertical NAND gate string to form a memory cell, wherein the conductors in the first stack and the second stack are configured as word lines.

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