Electrostatic protection device and chip

Abstract

The application provides an electrostatic protection device and a chip, and belongs to the field of integrated circuits.The electrostatic protection device comprises a power supply end, a grounding end, a first clamping circuit and a first parasitic resistance; the base of a parasitic transistor in the first clamping circuit is connected with the first end of the first parasitic resistance; the first N-type diffusion area of a P-type field effect transistor in the first clamping circuit is connected with the second end of the first parasitic resistance; the first parasitic resistance reduces the voltage of an N-type field effect transistor of an inverter in the first clamping circuit when passing through current, and discharges electrostatic current through the N-type field effect transistor of the inverter in the first clamping circuit, reduces the on-voltage of the parasitic transistor when passing through current, and discharges electrostatic current. The electrostatic protection device can discharge electrostatic current through the P-type field effect transistor and the parasitic transistor at the same time, and improves the electrostatic protection effect.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an electrostatic discharge protection device and chip. Background Technology

[0002] Electrostatic discharge (ESD) can severely damage IC (Integrated Circuit) chips, impairing performance, significantly reducing yield, and causing economic losses. Taking static electricity generated during chip manufacturing as an example, ESD can damage chip components, rendering the chip inoperable; the noise from ESD can cause malfunctions or breakdowns in chip manufacturing equipment; and damage can also occur during assembly and long-distance transportation. Therefore, how to protect IC chips from ESD is a problem that needs to be solved.

[0003] Currently, electrostatic discharge (ESD) protection is typically achieved by using an ESD clamp circuit that includes a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and its parasitic BJT (Bipolar Junction Transistor).

[0004] The problem with the above technical solution is that the MOS channel has a weak ability to discharge electrostatic current, resulting in poor electrostatic protection. On the other hand, the parasitic BJT has a high turn-on voltage, which may damage the core circuit of the IC chip, resulting in poor electrostatic protection. Summary of the Invention

[0005] This application provides an electrostatic discharge (ESD) protection device and chip, enabling the parasitic transistor to turn on and conduct in advance, thereby discharging electrostatic current together with the P-type field-effect transistor and improving the ESD protection effect. The technical solution is as follows:

[0006] On the one hand, an electrostatic discharge protection device is provided, the electrostatic discharge protection device comprising: a power supply terminal (A1), a grounding terminal (A2), a first clamping circuit (10) and a first parasitic resistor (20);

[0007] The base of the parasitic transistor (11) in the first clamping circuit (10) is connected to the first end of the first parasitic resistor (20). The parasitic transistor (11) is used to discharge electrostatic current when the turn-on voltage is reached.

[0008] In the first clamping circuit (10), the first N-type diffusion region of the P-type field-effect transistor (12) is connected to the second end of the first parasitic resistor (20). The P-type field-effect transistor (12) includes a gate, a source, a drain, a second N-type diffusion region, and the first N-type diffusion region, which is used to discharge electrostatic current through the channel between the source and the drain.

[0009] The first parasitic resistor (20) reduces the voltage of the N-type field-effect transistor of the inverter (13) in the first clamping circuit (10) when current flows through it, and discharges the electrostatic current through the N-type field-effect transistor of the inverter (13) in the first clamping circuit (10). It also reduces the conduction voltage of the parasitic transistor (11) and discharges the electrostatic current when current flows through it.

[0010] In some embodiments, the source of the P-type field-effect transistor (12) is connected to the power supply terminal (A1) and the emitter of the parasitic transistor (11);

[0011] The drain of the P-type field-effect transistor (12) is connected to the ground terminal (A2) and the collector of the parasitic transistor (11);

[0012] The gate of the P-type field-effect transistor (12) is connected to the output terminal of the inverter (13) in the first clamping circuit (10), and the inverter (13) is used to reverse the phase of the input current signal;

[0013] The second N-type diffusion region of the P-type field-effect transistor (12) is connected to the power supply terminal (A1) and the first end of the second parasitic resistor (14) in the first clamping circuit (10), and the second end of the second parasitic resistor (14) is connected to the base of the parasitic transistor (11).

[0014] The first N-type diffusion region of the P-type field-effect transistor (12) is connected to the output terminal of the inverter (13) in the first clamping circuit (10).

[0015] In some embodiments, the first clamping circuit (10) further includes a first trigger resistor (15) and a first capacitor (16);

[0016] The first end of the first trigger resistor (15) is connected to the ground terminal (A2), and the second end of the first trigger resistor (15) is connected to the input terminal of the inverter (13);

[0017] The first end of the first capacitor (16) is connected to the power supply terminal (A1), and the second end of the first capacitor (16) is connected to the input terminal of the inverter (13).

[0018] In some embodiments, the inverter (13) includes a P-type field-effect transistor (131) and an N-type field-effect transistor (132);

[0019] The source of the P-type field-effect transistor (131) is connected to the power supply terminal (A1);

[0020] The gates of the P-type field-effect transistor (131) and the N-type field-effect transistor (132) are connected to the input terminal of the inverter (13);

[0021] The drain of the P-type field-effect transistor (131) and the drain of the N-type field-effect transistor (132) are connected to the output terminal of the inverter (13);

[0022] The source of the N-type field-effect transistor (132) is connected to the ground terminal (A2).

[0023] On the other hand, an electrostatic discharge protection device is provided, which includes: a power supply terminal (A3), a grounding terminal (A4), a second clamping circuit (30), and a third parasitic resistor (40);

[0024] The base of the parasitic transistor (31) in the second clamping circuit (30) is connected to the first end of the third parasitic resistor (40). The parasitic transistor (31) is used to discharge electrostatic current when the turn-on voltage is reached.

[0025] In the second clamping circuit (30), the first P-type diffusion region of the N-type field-effect transistor (32) is connected to the second end of the third parasitic resistor (40). The N-type field-effect transistor (32) includes a gate, a source, a drain, a second P-type diffusion region, and the first P-type diffusion region, which is used to discharge electrostatic current through the channel between the source and the drain.

[0026] The third parasitic resistor (40) reduces the voltage of the N-type field-effect transistor of the inverter (33) in the second clamping circuit (30) when current flows through it, and discharges the electrostatic current through the N-type field-effect transistor of the inverter (33) in the second clamping circuit (30). It also reduces the conduction voltage of the parasitic transistor (31) and discharges the electrostatic current when current flows through it.

[0027] In some embodiments, the source of the N-type field-effect transistor (32) is connected to the ground terminal (A4) and the emitter of the parasitic transistor (31);

[0028] The drain of the N-type field-effect transistor (32) is connected to the power supply terminal (A3) and the collector of the parasitic transistor (31);

[0029] The gate of the N-type field-effect transistor (32) is connected to the output terminal of the inverter (33) in the second clamping circuit (30), and the inverter (33) is used to reverse the phase of the input current signal;

[0030] The second P-type diffusion region of the N-type field-effect transistor (32) is connected to the ground terminal (A4) and the first end of the fourth parasitic resistor (34) in the second clamping circuit (30), and the second end of the fourth parasitic resistor (34) is connected to the base of the parasitic transistor (31).

[0031] The first P-type diffusion region of the N-type field-effect transistor (32) is connected to the output terminal of the inverter (33) in the second clamping circuit (30).

[0032] In some embodiments, the second clamping circuit (30) further includes a second trigger resistor (35) and a second capacitor (36);

[0033] The first end of the second trigger resistor (35) is connected to the power supply terminal (A3), and the second end of the second trigger resistor (35) is connected to the input terminal of the inverter (33);

[0034] The first end of the second capacitor (36) is connected to the ground terminal (A4), and the second end of the second capacitor (36) is connected to the input terminal of the inverter (33).

[0035] In some embodiments, the inverter (33) includes a P-type field-effect transistor (331) and an N-type field-effect transistor (332);

[0036] The source of the P-type field-effect transistor (331) is connected to the power supply terminal (A3);

[0037] The gates of the P-type field-effect transistor (331) and the N-type field-effect transistor (332) are connected to the input terminal of the inverter (33);

[0038] The drain of the P-type field-effect transistor (331) and the drain of the N-type field-effect transistor (332) are connected to the output terminal of the inverter (33);

[0039] The source of the N-type field-effect transistor (332) is connected to the ground terminal (A4).

[0040] On the other hand, a chip is provided that includes any of the above-mentioned electrostatic discharge protection devices.

[0041] On the other hand, an electronic device is provided, which is configured with the aforementioned chip.

[0042] This application provides an electrostatic discharge (ESD) protection device. Since traditional ESD clamping circuits have poor ESD protection performance, a first N-type diffusion region can be added to the N-well region of the P-type field-effect transistor (FET) in the first clamping circuit as an ESD current trigger point. Because the distance between the first N-type diffusion region and the drain of the P-type FET affects the size of its well resistance, a smaller distance results in a smaller well resistance, which is more conducive to the turn-on of the parasitic transistor in the first clamping circuit. Since the N-well region of the P-type FET has inherent resistance, when ESD current flows through it, the base potential of the parasitic transistor decreases, causing the parasitic transistor to conduct and discharge the ESD current. By adding a first N-type diffusion region, the parasitic transistor can turn on and conduct earlier, thus enabling it to discharge ESD current together with the P-type FET, improving the ESD protection effect. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a circuit diagram of an electrostatic discharge protection device based on a P-type field-effect transistor provided in an embodiment of this application;

[0045] Figure 2 This is a partially enlarged circuit diagram of an electrostatic discharge protection device based on a P-type field-effect transistor provided in an embodiment of this application;

[0046] Figure 3 This is a circuit diagram of an electrostatic discharge protection device based on an N-type field-effect transistor provided in an embodiment of this application;

[0047] Figure 4 This is a partially enlarged circuit diagram of an electrostatic discharge protection device based on an N-type field-effect transistor provided in an embodiment of this application. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0049] In this application, the terms "first," "second," etc., are used to distinguish identical or similar items with essentially the same function. It should be understood that there is no logical or temporal dependency between "first," "second," and "n," nor is there any limitation on the quantity or execution order.

[0050] This application provides an electrostatic discharge (ESD) protection device. Since static electricity can damage chips, it is necessary to protect against electrostatic current. This application uses an ESD protection device based on a P-type field-effect transistor as an example. This ESD protection device includes a first clamping circuit and a first parasitic resistor.

[0051] Figure 1 This is a circuit diagram of an electrostatic discharge (ESD) protection device based on a P-type field-effect transistor, provided in an embodiment of this application. See also... Figure 1 The electrostatic discharge protection device includes: a first clamping circuit 10 and a first parasitic resistor 20.

[0052] The first clamping circuit 10 includes a power supply terminal A1, a ground terminal A2, a parasitic transistor 11, a P-type field-effect transistor 12, an inverter 13, a second parasitic resistor 14, a first trigger resistor 15, and a first capacitor 16, used for discharging electrostatic current. The power supply terminal A1 supplies power to the electrostatic protection device, and the electrostatic current flows into the device from the power supply terminal A1. The parasitic transistor 11, exemplified by a PNP transistor, includes a collector, emitter, and base, used for discharging electrostatic current. The P-type field-effect transistor 12 includes a source, gate, drain, a second N-type diffusion region, and a first N-type diffusion region, used for discharging electrostatic current through a channel between the source and drain. The second N-type diffusion region serves as the contact point connecting the N-well region (NW) to the power supply terminal A1. The inverter 13 consists of a P-type field-effect transistor 131 and an N-type field-effect transistor 132, used to invert the phase of the input current signal. The first capacitor 16 is obtained by connecting the source and drain of a P-type field-effect transistor.

[0053] The first end of the first parasitic resistor 20 is connected to the base of the parasitic transistor 11 in the first clamping circuit 10, and the second end of the first parasitic resistor 20 is connected to the output of the inverter 13 in the first clamping circuit 10 through a metal wire. This is used to reduce the conduction voltage of the parasitic transistor 11 when current flows through it and to discharge the electrostatic current.

[0054] See Figure 1As shown, the circuit connection relationship of the first clamping circuit 10 is described below. The first capacitor 16 is a P-type field-effect transistor (FET). The source and drain of this P-type FET are connected as the first terminal of the first capacitor 16, which is connected to the power supply terminal A1. The gate of this P-type FET serves as the second terminal of the first capacitor 16 and is connected to the input terminal of the inverter 13. The first terminal of the first trigger resistor 15 is connected to the ground terminal A2, and the second terminal of the first trigger resistor 15 is connected to the input terminal of the inverter 13. Optionally, the second terminal of the first capacitor 16 and the second terminal of the first trigger resistor 15 can be connected by a metal wire, and then connected to the input terminal of the inverter 13. The inverter 13 is composed of a P-type FET 131 and an N-type FET 132. The gates of the P-type FET 131 and the N-type FET 132 are connected to the input terminal of the inverter 13. The drains of the P-type FET 131 and the N-type FET 132 are connected to the output terminal of the inverter 13. The source of P-type field-effect transistor 131 and the first terminal of the first capacitor 16 are connected to power supply terminal A1. The source of N-type field-effect transistor 132 and the first terminal of the first trigger resistor 15 are connected to ground terminal A2. The source 121 of P-type field-effect transistor 12 is connected to power supply terminal A1 and the emitter 111 of parasitic transistor 11. The drain 122 of P-type field-effect transistor 12 is connected to ground terminal A2 and the collector 112 of parasitic transistor 11. The gate 123 of P-type field-effect transistor 12 is connected to the output terminal of inverter 13. The first terminal of the second parasitic resistor 14 is connected to the second N-type diffusion region of P-type field-effect transistor 12. The second terminal of the second parasitic resistor 14 is connected to the base 113 of parasitic transistor 11.

[0055] In traditional electrostatic discharge clamping circuits, the electrostatic protection effect is poor due to the weak ability of the MOSFET channel to discharge electrostatic current and the high turn-on voltage of the parasitic transistor. Therefore, a first N-type diffusion region 124 is added to the N-well region (NW) of the P-type field-effect transistor 12 as a current trigger point. Since the distance between the first N-type diffusion region 124 and the drain 122 of the P-type field-effect transistor 12 affects the size of its well resistance, the smaller the well resistance, the more favorable it is for turning on the parasitic transistor 11. The electrostatic current flows in from the power supply terminal A1, flows through the channel of the P-type field-effect transistor 131 in the inverter 13, then flows through the wire through the first parasitic resistor 20, and finally flows into the base of the parasitic transistor 11. Since the N-well region where the parasitic transistor 11 is located has its own resistance, when the electrostatic current flows through the N-well region, it will lower the base potential of the parasitic transistor 11, which is conducive to the turning on and conduction of the parasitic transistor 11 in the first clamping circuit 10. Figure 2 This is a partially enlarged circuit diagram of an electrostatic discharge (ESD) protection device based on a P-type field-effect transistor, provided in an embodiment of this application. See also... Figure 2As shown, by adding a first N-type diffusion region 124 and a first parasitic resistor 20, the parasitic transistor 11 can be turned on and conducted earlier. Therefore, electrostatic current can be discharged simultaneously through the channel of the P-type field-effect transistor 12 and the parasitic transistor 11, improving the electrostatic protection effect. Specifically, the first end of the first parasitic resistor 20 is connected to the base 113 of the parasitic transistor 11 in the first clamping circuit 10, and the second end of the first parasitic resistor 20 is connected to the first N-type diffusion region 124 of the P-type field-effect transistor 12. See also... Figure 2 As shown, the first N-type diffusion region 124 of the P-type field-effect transistor 12 is connected to the output terminal of the inverter 13. The second N-type diffusion region 125 of the P-type field-effect transistor 12 is connected to the power supply terminal A1 and the first terminal of the second parasitic resistor 14.

[0056] This application uses a P-type substrate to construct a MOS transistor as an example for illustration. Similarly, when constructing a MOS transistor with an N-type substrate, a P-type diffusion region can be added in the P-well region as a current trigger point to achieve electrostatic discharge protection as shown in the embodiments of this application. Further details in the embodiments of this application will not be elaborated further.

[0057] See Figure 2 As shown, the flow of electrostatic current is explained below. Electrostatic current flows in from the power supply terminal A1. When the voltage of the parasitic transistor 11 reaches the turn-on voltage, part of the electrostatic current flows into the P-type field-effect transistor 12, and part flows into the parasitic transistor 11. The electrostatic current flowing into the P-type field-effect transistor 12 opens the channel between its source 121 and drain 122 for discharge, i.e., it flows from the power supply terminal A1 to the ground terminal A2, thus discharging the electrostatic current. When the parasitic transistor 11 is not conducting, the electrostatic current flows from the emitter 111 of the parasitic transistor 11 to the base 113, passes through the first parasitic resistor 20 and the first N-type diffusion region 124 in the N-well region, reaches the N-type field-effect transistor 132 of the inverter 13, and then flows to the ground terminal A2, thus discharging the electrostatic current. Because the N-well region has inherent resistance, when electrostatic current flows through it, it can lower the base potential of the parasitic transistor 11, causing the parasitic transistor 11 to conduct. When the parasitic transistor 11 is conducting, the electrostatic current flows from the emitter 111 to the collector 112, and directly to the ground terminal A2, thus discharging the electrostatic current. Therefore, when electrostatic current arrives, part of it is discharged through the channel of the P-type field-effect transistor 12, and part is discharged through the parasitic transistor 11, improving the electrostatic protection effect.

[0058] This application also provides another electrostatic discharge protection device based on an N-type field-effect transistor. Figure 3 This is a circuit diagram of an electrostatic discharge (ESD) protection device implemented using an N-type field-effect transistor, as provided in an embodiment of this application. See also... Figure 3 The electrostatic discharge protection device includes: a second clamping circuit 30 and a third parasitic resistor 40.

[0059] The second clamping circuit 10 includes a power supply terminal A3, a ground terminal A4, a parasitic transistor 31, an N-type field-effect transistor 32, an inverter 33, a fourth parasitic resistor 34, a second trigger resistor 35, and a second capacitor 36, used for discharging electrostatic current. The power supply terminal A3 supplies power to the electrostatic protection device, and the electrostatic current flows into the device from the power supply terminal A3. The parasitic transistor 31, exemplified by an NPN transistor, includes a collector, emitter, and base, used for discharging electrostatic current. The N-type field-effect transistor 32 includes a source, gate, drain, a second P-type diffusion region, and a first P-type diffusion region, used for discharging electrostatic current through a channel between the source and drain. The second P-type diffusion region serves as the contact point connecting the P-substrate (P-sub) to the ground terminal A4. The inverter 33 consists of a P-type field-effect transistor 331 and an N-type field-effect transistor 332, used to invert the phase of the input current signal. The second capacitor 36 is obtained by connecting the source and drain of an N-type field-effect transistor.

[0060] The first end of the third parasitic resistor 40 is connected to the base of the parasitic transistor 31 in the second clamping circuit 30, and the second end of the third parasitic resistor 40 is connected to the output of the inverter 33 in the second clamping circuit 30 through a metal wire. It is used to reduce the conduction voltage of the parasitic transistor 31 when current flows through it and to discharge the electrostatic current.

[0061] See Figure 3As shown, the circuit connection relationship of the second clamping circuit 30 is explained below. The second capacitor 36 is an N-type field-effect transistor (FET). The source and drain of this N-type FET are connected as the first terminal of the second capacitor 36, which is connected to the ground terminal A4. The gate of this N-type FET serves as the second terminal of the second capacitor 36 and is connected to the input terminal of the inverter 33. The first terminal of the second trigger resistor 35 is connected to the power supply terminal A3, and the second terminal of the second trigger resistor 35 is connected to the input terminal of the inverter 33. Optionally, the second terminal of the second capacitor 36 and the second terminal of the second trigger resistor 35 can be connected by a metal wire, and then connected to the input terminal of the inverter 33. The inverter 33 is composed of a P-type FET 331 and an N-type FET 332. The gates of the P-type FET 331 and the N-type FET 332 are connected to the input terminal of the inverter 33. The drains of the P-type FET 331 and the N-type FET 332 are connected to the output terminal of the inverter 33. The source of the P-type field-effect transistor 331 and the first terminal of the second trigger resistor 35 are connected to the power supply terminal A3. The source of the N-type field-effect transistor 332 and the first terminal of the second capacitor 36 are connected to the ground terminal A4. The source 321 of the N-type field-effect transistor 32 is connected to the ground terminal A4 and the emitter 311 of the parasitic transistor 31. The drain 322 of the N-type field-effect transistor 32 is connected to the power supply terminal A3 and the collector 312 of the parasitic transistor 31. The gate 323 of the N-type field-effect transistor 32 is connected to the output terminal of the inverter 33. The first terminal of the fourth parasitic resistor 34 is connected to the second P-type diffusion region of the N-type field-effect transistor 32. The second terminal of the fourth parasitic resistor 34 is connected to the base 313 of the parasitic transistor 31.

[0062] Similar to the electrostatic discharge protection device based on the P-type field-effect transistor mentioned above, a first P-type diffusion region 324 is added in the P-substrate (P-sub) of the N-type field-effect transistor 32 as a current trigger point. Figure 4 This is a partially enlarged circuit diagram of an electrostatic discharge (ESD) protection device based on an N-type field-effect transistor, provided in an embodiment of this application. See also... Figure 4As shown, a first P-type diffusion region 324 and a third parasitic resistor 40 can be added. When electrostatic current flows in from the power supply terminal A3, it flows through the channel of the P-type field-effect transistor 331 in the inverter 33, and then through the wire through the third parasitic resistor 40, flowing into the base of the parasitic transistor 31. Since the P-sub where the parasitic transistor 31 is located has its own resistance, when the electrostatic current flows through the P-sub, it will cause the base potential of the parasitic transistor 31 to decrease, thereby causing the parasitic transistor 31 to turn on and conduct earlier. Therefore, the electrostatic current can be discharged simultaneously through the channel of the N-type field-effect transistor 32 and the parasitic transistor 31, improving the electrostatic protection effect. The first end of the third parasitic resistor 40 is connected to the base 313 of the parasitic transistor 31 in the second clamping circuit 30, and the second end of the third parasitic resistor 40 is connected to the first P-type diffusion region 324 of the N-type field-effect transistor 32. See also... Figure 4 As shown, the first P-type diffusion region 324 of the N-type field-effect transistor 32 is connected to the output terminal of the inverter 33. The second P-type diffusion region 325 of the N-type field-effect transistor 32 is connected to the ground terminal A4 and the first terminal of the fourth parasitic resistor 34.

[0063] The implementation process of the electrostatic discharge protection device based on the N-type field-effect transistor is basically the same as that of the electrostatic discharge protection device based on the P-type field-effect transistor, and will not be repeated here.

[0064] This application provides an electrostatic discharge (ESD) protection device. Since traditional ESD clamping circuits have poor ESD protection performance, a first N-type diffusion region can be added to the N-well region of the P-type field-effect transistor (FET) in the first clamping circuit as an ESD current trigger point. Because the distance between the first N-type diffusion region and the drain of the P-type FET affects the size of its well resistance, a smaller distance results in a smaller well resistance, which is more conducive to the turn-on of the parasitic transistor in the first clamping circuit. Since the N-well region of the P-type FET has inherent resistance, when ESD current flows through it, the base potential of the parasitic transistor decreases, causing the parasitic transistor to conduct and discharge the ESD current. By adding a first N-type diffusion region, the parasitic transistor can turn on and conduct earlier, thus enabling it to discharge ESD current together with the P-type FET, improving the ESD protection effect.

[0065] In this application embodiment, a chip is also provided, which includes any of the above-mentioned electrostatic discharge protection devices.

[0066] In this application embodiment, an electronic device is also provided, which includes the above-described chip.

[0067] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An electrostatic protection device, characterized in that, The electrostatic discharge protection device includes: a power supply terminal (A1), a grounding terminal (A2), a first clamping circuit (10), and a first parasitic resistor (20). The base of the parasitic transistor (11) in the first clamping circuit (10) is connected to the first end of the first parasitic resistor (20). The parasitic transistor (11) is used to discharge electrostatic current when the turn-on voltage is reached. The first clamping circuit (10) has a first N-type diffusion region in the N-well of the P-type field-effect transistor (12). The first N-type diffusion region is connected to the second end of the first parasitic resistor (20), and the first N-type diffusion region is connected to the output end of the inverter (13) in the first clamping circuit (10). The P-type field-effect transistor (12) includes a gate, a source, a drain, a second N-type diffusion region, and the first N-type diffusion region, which are used to discharge electrostatic current through the channel between the source and the drain. The first parasitic resistor (20) reduces the voltage of the N-type field-effect transistor of the inverter (13) in the first clamping circuit (10) when current flows through it, and discharges the electrostatic current through the N-type field-effect transistor of the inverter (13) in the first clamping circuit (10). It also reduces the conduction voltage of the parasitic transistor (11) and discharges the electrostatic current when current flows through it.

2. The electrostatic protection device according to claim 1, characterized in that, The source of the P-type field-effect transistor (12) is connected to the power supply terminal (A1) and the emitter of the parasitic transistor (11); The drain of the P-type field-effect transistor (12) is connected to the ground terminal (A2) and the collector of the parasitic transistor (11); The gate of the P-type field-effect transistor (12) is connected to the output terminal of the inverter (13) in the first clamping circuit (10), and the inverter (13) is used to reverse the phase of the input current signal; The second N-type diffusion region of the P-type field-effect transistor (12) is connected to the power supply terminal (A1) and the first end of the second parasitic resistor (14) in the first clamping circuit (10), and the second end of the second parasitic resistor (14) is connected to the base of the parasitic transistor (11).

3. The electrostatic protection device according to claim 2, characterized in that, The first clamping circuit (10) also includes a first trigger resistor (15) and a first capacitor (16). The first end of the first trigger resistor (15) is connected to the ground terminal (A2), and the second end of the first trigger resistor (15) is connected to the input terminal of the inverter (13); The first end of the first capacitor (16) is connected to the power supply terminal (A1), and the second end of the first capacitor (16) is connected to the input terminal of the inverter (13).

4. The electrostatic protection device according to claim 3, characterized in that, The inverter (13) includes a P-type field-effect transistor (131) and an N-type field-effect transistor (132). The source of the P-type field-effect transistor (131) is connected to the power supply terminal (A1); The gates of the P-type field-effect transistor (131) and the N-type field-effect transistor (132) are connected to the input terminal of the inverter (13). The drain of the P-type field-effect transistor (131) and the drain of the N-type field-effect transistor (132) are connected to the output terminal of the inverter (13); The source of the N-type field-effect transistor (132) is connected to the ground terminal (A2).

5. An electrostatic protection device, characterized in that, The electrostatic discharge protection device includes: a power supply terminal (A3), a grounding terminal (A4), a second clamping circuit (30), and a third parasitic resistor (40). The base of the parasitic transistor (31) in the second clamping circuit (30) is connected to the first end of the third parasitic resistor (40). The parasitic transistor (31) is used to discharge electrostatic current when the turn-on voltage is reached. The second clamping circuit (30) has a first P-type diffusion region in the P substrate of the N-type field-effect transistor (32). The first P-type diffusion region is connected to the second end of the third parasitic resistor (40), and the first P-type diffusion region is connected to the output end of the inverter (33) in the second clamping circuit (30). The N-type field-effect transistor (32) includes a gate, a source, a drain, a second P-type diffusion region, and the first P-type diffusion region, which are used to discharge electrostatic current through the channel between the source and the drain. The third parasitic resistor (40) reduces the voltage of the N-type field-effect transistor of the inverter (33) in the second clamping circuit (30) when current flows through it, and discharges the electrostatic current through the N-type field-effect transistor of the inverter (33) in the second clamping circuit (30). It also reduces the conduction voltage of the parasitic transistor (31) when current flows through it to discharge the electrostatic current.

6. The electrostatic protection device according to claim 5, characterized in that, The source of the N-type field-effect transistor (32) is connected to the ground terminal (A4) and the emitter of the parasitic transistor (31); The drain of the N-type field-effect transistor (32) is connected to the power supply terminal (A3) and the collector of the parasitic transistor (31); The gate of the N-type field-effect transistor (32) is connected to the output terminal of the inverter (33) in the second clamping circuit (30), and the inverter (33) is used to reverse the phase of the input current signal; The second P-type diffusion region of the N-type field-effect transistor (32) is connected to the ground terminal (A4) and the first end of the fourth parasitic resistor (34) in the second clamping circuit (30), and the second end of the fourth parasitic resistor (34) is connected to the base of the parasitic transistor (31).

7. The electrostatic protection device according to claim 6, characterized in that, The second clamping circuit (30) also includes a second trigger resistor (35) and a second capacitor (36); The first end of the second trigger resistor (35) is connected to the power supply terminal (A3), and the second end of the second trigger resistor (35) is connected to the input terminal of the inverter (33); The first end of the second capacitor (36) is connected to the ground terminal (A4), and the second end of the second capacitor (36) is connected to the input terminal of the inverter (33).

8. The electrostatic protection device according to claim 7, characterized in that, The inverter (33) includes a P-type field-effect transistor (331) and an N-type field-effect transistor (332). The source of the P-type field-effect transistor (331) is connected to the power supply terminal (A3); The gates of the P-type field-effect transistor (331) and the N-type field-effect transistor (332) are connected to the input terminal of the inverter (33). The drain of the P-type field-effect transistor (331) and the drain of the N-type field-effect transistor (332) are connected to the output terminal of the inverter (33); The source of the N-type field-effect transistor (332) is connected to the ground terminal (A4).

9. A chip, characterized in that, The chip includes the electrostatic discharge protection device according to any one of claims 1 to 4, or the chip includes the electrostatic discharge protection device according to any one of claims 5 to 8.

10. An electronic device, characterized in that, The electronic device is equipped with the chip as described in claim 9.

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