Array substrate and repairing method thereof

Abstract

The present application provides an array substrate and a repairing method thereof. The array substrate comprises a plurality of gate lines, a plurality of data lines, a plurality of bias voltage lines and a plurality of pixel units. The array substrate is divided into a display area and a virtual area. In the virtual area, the projection of the data line perpendicular to the array substrate surface and the projection of the bias voltage line perpendicular to the array substrate surface overlap. Therefore, when repairing the data line, laser radiation is performed on the overlapping area of the data line and the bias voltage line to make them short-circuit. Since there is only an insulating layer between the data line and the bias voltage line, the heat melting effect caused by the laser radiation will not cause peripheral problems, which helps to improve the product yield.

Description

Technical Field

[0001] This invention relates to the field of optoelectronic detection technology, specifically to an array substrate and its repair method. Background Technology

[0002] Flat panel detectors have applications in medical imaging (breast and chest examinations, radiotherapy, etc.), industrial non-destructive testing, and security inspection. The array substrate is a crucial component of a flat panel detector, composed of millions or even tens of millions of pixel unit circuits. Each pixel unit typically consists of devices such as thin-film transistors (TFTs) and photodiodes (PDs). In the array substrate, the data lines providing image signals have very narrow linewidths, making them prone to breakage during manufacturing. Laser repair is required to repair these breaks. Current repair methods typically involve laser-etching the thin-film transistors; however, the thermal melting effect caused by laser etching can lead to surrounding problems and affect product yield. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the present invention provides an array substrate and a repair method thereof. The array substrate includes multiple gate lines, multiple data lines, multiple bias voltage lines, and multiple pixel units. The array substrate is divided into a display area and a virtual area. In the virtual area, the projections of the data lines perpendicular to the surface of the array substrate overlap with the projections of the bias voltage lines perpendicular to the surface of the array substrate. Therefore, when repairing the data lines, laser lithography is performed on the overlapping area of ​​the data lines and bias voltage lines to short-circuit them. Since there is only an insulating layer between them, the thermal melting effect caused by laser lithography will not cause problems to the surrounding area, which helps to improve product yield.

[0004] To achieve the above and other related objectives, the present invention provides an array substrate comprising multiple gate lines, multiple data lines, multiple bias voltage lines, and multiple pixel units, wherein the multiple gate lines and the multiple data lines intersect to form multiple defined regions, and the pixel units are located within each of the defined regions; the array substrate is divided into a display area and a virtual area, wherein in the virtual area, the projections of the data lines perpendicular to the surface of the array substrate overlap with the projections of the bias voltage lines perpendicular to the surface of the array substrate.

[0005] Optionally, the pixel unit may include a thin-film transistor and an optical sensor.

[0006] Optionally, the plurality of bias voltage lines include a plurality of first bias voltage lines and a second bias voltage line, wherein the plurality of first bias voltage lines are arranged parallel to the plurality of data lines, and the second bias voltage line is located at one end of the plurality of first bias voltage lines and is arranged perpendicular to the plurality of first bias voltage lines.

[0007] Optionally, the first bias line includes a main line portion and a branch line portion, wherein in the virtual region, the branch line portion covers the thin-film transistor and a portion of the data line.

[0008] Optionally, in the virtual area, the projection of the data line perpendicular to the surface of the array substrate overlaps with the projection of the second bias voltage line perpendicular to the surface of the array substrate.

[0009] Optionally, the data line extends to the second bias voltage line so that the projection of the data line perpendicular to the surface of the array substrate overlaps with the projection of the second bias voltage line perpendicular to the surface of the array substrate.

[0010] Optionally, the second bias voltage line extends to the data line so that the projection of the data line perpendicular to the surface of the array substrate overlaps with the projection of the second bias voltage line perpendicular to the surface of the array substrate.

[0011] Optionally, the array substrate further includes a gate driving unit and a processing unit, wherein the gate driving unit is connected to the plurality of gate lines and is used to provide control signals to the plurality of gate lines, and the processing unit is connected to the plurality of data lines and is used to acquire and process the electrical signals output by the plurality of data lines.

[0012] The present invention also provides a method for repairing an array substrate, comprising the following steps:

[0013] S1: Provide an array substrate, wherein the array substrate is any of the array substrates described above, and position the data line to be repaired;

[0014] S2: In the virtual area, the data line to be repaired and the bias voltage line that overlaps with it are short-circuited;

[0015] S3: Cut off the gate line in the virtual region that is connected to the gate driving unit.

[0016] Optionally, in step S2, a laser lithography method is used to short-circuit the data line to be repaired and any overlapping bias voltage lines.

[0017] The array substrate and its repair method provided by this invention have at least the following beneficial effects:

[0018] The array substrate provided by this invention includes multiple gate lines, multiple data lines, multiple bias voltage lines, and multiple pixel units. The array substrate is divided into a display area and a virtual area. In the virtual area, the projections of the data lines perpendicular to the surface of the array substrate overlap with the projections of the bias voltage lines perpendicular to the surface of the array substrate. Therefore, when repairing the data lines, laser lithography is performed on the overlapping area of ​​the data lines and bias voltage lines to short-circuit them. Since there is only an insulating layer between them, the thermal melting effect caused by laser lithography will not cause problems to the surrounding area, which helps to improve product yield. Attached Figure Description

[0019] Figure 1 The diagram shown is a structural schematic of the array substrate provided in the embodiment.

[0020] Figure 2 The diagram shown is a structural schematic of the display area in the array substrate provided in Embodiment 1.

[0021] Figure 3 The diagram shown is a structural schematic of the virtual region in the array substrate provided in Embodiment 1.

[0022] Figure 4 The flowchart shown is a method for repairing an array substrate provided in an embodiment.

[0023] Figures 5-6 The diagram shown is a structural schematic of the virtual region in the array substrate provided in Embodiment 2.

[0024] Component designation explanation

[0025] 11 grid lines

[0026] 12 Data Cables

[0027] 13 Bias Voltage Line

[0028] 131 First bias voltage line

[0029] 1311 Main Story Section

[0030] 1312 Branch Line

[0031] 132 Second bias voltage line

[0032] 14-pixel unit

[0033] 141 Thin-film transistor

[0034] 142 Optical Sensors

[0035] 100 display area

[0036] 200 virtual zones

[0037] 20 Laser Positions Detailed Implementation

[0038] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0039] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components, the shape, quantity, positional relationship and proportion of each component can be arbitrarily changed under the premise of realizing the technical solution of this invention, and the layout of the components may also be more complex.

[0040] Example 1

[0041] This embodiment provides an array substrate, such as Figure 1 As shown, it includes multiple gate lines 11, multiple data lines 12, multiple bias voltage lines 13, and multiple pixel units 14.

[0042] As an example, multiple gate lines 11 extend along a first direction to provide control signals to the thin-film transistors 141 in the pixel unit, thereby controlling the thin-film transistors 141 to turn on or off; multiple data lines 12 extend along a second direction to read the charge signals stored in each column of pixel units 14 in parallel; multiple bias voltage lines 13 include multiple first bias voltage lines 131 and one second bias voltage line 132, for applying bias voltages to the optical sensors 142 in the pixel unit, wherein the multiple first bias voltage lines 131 extend along the second direction, and the second bias voltage line 132 is located at one end of the multiple first bias voltage lines 131 and is arranged perpendicularly to the multiple first bias voltage lines 131. In this embodiment, the first direction (i.e., the X direction shown in the figure) and the second direction (i.e., the Y direction shown in the figure) intersect perpendicularly as an example. As an example, multiple gate lines 11, multiple data lines 12, and multiple bias voltage lines 13 are located in different layers of the array substrate and are provided with insulating layers between them to avoid short circuits in their overlapping areas.

[0043] like Figure 1 As shown, multiple gate lines 11 and multiple data lines 12 intersect to form multiple defined regions, and pixel units 14 are located within these defined regions. Figure 2As shown, a thin-film transistor 141 and an optical sensor 142 are disposed in the pixel unit 14. The thin-film transistor 141 includes a gate, a source and a drain (not shown in the figure), wherein the gate is connected to the gate line 11, the source is connected to the data line 12, and the drain is connected to the optical sensor 142.

[0044] In this embodiment, as Figure 1 As shown, a portion of the area at the bottom of the array substrate is the virtual area 200, and the remaining portion is the display area 100. Typically, the virtual area 200 includes several or dozens of gate lines 11 located at the bottom of the array substrate. (Refer to...) Figure 2 and Figure 3 As shown, the first bias voltage line 131 includes a main line portion 1311 and a branch line portion 1312. In the display area 100, as... Figure 2 As shown, the branch portion 1312 of the first bias voltage line only covers the thin-film transistor 141, that is, the projection of the first bias voltage line 131 perpendicular to the surface of the array substrate only overlaps with the projection of the thin-film transistor 141 perpendicular to the surface of the array substrate; in the virtual region 200, as Figure 3 As shown, the branch portion 1312 of the first bias voltage line covers the thin film transistor 141 and part of the data line 12. That is, the projection of the first bias voltage line 131 perpendicular to the surface of the array substrate overlaps with the projections of the thin film transistor 141 and part of the data line 12 perpendicular to the surface of the array substrate.

[0045] like Figure 1 As shown, the array substrate also includes a gate driving unit 15 and a processing unit 16. As an example, the gate driving unit 15 is connected to multiple gate lines 11, providing control signals to the gate lines 11; the processing unit 16 is connected to multiple data lines 12, acquiring and processing the electrical signals output from the data lines 12 to display an image. The specific structure of the gate driving unit 15 and the processing unit 16 is not limited here.

[0046] This embodiment also provides a method for repairing an array substrate, such as... Figure 4 As shown, it includes the following steps:

[0047] S1: Provide an array substrate to position the data line to be repaired;

[0048] As an example, an array substrate is provided, in which a data line to be repaired is located, and the position of the data line 12 to be repaired is determined. In this embodiment, the array substrate is selected from the above-described array substrate, and its specific structure can be referred to the above description, which will not be repeated here.

[0049] S2: In the virtual area, the data line to be repaired and the bias voltage line that overlaps with it are short-circuited;

[0050] As an example, in virtual area 200, the data line 12 to be repaired and the first bias voltage line 131 that overlaps with it are short-circuited. In this embodiment, a laser lithography method is used to short-circuit the two, specifically, as shown below. Figure 3 As shown, at laser position 20, the insulating material in the overlapping area is ablated by laser. After the insulating material disappears, the data line 12 and the first bias voltage line 131 can be short-circuited. Since there is only an insulating layer between the data line 12 and the first bias voltage line 131 in the direction perpendicular to the surface of the array substrate, laser etching at this location will not cause thermal melting effects in the surrounding area, thus helping to improve product yield.

[0051] S3: Cut off the gate line in the virtual region that is connected to the gate driving unit.

[0052] As an example, in order to prevent interference from gate line 11, the gate line 11 connected to the gate drive unit 15 in the virtual region 200 is cut off.

[0053] Example 2

[0054] This embodiment provides an array substrate, such as Figure 1 As shown, it includes multiple gate lines 11, multiple data lines 12, multiple bias voltage lines 13, and multiple pixel units 14. The array substrate provided in this embodiment is similar to that in Embodiment 1, and will not be repeated here. The difference lies in:

[0055] like Figure 1 As shown, a portion of the area at the bottom of the array substrate is the virtual area 200, and the remaining portion is the display area 100. Generally, the virtual area 200 includes several or dozens of gate lines 11 located at the bottom of the array substrate. The first bias voltage line 131 includes a main line portion 1311 and a branch line portion 1312. In this embodiment, whether in the display area 100 or the virtual area 200, the branch line portion 1312 of the first bias voltage line only covers the thin-film transistor 141, such as... Figure 2 As shown, the projection of the first bias voltage line 131 perpendicular to the surface of the array substrate overlaps only with the projection of the thin film transistor 141 perpendicular to the surface of the array substrate.

[0056] As an example, at the bottom of the virtual region 200, the projection of the data line 12 perpendicular to the surface of the array substrate overlaps with the projection of the second bias voltage line 132 perpendicular to the surface of the array substrate. For example, in this embodiment, the data line 12 extends to the second bias voltage line 132 so that their projections perpendicular to the surface of the array substrate overlap. Figure 5 As shown; in another optional embodiment, the second bias voltage line 132 extends to the data line 12, which can also cause the projections of the two perpendicular to the surface of the array substrate to overlap, as shown. Figure 6 As shown.

[0057] This embodiment also provides a method for repairing an array substrate, including the following steps:

[0058] S1: Provide an array substrate to position the data line to be repaired;

[0059] As an example, an array substrate is provided, in which a data line to be repaired is located, and the position of the data line 12 to be repaired is identified. In this embodiment, the array substrate is the one described in this embodiment above, and its specific structure can be referred to the above description, which will not be repeated here.

[0060] S2: In the virtual area, the data line to be repaired and the bias voltage line that overlaps with it are short-circuited;

[0061] As an example, in virtual area 200, the data line 12 to be repaired and the second bias voltage line 132 that overlaps with it are short-circuited. In this embodiment, a laser lithography method is used to short-circuit the two; specifically, refer to... Figure 5 and Figure 6 As shown, at laser position 20, the insulating material in the overlapping area is ablated by laser. After the insulating material disappears, the data line 12 and the second bias voltage line 132 can be short-circuited. Since there is only an insulating layer between the data line 12 and the second bias voltage line 132 in the direction perpendicular to the surface of the array substrate, laser etching at this location will not cause thermal melting effects in the surrounding area, thus helping to improve product yield.

[0062] S3: Cut off the gate line in the virtual region that is connected to the gate driving unit.

[0063] As an example, in order to prevent interference from gate line 11, the gate line 11 connected to the gate drive unit 15 in the virtual region 200 is cut off.

[0064] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An array substrate, characterized in that, The array includes multiple gate lines, multiple data lines, multiple bias voltage lines, multiple pixel units, and gate driving units. The multiple gate lines and multiple data lines intersect to form multiple defined regions. Each pixel unit is located within a defined region and contains a thin-film transistor and an optical sensor. The multiple bias voltage lines include multiple first bias voltage lines and one second bias voltage line. The multiple first bias voltage lines are arranged parallel to the multiple data lines, and the second bias voltage line is located at one end of the multiple first bias voltage lines and is arranged perpendicular to them. The array substrate is divided into... The display area and the virtual area are defined as follows: In the virtual area, the projection of the data line perpendicular to the surface of the array substrate overlaps with the projection of the bias voltage line perpendicular to the surface of the array substrate, and there is only an insulating layer between the data line and the bias voltage line; The first bias voltage line includes a main line portion and a branch line portion, and in the virtual area, the branch line portion covers the thin-film transistor and part of the data line; The gate driving unit is connected to the multiple gate lines and is used to provide control signals to the multiple gate lines. When the data line to be repaired is short-circuited to the bias voltage line that overlaps with it, the gate line in the virtual area is disconnected from the gate driving unit.

2. The array substrate according to claim 1, characterized in that, In the virtual region, the projection of the data line perpendicular to the surface of the array substrate overlaps with the projection of the second bias voltage line perpendicular to the surface of the array substrate.

3. The array substrate according to claim 2, characterized in that, The data line extends to the second bias voltage line so that the projection of the data line perpendicular to the surface of the array substrate overlaps with the projection of the second bias voltage line perpendicular to the surface of the array substrate.

4. The array substrate according to claim 2, characterized in that, The second bias voltage line extends to the data line so that the projection of the data line perpendicular to the surface of the array substrate overlaps with the projection of the second bias voltage line perpendicular to the surface of the array substrate.

5. The array substrate according to claim 1, characterized in that, The array substrate further includes a processing unit connected to the plurality of data lines, which is used to acquire and process the electrical signals output by the plurality of data lines.

6. A method for repairing an array substrate, characterized in that, Includes the following steps: S1: Provide an array substrate, wherein the array substrate is the array substrate according to any one of claims 1-5, and position the data line to be repaired; S2: In the virtual area, the data line to be repaired and the bias voltage line that overlaps with it are short-circuited; S3: Cut off the gate line in the virtual region that is connected to the gate driving unit.

7. The method for repairing an array substrate according to claim 6, characterized in that, In step S2, a laser lithography method is used to short-circuit the data line to be repaired and the bias voltage line that overlaps with it.

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