Display panel

Abstract

This application provides a display panel including a high-voltage power supply signal line, a driving thin-film transistor (TFT), and a light-emitting element. The TFT includes an active layer comprising a source region, a drain region, and a channel region. The source region is connected to the high-voltage power supply signal line, and the drain region is connected to the light-emitting element. By making the channel region near the drain region have a lower majority carrier concentration than the channel region near the source region, the saturation voltage of the TFT can be reduced, thereby reducing the heat dissipation of the TFT and thus reducing the power consumption of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel. Background Technology

[0002] Organic light-emitting diode (OLED) display panels are widely used in our daily lives, such as in the screens of mobile phones and computers. With the development of display technology, people have increasingly higher requirements for the display quality and power consumption of display panels.

[0003] The power consumption of a display panel mainly includes the power consumption of the driving thin-film transistors, the power consumption of the light-emitting elements, and the heat dissipation of the metal traces. The driving thin-film transistors generate heat during operation, and the heat dissipation of a single driving thin-film transistor can be simplified as: W DTFT =I ds *V ds W DTFT To drive the heat dissipation of thin-film transistors, I ds V is the drain-source current. ds This is the drain-source voltage. When driving a thin-film transistor to drive a light-emitting element, in order to ensure the stability of the output current, the drain-source voltage V of the driving thin-film transistor is... ds It should be slightly higher than the saturation voltage. If the saturation voltage driving the thin-film transistor is large, the source-drain voltage V must be increased. ds To make it greater than the saturation voltage, this will increase the heat dissipation of the driving thin-film transistor, resulting in increased power consumption of the display panel.

[0004] In summary, existing display panels suffer from high power consumption due to the high saturation voltage required to drive the thin-film transistors. Therefore, it is necessary to provide a display panel that can mitigate this deficiency. Summary of the Invention

[0005] This application provides a display panel that can reduce the saturation voltage of the driving thin-film transistor and reduce the power consumption of the driving thin-film transistor, thereby reducing the power consumption of the display panel.

[0006] This application provides a display panel including a power high-voltage signal line, a driving thin-film transistor, and a light-emitting element. The driving thin-film transistor includes an active layer, which includes a source region, a drain region, and a channel region. The channel region is disposed between the source region and the drain region. The source region is electrically connected to the power high-voltage signal line, and the drain region is electrically connected to the light-emitting element.

[0007] The channel region near the drain region has a lower dopant ion concentration than the channel region near the source region.

[0008] According to one embodiment of this application, the channel region includes a first sub-channel region and a second sub-channel region, wherein the second sub-channel region is disposed between the first sub-channel region and the drain region;

[0009] The second sub-channel region has a lower dopant ion concentration than the first sub-channel region.

[0010] According to one embodiment of this application, the first sub-channel region and the second sub-channel region have the same doping type.

[0011] According to one embodiment of this application, the doping type of the first sub-channel region is different from the doping type of the second sub-channel region.

[0012] According to one embodiment of this application, the first sub-channel region is N-type doped or P-type doped, and the second sub-channel region is undoped.

[0013] According to one embodiment of this application, the doping type of the first sub-channel region is the same as the doping type of the source region and the drain region, and the doping ion concentration of the first sub-channel region is less than the doping ion concentration of the source region and the drain region.

[0014] According to one embodiment of this application, the length of the first sub-channel region is greater than or equal to the length of the second sub-channel region.

[0015] According to one embodiment of this application, the width of the first sub-channel region is greater than or equal to the width of the second sub-channel region.

[0016] According to one embodiment of this application, the trench area includes a third sub-trench area, which is disposed between the first sub-trench area and the second sub-trench area;

[0017] The first sub-channel region has the same doping type as the second and third sub-channel regions, the doped ion concentration of the first sub-channel region is greater than that of the third sub-channel region, and the doped ion concentration of the third sub-channel region is greater than that of the second sub-channel region.

[0018] According to one embodiment of this application, the trench area includes a third sub-trench area, which is disposed between the first sub-trench area and the second sub-trench area;

[0019] Wherein, the first sub-channel region and the second sub-channel region have different doping types, and the third sub-channel region has the same doping type as one of the first sub-channel region and the second sub-channel region; or, the third sub-channel region is undoped.

[0020] According to one embodiment of this application, the display panel includes a plurality of pixel driving circuits, and the pixel driving circuit includes a driving thin film transistor, a compensation thin film transistor, a switching thin film transistor, and a reset thin film transistor;

[0021] Wherein, the driving thin-film transistor and the switching thin-film transistor are both polycrystalline silicon thin-film transistors, the reset thin-film transistor is a polycrystalline silicon thin-film transistor or an oxide thin-film transistor, the compensation thin-film transistor is a polycrystalline silicon thin-film transistor or an oxide thin-film transistor, and the channel region of the active layer of any one of the reset thin-film transistor, the compensation thin-film transistor and the switching thin-film transistor is undoped or has the same doping ion concentration.

[0022] According to one embodiment of this application, the pixel driving circuit includes a first switching thin-film transistor, a second switching thin-film transistor, a third switching thin-film transistor, a compensation thin-film transistor, a first reset thin-film transistor, and a second reset thin-film transistor.

[0023] Wherein, the source region of the driving thin film transistor is electrically connected to the first terminal of the first switching thin film transistor and the first terminal of the second switching thin film transistor at the first node, the second terminal of the first switching thin film transistor is electrically connected to the data signal line, and the second terminal of the second switching thin film transistor is electrically connected to the power supply high voltage signal line;

[0024] The drain region of the driving thin-film transistor is electrically connected to the first terminal of the compensation thin-film transistor and the first terminal of the third switching thin-film transistor at the second node.

[0025] The gate of the driving thin film transistor is electrically connected to the second terminal of the compensation thin film transistor and the first terminal of the first reset thin film transistor at a third node, and the second terminal of the first reset thin film transistor is electrically connected to the first initialization signal line.

[0026] The second terminal of the third switching thin-film transistor is electrically connected to the first terminal of the second reset thin-film transistor and the anode of the light-emitting element at the fourth node. The gates of the second switching thin-film transistor and the third switching thin-film transistor are both electrically connected to the light-emitting control signal line. The second terminal of the second reset thin-film transistor is electrically connected to the second initialization signal line.

[0027] The beneficial effects of this application embodiment are as follows: This application embodiment provides a display panel, which includes a power supply high-voltage signal line, a driving thin-film transistor, and a light-emitting element. The driving thin-film transistor includes an active layer, which includes a source region, a drain region, and a channel region. The channel region is disposed between the source region and the drain region. The source region is connected to the power supply high-voltage signal line, and the drain region is connected to the light-emitting element. By making the channel region near the drain region have a lower majority carrier concentration than the channel region near the source region, the voltage drop of the driving thin-film transistor near the drain region can be increased, and the saturation voltage of the driving thin-film transistor can be reduced, thereby reducing the power consumption of the driving thin-film transistor and thus reducing the power consumption of the display panel. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of a pixel driving circuit according to an embodiment of this application;

[0030] Figure 2 A partial schematic diagram of a first type of display panel provided in an embodiment of this application;

[0031] Figure 3 for Figure 2 The first type of display panel shown is a cross-sectional view along the A-A' direction;

[0032] Figure 4 IDVD curves for driving thin-film transistors of related technologies;

[0033] Figure 5 A schematic diagram of carrier distribution in the channel of a driving thin-film transistor in a related technology when it has not entered the saturation region;

[0034] Figure 6 A schematic diagram of carrier distribution in the channel of a driving thin-film transistor after it enters the saturation region, based on related technologies.

[0035] Figure 7 IDVD curves of GC-DTFT and conventional DTFT provided for embodiments of this application;

[0036] Figure 8 A partial schematic diagram of a second type of display panel provided in an embodiment of this application;

[0037] Figure 9 for Figure 8The second type of display panel shown is a cross-sectional view along the A-A' direction;

[0038] Figure 10 A partial schematic diagram of a third type of display panel provided in an embodiment of this application;

[0039] Figure 11 A partial schematic diagram of a fourth type of display panel provided in an embodiment of this application;

[0040] Figure 12 A partial schematic diagram of the fifth type of display panel provided in an embodiment of this application;

[0041] Figure 13 for Figure 12 The fifth type of display panel shown is a cross-sectional view along the A-A' direction;

[0042] Figure 14 This is a pixel driving circuit diagram provided for an embodiment of this application. Detailed Implementation

[0043] The following descriptions of the embodiments are based on the accompanying illustrations and are used to illustrate specific embodiments in which this application can be implemented. Directional terms used in this application, such as [up], [down], [front], [back], [left], [right], [inner], [outer], [side], etc., are only for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative and understanding purposes and not for limiting the application. In the figures, structurally similar units are represented by the same reference numerals.

[0044] The present application will be further described below with reference to the accompanying drawings and specific embodiments.

[0045] The display panel provided in this application embodiment includes a power high-voltage signal line 20, a pixel driving circuit, a light-emitting element 30, and a cathode trace 40. The pixel driving circuit is connected to the power high-voltage signal line 20 and the light-emitting element 30 respectively. The power high-voltage signal line 20 is used to transmit the driving voltage VDD of the power signal of the display panel, and the cathode trace 40 is used to transmit the cathode voltage VSS shared by each light-emitting element 30.

[0046] like Figure 1 As shown, the pixel driving circuit may include a driving thin-film transistor T1, which is connected to the power supply high-voltage signal line 20 and the light-emitting element 30 respectively. The light-emitting element 30 is also connected to the cathode trace 40.

[0047] In this embodiment, the light-emitting element is an organic light-emitting diode (OLED). In other embodiments, the light-emitting element may also be, but is not limited to, a mini LED or a micro LED chip; this is not the only possible method.

[0048] It should be noted that, Figure 1 This illustration only shows the connection relationship between the pixel driving circuit, the high-voltage power signal line, and the light-emitting element, and does not represent the structure of the pixel driving circuit in actual applications. The structure of the pixel driving circuit can be referenced from the structure of pixel driving circuits in existing display panels, and is not limited here.

[0049] like Figure 2 As shown, the driving thin-film transistor T1 includes an active layer 11, which may include a source region 111, a drain region 112, and a channel region 113. The channel region 113 is disposed between the source region 111 and the drain region 112. The source region 111 is connected to the power supply high-voltage signal line 20, and the drain region 112 is connected to the light-emitting element 30.

[0050] It should be noted that the source region 111 can be directly connected to the high-voltage power signal line 20, or it can be indirectly connected to the high-voltage power signal line 20. The drain region 112 can be directly connected to the high-voltage power signal line 20, or it can be indirectly connected to the high-voltage power signal line 20.

[0051] In this embodiment, the driving thin-film transistor T1 is a low-temperature polycrystalline silicon thin-film transistor, and the active layer 11 is made of polycrystalline silicon.

[0052] like Figure 3 As shown, the driving thin-film transistor T1 may further include a source 12 and a drain 13, both of which are disposed in a different layer from the active layer 11 and are disposed on the side of the active layer 11 away from the substrate 100.

[0053] The driving thin-film transistor T1 may further include a gate 14, which is disposed in a different layer from the active layer 11 and is located on the side of the active layer 11 facing away from the substrate 100. The orthographic projection of the gate 14 on the substrate 100 is the same as the orthographic projection of the channel region 113 on the substrate 100.

[0054] The display panel may further include a gate insulating layer 101 and an interlayer dielectric layer 102. The gate insulating layer 101 is disposed between the active layer 11 and the gate 14, and the interlayer dielectric layer 102 is disposed between the source 12, the drain 13 and the gate 14.

[0055] It should be noted that, Figure 3 Only the positional and connection relationships between the active layer 11, the source 12, the drain 13, and the gate 14 are illustrated. Figure 3The structure of the display panel and driving thin-film transistors shown does not represent the actual structure of the display panel and driving thin-film transistors in practical applications. In practical applications, the driving thin-film transistors are not limited to... Figure 3 The top grid structure shown can also be a bottom grid structure or a double grid structure; there is no single limitation here.

[0056] In this embodiment, the channel region 113 near the drain region 112 has a lower dopant concentration than the channel region 113 near the source region 111.

[0057] It should be noted that the power consumption of the display panel is mainly determined by the voltage difference and current of the display panel, that is:

[0058] Power = (VDD - VSS) * I VSS ;

[0059] Where I VSS This is the sum of the operating currents of all light-emitting elements. Its magnitude is determined by the brightness setting of the display panel and the efficiency of the light-emitting elements. The lower the brightness of the display panel or the higher the efficiency of the light-emitting elements, the higher the required IL. VSS The smaller the size, the lower the power consumption, because:

[0060] VDD-VSS=VDD IR drop +V ds +V on +VSS IR drop ;

[0061] Among them, such as Figure 1 As shown, a series of components are included between the driving voltage VDD and the cathode voltage VSS: a high-voltage power signal line 20, a driving thin-film transistor T1, a light-emitting element 30, and a cathode trace 40. The driving thin-film transistor T1 controls the brightness of the light-emitting element by controlling the current flowing through it via the gate voltage, thereby controlling the image and brightness of the display panel. The driving voltage VDD and the cathode voltage VSS... SS The voltage difference will create a voltage drop across the above four components, mainly including: the voltage drop VDD caused by the resistance of the high-voltage signal line 20. IR drop The voltage drop VSS caused by the resistance of the cathode trace 40 IR drop The voltage divider source drain voltage V that drives the thin-film transistor T1 ds The operating voltage V required for the light-emitting element to emit light on .

[0062] Taking an existing display panel with low-temperature polycrystalline silicon driven thin-film transistors as an example, such as Figure 4 As shown, when the drain-source voltage V of the driving thin-film transistor is ds small, the drain-source current I ds and the drain-source voltage V ds are approximately linearly related. At this time, the carrier concentration in the channel corresponding to the driving thin-film transistor is Figure 5 distributed, and the drain-source voltage V ds is relatively uniformly distributed throughout the channel.

[0063] As Figure 6 shown, when the drain-source voltage V is continuously increased ds and satisfies the relationship: |V gs - V th | ≥ |V ds |, a pinch-off point appears, that is, the carriers in the channel near the drain are depleted, and a high-resistance region is formed in this part of the channel. To the left of the pinch-off point, there are carriers in the channel, and the resistance of the channel is relatively small. Therefore, the voltage drop of the drain-source voltage V ds mainly occurs in the high-resistance region, and the drain-source voltage V corresponding to the appearance of the pinch-off point in the channel ds is the saturation voltage of the driving thin-film transistor. At this time, the source-drain voltage V ds satisfies the relationship: |V gs - V th | = |V ds |. Continuing to increase the drain-source voltage V ds , at this time, the change amount of the drain-source current I ds with the increase of the drain-source voltage V ds is very small, and the driving thin-film transistor enters the saturation region. When the driving thin-film transistor drives the light-emitting element to emit light, in order to ensure the stability of the output current, the drain-source voltage V of the driving thin-film transistor ds should be slightly greater than the saturation voltage.

[0064] Heat is generated when the driving thin-film transistor works. The heat dissipation power consumption of a single driving thin-film transistor can be simplified as: W DTFT = I ds * V ds . By reducing the saturation voltage of the driving thin-film transistor, the drain-source voltage V when the driving thin-film transistor works can be reduced ds , thereby reducing the heat dissipation power consumption of the driving thin-film transistor, and further reducing the power consumption of the display panel.

[0065] In the embodiment of the present application, by making the channel region 113 near the drain region 112 have a lower doping ion concentration, when the drain-source voltage V is applied ds , the channel region 113 near the drain region 112 has a lower majority carrier concentration than the channel region 113 near the source region 111, and a smaller drain-source voltage V dsThis can deplete the carriers in the channel region 113 near the drain region 112, thus creating a pinch-off point and driving the thin-film transistor into the saturation region.

[0066] like Figure 7 As shown, compared with conventional DTFT, the driving thin film transistor in the display panel provided in this application embodiment is a graded channel driving thin film transistor (GD-DTFT). By making the channel region 113 near the drain region 112 have a lower majority carrier concentration, the resistance of the drain region 112 can be increased, so that the lateral voltage drop of the driving thin film transistor in the region near the drain region 112 is larger. Under the same device size, the driving thin film transistor in this application embodiment can have a smaller saturation voltage, thereby reducing the heat dissipation of the driving thin film transistor, and thus reducing the power consumption of the display panel.

[0067] In one embodiment, the channel region 113 includes a first sub-channel region 1131 and a second sub-channel region 1132, the second sub-channel region 1132 being disposed between the first sub-channel region 1131 and the drain region 112, and having a lower majority carrier concentration than the first sub-channel region when no voltage is applied.

[0068] like Figure 2 As shown, the opposite sides of the first sub-channel region 1131 are directly connected to the source region 111 and the second sub-channel region 1132, respectively. The side of the second sub-channel region 1132 facing away from the first sub-channel region 1131 is directly connected to the drain region 112. The orthographic projection of the gate 14 on the substrate 100 overlaps with the orthographic projections of the first sub-channel region 1131 and the second sub-channel region 1132 on the substrate 100.

[0069] In one embodiment, the first sub-channel region 1131 and the second sub-channel region 1132 have the same doping type, and the doping ion concentration of the first sub-channel region 1131 is greater than the doping ion concentration of the second sub-channel region 1132.

[0070] Taking the driving thin-film transistor as a P-type thin-film transistor as an example, both the first sub-channel region 1131 and the second sub-channel region 1132 are P-type doped. The doping element in the first sub-channel region 1131 and the second sub-channel region 1132 can be, but is not limited to, boron. The first sub-channel region 1131 can be doped with a higher concentration of P-type, while the second sub-channel region 1132 can be doped with a lower concentration of P-type. This allows the second sub-channel region 1132 near the drain to have a lower carrier concentration when a drain-source voltage V is applied.ds At that time, a smaller drain-source voltage V ds This depletes the carriers in the second sub-channel region 1132, creating a pinch-off point and driving the thin-film transistor into the saturation region. This allows the driving thin-film transistor to have a smaller saturation voltage, thus reducing the drain-source voltage V during operation. ds This reduces the heat and power consumption when driving thin-film transistors, thereby reducing the power consumption of the display panel.

[0071] The source region 111 and the drain region 112 are doped with the same type as the first sub-channel region 1131, namely P-type doping, and the doping ion concentrations of the source region 111 and the drain region 112 are both greater than the doping ion concentration of the first sub-channel region 1131.

[0072] In one specific embodiment, the source region 111, the drain region 112, and the channel region 113 are all doped with boron ions, and the ion doping dose of the source region 111 and the drain region 112 is 1*10⁻⁶. 15 / cm 2 The doping energy is 40 keV; the ion doping dose of the first sub-channel region 1131 is 2*10⁻⁶. 12 / cm 2 The doping energy is 10 keV; the ion doping dose of the second sub-channel region 1132 is 5*10^6 keV. 11 / cm 2 The doping energy is 10 keV. In practical applications, the ion doping dose of the first sub-channel region 1131 is not limited to 2*10 in the above embodiments. 12 / cm 2 It can also be 1*10 12 / cm 2 1.5*10 12 / cm 2 2.5*10 12 / cm 2 Or 3*10 12 / cm 2 Wait, only needs to be between 1*10 12 / cm 2 Up to 3*10 12 / cm 2 The ion doping dose of the second sub-channel region 1132 is not limited to 5*10 in the above embodiments. 11 / cm 2 It can also be 1*10 11 / cm 2 3*10 11 / cm 2 7*10 11 / cm2 Or 1*10 12 / cm 2 Wait, only those between 0 and 1*10 are required. 12 / cm 2 That's all.

[0073] Taking an N-type thin-film transistor as an example, both the first sub-channel region 1131 and the second sub-channel region 1132 are N-type doped. The doping elements in the first sub-channel region 1131 and the second sub-channel region 1132 can be, but are not limited to, elements such as phosphorus. The first sub-channel region 1131 can be doped with a higher concentration of N-type, while the second sub-channel region 1132 can be doped with a lower concentration of N-type.

[0074] The doping type and doping element of the source region 111 and the drain region 112 can be the same as those of the first sub-channel region 1131, and the doping ion concentration of the source region 111 and the drain region 112 is greater than that of the first sub-channel region 1131.

[0075] In one embodiment, the first sub-channel region is N-type doped or P-type doped, and the second sub-channel region is undoped.

[0076] Taking the driving thin-film transistor as a P-type thin-film transistor as an example, the first sub-channel region 1131 is doped with the same type as the source region 111 and the drain region 112, which is P-type doping. The doping ion concentrations of the source region 111 and the drain region 112 are both greater than the doping ion concentration of the first sub-channel region 1131. The elements doped in the first sub-channel region 1131, the source region 111, and the drain region 112 can be, but are not limited to, elements such as boron. The second sub-channel region 1132 is undoped, that is, the second sub-channel region 1132 is an intrinsic semiconductor.

[0077] In one specific embodiment, the source region 111, the drain region 112, and the first sub-channel region 1131 are all doped with boron ions, and the ion doping dose of the source region 111 and the drain region 112 is 1*10⁻⁶. 15 / cm 2 The doping energy is 40 keV; the ion doping dose of the first sub-channel region 1131 is 1*10⁻⁶. 12 / cm 2 The doping energy is 10keV, and the ion doping dose of the second sub-channel region 1132 is 0, that is, the second sub-channel region 1132 is undoped.

[0078] Taking the driving thin-film transistor as an example, the first sub-channel region 1131 is doped with the same doping type as the source region 111 and the drain region 112, which is N-type doping. The doping ion concentrations of the source region 111 and the drain region 112 are both greater than the doping ion concentration of the first sub-channel region 1131. The elements doped in the first sub-channel region 1131, the source region 111 and the drain region 112 can be, but are not limited to, elements such as phosphorus. The second sub-channel region 1132 is undoped, that is, the second sub-channel region 1132 is an intrinsic semiconductor.

[0079] In one embodiment, the doping type of the first sub-channel region 1131 is different from the doping type of the second sub-channel region 1132.

[0080] Taking a P-type thin-film transistor as an example, the first sub-channel region 1131 is doped with the same type as the source region 111 and the drain region 112, all being P-type doped. Furthermore, the dopant ion concentrations in the source region 111 and the drain region 112 are both greater than the dopant ion concentration in the first sub-channel region 1131. The second sub-channel region 1132 is N-type doped. The dopant element in the second sub-channel region 1132 can be, but is not limited to, elements such as phosphorus. The dopant ion concentration in the second sub-channel region 1132 should be less than the dopant ion concentration in the first sub-channel region 1131.

[0081] Taking an N-type thin-film transistor as an example, the first sub-channel region 1131 is doped with the same type as the source region 111 and the drain region 112, all being N-type doped. Furthermore, the dopant ion concentrations in the source region 111 and the drain region 112 are both greater than the dopant ion concentration in the first sub-channel region 1131. The second sub-channel region 1132 is P-type doped. The dopant element in the second sub-channel region 1132 can be, but is not limited to, boron, etc., and the dopant ion concentration in the second sub-channel region 1132 should be less than the dopant ion concentration in the first sub-channel region 1131.

[0082] In one embodiment, the length of the first sub-channel region 1131 is equal to the length of the second sub-channel region 1132.

[0083] like Figure 2 As shown, in the second direction Y, the length L1 of the first sub-channel region 1131 is equal to the length L2 of the second sub-channel region 1132.

[0084] In one embodiment, the length of the first sub-channel region 1131 is greater than the length of the second sub-channel region 1132.

[0085] like Figure 8 and Figure 9As shown, in the second direction Y, the length L1 of the first sub-channel region 1131 is greater than the length L2 of the second sub-channel region 1132.

[0086] It should be noted that the relationship between the electric field strength in the second sub-channel region 1132 is as follows:

[0087]

[0088] Wherein, E2 is the electric field strength in the second sub-channel region 1132, V2 is the horizontal voltage division of the second sub-channel region 1132, R1 is the resistance of the first sub-channel region 1131, R2 is the resistance of the second sub-channel region 1132, L1 is the channel length of the first sub-channel region 1131, ρ1 is the resistivity of the first sub-channel region 1131, W1 is the channel width of the first sub-channel region 1131, V2 is the horizontal voltage division of the second sub-channel region 1132, L2 is the channel length of the second sub-channel region 1132, W2 is the channel width of the second sub-channel region 1132, and ρ2 is the resistivity of the second sub-channel region 1132. While keeping the length (L1+L2) of the channel region 113 unchanged, increasing the length L1 of the first sub-channel region 1131 and decreasing the length L2 of the second sub-channel region 1132 can increase the electric field intensity E2 in the second sub-channel region 1132.

[0089] In one embodiment, the width of the first sub-channel region 1131 is equal to the width of the second sub-channel region 1132.

[0090] like Figure 2 or Figure 4 As shown, in the first direction X, the width W1 of the first sub-channel region 1131 is equal to the width W2 of the second sub-channel region 1132. The first direction X is perpendicular to the second direction Y, and the third direction Z is perpendicular to the first direction X and the second direction Y. In some other embodiments, the first direction X intersects the second direction Y, but is not perpendicular to it; this is not a unique limitation.

[0091] In one embodiment, the width of the first sub-channel region 1131 is greater than the width of the second sub-channel region 1132.

[0092] like Figure 10 As shown, in the first direction X, the width W1 of the first sub-channel region 1131 is greater than the width W2 of the second sub-channel region 1132, and in the second direction Y, the length L1 of the first sub-channel region 1131 is equal to the length L2 of the second sub-channel region 1132.

[0093] It should be noted that the resistance R1 of the first sub-channel region 1131 is inversely proportional to the width W1 of the first sub-channel region 1131, and the resistance R2 of the second sub-channel region 1132 is also inversely proportional to the width W2 of the second sub-channel region 1132. Increasing the width W1 of the first sub-channel region 1131 can decrease the resistance R1 of the first sub-channel region 1131, and decreasing the width W2 of the second sub-channel region 1132 can increase the resistance R2 of the second sub-channel region 1132. Combining the above-mentioned relationship of the electric field intensity E2 in the second sub-channel region 1132, it can be seen that decreasing the resistance R1 of the first sub-channel region 1131 and increasing the resistance R2 of the second sub-channel region 1132 can increase the electric field intensity in the second sub-channel region 1132.

[0094] In one embodiment, such as Figure 11 As shown, in the second direction Y, the length L1 of the first sub-channel region 1131 is equal to the length L2 of the second sub-channel region 1132. In the first direction X, the width W1 of the first sub-channel region 1131 is greater than the width W2 of the second sub-channel region 1132. This also allows the channel region 113 near the drain to have a lower carrier concentration, thereby reducing the saturation voltage of the driving thin-film transistor and reducing the heat dissipation of the driving thin-film transistor, thus reducing the power consumption of the display panel.

[0095] In one embodiment, the channel region may further include a third sub-channel region 1133, which is disposed between the first sub-channel region 1131 and the second sub-channel region 1132.

[0096] like Figure 12 As shown, the opposite sides of the first sub-channel region 1131 are directly connected to the source region 111 and the third sub-channel region 1133, respectively, and the opposite sides of the second sub-channel region 1132 are directly connected to the third sub-channel region 1133 and the drain region 112, respectively.

[0097] like Figure 13 As shown, the orthogonal projection of the gate 14 onto the substrate 100 can overlap with the first sub-channel region 1131, the second sub-channel region 1132, and the third sub-channel region 1133.

[0098] In one embodiment, the first sub-channel region 1131 has the same doping type as the second sub-channel region 1132 and the third sub-channel region 1133. The doping concentration of the first sub-channel region 1131 is greater than that of the third sub-channel region 1133, and the doping concentration of the third sub-channel region 1133 is greater than that of the second sub-channel region 1132. With this structure, the channel region 113 near the drain can have a lower carrier concentration, thereby reducing the saturation voltage of the driving thin-film transistor and lowering the heat dissipation of the driving thin-film transistor, thus reducing the power consumption of the display panel.

[0099] Taking a P-type thin-film transistor as an example, the first sub-channel region 1131, the second sub-channel region 1132, and the third sub-channel region 1133 are all P-type doped. The dopant concentration in the first sub-channel region 1131 is greater than that in the third sub-channel region 1133, and the dopant concentration in the third sub-channel region 1133 gradually decreases from that in the second sub-channel region 1132. The source region 111 and the drain region 112 are also P-type doped, and the dopant concentration in the first sub-channel region 1131 should be less than that in the source region 111 and the drain region 112.

[0100] Taking an N-type thin-film transistor as an example, the first sub-channel region 1131, the second sub-channel region 1132, and the third sub-channel region 1133 are all N-type doped. The dopant concentration in the first sub-channel region 1131 is greater than that in the third sub-channel region 1133, and the dopant concentration in the third sub-channel region 1133 gradually decreases from that in the second sub-channel region 1132. The source region 111 and the drain region 112 are also N-type doped, and the dopant concentration in the first sub-channel region 1131 should be less than that in the source region 111 and the drain region 112.

[0101] In one embodiment, the first sub-channel region 1131 and the second sub-channel region 1132 have different doping types, and the third sub-channel region 1133 has the same doping type as one of the first sub-channel region 1131 and the second sub-channel region 1132; or, the third sub-channel region 1133 is undoped.

[0102] Taking a P-type thin-film transistor as an example, the first sub-channel region 1131, the source region 111, and the drain region 112 are all P-type doped, and the doping concentration of the first sub-channel region 1131 should be lower than that of the source region 111 and the drain region 112. The second sub-channel region 1132 is N-type doped, and the third sub-channel region 1133 can be either P-type or N-type doped. Alternatively, the third sub-channel region 1133 can be left undoped. This also allows the channel region 113 near the drain to have a lower carrier concentration, thereby reducing the saturation voltage of the driving thin-film transistor, lowering its heat dissipation, and ultimately reducing the power consumption of the display panel.

[0103] Taking the driving thin-film transistor as an example, the first sub-channel region 1131 is N-type doped, the second sub-channel region 1132 is N-type doped, and the third sub-channel region 1133 can be P-type doped or N-type doped. Alternatively, the third sub-channel region 1133 may not be doped.

[0104] In one embodiment, the lengths of the first sub-channel region 1131, the second sub-channel region 1132, and the third sub-channel region 1133 along the second direction Y can be equal or gradually decrease. The widths of the first sub-channel region 1131, the second sub-channel region 1132, and the third sub-channel region 1133 along the first direction X can be equal or gradually decrease; this is not a specific limitation.

[0105] It should be noted that the embodiments of this application only illustrate that the channel region 113 of the active layer 11 is divided into two or three sub-channel regions with different doping ion concentrations or doping types. In practical applications, the channel region 113 is also divided into three or more sub-channel regions. The doping type of each sub-channel region, the relationship between the doping ion concentrations of each sub-channel region, and the relationship between the length and width of each sub-channel region can be referred to the above embodiments, and will not be repeated here.

[0106] Furthermore, the display panel includes multiple pixel driving circuits, each including a driving thin-film transistor, a compensation thin-film transistor, a switching thin-film transistor, and a reset thin-film transistor.

[0107] In the embodiments of this application, the display panel may include one or more switching thin-film transistors. Both the driving thin-film transistor and the switching thin-film transistor are polycrystalline silicon thin-film transistors. Since the switching thin-film transistor only performs the switching function and has no power loss, the channel region of the active layer of the switching thin-film transistor may or may not be doped. When the channel region of the switching thin-film transistor is doped, the doping ion concentration of each part of the channel region of the active layer of the switching thin-film transistor is consistent, and there is no need to differentiate the doping ion concentration of different parts of the channel region of the active layer of the switching thin-film transistor.

[0108] The reset thin-film transistor can be a polysilicon thin-film transistor or an oxide thin-film transistor. When the reset thin-film transistor is a polysilicon thin-film transistor, the channel region of the reset thin-film transistor may or may not be doped. When the channel region of the reset thin-film transistor is doped, the doping ion concentration is uniform in all parts of the channel region of the active layer of the reset thin-film transistor. When the reset thin-film transistor is an oxide thin-film transistor, the channel region of the reset thin-film transistor is undoped.

[0109] The compensation thin-film transistor can also be a polycrystalline silicon thin-film transistor or a silicon oxide thin-film transistor. When the compensation thin-film transistor is a polycrystalline silicon thin-film transistor, the channel region of the compensation thin-film transistor may or may not be doped. When the channel region of the compensation thin-film transistor is doped, the doping ion concentration is uniform in all parts of the channel region of the active layer of the compensation thin-film transistor. When the compensation thin-film transistor is an oxide thin-film transistor, the channel region of the compensation thin-film transistor is undoped.

[0110] In one embodiment, such as Figure 14 As shown, the pixel driving circuit includes a driving thin-film transistor T1, a first switching thin-film transistor T2, a second switching thin-film transistor T5, a third switching thin-film transistor T6, a compensation thin-film transistor T3, a first reset thin-film transistor T4, a second reset thin-film transistor T7, a storage capacitor Cst, and a bootstrap capacitor Cboost. The driving thin-film transistor T1, the first switching thin-film transistor T2, the second switching thin-film transistor T5, the third switching thin-film transistor T6, and the second reset thin-film transistor T7 are all P-type polysilicon thin-film transistors. The compensation thin-film transistor T3 and the first reset thin-film transistor T4 are both N-type oxide thin-film transistors. The active layer channel regions of the first switching thin-film transistor T2, the second switching thin-film transistor T5, the third switching thin-film transistor T6, and the second reset thin-film transistor T7 are all doped with the same doping ion concentration. The active layer channel regions of the compensation thin-film transistor T3 and the first reset thin-film transistor T4 are not doped.

[0111] The source region 111 or source 12 of the driving thin-film transistor T1 is electrically connected to the first terminal of the first switching thin-film transistor T2 and the first terminal of the second switching thin-film transistor T5 at the first node A. The second terminal of the first switching thin-film transistor T2 is electrically connected to the data signal line Data. The second terminal of the second switching thin-film transistor T5 and the first plate of the storage capacitor Cst are both electrically connected to the high-voltage power supply signal line for transmitting the driving voltage VDD. The gate of the first switching thin-film transistor T2 and the first plate of the bootstrap capacitor Cboost are both electrically connected to the first scan signal line Pscan(n).

[0112] The drain region 112 or drain 13 of the driving thin-film transistor T1 is electrically connected to the first terminal of the compensation thin-film transistor T3 and the first terminal of the third switching thin-film transistor T6 at the second node B. The gate of the driving thin-film transistor T1 is electrically connected to the second terminal of the compensation thin-film transistor T3, the first terminal of the first reset thin-film transistor T4, the second plate of the bootstrap capacitor Cboost, and the second plate of the storage capacitor Cst at the third node Q. The second terminal of the first reset thin-film transistor T4 is electrically connected to the first initialization signal line VI1. The gate of the first reset thin-film transistor T4 is electrically connected to the second scan signal line Nscan(n-7). The gate of the compensation transistor T3 is connected to the third scan signal line Nscan(n).

[0113] The second terminal of the third switching thin-film transistor T6, the first terminal of the second reset thin-film transistor T7, and the anode of the light-emitting element 30 are electrically connected to the fourth node C. The cathode of the light-emitting element 30 is connected to the low-voltage power supply signal line for transmitting the cathode voltage VSS. The gates of the second switching thin-film transistor T5 and the third switching thin-film transistor T6 are both electrically connected to the light-emitting control signal line EM. The second terminal of the second reset thin-film transistor T7 is electrically connected to the second initialization signal line VI2. The gate of the second reset thin-film transistor T7 is electrically connected to the first scan signal line Pscan(n).

[0114] It should be noted that the first end of each of the above thin-film transistors can refer to one of the source and drain of the thin-film transistor, and the second end can refer to the other of the source and drain of the thin-film transistor.

[0115] It should also be noted that, Figure 14 The compensation thin-film transistor T3 and the first reset thin-film transistor T4 in the illustrated embodiment can also be P-type polycrystalline silicon thin-film transistors. Figure 14This illustration only shows the position of the driving thin-film transistor T1 in the pixel driving circuit and its connection relationship with the previous switching thin-film transistor, reset thin-film transistor and compensation thin-film transistor in the embodiment of this application. It does not represent the circuit structure of the pixel driving circuit in actual application. The driving thin-film transistor T1 can be applied to the pixel driving circuit of existing OLED display panels and is not limited here.

[0116] The beneficial effects of this application embodiment are as follows: This application embodiment provides a display panel, which includes a power supply high-voltage signal line, a driving thin-film transistor, and a light-emitting element. The driving thin-film transistor includes an active layer, which includes a source region, a drain region, and a channel region. The channel region is disposed between the source region and the drain region. The source region is connected to the power supply high-voltage signal line, and the drain region is connected to the light-emitting element. By making the channel region near the drain region have a lower majority carrier concentration than the channel region near the source region, the voltage drop of the driving thin-film transistor near the drain region can be increased, and the saturation voltage of the driving thin-film transistor can be reduced, thereby reducing the power consumption of the driving thin-film transistor and thus reducing the power consumption of the display panel.

[0117] In summary, although the present application discloses the preferred embodiments as described above, the above preferred embodiments are not intended to limit the present application. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application is based on the scope defined by the claims.

Claims

1. A display panel, characterized in that, The device includes a high-voltage power signal line, a driving thin-film transistor, and a light-emitting element. The driving thin-film transistor includes an active layer, which includes a source region, a drain region, and a channel region. The channel region is disposed between the source region and the drain region. The source region is electrically connected to the high-voltage power signal line, and the drain region is electrically connected to the light-emitting element. The channel region near the drain region has a lower doping ion concentration than the channel region near the source region; the channel region includes a first sub-channel region and a second sub-channel region, the second sub-channel region being disposed between the first sub-channel region and the drain region, and the second sub-channel region having a lower doping ion concentration than the first sub-channel region.

2. The display panel as described in claim 1, characterized in that, The first sub-channel region and the second sub-channel region have the same doping type.

3. The display panel as described in claim 1, characterized in that, The doping type of the first sub-channel region is different from that of the second sub-channel region.

4. The display panel as described in claim 1, characterized in that, The first sub-channel region is N-type doped or P-type doped, while the second sub-channel region is undoped.

5. The display panel as described in any one of claims 2 to 4, characterized in that, The doping type of the first sub-channel region is the same as that of the source region and the drain region, and the doping ion concentration of the first sub-channel region is less than that of the source region and the drain region.

6. The display panel as described in claim 1, characterized in that, The length of the first sub-channel region is greater than or equal to the length of the second sub-channel region.

7. The display panel as described in claim 1, characterized in that, The width of the first sub-channel region is greater than or equal to the width of the second sub-channel region.

8. The display panel as described in claim 1, characterized in that, The trench area includes a third sub-trench area, which is located between the first sub-trench area and the second sub-trench area; The first sub-channel region has the same doping type as the second and third sub-channel regions, the doped ion concentration of the first sub-channel region is greater than that of the third sub-channel region, and the doped ion concentration of the third sub-channel region is greater than that of the second sub-channel region.

9. The display panel as claimed in claim 1, characterized in that, The trench area includes a third sub-trench area, which is located between the first sub-trench area and the second sub-trench area; Wherein, the first sub-channel region and the second sub-channel region have different doping types, and the third sub-channel region has the same doping type as one of the first sub-channel region and the second sub-channel region; or, the third sub-channel region is undoped.

10. The display panel as claimed in claim 1, characterized in that, The display panel includes multiple pixel driving circuits, and the pixel driving circuits include driving thin-film transistors, compensation thin-film transistors, switching thin-film transistors, and reset thin-film transistors. Wherein, the driving thin-film transistor and the switching thin-film transistor are both polycrystalline silicon thin-film transistors, the reset thin-film transistor is a polycrystalline silicon thin-film transistor or an oxide thin-film transistor, the compensation thin-film transistor is a polycrystalline silicon thin-film transistor or an oxide thin-film transistor, and the channel region of the active layer of any one of the reset thin-film transistor, the compensation thin-film transistor and the switching thin-film transistor is undoped or has the same doping ion concentration.

11. The display panel as claimed in claim 10, characterized in that, The pixel driving circuit includes a first switching thin-film transistor, a second switching thin-film transistor, a third switching thin-film transistor, a compensation thin-film transistor, a first reset thin-film transistor, and a second reset thin-film transistor. Wherein, the source region of the driving thin film transistor is electrically connected to the first terminal of the first switching thin film transistor and the first terminal of the second switching thin film transistor at the first node, the second terminal of the first switching thin film transistor is electrically connected to the data signal line, and the second terminal of the second switching thin film transistor is electrically connected to the power supply high voltage signal line; The drain region of the driving thin-film transistor is electrically connected to the first terminal of the compensation thin-film transistor and the first terminal of the third switching thin-film transistor at the second node. The gate of the driving thin film transistor is electrically connected to the second terminal of the compensation thin film transistor and the first terminal of the first reset thin film transistor at a third node, and the second terminal of the first reset thin film transistor is electrically connected to the first initialization signal line. The second terminal of the third switching thin-film transistor is electrically connected to the first terminal of the second reset thin-film transistor and the anode of the light-emitting element at the fourth node. The gates of the second switching thin-film transistor and the third switching thin-film transistor are both electrically connected to the light-emitting control signal line. The second terminal of the second reset thin-film transistor is electrically connected to the second initialization signal line.

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