Semiconductor devices and methods for manufacturing semiconductor devices

Abstract

This invention relates to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes: a substrate; a first nitride semiconductor layer located above the substrate; a second nitride semiconductor layer located above the first nitride semiconductor layer and having a bandgap larger than that of the first nitride semiconductor layer, the second nitride semiconductor layer including a first doped region and a first intrinsic region; a source contact and a drain contact located above the second nitride semiconductor layer; a gate structure located above the second nitride semiconductor layer and between the source contact and the drain contact, the gate structure including a third nitride semiconductor layer and a gate contact located above thereon; and a fourth nitride semiconductor layer located above the second nitride semiconductor layer and between the gate structure contact and the drain contact; wherein, generally along the direction connecting the source contact and the drain contact, the projection of the gate structure toward the substrate overlaps with the projection of the first doped region toward the substrate. This invention improves the gate leakage current effect of the semiconductor device, minimizing or even completely blocking the gate leakage current.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing technology, and particularly relates to nitride-based semiconductor devices. More specifically, this invention relates to a semiconductor device with improved gate leakage current effect and a method for manufacturing the same. Background Technology

[0002] Components containing direct bandgap semiconductors, such as semiconductor components containing III-V materials or III-V compounds (category: III-V compounds), can operate or function under a variety of conditions or in a variety of environments (e.g., at different voltages and frequencies).

[0003] Semiconductor components may include heterojunction bipolar transistors (HBTs), heterojunction field effect transistors (HFETs), high-electron-mobility transistors (HEMTs), and modulation-doped field effect transistors (MODFETs), etc. Summary of the Invention

[0004] The present invention provides a semiconductor device comprising: a substrate; a first nitride semiconductor layer located above the substrate; a second nitride semiconductor layer located above the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer, the second nitride semiconductor layer comprising a first doped region and a first intrinsic region; a source contact and a drain contact located above the second nitride semiconductor layer; a gate structure located above the second nitride semiconductor layer and between the source contact and the drain contact, the gate structure comprising a third nitride semiconductor layer and a gate contact located above thereon; and a fourth nitride semiconductor layer located above the second nitride semiconductor layer and between the gate structure contact and the drain contact; wherein, generally along the direction connecting the source contact and the drain contact, the projection of the gate structure toward the substrate overlaps with the projection of the first doped region toward the substrate.

[0005] This invention provides a semiconductor device comprising: a substrate; a first nitride semiconductor layer located above the substrate; a second nitride semiconductor layer located above the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer, the second nitride semiconductor layer including a first doped region and a first intrinsic region; a source contact and a drain contact located above the second nitride semiconductor layer; and a gate structure located above the second nitride semiconductor layer and between the source contact and the drain contact, comprising a third nitride semiconductor layer and a gate contact located thereon, the third nitride semiconductor layer containing... The gate structure includes a first-doped second doped region and a second-doped second doped region; and a fourth nitride semiconductor layer covering the gate structure and the second nitride semiconductor layer; wherein, generally along the direction connecting the source contact and the drain contact, the maximum width of the first doped region is W1, the maximum width of the second-doped second doped region is W2, and in the direction perpendicular to the direction, the maximum height of the first doped region is H1, the maximum height of the second-doped second doped region is H2, and 0.5≤(H1+H2) / (W1+W2)≤3.

[0006] The present invention provides a method for manufacturing a semiconductor device, comprising: providing a substrate; disposing a first nitride semiconductor layer over the substrate; disposing a second nitride semiconductor layer over the first nitride semiconductor layer, the second nitride semiconductor layer having a bandgap larger than that of the first nitride semiconductor layer; disposing a source contact and a drain contact over the second nitride semiconductor layer; arranging a gate structure over the second nitride semiconductor layer and between the source contact and the drain contact, the gate structure including a third nitride semiconductor layer located over the second nitride semiconductor layer and a gate contact located over the third nitride semiconductor layer; implanting dopant species at an acute angle to the surface of the second nitride semiconductor layer at the junction of the third nitride semiconductor layer and the second nitride semiconductor layer to form a first doped region and a first intrinsic region in the second nitride semiconductor layer; and disposing a fourth nitride semiconductor layer over the second nitride semiconductor layer and between the gate structure and the drain contact.

[0007] It has been found that by using an implantation process to dope non-nitrogen elements (e.g., oxygen), nitrogen elements, or combinations thereof at the acute angle of the junction between the side surface of the gate structure adjacent to the source or drain contact and the upper surface of the second nitride semiconductor layer away from the substrate, and then placing a fourth nitride semiconductor layer above the second nitride semiconductor layer and between the gate structure and the drain contact, the gate leakage current of the semiconductor device can be improved, the gate leakage current can be minimized or even completely blocked, thereby achieving the goals of reducing system power consumption, increasing gate breakdown voltage, and improving device reliability. Attached Figure Description

[0008] When read in conjunction with the accompanying drawings, various aspects of the invention will be readily understood from the following detailed description. It should be noted that the features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0009] The accompanying drawings, which are referred to below, provide a more detailed description of embodiments of the present invention, wherein:

[0010] Figure 1 The image shown is a cross-sectional view of a semiconductor device 100 according to some embodiments of the present invention.

[0011] Figure 2 The one shown is Figure 1 Transmission electron microscope (TEM) image of region A of semiconductor device 100.

[0012] Figure 3 The image shown is a cross-sectional view of a semiconductor device 300 according to some embodiments of the present invention, wherein the second nitride semiconductor layer includes a first doped region.

[0013] Figure 4 The image shown is a transmission electron microscope image of the doped region 105-1 of a semiconductor device 300 according to some embodiments of the present invention.

[0014] Figure 5 The diagram shown is a flowchart of the steps for manufacturing a semiconductor device 300 according to some embodiments of the present invention.

[0015] Figure 6 The one shown is Figure 5 A cross-sectional view of the structure in step S501 of the flowchart.

[0016] Figure 7 The one shown is Figure 5 A cross-sectional view of the structure in step S503 of the flowchart.

[0017] Figure 8 The one shown is Figure 5A cross-sectional view of the structure in step S505 of the flowchart.

[0018] Figure 9 The one shown is Figure 5 A cross-sectional view of the structure in step S507 of the flowchart.

[0019] Figure 10 The one shown is Figure 5 A cross-sectional view of the structure in step S509 of the flowchart.

[0020] Figure 11 The one shown is Figure 5 A cross-sectional view of the structure in step S511 of the flowchart.

[0021] Figure 12 The one shown is Figure 5 A cross-sectional view of the structure in step S513 of the flowchart.

[0022] Figure 13 The diagram shows a cross-sectional view of a semiconductor device 301 according to some embodiments of the present invention, wherein the nitride semiconductor layer 105 includes two doped regions 105-1. Generally along the direction connecting the source contact 107 and the drain contact 109, the projection of the gate structure 111 toward the substrate 101 overlaps with the projection of the doped regions 105-1 toward the substrate 101.

[0023] Figure 14 The image shown is a cross-sectional view of a semiconductor device 302 according to some embodiments of the present invention, wherein the nitride semiconductor layer 113 includes a doped region 113-1 that has been doped once and a doped region 113-2 that has been doped twice, wherein the doped region 113-2 that has been doped twice is in contact with the nitride semiconductor layer 117.

[0024] Figure 15 The image shown is a cross-sectional view of a semiconductor device 303 according to some embodiments of the present invention, wherein the nitride semiconductor layer 113 includes a side 113SW1 adjacent to the drain contact 109, wherein, generally along the direction connecting the source contact 107 and the drain contact 109, the projection of the side 113SW1 toward the substrate 101 overlaps with the projection of the intrinsic region 105-2 toward the substrate 101.

[0025] Figure 16 The image shown is a cross-sectional view of a semiconductor device 304 according to some embodiments of the present invention, wherein the semiconductor device 304 includes a source field plate 721 and a dielectric layer 122. Detailed Implementation

[0026] To ensure clarity and simplicity of the illustrations, unless otherwise specified, the same reference numerals in different figures indicate the same components. The X-direction shown in each figure is generally the direction connecting the source and drain contacts, and the Y-direction is generally perpendicular to the X-direction.

[0027] Furthermore, for the sake of simplicity, descriptions and details of known steps and components may be omitted. Although devices may be described herein as certain n-channel or p-channel devices or certain n-type or p-type doped devices, the invention is also applicable to complementary devices. The use of the terms “generally” or “substantially” means that the values ​​of components have parameters that are expected to be close to the stated values ​​or locations. However, as is well known in the art, there are always small differences that prevent the values ​​or locations from being exactly the stated values ​​or locations. It is generally accepted in the art that a deviation of at least ten percent (10%) (and even up to twenty percent (20%) for some components including semiconductor doping concentrations) is a reasonable deviation from the ideal target exactly as described. The terms “first,” “second,” “third,” etc., in the claims and / or detailed embodiments (as used in part of the component name) are used to distinguish similar components and do not necessarily describe a temporal, spatial, hierarchical, or any other order. It should be understood that the terms thus used are interchangeable where appropriate, and the embodiments described herein can operate in orders other than those described herein or illustrated by example. The reference to "some embodiments" or "some implementations" means that a specific feature, structure, or characteristic described in connection with the implementation is included in at least one embodiment of the invention. Therefore, the phrase "some implementations" appearing in different places throughout this specification does not necessarily refer to the same implementation, but in some cases, it may refer to the same implementation. Furthermore, as will be apparent to those skilled in the art, specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0028] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. In this application, the description in the following description of a first feature forming on or above a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances throughout this application. This repetition is for the purpose of simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0029] Embodiments of the present invention will now be discussed in detail. However, it should be understood that the present invention provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the invention.

[0030] Third-generation semiconductor materials, represented by group III-V materials, have revolutionized the power electronics industry. Compared to first-generation semiconductor materials (such as silicon (Si) or silicon carbide (SiC)) and second-generation semiconductor materials (such as gallium arsenide (GaAs)), third-generation semiconductor materials (such as gallium nitride (GaN)) are superior. Third-generation semiconductor materials possess excellent properties such as large bandgap, high breakdown voltage, high peak electron velocity, high saturated electron drift velocity, as well as excellent heat resistance and good radiation and corrosion resistance. Furthermore, the polarization effect in their heterostructures can create a high-concentration two-dimensional electron gas at the interface, providing a high-mobility, high-carrier-concentration channel transport layer for power devices, making them highly suitable for high-temperature, high-frequency, high-power, and high-breakdown-voltage power electronic devices. Group III-V materials and their heterostructures have shown significant application potential in optoelectronic devices, power electronics, radio frequency (RE) and microwave power amplifiers, lasers, and detectors.

[0031] In the fabrication of GaN-based semiconductor devices, a two-dimensional electron gas is typically achieved at the heterojunction structure of the GaN material system. This two-dimensional electron gas is formed at the AlGaN / GaN interface due to the strong spontaneous polarization and piezoelectric polarization present in the GaN-based heterojunction.

[0032] In AlGaN / GaN material systems, due to extremely strong spontaneous polarization and piezoelectric polarization effects, high-concentration electron channels can be formed even without intentional doping. In this case, since there is no scattering caused by donor impurities in the channel, electrons can move at high speeds, achieving very high electron mobility. The end result is a thin layer of high-concentration, high-mobility electrons in the heterostructure, leading to very low channel resistance. In field-effect transistors (FETs), the conductivity of this layer is changed by applying a bias voltage to the gate electrode, thereby enabling the transistor to function. This is an advantage that second-generation semiconductor materials (such as gallium arsenide) do not possess.

[0033] Because HEMTs exhibit lower impurity scattering and lattice scattering, they offer superior carrier concentration and electron mobility compared to MESFETs. Therefore, GaN materials are highly suitable for manufacturing HEMTs for high-frequency, high-power, or microwave applications. High-frequency, high-power components require high breakdown voltage and high electron velocity. From a power amplifier perspective, third-generation semiconductor HEMTs offer better power density than second-generation semiconductor HEMTs, better meeting the miniaturization requirements of semiconductor devices.

[0034] AlGaN / GaN HEMTs are the most common heterojunction high-mobility transistors. They can be fabricated by sequentially epitaxially growing GaN layers, AlGaN layers, and related structures on a substrate material (e.g., sapphire, silicon, silicon carbide) using techniques such as metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0035] While the inherent physical properties of GaN / AlGaN allow for the simultaneous achievement of high breakdown voltage and high current levels on small semiconductor substrate areas, several different physical effects still limit the breakdown voltage performance of gallium nitride power devices. In most cases, the maximum permissible operating voltage is limited by excessive gate leakage current, which refers to the current that leaks from the gate metal along the sidewalls of the doped nitride semiconductor layer and the interface between the first nitride semiconductor layer and the passivation layer to the source and / or drain. Excessive gate leakage current can suppress the operating voltage of the semiconductor device, degrading its performance and reliability.

[0036] Gallium nitride on silicon (GaN-on-Si) has become a recent trend in process technology development. Silicon substrates offer cost advantages, and GaN-on-Si is compatible with modern silicon semiconductor processes. However, due to a high lattice mismatch of approximately 4.2% between silicon and gallium, surface tension leads to a high surface dislocation density (TDD) in the gallium lattice, reducing device performance. Furthermore, the difference in thermal expansion coefficients between gallium nitride and silicon is as high as 34%, which can cause epitaxial film cracking or silicon substrate bending deformation during crystal growth or at room temperature. Poor crystal quality of the epitaxial film results in a high surface defect density; therefore, even after passivation, GaN-on-Si HEMTs still exhibit 10-1 surface defects at gate operating voltages of 5 to 6 MΩ. -12 A / mm to 10 -8 Gate leakage current is around A / mm. It has been found that when silicon-based gallium nitride HEMTs are used in circuits such as comparators or oscillators, 10 -12 A / mm to 10 -8 A gate leakage current of around A / mm will still cause premature breakdown at an operating voltage of 6-8M and system power consumption of around 10Watt, thereby reducing system efficiency by about 5%. Such a reduction in system efficiency makes it impossible to meet industry standards and requirements.

[0037] Figure 1The diagram shown is a cross-sectional view of a semiconductor device 100 according to some embodiments of the present invention. The semiconductor device 100 includes: a substrate 101; a nitride semiconductor layer 103 located above the substrate 101; a nitride semiconductor layer 105 located above the nitride semiconductor layer 103 and having a band gap larger than that of the nitride semiconductor layer 103, the nitride semiconductor layer 105 having a surface 105SF1 and a surface 105SF2, the surface 105SF1 contacting the nitride semiconductor layer 103, and the surface 105SF2 located on the opposite side of the surface 105SF1; a source contact 107 and a drain contact 109, at least partially buried in the nitride semiconductor layer 105 and located on the surface of the nitride semiconductor layer 105. Above surface 105SF1; gate structure 111, located above nitride semiconductor layer 105 and between source contact 107 and drain contact 109, gate structure 111 includes nitride semiconductor layer 113 and gate electrode 115 located above it, nitride semiconductor layer 113 has surface 113SF3 and surface 113SF4, surface 113SF3 contacts surface 105SF2 of nitride semiconductor layer 105, surface 113SF4 contacts gate electrode 115; and nitride semiconductor layer 117, located above nitride semiconductor layer 105 and between gate contact 107 and drain contact 109.

[0038] During the free growth process, the nitride semiconductor layer 117 will crystallize. The crystallized areas appear as atomically packed regions in failure analysis. Transmission electron microscopy (TEM) images of these crystallized areas are shown below. Figure 2 As shown. When a voltage is applied to the semiconductor device 100, the movement of electrons through the atomic stacking region generates a leakage current effect.

[0039] Figure 2 The one shown is Figure 1 A transmission electron microscope image of region A of semiconductor device 100. Due to... Figure 1 The junction of the nitride semiconductor layer 105 and the nitride semiconductor layer 113 on the side of the gate structure 111 on the substrate 100 of the semiconductor device is undoped, therefore, the nitride semiconductor layer 117 has high crystallinity.

[0040] Figure 3 and Figure 4 Cross-sectional views of a semiconductor device 300 according to some embodiments of the present invention are shown, drawn generally along the line connecting the source contact 107 and the drain contact 109.

[0041] Semiconductor device 300 includes: a substrate 101; a nitride semiconductor layer 103; a nitride semiconductor layer 105; a source contact 107; a drain contact 109; a gate structure 111 including a nitride semiconductor layer 113 and a gate electrode 115 located thereon; and a nitride semiconductor layer 117.

[0042] The nitride semiconductor layer 103 is located above the substrate 101.

[0043] A nitride semiconductor layer 105 is located above a nitride semiconductor layer 103 and has a larger band gap than the nitride semiconductor layer 103. The nitride semiconductor layer 105 has a surface 105SF1 and a surface 105SF2, with surface 105SF1 in contact with the nitride semiconductor layer 103 and surface 105SF2 located on the opposite side of surface 105SF1. The nitride semiconductor layer 105 includes a doped region 105-1 and an intrinsic region 105-2.

[0044] The doped region 105-1 is in contact with the nitride semiconductor 113. The doped region 105-1 is in contact with the nitride semiconductor 117. The doped region 105-1 is in contact with one side 113SW1 of the nitride semiconductor layer 113 adjacent to the drain contact 109. The top surface of the doped region 105-1 is coplanar with the bottom surface of the nitride semiconductor 113. The top surface of the doped region 105-1 is coplanar with the bottom surface of the nitride semiconductor 117.

[0045] Intrinsic region 105-2 is in contact with nitride semiconductor 113. Intrinsic region 105-2 is in contact with nitride semiconductor 117. The top surface of intrinsic region 105-2 is coplanar with the top surface of doped region 105-1. The top surface of intrinsic region 105-2 is coplanar with the top surface of doped region 105-1. The top surface of intrinsic region 105-2 is coplanar with the bottom surface of nitride semiconductor 113. The top surface of intrinsic region 105-2 is coplanar with the bottom surface of nitride semiconductor 117.

[0046] Intrinsic region 105-2 at least partially surrounds doped region 105-1. The perimeter of doped region 105-1 is generally parallel to a cross-section of substrate 101, one of which is further away from substrate 101 than surface 105SF1. The perimeter of intrinsic region 105-1 is generally perpendicular to a cross-section of substrate 101, one of which lies between nitride semiconductor 113 and drain contact 109. The perimeter of doped region 105-1 is generally parallel to a cross-section of substrate 101, one of which lies above surface 105SF1. The perimeter of doped region 105-1 is generally perpendicular to a cross-section of substrate 101, one of which lies between gate electrode 115 and drain contact 109. The perimeter of doped region 105-1 is generally perpendicular to a cross-section of substrate 101, one of which intersects nitride semiconductor 113. One of the generally perpendicular cross-sections of the perimeter of the doped region 105-1 to the substrate 101 intersects the gate electrode 115. One of the generally perpendicular cross-sections of the perimeter of the doped region 105-1 to the substrate 101 intersects the nitride semiconductor 117. One of the generally perpendicular cross-sections of the perimeter of the doped region 105-1 to the substrate 101 is coplanar with one side 113SW1 of the nitride semiconductor layer 113 adjacent to the drain contact 109.

[0047] The source contact 107 and the drain contact 109 are at least partially buried in the nitride semiconductor layer 105 and are located above the surface 105SF1 of the nitride semiconductor layer 105.

[0048] Gate structure 111 is located above nitride semiconductor layer 105. Gate structure 111 is located between source contact 107 and drain contact 109. Gate structure 111 includes nitride semiconductor layer 113 and gate electrode 115 located above it. Nitride semiconductor layer 113 has surface 113SF3 and surface 113SF4, surface 113SF3 contacts surface 105SF2 of nitride semiconductor layer 105, and surface 113SF4 contacts gate electrode 115.

[0049] The junction between the nitride semiconductor layer 113 in the semiconductor device 300 and the drain contact 109 on one side 113SW1 and the nitride semiconductor layer 105 is doped.

[0050] Generally along the direction connecting the source contact 107 and the drain contact 109, the projection of the gate structure 111 toward the substrate 101 overlaps with the projection of the doped region 105-1 toward the substrate 101.

[0051] The semiconductor device 300 according to the present invention can operate at a variety of voltage levels. For example, the semiconductor device 300 can operate at relatively high voltage levels (e.g., equal to or greater than about 200V).

[0052] Substrate 101 can be any semiconductor substrate known in the art, including but not limited to silicon (Si), doped silicon, silicon carbide (SiC), gallium nitride, zinc oxide, silicon carbide (SiC), germanium silicide (SiGe), gallium arsenide (GaAs), sapphire, silicon-on-insulator (SOI), or other suitable materials, preferably silicon. Substrate 301 may also include doped regions (not shown in the figure), such as p-wells, n-wells, or the like. Exemplary dopants may include, for example, but not limited to, magnesium (Mg), zinc (Zn), cadmium (Cd), silicon (Si), germanium (Ge), etc. Substrate 301 may also include impurities. Substrate 101 has an active layer and a back surface opposite to the active layer, on which an integrated circuit can be formed.

[0053] The nitride semiconductor layer 103 may be formed over the substrate 101 and may include, but is not limited to, group III nitrides, for example, those represented by the formula In x Al y Ga 1-x-y Compounds of N, wherein x + y ≤ 1. Group III nitrides may further include, but are not limited to, for example, those represented by the formula Al. y Ga (1-y) A compound of N, wherein y ≤ 1. Preferably, the nitride semiconductor layer 103 may comprise a GaN layer having a band gap of about 3.4 eV. The thickness of the nitride semiconductor layer 103 along the Y direction may be from about 100 nm to about 1000 nm, preferably from about 100 nm to about 500 nm.

[0054] The nitride semiconductor layer 103 and the substrate 101 can be made of the same material, such as but not limited to GaN. During epitaxial growth, there is no problem of mismatch between the lattice constant or thermal expansion coefficient between the nitride semiconductor layer 103 and the substrate 101. Therefore, the nitride semiconductor layer 103 can be grown directly on the substrate 101 and in contact with the substrate 101 without the need for a buffer layer.

[0055] The nitride semiconductor layer 103 and the substrate 101 are heterogeneous materials. Because the nitride semiconductor layer 103 and the substrate 101 have different lattice constants and coefficients of thermal expansion, a large number of dislocations and cracks are typically generated during epitaxial growth, thereby reducing the efficiency of the semiconductor device 300 and even causing it to fail. To avoid this, a buffer layer (not shown in the figure) can be formed between the substrate 101 and the nitride semiconductor layer 103. The buffer layer can be used to promote lattice matching between the nitride semiconductor layer 103 and the substrate 101, thereby reducing interfacial stress and / or thermal stress in the heterogeneous materials, and thus improving the defect and crack density in the nitride semiconductor layer 103. Suitable materials for the buffer layer include, but are not limited to, oxides (e.g., zinc oxide) or nitrides (e.g., aluminum nitride (AlN), aluminum gallium nitride (AlGaN)).

[0056] A superlattice layer (not shown in the figure) can be formed on the buffer layer. The superlattice layer can be a complex layer or a stack of complex layers, such as multiple stacks of AlGaN / GaN layers or AlN / GaN layers. The superlattice layer can reduce the tensile stress of the semiconductor device. The superlattice layer can also prevent defects (such as dislocations) from traveling from the underlying layer (such as the buffer layer) into the nitride semiconductor layer 103, thereby increasing the crystal quality of the nitride semiconductor layer 103 and preventing the semiconductor device 300 from failing. The superlattice layer can trap electrons diffused from the substrate 101 to the nitride semiconductor layer 103, thereby improving the reliability of the semiconductor device 300. The superlattice layer can reduce electron trapping. Along the Y direction, the thickness of the superlattice layer is typically about 1 μm to 4 μm, which is thicker than the buffer layer.

[0057] In high-voltage applications, to prevent voltage from directly breaking down to the substrate 101, the buffer layer or superlattice layer may be doped with other heterogeneous elements, such as, but not limited to, carbon, oxygen, or nitrogen, which may be intentionally or unintentionally doped.

[0058] A nitride semiconductor layer 105 is formed above the nitride semiconductor layer 103. The band gap of the nitride semiconductor layer 105 may be larger than that of the nitride semiconductor layer 103. The nitride semiconductor layer 105 has a surface 105SF1 and a surface 105SF2, with surface 105SF1 in contact with the nitride semiconductor layer 103 and surface 105SF2 located on the opposite side of surface 105SF1. The nitride semiconductor layer 105 may include, but is not limited to, group III nitrides, for example, those expressed as In... x Al y Ga 1-x-y Compounds of N, where x + y ≤ 1. Group III nitrides may further include, but are not limited to, for example, those expressed as Al. y Ga (1-y)A compound of N, where y ≤ 1. Preferably, the nitride semiconductor layer 105 may comprise an AlGaN layer having a band gap of about 4 eV. The nitride semiconductor layer 105 includes a doped region 105-1 and an intrinsic region 105-2. Along the Y direction, the nitride semiconductor layer 105 may have a thickness of about 10 to about 30 nm, preferably, along the Y direction, the nitride semiconductor layer 105 has a thickness of about 10 to about 20 nm.

[0059] A heterojunction can be formed between nitride semiconductor layer 103 and nitride semiconductor layer 105, for example at the interface between nitride semiconductor layer 103 and nitride semiconductor layer 105. The polarization of the heterojunctions of different nitrides forms a two-dimensional electron gas (2DEG) region adjacent to the interface between nitride semiconductor layer 103 and nitride semiconductor layer 105. The 2DEG region can be formed in nitride semiconductor layer 103. Nitride semiconductor layer 103 can provide electrons to or remove electrons from the 2DEG region, thereby controlling the conduction of the semiconductor device 300.

[0060] Source contact 107 and drain contact 109 are disposed above nitride semiconductor layer 105. Source contact 107 and drain contact 109 are at least partially buried in nitride semiconductor layer 105 and located above surface 105SF1 of nitride semiconductor layer 105. The metal of source contact 307 and drain contact 309 forms an ohmic contact with nitride semiconductor layer 105 to collect electrons or provide electrons to the channel region. The metals used to form the source contact 307 and drain contact 307 may include refractory metals or compounds thereof, such as, but not limited to, aluminum (Al), titanium (Ti), niobium (Nb), molybdenum (MO), tantalum (Ta), tungsten (W), rhenium (Re), titanium (Ti), vanadium (V), chromium (Cr), zirconium (Zr), hafnium (Hf), ruthenium (Ru), osmium (Os), iridium (Ir), and compounds of such metals, such as tantalum nitride (TaN), titanium nitride (TiN), tungsten carbide (WC), etc. Those skilled in the art will understand that the source contact 307 and drain contact 309 may be formed from a single metal or a stack of metals (such as tungsten and / or titanium or other well-known electrode materials).

[0061] Gate structure 111 is located above nitride semiconductor layer 305. Gate structure 311 is located between source contact 107 and drain contact 109. Gate structure 111 includes nitride semiconductor layer 113 and gate electrode 115 located thereon. Nitride semiconductor layer 113 has surface 113SF3 and surface 113SF4, surface 113SF3 contacts surface 105SF2 of nitride semiconductor layer 105, and surface 113SF4 contacts gate electrode 115. Gate structure 111 can be formed using a gate first process, i.e., the gate structure 111 is formed before the source contact 107 and drain contact 109 are formed. Gate structure 311 can also be formed using a gate last process, i.e., the gate structure 111 is formed after the source contact 107 and drain contact 109 are formed.

[0062] The nitride semiconductor layer 113 in the gate structure 111 includes a first-doped doped region 113-1 and a second-doped doped region 113-2. The term "first-doped" means that the intrinsic nitride semiconductor layer 113 has undergone one doping process, and the first-doped nitride semiconductor layer 113 may contain one or more doped materials. The term "second-doped" means that the first-doped nitride semiconductor layer 113 has undergone another doping process, and the doped material used in the second doping can be the same as or different from that used in the first doping, for example, but not limited to: non-nitrogen elements, nitrogen elements, or combinations thereof. The nitride semiconductor layer 113 contains p-type doped group III-V materials. Preferably, the nitride semiconductor layer 113 contains p-type doped group III nitrides, for example, represented by the formula Al. y Ga (1-y) A compound of N, where y ≤ 1. More preferably, the nitride semiconductor layer 113 comprises p-type doped GaN. The doped region 113-2 is a region further doped with a non-nitrogen element, a nitrogen element, or a combination thereof on the basis of the nitride semiconductor layer 113. The width of the nitride semiconductor layer 311 may be between about 0.5 μm and about 1.5 μm. Along the X direction, the width of the nitride semiconductor layer 311 may be between about 0.8 μm and about 1.2 μm. Preferably, along the X direction, the width of the nitride semiconductor layer 311 is about 1.0 μm.

[0063] The gate electrode 115 in the gate structure 111 may be or includes a gate metal. The gate metal may include, for example, but not limited to, titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), copper (Cu), nickel (Ni), platinum (Pt), lead (Pb), molybdenum (Mo) and their compounds (e.g., but not limited to titanium nitride (TiN), tantalum nitride (TaN), other conductive nitrides, or conductive oxides), metal alloys (e.g., aluminum-copper alloys (Al-Cu)), or other suitable materials. The gate electrode 115 comprises a single metal. The gate electrode 115 comprises a metal stack (such as tungsten and / or titanium or other well-known electrode materials).

[0064] The nitride semiconductor layer 113 includes a side 113SW1 adjacent to the drain contact 109 and a side 113SW2 adjacent to the source contact 107. Generally, along the direction connecting the source contact 107 and the drain contact 109, the projection of side 113SW1 toward the substrate 101 overlaps with the projection of the intrinsic region 105-2 toward the substrate 101. The junction of side 113SW1 and the surface 105SF2 of the nitride semiconductor layer 105 has a doped region 113-2, which is doped with a non-nitrogen element, a nitrogen element, or a combination thereof, and is a secondary doped region. The outline of the doped region 113-2 is not particularly limited; for example, it can be linear, radial, circular, semi-circular, elliptical, rectangular, irregular, etc. Figure 3 and Figure 4 As shown, along the X direction, the doped region 311-2, which has undergone secondary doping, has a maximum width W1 that is generally parallel to the nitride semiconductor layer 105, and a maximum height H1 along the Y direction that is generally perpendicular to one side 113SW1 of the nitride semiconductor layer 113. The ratio of the maximum height H1 to the maximum width W1 is between about 0.5 and about 3, preferably between about 0.5 and about 2, and more preferably between about 0.5 and about 1.5. There are no particular limitations on the manner in which the doping step is performed; it can be carried out by any process known to those skilled in the art, preferably by an implantation process.

[0065] Because the nitride semiconductor layer 103 has created an actual channel (electron channel region) below the gate electrode 115, it is preset to be in the ON state when the gate electrode 115 is in the zero-bias state. Such a device can also be called a depletion-type device. When the gate electrode 115 is in the zero-bias state, the 2DEG region formed under the nitride semiconductor layer 113 can be preset to be in the OFF state. When a voltage is applied to the gate electrode 115, electrons or charges are induced in the 2DEG region below the gate electrode 115. As the voltage increases, the number of induced electrons or charges also increases. Such a device can be called an enhancement-type device. When the gate electrode 115 is in the zero-bias state, no current flows through the semiconductor device, that is, the threshold voltage of the semiconductor device is positive. At this time, the gate electrode 115 being a doped p-type III-V material can help reduce leakage current and increase the threshold voltage.

[0066] The nitride semiconductor layer 117 can conformally cover the gate structure 111 and the nitride semiconductor layer 105 located between the source contact 107 and the drain contact 109. The nitride semiconductor layer 117 may include, but is not limited to, for example, a structure represented by the formula Al. y Ga (1-y) A compound of N, where y ≤ 1. Preferably, the nitride semiconductor layer 313 is an AlN layer. The thickness of the nitride semiconductor layer 117 along the Y direction can be approximately... to approximately between.

[0067] Figure 4 The image shown is a transmission electron microscope (TEM) image of a doped region 105-1 of a semiconductor device 300 according to some embodiments of the present invention. The junction of the nitride semiconductor layer 113 near the drain 109 (side 113SW1) of the gate structure of the semiconductor device 300 and the surface 105SF2 of the nitride semiconductor layer 105 is doped at an acute angle using an implantation process with non-nitrogen elements, nitrogen elements, or combinations thereof, forming the doped region 105-1. This significantly reduces the crystallinity of the subsequently formed nitride semiconductor layer 117, resulting in fewer free electrons. When a voltage is applied, fewer electrons move, and since the electron movement per unit time is reduced, the current decreases, thereby reducing leakage current.

[0068] The semiconductor component 300 according to the present invention may include a heterojunction bipolar transistor (HBT), a heterojunction field-effect transistor (HFET), a high electron mobility transistor (HEMT), a modulated doped FET (MODFET), or the like.

[0069] refer to Figure 5 It displays flowcharts of relevant steps in a method for manufacturing a semiconductor device according to some embodiments of the present invention. Additionally, Figures 6 to 16The figures shown represent some steps or operations involved in manufacturing a semiconductor device according to some embodiments of the present invention.

[0070] refer to Figure 5 and Figure 6 In step S501, a substrate 101 is provided. The substrate 101 can be any semiconductor substrate known to those skilled in the art, including but not limited to silicon (Si), doped silicon, silicon carbide (SiC), gallium nitride, zinc oxide, silicon carbide (SiC), germanium silicide (SiGe), gallium arsenide (GaAs), sapphire, silicon-on-insulator (SOI), or other suitable materials, preferably silicon.

[0071] refer to Figure 5 and Figure 7 In step S503, a nitride semiconductor layer 103 is formed over the substrate 101. The nitride semiconductor layer 103 can be formed using any semiconductor manufacturing technique known to those skilled in the art. For example, the nitride semiconductor layer 103 can be formed through physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), electroplating, and / or other suitable deposition steps. Preferably, the nitride semiconductor layer 103 is formed through ALD. The thickness of the nitride semiconductor layer 103 is not particularly limited; typically, the thickness along the Y direction can be from about 100 nm to about 1000 nm, preferably from about 100 nm to about 500 nm.

[0072] The nitride semiconductor layer 303 is grown directly on the substrate 301 and is in contact with the substrate 101. Since the nitride semiconductor layer 103 and the substrate 101 are heterogeneous materials, to avoid misalignment and cracks during epitaxial growth, the method of the present invention may further include forming a nucleation layer (not shown in the figure) between the substrate 101 and the nitride semiconductor layer 103. The method of the present invention may further include forming a buffer layer (not shown in the figure) between the substrate 101 and the nitride semiconductor layer 103. The buffer layer can be formed using any semiconductor manufacturing technique known to those skilled in the art. Suitable materials for the buffer layer include, but are not limited to, oxides (e.g., zinc oxide) or nitrides (e.g., aluminum nitride (AlN), aluminum gallium nitride (AlGaN)).

[0073] The method of the present invention further includes the step of forming a superlattice layer (not shown) on a buffer layer. The superlattice layer can reduce the tensile stress of the semiconductor device 300 and prevent defects (e.g., dislocations) from the underlying layer (e.g., the buffer layer) into the nitride semiconductor layer 103. Therefore, the crystal quality of the nitride semiconductor layer 103 can be increased, thereby preventing semiconductor device 300 failure and improving its reliability. Any semiconductor manufacturing technique known to those skilled in the art can be used to form the superlattice layer. There is no particular limitation on the thickness of the superlattice layer; typically, the thickness along the Y direction is from about 1 μm to about 4 μm, which is thicker than the buffer layer.

[0074] refer to Figure 5 and Figure 8 In step S505, a nitride semiconductor layer 105 is formed over the nitride semiconductor layer 103, the nitride semiconductor layer 105 having a larger band gap than the nitride semiconductor. The nitride semiconductor layer 105 can be formed using any semiconductor manufacturing technique known to those skilled in the art. For example, the nitride semiconductor layer 105 can be formed through physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), electroplating, and / or other suitable deposition steps. Preferably, the nitride semiconductor layer 105 is formed through ALD.

[0075] refer to Figure 5 and Figure 9 In step S507, a source contact 107 is formed above the nitride semiconductor layer 105. A drain contact 109 is formed above the nitride semiconductor layer 105. The source contact 107 and drain contact 109 can be formed using any semiconductor known to those skilled in the art.

[0076] refer to Figure 6 and Figure 10In step S509, a gate structure 111 is disposed above the second nitride semiconductor layer 305. The gate structure 111 is disposed between the source contact 107 and the drain contact 109. The relative distance between the gate structure 111 and the source and drain contacts 107 can be adjusted according to design requirements. The distance between the gate structure 111 and the source contact 107 is greater than the distance between the gate structure 111 and the drain contact 109. The distance between the gate structure 111 and the source contact 107 is equal to the distance between the gate structure 111 and the drain contact 109. The distance between the gate structure 111 and the source contact 107 is less than the distance between the gate structure 111 and the drain contact 109. Gate structure 111 includes a nitride semiconductor layer 113 located above nitride semiconductor layer 105, and a gate electrode 115 located above the third nitride semiconductor layer 113. The nitride semiconductor layer 113 has a side 113SW1 adjacent to the drain contact 109. The nitride semiconductor layer 113 has a side 113SW2 adjacent to the source contact 307. The gate electrode 115 can be formed using any semiconductor manufacturing technique known to those skilled in the art, including but not limited to deposition, photolithography, and etching processes.

[0077] refer to Figure 5 and Figure 11In step S511, a non-nitrogen element, a nitrogen element, or a combination thereof is doped at the junction of the surface 105SF2 of the nitride semiconductor layer 105 and one side 113SW1 of the nitride semiconductor layer 113 using an implantation process acute angle. The term "acute angle" refers to the angle along the surface 105SF2 of the nitride semiconductor layer 105. Preferably, the acute angle is an angle of approximately 25° to approximately 45° along the surface 105SF2 of the nitride semiconductor layer 105. More preferably, the acute angle is an angle of approximately 35° to approximately 45° along the surface 105SF2 of the nitride semiconductor layer 105. The nitride semiconductor layer 105 includes a doped region 105-1 and an intrinsic region 105-2. The outline of the doped region 105-1 is not particularly limited; for example, it can be linear, radial, circular, semi-circular, elliptical, rectangular, irregular, etc. Here, the doped region 105-1 is configured such that the perimeter of the doped region 105-1 is substantially perpendicular to a cross-section of the substrate 101, one of which is coplanar with one side 113SW1 of the nitride semiconductor layer 113 adjacent to the drain contact 109. One of the cross-sections of the doped region 105-1 substantially perpendicular to the cross-section of the substrate 101 is located between the nitride semiconductor layer 113 and the drain contact 109. One of the cross-sections of the doped region 105-1 substantially perpendicular to the cross-section of the substrate 101 is located between the gate electrode 115 and the drain contact 109. One of the cross-sections of the doped region 105-1 substantially perpendicular to the cross-section of the substrate 101 intersects with the nitride semiconductor layer 113. One of the cross-sections of the doped region 105-1 substantially perpendicular to the cross-section of the substrate 101 intersects with the gate electrode 115.

[0078] refer to Figure 5 and Figure 12 In step S513, a nitride semiconductor layer 117 is formed, which conformally covers the gate structure 111 and the nitride semiconductor layer 105 located between the source contact 107 and the drain contact 109. The nitride semiconductor layer 117 can be formed using any semiconductor manufacturing technique known in the art. For example, the nitride semiconductor layer 117 can be formed through physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, and / or other suitable deposition methods. Preferably, the nitride semiconductor layer 117 is formed through ALD.

[0079] Reference Figure 12The doped region 105-1 has a maximum width W1 generally along the direction connecting the source contact 107 and the drain contact 109. The doped region 105-1 has a maximum height H1 generally perpendicular to one side 113SW1 of the third nitride semiconductor layer 113. The ratio of the maximum height H1 to the maximum width W1 is between about 0.5 and about 3, preferably between about 0.5 and about 2, and more preferably between about 0.5 and about 1.5.

[0080] Figure 13 The semiconductor device 301 shown is largely the same as Figure 3 The semiconductor device 300 shown differs in that it includes two distinct doped regions 105-1 and 105-1', further improving the gate leakage current of the semiconductor device 301. The configuration of the doped region 105-1' is largely the same as that of the doped region 105-1', except that one of the generally perpendicular cross-sections of the doped region 105-1' to the substrate 101 is coplanar with one side 113SW2 of the nitride semiconductor layer 113 adjacent to the drain contact 109. One of the generally perpendicular cross-sections of the doped region 105-1' to the substrate 101 is located between the source contact 107 and the nitride semiconductor layer 113. Another generally perpendicular cross-section of the doped region 105-1' to the substrate 101 is located between the source contact 107 and the gate electrode 115.

[0081] Figure 14 The semiconductor device 302 shown is largely the same as Figure 3 The semiconductor device 300 shown differs in that it includes a doped region 113-1 that has undergone primary doping and a doped region 113-2 that has undergone secondary doping. In the semiconductor device 302 of the present invention, the doped region 105-1 of the nitride semiconductor layer 105 and the doped region 113-2 of the nitride semiconductor layer 113 constitute a common region located between the nitride semiconductor layer 105 and the nitride semiconductor layer 113. The doped region 113-2 of the nitride semiconductor layer 113 is in contact with the nitride semiconductor layer 117. In the semiconductor device 302 of the present invention, the nitride semiconductor layer 113 includes a side 113SW1 adjacent to the drain contact 109, wherein, generally along the direction connecting the source contact 107 and the drain contact 109, the projection of side 113SW1 toward the substrate 101 overlaps with the projection of the intrinsic region 105-2 toward the substrate 101.

[0082] The contour perimeter of the secondary doped region 113-2 is generally parallel to the cross-section of the substrate 101, one of which intersects with the source contact 107. The contour perimeter of the secondary doped region 113-2 is generally parallel to the cross-section of the substrate 101, one of which intersects with the drain contact 109. The contour perimeter of the secondary doped region 113-2 is generally parallel to the cross-section of the substrate 101, one of which lies below the surface 113SF4. The surface 113SF4 is further away from the substrate 101 than the contour perimeter of the secondary doped region 113-2 which is generally parallel to the cross-section of the substrate 101. The bottom surface of the secondary doped region 113-2 is coplanar with the bottom surface of the primary doped region 113-1. The bottom surface of the secondary doped region 113-2 is coplanar with the bottom surface of the nitride semiconductor layer 113. The bottom surface of the first-doped region 113-1 is coplanar with the bottom surface of the nitride semiconductor layer 113. The bottom surface of the first-doped region 113-1 is coplanar with the bottom surface of the nitride semiconductor layer 117. The bottom surface of the second-doped region 113-2 is coplanar with the bottom surface of the nitride semiconductor layer 117. The bottom surface of the first-doped region 113-1 is coplanar with the top surface of the doped region 105-1. The bottom surface of the first-doped region 113-1 is coplanar with the top surface of the intrinsic region 105-2. The bottom surface of the first-doped region 113-1 is coplanar with the top surface of the nitride semiconductor layer 105. The second-doped region 113-2 is in contact with the doped region 105-1.

[0083] One of the contours of the doped region 113-2, which is substantially perpendicular to the cross-section of the substrate 101, is coplanar with one side 113SW1 of the nitride semiconductor layer 113 adjacent to the drain contact 109. One of the contours of the doped region 113-2, which is substantially perpendicular to the cross-section of the substrate 101, is coplanar with one of the contours of the doped region 105-1, which is substantially perpendicular to the cross-section of the substrate 101. One of the contours of the doped region 113-2, which is substantially perpendicular to the cross-section of the substrate 101, intersects with the doped region 105-1. One of the contours of the doped region 105-1, which is substantially perpendicular to the cross-section of the substrate 101, intersects with the doped region 113-2. One of the contours of the doped region 113-2, which is substantially perpendicular to the cross-section of the substrate 101, intersects with the gate electrode 115. One of the doped regions 113-2, whose outlines are generally perpendicular to the cross-section of the substrate 101, lies between the boundary of the intrinsic region 105-2, whose outlines are generally perpendicular to the cross-section of the substrate 101, and one of them, adjacent to the drain contact 109 of the nitride semiconductor layer 113, on one side 113SW1. Similarly, one of the doped regions 105-1, whose outlines are generally perpendicular to the cross-section of the substrate 101, lies between the boundary of the doped region 113-2, whose outlines are generally perpendicular to the cross-section of the substrate 101, and one of them, adjacent to the drain contact 109 of the nitride semiconductor layer 113, on one side 113SW1.

[0084] Figure 15 The semiconductor device 303 shown is largely the same as semiconductor device 302, with the following differences: one of the contours of the doped region 113-2, which is substantially perpendicular to the cross-section of the substrate 101, is coplanar with one side 113SW1 of the nitride semiconductor layer 113 adjacent to the drain contact 109; one of the contours of the doped region 105-1, which is substantially perpendicular to the cross-section of the substrate 101, is located between the nitride semiconductor layer 113 and the source contact 109. One of the contours of the doped region 113-2, which is substantially perpendicular to the cross-section of the substrate 101, is located between one and the other of the contours of the doped region 105-1, which is substantially perpendicular to the cross-section of the substrate 101. In the semiconductor device 303 of the present invention, the doped region 105-1 of the nitride semiconductor layer 105 and the doped region 113-2 of the doped region 113, which is substantially doped, constitute a common region. In the semiconductor device 303 of the present invention, the nitride semiconductor layer 113 includes a side 113SW1 adjacent to the drain contact 109, wherein, generally along the direction connecting the source contact 307 and the drain contact 309, the projection of side 113SW1 toward the substrate 101 overlaps with the projection of the intrinsic region 105-2 toward the substrate 101.

[0085] In the semiconductor device 300 of the present invention, generally along the direction connecting the source contact 107 and the drain contact 109, the maximum width of the doped region 105-1 of the nitride semiconductor layer 105 is W1, and the maximum width of the doped region 113-2 (which is doped twice) is W2. In the direction perpendicular to the direction, the maximum height of the doped region 105-1 is H1, and the maximum height of the doped region 113-2 (which is doped twice) is H2, where 0.5 ≤ (H1 + H2) / (W1 + W2) ≤ 3. In the direction perpendicular to the direction, the nitride semiconductor layer 113 has a thickness H3, where H3 > 50 nm, and 1 ≤ (H1 + H2) / (W1 + W2) ≤ 2.5. In the direction perpendicular to the direction, the nitride semiconductor layer 113 has a thickness H3, where H3 > 50 nm, and H2 / H3 ≤ 0.5. In the direction perpendicular to the directional direction, the nitride semiconductor layer 113 has a thickness H3, where H3 ≤ 50 nm and 0.5 ≤ (H1 + H2) / (W1 + W2) < 1.5. In the direction perpendicular to the directional direction, the nitride semiconductor layer 113 has a thickness H3, where H3 ≤ 50 nm and H2 / H3 ≤ 0.8.

[0086] Reference Figure 16 , Figure 16 Display device 304, Figure 16 The semiconductor device 304 shown is largely the same as Figure 3 The semiconductor device 300 shown differs in that it additionally includes a dielectric layer 122. The dielectric layer 122 is disposed above the nitride semiconductor layer 117. The dielectric layer 122 is disposed above the gate structure 111. The dielectric layer 122 is disposed above the nitride semiconductor layer 113. The dielectric layer 122 is disposed above the gate electrode 115. The dielectric layer 122 is located between the source contact 107 and the drain contact 109. The dielectric layer 122 surrounds the gate structure 111. The dielectric layer 122 surrounds the nitride semiconductor layer 113. The dielectric layer 122 surrounds the gate electrode 115.

[0087] Reference Figure 16 , Figure 16The semiconductor device 304 shown further includes a field plate 121. The field plate 121 is disposed above the dielectric layer 122. The field plate 121 is electrically connected to the source contact 107. The field plate 121 can be electrically connected to the source contact 107 via a via (123). The projection of the field plate 121 toward the substrate 101 overlaps with the source contact 107. The projection of the field plate 121 toward the substrate 101 overlaps with the gate structure 111. The projection of the field plate 121 toward the substrate 101 overlaps with the nitride semiconductor layer 113. The projection of the field plate 121 toward the substrate overlaps with the gate electrode 115. The projection of the field plate 121 toward the substrate 101 does not overlap with the source contact 107. The projection of the field plate 121 toward the substrate 101 does not overlap with the gate structure 111. The projection of the field plate 121 toward the substrate 101 does not overlap with the nitride semiconductor layer 113. The projection of field plate 121 toward substrate 101 overlaps with gate electrode 115. The projection of field plate 121 toward substrate 101 covers gate structure 111. The projection of field plate 121 toward substrate 101 covers nitride semiconductor layer 113. The projection of field plate 121 toward substrate 101 covers gate electrode 115. The bottom surface of field plate 121 toward the substrate is lower than the top surface of gate electrode 115 away from substrate 101. The bottom surface of field plate 121 toward the substrate is higher than the top surface of gate electrode 115 away from substrate 101. The projection of field plate 121 toward substrate 101 overlaps with the projection of doped region 105-1 toward substrate 101. The projection of field plate 121 toward substrate 101 does not overlap with the projection of doped region 105-1 toward substrate 101. A portion of the projection of field plate 121 toward substrate 101 lies between source contact 107 and nitride semiconductor layer 113. A portion of the projection of the field plate 121 toward the substrate 101 is located between the nitride semiconductor layer 113 and the drain contact 109.

[0088] One of the generally perpendicular cross-sections of the perimeter of the doped region 105-1 to the substrate 101 intersects the field plate 121. One of the generally perpendicular cross-sections of the perimeter of the doped region 105-1 to the substrate 101 does not intersect the field plate 121. Two of the generally perpendicular cross-sections of the perimeter of the doped region 105-1 to the substrate 101 intersect the field plate 121.

[0089] Figure 16 The manufacturing method of the semiconductor device 304 shown is largely the same as that of... Figure 3 The manufacturing method of the semiconductor device 300 shown differs in that, in the manufacturing method of the semiconductor device 304, the following additional steps are added: depositing a dielectric layer 122, opening vias, filling with metal as vias 123, and setting a field plate 121. These additional steps can be performed using any semiconductor manufacturing technology known to those skilled in the art. Because... Figure 16The semiconductor device 304 shown has an additional field plate 121 and dielectric layer 122, which further improves the gate leakage current of the semiconductor device 304.

[0090] Unless otherwise specified, spatial descriptions such as “above,” “below,” “upward,” “left,” “right,” “downward,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “above,” “below,” “upper part,” “above,” and “below” are relative to the orientation indicated in the drawings. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that the advantages of the embodiments of the invention are not deviated from by such arrangements.

[0091] As used in this article, the term "vertical" refers to the upward and downward directions, while the term "horizontal" refers to the direction that is transverse to the vertical direction.

[0092] As used herein, the terms “approximately,” “generally,” “roughly,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to examples of events or situations that occurred precisely or very approximately. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a first value is within a range of variation less than or equal to ±10% of a second value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first value may be considered “generally” the same as or equal to the second value. For example, "generally" vertical can refer to an angular variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0093] If the displacement between two surfaces does not exceed 5 μm, 2 μm, 1 μm, or 0.5 μm, then the two surfaces can be considered coplanar or substantially coplanar. If the displacement between the highest and lowest points of a surface does not exceed 5 μm, 2 μm, 1 μm, or 0.5 μm, then the surface can be considered substantially flat.

[0094] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include multiple indicators.

[0095] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to conduct electric current. Conductive materials generally indicate those that exhibit very little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, conductive materials are those with a conductivity greater than about 10⁴ S / m (e.g., at least 10⁵ S / m or at least 10⁶ S / m). The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0096] In addition, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values ​​explicitly specified as the limits of the range, but also all individual numerical values ​​or subranges covered within that range, as if each numerical value and subrange were explicitly specified.

[0097] Although the invention has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of the invention as defined by the appended claims. Illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the process reproduction in this invention and actual equipment. Other embodiments of the invention may exist that are not specifically described. This specification and drawings should be considered illustrative rather than limiting. Modifications may be made to suit particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications are intended to be within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Accordingly, unless specifically indicated herein, the order and grouping of operations are not limitations of the invention.

Claims

1. A semiconductor device comprising: Substrate; A first nitride semiconductor layer is located above the substrate; The second nitride semiconductor layer is located above the first nitride semiconductor layer and has a larger band gap than the first nitride semiconductor layer. The second nitride semiconductor layer includes a first doped region and a first intrinsic region. The source and drain contacts are located above the second nitride semiconductor layer; A gate structure is located above the second nitride semiconductor layer and between the source contact and the drain contact. The gate structure includes a third nitride semiconductor layer and a gate contact located above it. The third nitride semiconductor layer includes a second doped region that has been doped once and a second doped region that has been doped twice. as well as, A fourth nitride semiconductor layer is located above the second nitride semiconductor layer and between the gate structure contact and the drain contact; In this context, generally along the direction connecting the source contact and the drain contact, the projection of the gate structure toward the substrate overlaps with the projection of the first doped region toward the substrate. Wherein, generally along the direction connecting the source contact and the drain contact, the maximum width of the first doped region is W1, the maximum width of the second doped region after secondary doping is W2, and in the direction perpendicular to the direction, the maximum height of the first doped region is H1, the maximum height of the second doped region after secondary doping is H2, where 0.5≤(H1+H2) / (W1+W2)≤3.

2. The semiconductor device of claim 1, wherein, Generally along the direction connecting the source contact and the drain contact, the projection of the gate structure toward the substrate overlaps with the projection of the first intrinsic region toward the substrate.

3. The semiconductor device of claim 1, wherein the third nitride semiconductor layer comprises a second doped region that has undergone primary doping and a second doped region that has undergone secondary doping.

4. The semiconductor device according to claim 1 or 2, wherein the first doped region is in contact with the fourth nitride semiconductor layer.

5. The semiconductor device of claim 3, wherein the second doped region, which has undergone secondary doping, is in contact with the fourth nitride semiconductor layer.

6. The semiconductor device according to claim 1 or 2, wherein the fourth nitride semiconductor layer comprises AlN.

7. The semiconductor device according to claim 1 or 2, wherein the first doped region comprises oxygen.

8. The semiconductor device of claim 3, wherein the second doped region after secondary doping comprises gallium oxynitride.

9. The semiconductor device according to claim 1 or 2, wherein the first doped region comprises gallium aluminum oxynitride.

10. The semiconductor device according to claim 1 or 2, wherein the first doped region comprises an amorphous second nitride semiconductor.

11. A method for manufacturing a semiconductor device, comprising: Provide substrate; A first nitride semiconductor layer is disposed above the substrate; A second nitride semiconductor layer is disposed above the first nitride semiconductor layer, the second nitride semiconductor layer having a larger band gap than the first nitride semiconductor layer; Source and drain contacts are arranged above the second nitride semiconductor layer; A gate structure is arranged above the second nitride semiconductor layer and between the source contact and the drain contact. The gate structure includes a third nitride semiconductor layer above the second nitride semiconductor layer and a gate contact above the third nitride semiconductor layer. Doping elements are implanted at an acute angle to the junction of the third nitride semiconductor layer and the second nitride semiconductor layer to form a first doped region and a first intrinsic region in the second nitride semiconductor layer. as well as, A fourth nitride semiconductor layer is disposed above the second nitride semiconductor layer and between the gate structure and the drain contact.

12. The method according to claim 11, wherein, Generally along the direction connecting the source contact and the drain contact, the projection of the gate structure toward the substrate overlaps with the projection of the first intrinsic region toward the substrate.

13. The method of claim 11, wherein the first doped region has a maximum width W1 generally along the direction connecting the source contact and the drain contact, and the first doped region has a maximum height H1 in the direction perpendicular to the direction, the ratio of the maximum height H1 to the maximum width W1 being 0.5 to 3.

14. The method according to claim 11, wherein, The third nitride semiconductor layer includes a second doped region that has undergone primary doping and a second doped region that has undergone secondary doping.

15. A semiconductor device comprising: Substrate; A first nitride semiconductor layer is located above the substrate; The second nitride semiconductor layer is located above the first nitride semiconductor layer and has a larger band gap than the first nitride semiconductor layer. The second nitride semiconductor layer includes a first doped region and a first intrinsic region. The source and drain contacts are located above the second nitride semiconductor layer; A gate structure, located above the second nitride semiconductor layer and between the source contact and the drain contact, includes a third nitride semiconductor layer and a gate contact located above it, the third nitride semiconductor layer including a second doped region that has been doped once and a second doped region that has been doped twice; as well as, A fourth nitride semiconductor layer covers the gate structure and the second nitride semiconductor layer; Wherein, generally along the direction connecting the source contact and the drain contact, the maximum width of the first doped region is W1, the maximum width of the second doped region after secondary doping is W2, and in the direction perpendicular to the direction, the maximum height of the first doped region is H1, the maximum height of the second doped region after secondary doping is H2, where 0.5≤(H1+H2) / (W1+W2)≤3.

16. The semiconductor device according to claim 15, wherein, In the direction perpendicular to the stated direction, the third nitride semiconductor layer has a thickness H3, wherein H3 > 50 nm and 1 ≤ (H1 + H2) / (W1 + W2) ≤ 2.

5.

17. The semiconductor device according to claim 15, wherein, In the direction perpendicular to the stated direction, the third nitride semiconductor layer has a thickness H3, wherein H3 > 50 nm and H2 / H3 ≤ 0.

5.

18. The semiconductor device according to claim 15, wherein, In the direction perpendicular to the stated direction, the third nitride semiconductor layer has a thickness H3, wherein H3 ≤ 50 nm and 0.5 ≤ (H1 + H2) / (W1 + W2) < 1.

5.

19. The semiconductor device according to claim 15, wherein, In the direction perpendicular to the stated direction, the third nitride semiconductor layer has a thickness H3, wherein H3 ≤ 50 nm and H2 / H3 ≤ 0.8.

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