Semiconductor device and method for manufacturing the same, power conversion device

Abstract

The present disclosure provides a semiconductor device, a method for manufacturing the same, and a power conversion device. The semiconductor device includes a semiconductor layer having a first side surface and a second side surface opposite to each other, a first trench-second trench group alternately arranged along a first direction on the first side surface, the second trench group including one second trench or a plurality of second trenches arranged along the first direction, the first trench and the second trench both extending along a second direction, the first direction and the second direction being parallel to a plane in which the semiconductor layer is located and intersecting with each other, the second trench adjacent to the first trench including a main body region extending along the second direction and a branch region protruding from the main body region toward a direction of the adjacent first trench, the branch regions on the same side of the main body region being arranged at intervals, the semiconductor layer including a source region connected to the first trench, the source region being located between the first trench and the branch region of the second trench; a gate structure; a dummy gate structure; a first electrode; an interlayer dielectric layer; and a second electrode.

Description

Technical Field

[0001] This disclosure belongs to the field of power electronics technology, specifically relating to a semiconductor device and its fabrication method, and a power conversion device. Background Technology

[0002] This section is intended to provide background or context for the embodiments set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section.

[0003] MOS-type semiconductor devices include metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated-gate bipolar transistors (IGBTs). The gate structures of MOS-type semiconductor devices include planar gate structures and trench gate structures. Summary of the Invention

[0004] This disclosure provides a semiconductor device and its fabrication method, as well as a power conversion device.

[0005] This disclosure adopts the following technical solution: a semiconductor device, comprising:

[0006] A semiconductor layer has a first side surface and a second side surface opposite to each other. A first trench and a second trench group are alternately arranged along a first direction on the first side surface. The second trench group includes one second trench or a plurality of second trenches arranged along the first direction. The first trench and the second trench both extend along a second direction. The first direction and the second direction are parallel to the plane in which the semiconductor layer is located and intersect each other. The second trench adjacent to the first trench includes a main region extending along the second direction and a branch region protruding from the main region toward the adjacent first trench. The branch regions on the same side of the main region are spaced apart. The semiconductor layer includes a source region connected to the first trench. The source region is located between the branch regions of the first trench and the second trench.

[0007] A gate structure is disposed within the first trench, including a gate insulating layer and a gate;

[0008] A dummy gate structure is disposed within the second trench, including a dummy gate insulating layer and a dummy gate;

[0009] The first electrode is disposed on the first side surface of the semiconductor layer and is in conductive contact with the source region;

[0010] An interlayer dielectric layer separates the first electrode and the gate structure.

[0011] The second electrode is disposed on the second side surface of the semiconductor layer.

[0012] In some embodiments, a second groove is provided between two first grooves that are adjacent to each other along a first direction, the second groove including a branch region protruding from its main region toward the first grooves on both sides.

[0013] In some embodiments, a plurality of second grooves are provided between two first grooves that are adjacent to each other along a first direction. The second groove includes a branch region protruding from its main region toward the first grooves on both sides, and the branch regions of adjacent second grooves that are opposite to each other are connected as one.

[0014] In some embodiments, the dummy gate is either floating or in conductive contact with the first electrode.

[0015] In some embodiments, a plurality of third trenches are further provided on the first side surface of the semiconductor layer, and the first electrode fills the third trenches to make at least conductive contact with the source region.

[0016] In some embodiments, a portion of the third trench exposes the side surface of the source region and is spaced apart from the second trench.

[0017] In some embodiments, a portion of the third trench exposes the side surface of the source region and the dummy gate.

[0018] In some embodiments, one or more isolated third trenches are provided between the main regions of adjacent first and second trenches and between two adjacent branch regions of the main region 5 facing the first trench.

[0019] In some embodiments, the top surface of the dummy gate is lower than the top surface of the gate.

[0020] In some embodiments, the semiconductor device is configured as an IGBT or a MOSFET.

[0021] This disclosure adopts the following technical solution: a method for fabricating a semiconductor device, comprising:

[0022] A semiconductor layer is provided, having a first side surface and a second side surface opposite to each other. A first trench and a second trench group are alternately disposed on the first side surface along a first direction. The second trench group includes one second trench or a plurality of second trenches arranged along the first direction. The first trench and the second trench both extend along a second direction. The first direction and the second direction are parallel to the plane in which the semiconductor layer is located and intersect each other. The second trench adjacent to the first trench includes a main region extending along the second direction and a branch region protruding from the main region toward the adjacent first trench. The branch regions on the same side of the main region are spaced apart. The semiconductor layer includes a source region connected to the first trench. The source region is located between the branch regions of the first trench and the second trench.

[0023] The step of forming a gate structure in the first trench, wherein the gate structure includes a gate insulating layer and a gate;

[0024] The step of constructing a dummy gate structure within the second trench, wherein the dummy gate structure includes a dummy gate insulating layer and a dummy gate;

[0025] The step of forming a first electrode that makes a conductive contact with the source region on a first side surface of the semiconductor layer;

[0026] The step of forming an interlayer dielectric layer between the first electrode and the gate structure;

[0027] The step of forming a second electrode on the second side surface of the semiconductor layer.

[0028] In some embodiments, the gate and the dummy gate are formed simultaneously, and then the dummy gate is selectively etched to reduce the top surface height of the dummy gate.

[0029] The present disclosure adopts the following technical solution: a power conversion device, comprising: the aforementioned semiconductor device. Attached Figure Description

[0030] Figure 1 This is a top perspective view of a portion of the semiconductor device structure according to an embodiment of this disclosure.

[0031] Figure 2 This is a top perspective view of a portion of the semiconductor device structure according to other embodiments of this disclosure.

[0032] Figure 3 yes Figure 1 Four variations of the top view pattern of the third trench in the semiconductor device shown.

[0033] Figure 4 yes Figure 1 Two variations of the cross-sectional view of the third trench in the semiconductor device shown.

[0034] Figures 5a to 5f yes Figure 1 The image shows a partial cross-sectional view of the semiconductor device during an intermediate stage of fabrication.

[0035] The reference numerals in the attached figures are as follows: 1, semiconductor layer; 11, carrier storage layer; 12, well region; 13, base region; 14, collector region; S, source region; 21, gate; 21a, dummy gate; 22, gate insulating layer; 220, gate insulating material layer; 22a, dummy gate insulating layer; 23, interlayer dielectric layer; 24, insulating layer; 3, first electrode; 4, second electrode; AT, first trench; DT, second trench; H3, third trench; W, D, stub region size; Tr, main region size; Mesa, source region size; P, maximum spacing between adjacent first and second trenches; D1, first direction; D2, second direction. Detailed Implementation

[0036] The present disclosure will be further described below with reference to the embodiments shown in the accompanying drawings.

[0037] Figure 1 This is a top perspective view of a portion of the semiconductor device structure according to an embodiment of this disclosure. Figure 2 This is a top perspective view of a portion of the semiconductor device structure according to other embodiments of this disclosure. Figure 3 yes Figure 1 Four variations of the top view pattern of the third trench in the semiconductor device shown. Figure 4 yes Figure 1 Two variations of the cross-sectional view of the third trench in the semiconductor device shown.

[0038] refer to Figures 1 to 4 Embodiments of this disclosure provide a semiconductor device, including:

[0039] Semiconductor layer 1 has a first side surface and a second side surface that are opposite to each other. A first trench AT and a second trench DT are alternately arranged along a first direction D1 on the first side surface. The second trench DT group includes one second trench DT or a plurality of second trenches DT arranged along the first direction D1. The first trench AT and the second trench DT both extend along a second direction D2. The first direction D1 and the second direction D2 are parallel to the plane where the semiconductor layer 1 is located and intersect each other. The second trench DT adjacent to the first trench AT includes a main region extending along the second direction D2 (the width of the main region is marked as Tr) and a branch region protruding from the main region toward the adjacent first trench AT (the size of the branch region is marked as W and D). The branch regions on the same side of the main region are spaced apart. Semiconductor layer 1 includes a source region S connected to the first trench AT (the size of the source region along the first direction D1 is marked as Mesa). The source region S is located between the branch regions of the first trench AT and the second trench DT.

[0040] The gate 21 structure is disposed in the first trench AT and includes a gate insulating layer 2422 and a gate 21.

[0041] The dummy gate 21a structure is disposed in the second trench DT and includes a dummy gate insulating layer 2422a and a dummy gate 21a;

[0042] The first electrode 3 is disposed on the first side surface of the semiconductor layer 1 and is in conductive contact with the source region S.

[0043] The interlayer dielectric layer 23 at least separates the first electrode 3 and the gate 21.

[0044] The second electrode 4 is disposed on the second side surface of the semiconductor layer 1.

[0045] In some embodiments, D = 0.2 μm, Tr = 0.8 μm, W ranges from 0.25 μm to 10 μm, and P = Mesa + D.

[0046] Figure 1 In the embodiment shown, gate 21 and dummy gate 21a are alternately arranged along the first direction D1. Figure 2 In the embodiment shown, the gate 21 and the group of dummy gates 21a consisting of two dummy gates 21a are alternately arranged along the first direction D1.

[0047] In some embodiments, the semiconductor device is configured as an IGBT or a MOSFET. When the semiconductor device is configured as an IGBT, the first electrode 3 is the emitter and the second electrode 4 is the collector. When the semiconductor device is configured as a MOSFET, the first electrode 3 is the source and the second electrode 4 is the drain. In the following description of the embodiments, the semiconductor device is configured as an IGBT and the source region S is N-type as an example.

[0048] refer to Figure 4 As shown in Figure a, semiconductor layer 1, from bottom to top, consists of a P-type collector region 14; an N-type base region 13; an N-type carrier storage layer 11; a P-type well region 12; and an N-type source region S. The first electrode 3 serves as the emitter. A third trench H3 is formed on the first side surface of semiconductor layer 1, exposing both the side surface of the source region S and the top surface of the dummy gate 21a. The first electrode 3 fills the third trench H3, thereby achieving conductive contact with the source region S and the dummy gate 21a.

[0049] refer to Figure 4 Figure b differs from figure a in that the third trench H3 only exposes the side surface of the source region S, so that after the first electrode 3 fills the third trench H3, the first electrode 3 only makes conductive contact with the source region S. The dummy gate 21a is floating. Of course, the dummy gate 21a can also be electrically connected to the first electrode 3 at other locations via vias.

[0050] In some embodiments, continue to refer to Figure 1 A second trench DT is provided between two adjacent first trenches AT along the first direction D1. The second trench DT includes branch regions protruding from its main region toward the two adjacent first trenches AT. The distance between the main region of the second trench DT and the nearest neighboring first trench AT is marked as P.

[0051] In some embodiments, a plurality of second grooves DT are provided between two first grooves AT that are adjacent to each other along the first direction D1. The second groove DT includes a branch region protruding from its main region toward the first grooves AT on both sides, and the branch regions of adjacent second grooves DT that are opposite to each other are connected as one.

[0052] Of course, the branch area may not be set on the opposite side between adjacent second trenches DT.

[0053] Using the above design approach, the spacing between the stub regions of the second trench DT and the first trench AT can be designed to be sufficiently short according to design requirements, thereby satisfying the local fine-grained cell design and helping to improve current density. Furthermore, there is a sufficiently large area between the two stub regions on the same side of the second trench DT for the well region 12 to connect to the power supply voltage, for example, for P-well grounding, providing a larger flow area for holes and improving the device's latch-up resistance. Furthermore, the space between the two stub regions on the same side of the second trench DT is large enough that the area of ​​the P-well grounding (e.g., conductively connected to the first electrode 3 to achieve P-well grounding) can be flexibly designed to meet the device's differentiated design requirements for di / dt or dv / dt.

[0054] In some embodiments, reference Figure 4 The dummy gate 21a is either floating or in conductive contact with the first electrode 3.

[0055] In some embodiments, reference Figure 4 The first side surface of the semiconductor layer 1 is also provided with a plurality of third trenches H3, and the first electrode 3 fills the third trenches H3 to make at least conductive contact with the source region S.

[0056] In some embodiments, reference Figure 4 Figure b shows that part of the third trench H3 exposes the side surface of the source region S and is spaced apart from the second trench DT.

[0057] In some embodiments, reference Figure 4 Figure a shows that part of the third trench H3 exposes the side surface of the source region S and exposes the dummy gate 21a.

[0058] In some embodiments, reference Figure 3Figures c and d show that one or more isolated third trenches H3 are provided between the main regions of adjacent first trenches AT and second trenches DT, and between two adjacent branch regions of the main region facing the first trench AT.

[0059] And in Figure 3 In Figures a and b, the third trench H3 extends from a source region S on the same side as the first trench AT to another source region S on the same side as the first trench AT. Figure 3 In Figure a, the third trench H3 is a rectangle of equal width. Figure 3 In Figure b, the third groove H3 increases in width in the region between two adjacent branch areas.

[0060] The third trench H3 enables the first electrode 3 to be electrically connected to the source region S and the well region 12. The above demonstrates the flexibility in the area and position of the connection between the first electrode 3 and the well region 12.

[0061] In some embodiments, reference Figure 4 The top surface of the dummy gate 21a is lower than the top surface of the gate 21. This helps to reduce parasitic capacitance and improve the switching speed of the device.

[0062] Figures 5a to 5f yes Figure 1 The image shows a partial cross-sectional view of the semiconductor device during an intermediate stage of fabrication.

[0063] Based on the same inventive concept as the foregoing embodiments, some embodiments of this disclosure also provide a method for fabricating a semiconductor device, including:

[0064] A semiconductor layer 1 is provided, having a first side surface and a second side surface opposite to each other. A first trench AT and a second trench DT are alternately arranged along a first direction D1 on the first side surface. The second trench DT group includes one second trench DT or includes a plurality of second trench DTs arranged along the first direction D1. The first trench AT and the second trench DT both extend along a second direction D2. The first direction D1 and the second direction D2 are parallel to the plane where the semiconductor layer 1 is located and intersect each other. The second trench DT adjacent to the first trench AT includes a main region extending along the second direction D2 and a branch region protruding from the main region toward the adjacent first trench AT. The branch regions located on the same side of the main region are spaced apart. The semiconductor layer 1 includes a source region S connected to the first trench AT. The source region S is located between the branch regions of the first trench AT and the second trench DT.

[0065] The step of forming a gate 21 structure in the first trench AT, wherein the gate 21 structure includes a gate insulating layer 2422 and a gate 21;

[0066] In the step of constructing a dummy gate 21a structure in the second trench DT, the dummy gate 21a structure includes a dummy gate insulating layer 2422a and a dummy gate 21a.

[0067] The step of forming a first electrode 3 that is in conductive contact with the source region S on the first side surface of the semiconductor layer 1;

[0068] The step of forming an interlayer dielectric layer 23 between the first electrode 3 and the gate 21 structure;

[0069] The step of forming a second electrode 4 on the second side surface of semiconductor layer 1.

[0070] Specifically, refer to Figure 5a A first trench AT and a second trench DT are etched on the first side surface of semiconductor layer 1. A well region 12 has been formed within the first side surface of semiconductor layer 1.

[0071] refer to Figure 5b A gate insulating material layer 220 is deposited over the entire surface. The gate insulating material layer 220 fills the inner surfaces of the first trench AT and the second trench DT.

[0072] refer to Figure 5c Polysilicon is deposited in the first trench AT and the second trench DT to obtain the gate 21 and the dummy gate 21a.

[0073] refer to Figure 5d Ion implantation is performed on the first side surface of semiconductor layer 1 to obtain carrier storage layer 11 and source region S.

[0074] refer to Figure 5e The dummy gate 21a is selectively etched to reduce its height. This helps to reduce parasitic capacitance.

[0075] refer to Figure 5f An insulating layer 24 is filled into the second trench DT, and a planarization process is performed to obtain an interlayer dielectric layer 23 covering the gate 21. In some embodiments, the interlayer dielectric layer 23 and the insulating layer 24 are integral layers of the same material.

[0076] Continue to refer to Figure 4 In Figure a, a third trench H3 is formed to expose the side surface of the source region S, the top surface of the well region 12, and the top surface of the dummy gate 21a. Subsequently, the first electrode 3 is deposited and patterned. If a floating dummy gate 21a is required, its top surface is etched lower in the preceding steps so that the dummy gate 21a is not exposed even when the insulating layer 24 is etched during the formation of the third trench H3.

[0077] In conventional processes, forming the third trench H3 requires simultaneous etching of the dummy gate 21a (e.g., polysilicon), the gate dielectric layer, and the semiconductor layer 1. However, the etching process for the third trench H3 in this disclosure only requires etching of the dielectric layer (including the insulating layer 24 and the interlayer dielectric layer 23) and the semiconductor layer 1. In conventional processes, after polysilicon deposition and planarization, the top surface of the polysilicon has chamfers at the corners, partially obscuring the insulating layer 24 and increasing the difficulty of etching the insulating layer 24. The top surface of the dummy gate 21a in this disclosure is a relatively flat surface obtained through etching, avoiding the aforementioned chamfer problem and reducing the difficulty of the etching process.

[0078] Based on the same inventive concept, embodiments of this disclosure also provide a power conversion device, including the aforementioned semiconductor device.

[0079] Power conversion devices include, for example, ACAC converters, AC-DC converters, DC-DC converters, and DCAC converters. The semiconductor devices provided in this disclosure can be used as power switches in these converters. Power conversion devices can be used as power supply devices for electrical discharge machining machines, laser processing machines, induction heating cookers, contactless power supply systems, and also as power regulators or power systems for solar power generation systems, energy storage systems, trains, etc.

[0080] The various embodiments in this disclosure are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0081] The scope of protection of this disclosure is not limited to the embodiments described above. Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its scope and spirit. If such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, then the intent of this disclosure also includes such modifications and variations.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor layer has a first side surface and a second side surface opposite to each other. A first trench and a second trench group are alternately disposed on the first side surface along a first direction. The second trench group includes one second trench or a plurality of second trenches arranged along the first direction. The first trench and the second trench both extend along a second direction. The first direction and the second direction are parallel to the plane in which the semiconductor layer is located and intersect each other. The second trench adjacent to the first trench includes a main region extending along the second direction and a branch region protruding from the main region toward the adjacent first trench. The branch regions on the same side of the main region are spaced apart. The semiconductor layer includes a source region connected to the first trench. The source region is located between the branch regions of the first trench and the second trench. A gate structure is disposed within the first trench, including a gate insulating layer and a gate; A dummy gate structure is disposed within the second trench, including a dummy gate insulating layer and a dummy gate; The first electrode is disposed on the first side surface of the semiconductor layer and is in conductive contact with the source region; An interlayer dielectric layer separates the first electrode and the gate structure. The second electrode is disposed on the second side surface of the semiconductor layer; One or more isolated third trenches are provided between the main areas of adjacent first and second trenches and between two adjacent branch areas of the main area facing the first trench.

2. The semiconductor device according to claim 1, characterized in that, A second groove is provided between two adjacent first grooves along a first direction, the second groove including a branch region protruding from its main region toward the two first grooves on both sides.

3. The semiconductor device according to claim 1, characterized in that, Multiple second grooves are provided between two adjacent first grooves along a first direction. Each second groove includes a branch region protruding from its main area toward the first grooves on both sides. The branch regions of adjacent second grooves that are opposite to each other are connected as one.

4. The semiconductor device according to claim 1, characterized in that, The dummy gate is either floating or in conductive contact with the first electrode.

5. The semiconductor device according to claim 1, characterized in that, A plurality of third trenches are also provided on the first side surface of the semiconductor layer, and the first electrode fills the third trenches to make at least conductive contact with the source region.

6. The semiconductor device according to claim 5, characterized in that, Part of the third trench exposes the side surface of the source region and is spaced apart from the second trench.

7. The semiconductor device according to claim 5, characterized in that, Part of the third trench exposes the side surface of the source region and the dummy gate.

8. The semiconductor device according to claim 1, characterized in that, The top surface of the dummy gate is lower than the top surface of the gate.

9. The semiconductor device according to claim 1, characterized in that, The semiconductor device is constructed as an IGBT or a MOSFET.

10. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor layer is provided having a first side surface and a second side surface opposite to each other. A first trench and a group of second trenches are alternately disposed on the first side surface along a first direction. The second trench group includes one second trench or a plurality of second trenches arranged along the first direction. Both the first trench and the second trench extend along a second direction, which is parallel to the plane of the semiconductor layer and intersects each other. A second trench adjacent to the first trench includes a main region extending along the second direction and a branch region protruding from the main region toward the adjacent first trench. Branch regions located on the same side of the main region are spaced apart. The semiconductor layer includes a source region connected to the first trench, the source region being located between the branch regions of the first trench and the second trench. One or more isolated third trenches are disposed between the main regions of adjacent first trenches and second trenches and between two adjacent branch regions of the main region toward the first trench. The step of forming a gate structure in the first trench, wherein the gate structure includes a gate insulating layer and a gate; The step of constructing a dummy gate structure within the second trench, wherein the dummy gate structure includes a dummy gate insulating layer and a dummy gate; The step of forming a first electrode that makes a conductive contact with the source region on a first side surface of the semiconductor layer; The step of forming an interlayer dielectric layer between the first electrode and the gate structure; The step of forming a second electrode on the second side surface of the semiconductor layer.

11. The preparation method according to claim 10, characterized in that, The gate and the dummy gate are formed simultaneously, and then the dummy gate is selectively etched to reduce the top surface height of the dummy gate.

12. A power conversion device, characterized in that, include: The semiconductor device according to any one of claims 1 to 9.

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