Nitride semiconductor device having a composite buffer layer and method of fabricating the same

Abstract

The present disclosure provides a nitride semiconductor device with a composite buffer layer and a preparation method thereof, and belongs to the field of semiconductor devices. The nitride semiconductor device comprises a substrate, and a composite buffer layer and a nitride semiconductor layer sequentially grown on one side of the substrate; the composite buffer layer comprises a nucleation layer, a buffer layer and a stress adjustment layer sequentially grown. The present disclosure can effectively reduce the problem of lattice mismatch.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductor devices, and particularly relates to a nitride semiconductor device with a composite buffer layer and its fabrication method. Background Technology

[0002] Semiconductor devices are common functional electronic devices that are widely used in various sub-fields.

[0003] In related technologies, GaN, as a typical representative of III-V compound semiconductors, is the third-generation semiconductor material following Si and GaAs. It possesses excellent properties such as a large bandgap, strong breakdown electric field, high electron mobility, and good thermal stability. The epitaxial layer of nitride semiconductor devices mainly consists of a nitride semiconductor layer grown on a substrate.

[0004] However, due to the large lattice mismatch between the substrate and the nitride semiconductor layer, the epitaxial film may exhibit cracks and uneven surface morphology. Summary of the Invention

[0005] This disclosure provides a nitride semiconductor device with a composite buffer layer and its fabrication method, which can effectively reduce the problem of lattice mismatch. The technical solution is as follows:

[0006] On one hand, embodiments of this disclosure provide a nitride semiconductor device with a composite buffer layer, comprising:

[0007] A substrate, and a composite buffer layer and a nitride semiconductor layer sequentially grown on one side of the substrate;

[0008] The composite buffer layer comprises a nucleation layer, a buffer layer, and a stress-regulating layer that grow sequentially.

[0009] In one implementation of this disclosure, the growth thickness of the nucleation layer is 30–50 nm;

[0010] The thickness of the buffer layer is 10–20 nm.

[0011] The growth thickness of the stress-adjusting layer is 0.1–0.6 μm.

[0012] In one implementation of this disclosure, the nucleation layer is a periodically stacked Al a N 1-a / In b N 1-b Layer (0 < a < 1; 0 < b < 1), the buffer layer is an N-type Al c Ga 1-c N layers (0 < c < 1), the stress-regulating layer is a periodically stacked In layer. dGa 1-d N / GaN layer (0 < d < 1).

[0013] In one implementation of this disclosure, the nitride semiconductor layer comprises an N-type layer, a multiple quantum well layer, and a P-type layer stacked sequentially.

[0014] On the other hand, embodiments of this disclosure provide a method for fabricating a nitride semiconductor device with a composite buffer layer, comprising:

[0015] Provide a substrate;

[0016] A composite buffer layer and a nitride semiconductor layer are sequentially grown on one side of the substrate;

[0017] The composite buffer layer is grown in the following manner:

[0018] The nucleus layer, buffer layer, and stress-regulating layer grow sequentially.

[0019] In one implementation of this disclosure, growing the nucleation layer includes:

[0020] The growth temperature of the nucleation layer was set to 700–900°C, and the growth pressure was set to 100–500 torr, to grow periodically stacked Al layers with a thickness of 30–50 nm. a N 1-a / In b N 1-b layer.

[0021] In one implementation of this disclosure, growing the buffer layer includes:

[0022] The growth temperature of the buffer layer was set to 700–900℃, and the growth pressure was set to 100–500 torr, to grow N-type Al with a thickness of 10–20 nm. c Ga 1-c N layers.

[0023] In one implementation of this disclosure, growing the stress-regulating layer includes:

[0024] The growth temperature of the stress-regulating layer was set to 700–900°C, and the growth pressure was set to 100–500 torr, to grow periodically stacked In layers with a thickness of 0.1–0.6 μm. d Ga 1-d N / GaN layer.

[0025] In one implementation of this disclosure, the nitride semiconductor layer is grown in the following manner:

[0026] The N-type layer, the multiple quantum well layer, and the P-type layer are grown sequentially.

[0027] In one implementation of this disclosure, growing the N-type layer includes:

[0028] The growth temperature of the N-type layer was set to 1000-1200℃, and the growth pressure was set to 100-500 torr, to grow a heavily Si-doped N-type GaN layer with a thickness of 3-4 μm.

[0029] The beneficial effects of the technical solutions provided in this disclosure are:

[0030] Since the nitride semiconductor layer provided in this embodiment has a composite buffer layer, the composite buffer layer includes a nucleation layer, a buffer layer and a stress adjustment layer grown sequentially.

[0031] For the nucleation layer, the nucleation layer provides nucleation centers with the same orientation as the substrate, reducing the problem of lattice mismatch between the substrate and the nitride semiconductor layer, and is more conducive to axial three-dimensional island growth.

[0032] For the buffer layer, the buffer layer can fill Ga vacancies and merge with the three-dimensional islands to form a high-quality buffer layer, further reducing lattice mismatch and thermal mismatch with the substrate, playing a role in blocking underlying defects, thereby reducing the generation of dislocations and cracks.

[0033] For the stress adjustment layer, the stress adjustment layer forms a lattice constant matching relationship with the nitride semiconductor layer, which can be used as a lattice mismatch stress relief layer, thereby achieving low stress, no cracks and bending inside the nitride semiconductor layer, thus improving the problem of substrate lattice mismatch, controlling the corresponding epitaxial wafer stress, and thus improving the yield and optoelectronic performance of the epitaxial wafer.

[0034] In other words, the combination of nucleation layer, buffer layer and stress adjustment layer reduces the problem of lattice mismatch. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the structure of a nitride semiconductor device provided in an embodiment of this disclosure;

[0037] Figure 2 This is a flowchart of a method for fabricating a nitride semiconductor device according to an embodiment of this disclosure;

[0038] Figure 3This is a flowchart of another method for fabricating a nitride semiconductor device provided in this disclosure.

[0039] The symbols in the diagram represent the following meanings:

[0040] 10. Substrate;

[0041] 20. Composite buffer layer;

[0042] 210. Nucleation layer; 220. Buffer layer; 230. Stress-regulating layer;

[0043] 30. N-type layer;

[0044] 40. Multiple quantum well layers;

[0045] 50. P-type layer;

[0046] 60. Electron blocking layer;

[0047] 70. P-type contact layer;

[0048] 80. Nitride semiconductor layer. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0050] Semiconductor devices are common functional electronic devices that are widely used in various sub-fields.

[0051] In related technologies, GaN, as a typical representative of III-V compound semiconductors, is the third-generation semiconductor material following Si and GaAs. It possesses excellent properties such as a large bandgap, strong breakdown electric field, high electron mobility, and good thermal stability. The epitaxial layer of nitride semiconductor devices mainly consists of a nitride semiconductor layer grown on a substrate.

[0052] However, due to the large lattice mismatch between the substrate and the nitride semiconductor layer, the epitaxial film may exhibit cracks and uneven surface morphology.

[0053] To address the aforementioned technical problems, this disclosure provides a nitride semiconductor device with a composite buffer layer. Figure 1 See the schematic diagram of the structure of this nitride semiconductor device. Figure 1 In this embodiment, the nitride semiconductor device includes a substrate 10 and a nitride semiconductor layer 80.

[0054] The composite buffer layer 20 includes a nucleation layer 210, a buffer layer 220, and a stress-adjusting layer 230 grown sequentially. Since the nitride semiconductor device provided in this embodiment of the present disclosure includes a composite buffer layer 20, the composite buffer layer 20 includes a nucleation layer 210, a buffer layer 220, and a stress-adjusting layer 230 grown sequentially.

[0055] For the nucleation layer 210, the nucleation layer 210 provides a nucleation center with the same orientation as the substrate 10, which reduces the problem of lattice mismatch between the substrate 10 and the nitride semiconductor layer 80 and is more conducive to axial three-dimensional island growth.

[0056] For the buffer layer 220, the buffer layer 220 can fill Ga vacancies and merge with the three-dimensional islands to form a high-quality buffer layer 220, which further reduces the lattice mismatch and thermal mismatch between the buffer layer 220 and the substrate 10, and plays the role of blocking the underlying defects, thereby reducing the generation of dislocations and cracks.

[0057] As for the stress adjustment layer 230, the stress adjustment layer 230 forms a lattice constant matching relationship with the nitride semiconductor layer 80, and can be used as a lattice mismatch stress relief layer, thereby achieving low stress, no cracks and bending inside the nitride semiconductor layer 80, thus improving the lattice mismatch problem of the substrate 10, controlling the corresponding epitaxial wafer stress, and thus improving the yield and optoelectronic performance of the epitaxial wafer.

[0058] In other words, the combination of nucleation layer 210, buffer layer 220 and stress adjustment layer 230 reduces the problem of lattice mismatch.

[0059] In this embodiment, the growth thickness of the nucleation layer 210 is 30-50 nm, the growth thickness of the buffer layer 220 is 10-20 nm, and the growth thickness of the stress adjustment layer 230 is 0.1-0.6 μm.

[0060] In the above implementation, the thicknesses of the nucleation layer 210, the buffer layer 220, and the stress adjustment layer 230 are designed to the values ​​mentioned above, which can ensure their respective functionality, improve growth efficiency, and reduce preparation costs.

[0061] Therefore, the nucleation layer 210, buffer layer 220, and stress adjustment layer 230 play a crucial role in reducing lattice mismatch. The nucleation layer 210, buffer layer 220, and stress adjustment layer 230 will be described in detail below.

[0062] In this embodiment, the nucleation layer 210 is a periodically stacked Al a N 1-a / In b N 1-b Layer (0<a<1; 0<b<1).

[0063] For nucleation layer 210, since nucleation layer 210 is a periodically stacked Al a N 1-a / In b N 1-b In the N-type layer 30, AlN provides nucleation centers with the same orientation as the substrate 10, reducing the lattice mismatch problem between the substrate 10 and the N-type layer 30. In addition, InN is more conducive to axial three-dimensional island growth than GaN in the N-type layer 30, and In atoms can generate tensile stress, which alleviates warping and makes the three-dimensional cell distribution more uniform.

[0064] In this embodiment, the buffer layer 220 is an N-type Al c Ga 1-c N layers (0 < c < 1).

[0065] For buffer layer 220, since buffer layer 220 is an N-type Al c Ga 1-c The N layer, with its smaller Al atoms, can fill Ga vacancies and merge with the three-dimensional islands to form a high-quality buffer layer 220. This further reduces lattice and thermal mismatches with the substrate 10, blocks the effects of underlying defects, and thus reduces the generation of dislocations and cracks.

[0066] In this embodiment, the stress-adjusting layer 230 is a periodically stacked In d Ga 1-d N / GaN layer (0 < d < 1)

[0067] For the stress-adjusting layer 230, since the stress-adjusting layer 230 is a periodically stacked In d Ga 1-d N / GaN layer, so through In d Ga 1-d The N-type layer 30 forms a lattice constant matching relationship with the N-type layer 30, which can be used as a lattice mismatch stress relief layer. This achieves low stress, no cracks or bending inside the N-type layer 30, thereby improving the lattice mismatch problem of the substrate 10, controlling the corresponding epitaxial wafer stress, and thus improving the yield and optoelectronic performance of the epitaxial wafer.

[0068] In other words, the combination of nucleation layer 210, buffer layer 220 and stress adjustment layer 230 reduces the problem of lattice mismatch.

[0069] In this embodiment, the nitride semiconductor layer 80 includes an N-type layer 30, a multiple quantum well layer 40, and a P-type layer 50 stacked sequentially.

[0070] In some examples, the N-type layer 30 is a heavily Si-doped N-type GaN layer with a growth thickness of 3–4 μm.

[0071] In some examples, the multiple quantum well layer 40 includes periodically stacked InGaN well layers and GaN barrier layers. The InGaN well layers have a growth thickness of 2.5 nm to 4.5 nm, and the GaN barrier layers have a growth thickness of 8 nm to 12 nm.

[0072] In some examples, the P-type layer 50 is a Mg-doped P-type GaN layer with a growth thickness of 100–750 nm.

[0073] In this embodiment, the nitride semiconductor device further includes an electron blocking layer 60, which is grown on the side of the multiple quantum well layer 40 facing away from the substrate 10.

[0074] For example, the electron blocking layer 60 is a p-type AlGaN layer, and the growth thickness of the electron blocking layer 60 is 100-450 nm.

[0075] In this embodiment, the nitride semiconductor device further includes a P-type contact layer 70, which is grown on the side of the P-type layer 50 that is away from the substrate 10.

[0076] For example, the P-type contact layer 70 is a Mg-doped P-type GaN layer.

[0077] In some examples, light-emitting diodes (LEDs) were fabricated based on the nitride semiconductor devices provided in the embodiments of this disclosure. Experiments yielded a comparison table as shown in Table 1, which displays the comparison results between the LEDs provided in the embodiments of this disclosure and LEDs in related technologies. LEDs in related technologies refer to LEDs with only a conventional AlN buffer layer.

[0078] Voltage brightness ESD yield Overall yield Related technologies 2.583 9.71 96.7 92.4 This disclosure 2.579 9.75 97.5 93.1 Increase ratio -0.15％ 0.38％ 0.79％ 0.81％

[0079] Table 1

[0080] Therefore, the light-emitting diode provided in this embodiment of the present disclosure, compared with the light-emitting diode in the related art, has a voltage reduction of 0.15%, a brightness increase of 0.38%, an ESD yield increase of 0.79%, and an overall yield increase of 0.81%.

[0081] Figure 2 A flowchart illustrating a method for fabricating a nitride semiconductor device according to an embodiment of this disclosure is provided. See also... Figure 2 In this embodiment, the preparation method includes:

[0082] Step 201: Provide a substrate 10.

[0083] Step 202: Grow a composite buffer layer 20 on one side of the substrate 10.

[0084] Step 203: Grow a nitride semiconductor layer 80 on one side of the composite buffer layer 20.

[0085] The preparation method provided in this embodiment can be used to prepare a nitride semiconductor layer 80 having a composite buffer layer 20, wherein the composite buffer layer 20 includes a nucleation layer 210, a buffer layer 220 and a stress adjustment layer 230 grown sequentially.

[0086] For the nucleation layer 210, the nucleation layer 210 provides a nucleation center with the same orientation as the substrate 10, which reduces the problem of lattice mismatch between the substrate 10 and the nitride semiconductor layer 80 and is more conducive to axial three-dimensional island growth.

[0087] For the buffer layer 220, the buffer layer 220 can fill Ga vacancies and merge with the three-dimensional islands to form a high-quality buffer layer 220, which further reduces the lattice mismatch and thermal mismatch between the buffer layer 220 and the substrate 10, and plays the role of blocking the underlying defects, thereby reducing the generation of dislocations and cracks.

[0088] As for the stress adjustment layer 230, the stress adjustment layer 230 forms a lattice constant matching relationship with the nitride semiconductor layer 80, and can be used as a lattice mismatch stress relief layer, thereby achieving low stress, no cracks and bending inside the nitride semiconductor layer 80, thus improving the lattice mismatch problem of the substrate 10, controlling the corresponding epitaxial wafer stress, and thus improving the yield and optoelectronic performance of the epitaxial wafer.

[0089] In other words, the combination of nucleation layer 210, buffer layer 220 and stress adjustment layer 230 reduces the problem of lattice mismatch.

[0090] Figure 3 This is a flowchart illustrating another method for fabricating a nitride semiconductor device according to an embodiment of the present disclosure. This method is used to fabricate... Figure 1 The nitride semiconductor device shown is described in the following document. Figure 3 In this embodiment, the preparation method includes:

[0091] Step 301: Provide a substrate 10.

[0092] For example, the substrate 10 is heated to 1000-1200°C for surface cleaning treatment for 5-10 minutes.

[0093] Step 302: Growing a nucleation layer 210 on one side of the substrate 10.

[0094] In step 302, the growth temperature of the nucleation layer 210 is set to 700–900°C, and the growth pressure is set to 100–500 torr, to grow periodically stacked Al layers with a thickness of 30–50 nm. a N 1-a / Inb N 1-b layer.

[0095] Step 303: Grow a buffer layer 220 on one side of the nucleation layer 210.

[0096] In step 303, the growth temperature of the buffer layer 220 is set to 700–900°C, and the growth pressure is set to 100–500 torr, to grow an N-type Al layer with a thickness of 10–20 nm. c Ga 1-c N layers.

[0097] Step 304: Grow a stress-regulating layer 230 on one side of the buffer layer 220.

[0098] In step 304, the growth temperature of the stress-regulating layer 230 is set to 700–900°C, and the growth pressure is set to 100–500 torr, to grow periodically stacked In layers with a thickness of 0.1–0.6 μm. d Ga 1-d N / GaN layer.

[0099] In this embodiment, through steps 302-304, a composite buffer layer 20 can be grown on one side of the substrate 10.

[0100] The preparation method provided in this embodiment can be used to prepare a nitride semiconductor layer 80 with a composite buffer layer 20. The composite P-type layer 50 includes a nucleation layer 210, a buffer layer 220 and a stress adjustment layer 230 grown sequentially.

[0101] For nucleation layer 210, since nucleation layer 210 is a periodically stacked Al a N 1-a / In b N 1-b In the N-type layer 30, AlN provides nucleation centers with the same orientation as the substrate 10, reducing the lattice mismatch problem between the substrate 10 and the N-type layer 30. In addition, InN is more conducive to axial three-dimensional island growth than GaN in the N-type layer 30, and In atoms can generate tensile stress, which alleviates warping and makes the three-dimensional cell distribution more uniform.

[0102] For buffer layer 220, since buffer layer 220 is an N-type Al c Ga 1-c The N layer, with its smaller Al atoms, can fill Ga vacancies and merge with the three-dimensional islands to form a high-quality buffer layer 220. This further reduces lattice and thermal mismatches with the substrate 10, blocks the effects of underlying defects, and thus reduces the generation of dislocations and cracks.

[0103] For the stress-adjusting layer 230, since the stress-adjusting layer 230 is a periodically stacked In d Ga 1-d N / GaN layer, so through In d Ga 1-d The N-type layer 30 forms a lattice constant matching relationship with the N-type layer 30, which can be used as a lattice mismatch stress relief layer. This achieves low stress, no cracks or bending inside the N-type layer 30, thereby improving the lattice mismatch problem of the substrate 10, controlling the corresponding epitaxial wafer stress, and thus improving the yield and optoelectronic performance of the epitaxial wafer.

[0104] In other words, the combination of nucleation layer 210, buffer layer 220 and stress adjustment layer 230 reduces the problem of lattice mismatch.

[0105] Step 305: Grow an N-type layer 30 on one side of the stress-adjusting layer 230.

[0106] In step 305, the growth temperature of the N-type layer 30 is set to 1000-1200℃ and the growth pressure is set to 100-500 torr, to grow a heavily Si-doped N-type GaN layer with a thickness of 3-4 μm.

[0107] Step 306: Grow a quantum well layer on one side of the N-type layer 30.

[0108] In step 306, the growth temperature of the multi-quantum well layer 40 is set to 720–950°C and the growth pressure is set to 100–500 torr to grow periodically stacked InGaN well layers and GaN barrier layers, wherein the growth thickness of the InGaN well layer is 2.5 nm–4.5 nm and the growth thickness of the GaN barrier layer is 8 nm–12 nm.

[0109] For example, the number of periods in the periodically stacked InGaN well layer and GaN barrier layer is 5 to 12.

[0110] Step 307: Grow an electron blocking layer 60 on one side of the multi-quantum well layer 40.

[0111] In step 307, the growth temperature of the electron blocking layer 60 is set to 700-800°C and the growth pressure is set to 100-500 torr, to grow a P-type AlGaN layer with a thickness of 100-450 nm.

[0112] Step 308: Grow a P-type layer 50 on one side of the electron blocking layer 60.

[0113] In step 308, the growth temperature of the P-type layer 50 is set to 800–980°C and the growth pressure is set to 100–500 torr, to grow a Mg-doped P-type GaN layer with a thickness of 100–750 nm.

[0114] Step 309: Grow a P-type contact layer 70 on one side of the P-type layer 50.

[0115] In step 309, the growth temperature of the P-type contact layer 70 is set to 700-800℃ and the growth pressure is set to 100-500 torr to grow a Mg-doped P-type GaN layer.

[0116] When an electric current passes through, electrons in the N-type region and holes in the P-type region enter the active layer and recombine, emitting visible light of the required wavelength.

[0117] In this embodiment, through steps 305-309, a nitride semiconductor layer 80 can be grown on one side of the composite buffer layer 20.

[0118] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” etc., are used only to indicate relative positional relationships; when the absolute position of the described objects changes, the relative positional relationship may also change accordingly.

[0119] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A nitride semiconductor device having a composite buffer layer, characterized in that, include: Substrate (10), and a composite buffer layer (20) and a nitride semiconductor layer (80) sequentially grown on one side of the substrate (10). The composite buffer layer (20) includes a nucleation layer (210), a buffer layer (220) and a stress-regulating layer (230) grown sequentially. The nucleation layer (210) is a periodically stacked Al a N 1-a / In b N 1-b Layer, 0 < a < 1, 0 < b < 1, where Al a N 1-a The layer is used to provide nucleation centers with the same orientation as the substrate (10) for growing three-dimensional islands, In b N 1-b The layer is used to generate tensile stress acting on the three-dimensional island; The buffer layer (220) is an N-type Al c Ga 1-c N layers, 0 < c < 1, where Al c Ga 1-c Al atoms in the N layer are used to merge with the three-dimensional islands to fill Ga vacancies; The stress adjustment layer (230) is a periodic stack of In d Ga 1-d N / GaN layers, 0 < d < 1.

2. The nitride semiconductor device according to claim 1, wherein The growth thickness of the nucleation layer (210) is 30~50 nm; The growth thickness of the buffer layer (220) is 10~20nm; The growth thickness of the stress-adjusting layer (230) is 0.1~0.6 μm.

3. The nitride semiconductor device according to claim 1, wherein The nitride semiconductor layer (80) comprises an N-type layer (30), a multiple quantum well layer (40), and a P-type layer (50) stacked sequentially.

4. A method for manufacturing a nitride semiconductor device having a composite buffer layer, characterized by include: Provide a substrate (10); A composite buffer layer (20) and a nitride semiconductor layer (80) are sequentially grown on one side of the substrate (10). The composite buffer layer (20) is grown in the following manner: A nucleation layer (210), a buffer layer (220), and a stress-regulating layer (230) are grown sequentially, wherein the nucleation layer (210) is a periodically stacked Al a N 1-a / In b N 1-b Layer, 0 < a < 1, 0 < b < 1, where Al a N 1-a The layer is used to provide nucleation centers with the same orientation as the substrate (10) for growing three-dimensional islands, In b N 1-b The buffer layer (220) is used to generate tensile stress acting on the three-dimensional island and is an N-type Al. c Ga 1-c N layers, 0 < c < 1, where Al c Ga 1-c The Al atoms in the N layer are used to merge with the three-dimensional islands to fill Ga vacancies, and the stress-regulating layer (230) is a periodically stacked In layer. d Ga 1-d For N / GaN layers, 0 < d < 1.

5. The preparation method according to claim 4, characterized in that, The growth of the nucleation layer (210) includes: The growth temperature of the nucleation layer (210) was set to 700~900℃, and the growth pressure was set to 100~500 torr, to grow periodically stacked Al layers with a thickness of 30~50nm. a N 1-a / In b N 1-b layer.

6. The preparation method according to claim 4, characterized in that, Growing the buffer layer (220) includes: The growth temperature of the buffer layer (220) was set to 700~900℃, and the growth pressure was set to 100~500 torr, to grow an N-type Al with a thickness of 10~20nm. c Ga 1-c N layers.

7. The preparation method according to claim 4, characterized in that, Growing the stress-regulating layer (230) includes: The growth temperature of the stress-regulating layer (230) was set to 700~900℃, and the growth pressure was set to 100~500 torr, to grow periodically stacked In layers with a thickness of 0.1~0.6 μm. d Ga 1-d N / GaN layer.

8. The preparation method according to claim 4, characterized in that, The nitride semiconductor layer (80) is grown in the following manner: An N-type layer (30), a multi-quantum well layer (40), and a P-type layer (50) are grown sequentially.

9. The production method according to claim 8, characterized by, Growing the N-type layer (30) includes: The growth temperature of the N-type layer (30) is set to 1000~1200℃ and the growth pressure is set to 100-500 torr, and a heavily Si-doped N-type GaN layer with a thickness of 3~4 μm is grown.

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