Light Emitting Diode Chips and Their Fabrication Methods

Abstract

This disclosure provides a light-emitting diode (LED) chip and its fabrication method, belonging to the field of optoelectronic manufacturing technology. The LED chip includes a substrate, a light-emitting structure, and an anti-reflection layer. The light-emitting structure and the anti-reflection layer are located on opposite sides of the substrate. The anti-reflection layer includes multiple high-refractive-index layers and multiple low-refractive-index layers, which are alternately stacked on the substrate. The surface of the anti-reflection layer away from the substrate has multiple recesses, allowing light to escape from the recess walls and be reflected outwards. The recesses allow some light to exit the anti-reflection layer more quickly, reducing the number of refractions and reflections within the anti-reflection layer, thereby reducing light loss and further improving the brightness of the LED chip.

Description

Technical Field

[0001] This disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light-emitting diode chip and its fabrication method. Background Technology

[0002] Light-emitting diodes (LEDs) are highly influential new products in the optoelectronics industry. They are characterized by their small size, long lifespan, rich and colorful colors, and low energy consumption, and are widely used in display devices.

[0003] To improve the light extraction efficiency of light-emitting diodes (LEDs), reflective or anti-reflective layers are typically incorporated into the LED chip. For example, in LED chips where the back side of the substrate is the light-emitting surface, an anti-reflective layer is placed on the back side of the substrate, which facilitates light emission and improves the brightness of the LED chip.

[0004] However, the brightness of the LED chips with anti-reflection layers is still insufficient to meet the requirements and needs to be further improved. Summary of the Invention

[0005] This disclosure provides a light-emitting diode (LED) chip and its fabrication method, which can further improve the brightness of the LED chip. The technical solution is as follows:

[0006] In a first aspect, embodiments of this disclosure provide a light-emitting diode chip, which includes a substrate, a light-emitting structure, and an anti-reflection layer. The light-emitting structure and the anti-reflection layer are located on opposite sides of the substrate. The anti-reflection layer includes a plurality of high-refractive-index layers and a plurality of low-refractive-index layers, which are alternately stacked on the substrate. The surface of the anti-reflection layer away from the substrate has a plurality of recesses.

[0007] Optionally, the blind end of the recess is located in the low-refractive-index layer.

[0008] Optionally, the cross-sectional area of ​​the recess is positively correlated with the distance from the cross-section to the substrate.

[0009] Optionally, the bottom surface of the recess is parallel to the surface of the substrate near the antireflection layer, and the angle between the sidewall of the recess and the bottom surface of the recess is not less than the total reflection angle of the low refractive index layer.

[0010] Optionally, the recess is frustum-shaped.

[0011] Optionally, the ratio of the total area of ​​the openings of the plurality of recesses to the area of ​​the surface of the antireflective layer away from the substrate is 10% to 20%.

[0012] Optionally, the low refractive index layer is a SiO2 layer.

[0013] Optionally, the side of the antireflective layer closer to the substrate is the high refractive index layer, and the side farther from the substrate is the low refractive index layer.

[0014] Optionally, in the antireflection layer, the thickness of the high-refractive-index layer closest to the substrate is [missing information].

[0015] Secondly, embodiments of this disclosure also provide a method for fabricating the light-emitting diode chip described in the preceding aspect, the method comprising:

[0016] A light-emitting structure is formed on one side of the substrate;

[0017] An antireflection layer is formed on the other side of the substrate. The antireflection layer includes a plurality of high refractive index layers and a plurality of low refractive index layers, which are alternately stacked on the substrate.

[0018] Multiple recesses are formed on the surface of the antireflective layer away from the substrate.

[0019] The beneficial effects of the technical solutions provided in this disclosure include at least the following:

[0020] By placing a light-emitting structure on one side of a substrate and an anti-reflection layer on the other side, the anti-reflection layer is formed by alternating layers of multiple high-refractive-index and low-refractive-index layers. As light emitted from the light-emitting structure passes through the anti-reflection layer, it is reflected back towards the substrate at the interfaces between the anti-reflection layer and the substrate, and at the interfaces between the high-refractive-index and low-refractive-index layers. By configuring the thicknesses of the high-refractive-index and low-refractive-index layers according to the emission wavelength of the light-emitting structure, a phase difference of π (an odd multiple of π) between the reflected light at different interfaces can be created, causing them to cancel each other out. This reduces the amount of light reflected back to the substrate, thereby improving the light efficiency of the LED chip and increasing its brightness. Furthermore, because multiple recesses are also provided on the surface of the anti-reflection layer away from the substrate, light can also escape from the walls of these recesses and be reflected outwards. These recesses allow some light to exit the anti-reflection layer more quickly, reducing the number of refractions and reflections within the anti-reflection layer, thus reducing light loss and further improving the brightness of the LED chip. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of a light-emitting diode chip provided in an embodiment of this disclosure;

[0023] Figure 2 This is a flowchart of a method for fabricating a light-emitting diode chip according to an embodiment of the present disclosure;

[0024] Figure 3 This is a flowchart illustrating the fabrication process of a light-emitting diode chip according to an embodiment of this disclosure;

[0025] Figure 4 This is a schematic diagram illustrating the fabrication process of a light-emitting diode chip according to an embodiment of this disclosure;

[0026] Figure 5 This is a schematic diagram illustrating the fabrication process of a light-emitting diode chip according to an embodiment of this disclosure;

[0027] Figure 6 This is a schematic diagram illustrating the fabrication process of a light-emitting diode chip according to an embodiment of this disclosure;

[0028] Figure 7 This is a schematic diagram of the fabrication process of a light-emitting diode chip provided in an embodiment of this disclosure. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0030] Figure 1 This is a schematic diagram of the structure of a light-emitting diode chip provided in an embodiment of this disclosure. Figure 1 As shown, the light-emitting diode chip includes a substrate 10, a light-emitting structure 20, and an anti-reflection layer 30.

[0031] like Figure 1 As shown, the light-emitting structure 20 and the anti-reflection layer 30 are located on opposite sides of the substrate 10. The substrate 10 has a bearing surface and a back surface, which are opposite to each other. The bearing surface and the back surface are the two largest surfaces of the substrate 10. The light-emitting structure 20 is located on the bearing surface of the substrate 10, and the anti-reflection layer 30 is located on the back surface of the substrate 10.

[0032] For example, the substrate 10 may be a transparent substrate, such as a patterned sapphire substrate.

[0033] The antireflective layer 30 includes a plurality of high-refractive-index layers 31 and a plurality of low-refractive-index layers 32, which are alternately stacked on the substrate 10. The surface of the antireflective layer 30 away from the substrate 10 has a plurality of recesses 30a.

[0034] By setting a light-emitting structure 20 on one side of the substrate 10 and an anti-reflection layer 30 on the other side, the anti-reflection layer 30 is formed by alternating layers of multiple high-refractive-index layers 31 and multiple low-refractive-index layers 32. By configuring the thickness of the high-refractive-index layers 31 and 32 according to the emission wavelength of the light-emitting structure 20, the light emitted by the light-emitting structure 20 can be reflected back to the side of the substrate 10 at the interfaces between the anti-reflection layer 30 and the substrate 10, and at the interfaces between the high-refractive-index layers 31 and 32. The reflected light at these different interfaces has a phase difference of an odd multiple of π, which cancels each other out, reducing the light reflected back to the substrate 10. This improves the light extraction efficiency of the light-emitting diode chip and increases its brightness. Furthermore, since multiple recesses 30a are provided on the surface of the antireflection layer 30 away from the substrate 10, light can also be emitted from the hole wall of the recess 30a and reflected outward through the hole wall of the recess 30a. The recesses 30a can allow some light to exit the antireflection layer 30 faster, reducing the number of refractions and reflections of this part of the light in the antireflection layer 30, thereby reducing light loss and further improving the brightness of the light-emitting diode chip.

[0035] For example, the high refractive index layer 31 and the low refractive index layer 32 can be stacked alternately in 10 to 20 layers. If the total number of high refractive index layer 31 and low refractive index layer 32 is too large, it will increase the absorption of light by the anti-reflection layer 30, which is not conducive to improving the light extraction efficiency of the light-emitting diode chip.

[0036] like Figure 1 As shown, the blind end of the concave hole 30a is located in the low refractive index layer 32.

[0037] The recessed aperture 30a is a blind aperture, meaning that one end of the recessed aperture 30a is closed. The blind end of the recessed aperture 30a refers to the closed end of the recessed aperture 30a. By placing the blind end of the recessed aperture 30a in the low refractive index layer 32, when light exits from the blind end of the recessed aperture 30a, it travels from the low refractive index layer 32 into the air. This reduces the refractive index difference between the antireflection layer 30 and the air, allowing light to exit more easily from the blind end of the recessed aperture 30a. This reduces the reflected light formed at the blind end of the recessed aperture 30a, which is beneficial for further improving the light extraction efficiency of the light-emitting diode chip and increasing its brightness.

[0038] As an example, Figure 1 The blind end of the recessed aperture 30a is located in the low-refractive-index layer 32 closest to the substrate 10. In other examples, the blind end of the recessed aperture 30a may also be located in other low-refractive-index layers 32. The depth of the recessed aperture 30a can be determined according to the emission wavelength of the light-emitting diode chip. For example, a suitable depth of the recessed aperture 30a can be determined by software simulation to better improve the luminous brightness of the light-emitting diode chip.

[0039] Optionally, the cross-sectional area of ​​the recess 30a is positively correlated with the distance from the cross-section to the substrate 10.

[0040] In other words, the recessed aperture 30a can be funnel-shaped, so that after light is emitted from the aperture wall of the recessed aperture 30a, it is more easily reflected by the aperture wall and directed outwards, which is beneficial to further improve the brightness of the light-emitting diode chip. In this embodiment of the present disclosure, the aperture wall of the recessed aperture 30a includes the sidewall of the recessed aperture 30a and the bottom surface of the recessed aperture 30a, and the bottom surface of the recessed aperture 30a is the end face of the blind end of the recessed aperture 30a.

[0041] As an example, the concave hole 30a is frustum shaped.

[0042] In other words, the bottom surface of the concave hole 30a is a circular surface, and the side wall of the concave hole 30a is a conical surface. Light rays emitted from the hole wall of the concave hole 30a can be reflected out of the concave hole 30a by the conical surface.

[0043] For example, the diameter of the recess 30a is 3μm to 5μm. The diameter of the recess 30a refers to the diameter of the opening of the recess 30a, that is, the diameter of the end of the recess 30a away from the substrate 10. The larger the diameter of the recess 30a, the larger the area of ​​the sidewall of the recess 30a, which will reflect more light rays emitted perpendicularly from the substrate 10, resulting in light loss and affecting the brightness of the light emission. If the diameter of the recess 30a is too small, it will increase the difficulty of manufacturing.

[0044] In other examples, the recess 30a can also be other shapes, such as the cross-section of the recess 30a being a polygon.

[0045] Optionally, the bottom surface of the recess 30a is parallel to the surface of the substrate 10 near the antireflection layer 30. The angle between the sidewall of the recess 30a and the bottom surface of the recess 30a is not less than the total reflection angle of the low refractive index layer 32.

[0046] When light emitted from inside the LED chip shines on the bottom surface of the recess 30a, total internal reflection may occur. Light that does not undergo total internal reflection will be refracted from the bottom surface of the recess 30a and enter the recess 30a. Of the light that enters the recess 30a after refraction from the bottom surface, some will directly shine out of the recess 30a, while some will shine on the sidewall of the recess 30a and, after multiple reflections from the sidewall, will shine out of the recess 30a. When light is refracted at the bottom surface of the recess 30a, it is refracted at the interface between the low refractive index layer 32 and the air. By setting the angle between the sidewall of the recess 30a and the bottom surface of the recess 30a to be no less than the total internal reflection angle of the low refractive index layer 32, more light rays emitted from the bottom surface of the recess 30a can directly exit the recess 30a. The light rays that hit the sidewall of the recess 30a can also exit the recess 30a after fewer reflections, thereby reducing the light loss caused by the reflection of light by the sidewall of the recess 30a, which is beneficial to further improve the luminous brightness of the light-emitting diode chip.

[0047] For example, the low refractive index layer 32 is a SiO2 layer.

[0048] Using a SiO2 layer as a low refractive index layer 32, the low refractive index of SiO2 and the small difference in refractive index between SiO2 and air are beneficial for light to be emitted from the bottom surface of the concave hole 30a.

[0049] In this example, the angle between the sidewall of the recess 30a and the bottom surface of the recess 30a can be 46° to 50°.

[0050] The total internal reflection angle between SiO2 and air is 46°, therefore the angle between the sidewall of the recessed hole 30a and the bottom surface of the recessed hole 30a is set to be no less than 46°.

[0051] A portion of the light emitted perpendicularly from the substrate 10 will strike the sidewall of the recess 30a and be reflected. This increases the number of reflections within the anti-reflection layer 30, thus increasing light loss. The larger the angle between the sidewall and the bottom surface of the recess 30a, the more light strikes the sidewall, further increasing light loss. To avoid excessive light loss and affecting the brightness of the LED chip, the angle between the sidewall and the bottom surface of the recess 30a is set to within 50°.

[0052] like Figure 1 As shown, the side of the antireflective layer 30 closest to the substrate 10 is a high refractive index layer 31, and the side furthest from the substrate 10 is a low refractive index layer 32.

[0053] The side of the antireflection layer 30 closest to the substrate 10 is designated as a high-refractive-index layer 31. This means the interface between the antireflection layer 30 and the substrate 10 is also the interface between the high-refractive-index layer 31 and the substrate 10. The refractive index of the high-refractive-index layer 31 differs significantly from that of the substrate 10, and the refractive index of the high-refractive-index layer 31 is higher than that of the substrate 10. This helps prevent total internal reflection when light travels from the substrate 10 to the antireflection layer 30, thus improving the brightness of the LED chip. For example, using a TiO2 layer as the high-refractive-index layer 31 and designating the side of the antireflection layer 30 closest to the substrate 10 as a TiO2 layer, experimental tests show that this can improve the light extraction efficiency of the LED chip by approximately 0.5%.

[0054] As an example, in the antireflection layer 30, the thickness of the high refractive index layer 31 closest to the substrate 10 is...

[0055] If the high refractive index layer 31 is set too thick, it will increase the absorption of light emitted from the substrate 10 by the high refractive index layer 31, resulting in light loss, which is not conducive to improving the brightness of the light-emitting diode chip.

[0056] For example, the high refractive index layer 31 can be a TiO2 layer, a Ga2O2 layer, or a SiN layer. x layer.

[0057] Optionally, the ratio of the total area of ​​the openings of the plurality of recesses 30a to the area of ​​the surface of the antireflective layer 30 away from the substrate 10 is 10% to 20%.

[0058] The sidewalls of the recesses 30a reflect a portion of the light emitted perpendicularly from the surface of the substrate 10, resulting in light loss. The more recesses 30a there are, the larger the total area of ​​the openings, and the larger the total area of ​​the sidewalls of the recesses 30a. This causes more light emitted perpendicularly from the substrate 10 to reach the sidewalls of the recesses 30a and be reflected, thus creating light loss and affecting the brightness of the LED chip. Furthermore, too many recesses 30a can damage the structure of the antireflection layer 30, which is detrimental to improving the light extraction efficiency of the LED chip and hinders brightness enhancement.

[0059] like Figure 1 As shown, in this light-emitting diode chip, the light-emitting structure 20 includes an epitaxial structure 21 and an electrode 22. The epitaxial structure 21 may include an N-type layer 212, a multiple quantum well layer 213, and a P-type layer 214 sequentially stacked on the substrate 10. The side of the epitaxial structure 21 away from the substrate 10 has a groove exposing the N-type layer 212. Exemplarily, the N-type layer 212 includes an N-type GaN layer, and the P-type layer 214 includes a P-type GaN layer. A U-type GaN layer 211 may also be disposed between the substrate 10 and the N-type GaN layer.

[0060] Electrode 22 includes a first electrode 221 and a second electrode 222. The first electrode 221 is a P electrode, located on the P-type layer 214 and electrically connected to the P-type layer 214. The second electrode 222 is an N electrode, located in the groove 21a and electrically connected to the N-type layer 212.

[0061] A transparent conductive layer 23 may also be disposed on the P-type layer 214, and the first electrode 221 may be located on the transparent conductive layer 23.

[0062] like Figure 1 As shown, the light-emitting structure 20 may further include a reflective layer 24, which covers the surfaces of the epitaxial structure 21 and the electrode 22. The reflective layer 24 is used to reflect the light emitted by the multiple quantum well layer 213 toward the side where the substrate 10 is located.

[0063] For example, the reflective layer 24 may be a distributed Bragg reflector layer (DBR).

[0064] like Figure 1 As shown, the light-emitting structure 20 may also include solder joints 25, which are located on the surface of the reflective layer 24 away from the substrate 10, and are connected to the electrode 22.

[0065] The solder joint 25 may include a first solder joint 251 and a second solder joint 252. The first solder joint 251 is electrically connected to the first electrode 221, and the second solder joint 252 is electrically connected to the second electrode 222.

[0066] Figure 2 This is a flowchart illustrating a method for fabricating a light-emitting diode (LED) chip according to an embodiment of this disclosure. This method is used to fabricate... Figure 1 The light-emitting diode chip shown is an example. Figure 2 As shown, the preparation method includes:

[0067] In step S11, a light-emitting structure 20 is formed on one side of the substrate 10.

[0068] In step S12, an antireflection layer 30 is formed on the other side of the substrate 10.

[0069] The antireflective layer 30 includes multiple high-refractive-index layers 31 and multiple low-refractive-index layers 32, which are alternately stacked on the substrate 10.

[0070] In step S13, a plurality of recesses 30a are formed on the surface of the antireflective layer 30 away from the substrate 10.

[0071] By setting a light-emitting structure 20 on one side of the substrate 10 and an anti-reflection layer 30 on the other side, the anti-reflection layer 30 is formed by alternating layers of multiple high-refractive-index layers 31 and multiple low-refractive-index layers 32. By configuring the thickness of the high-refractive-index layers 31 and 32 according to the emission wavelength of the light-emitting structure 20, the light emitted by the light-emitting structure 20 can be reflected back to the side of the substrate 10 at the interfaces between the anti-reflection layer 30 and the substrate 10, and at the interfaces between the high-refractive-index layers 31 and 32. The reflected light at these different interfaces has a phase difference of an odd multiple of π, which cancels each other out, reducing the light reflected back to the substrate 10. This improves the light extraction efficiency of the light-emitting diode chip and increases its brightness. Furthermore, since multiple recesses 30a are provided on the surface of the antireflection layer 30 away from the substrate 10, light can also be emitted from the hole wall of the recess 30a and reflected outward through the hole wall of the recess 30a. The recesses 30a can allow some light to exit the antireflection layer 30 faster, reducing the number of refractions and reflections of this part of the light in the antireflection layer 30, thereby reducing light loss and further improving the brightness of the light-emitting diode chip.

[0072] Figure 3 This is a flowchart illustrating the fabrication process of a light-emitting diode chip according to an embodiment of this disclosure. Figures 4-7 This is a schematic diagram illustrating the fabrication process of a light-emitting diode chip according to an embodiment of this disclosure. The following is combined with... Figures 4-7 The fabrication method of this light-emitting diode chip is described. For example... Figure 3 As shown, the preparation method includes:

[0073] In step S21, a substrate 10 is provided.

[0074] Optionally, the substrate 10 is a sapphire substrate, a silicon substrate, or a silicon carbide substrate. The substrate 10 can be a flat substrate or a patterned substrate.

[0075] As an example, in this embodiment of the disclosure, the substrate 10 is a patterned sapphire substrate. Sapphire substrates are a commonly used substrate, with mature technology and low cost.

[0076] In step S21, the sapphire substrate can be pretreated by placing it in an MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and baking it for 12 to 18 minutes.

[0077] In step S22, an N-type layer 212 is formed on one side of the substrate 10.

[0078] For example, the N-type layer 212 may be an N-type GaN layer.

[0079] Optionally, the growth temperature of the N-type layer 212 is 1000℃~1200℃; the growth pressure can be 50Torr~200Torr; and the Si doping concentration in the N-type layer 212 can be 5×10⁻⁶. 18 cm -3 ~10 20 cm -3 The thickness of the N-type layer 212 can be 1μm to 4μm.

[0080] In some examples, such as Figure 4 As shown, before forming the N-type layer 212, a U-type GaN layer 211 can be formed on the substrate 10. Furthermore, before forming the U-type GaN layer 211, a buffer layer can be formed on the substrate 10; for example, the buffer layer can be an AlN buffer layer.

[0081] In step S23, a multi-quantum well layer 213 is formed on the N-type layer 212.

[0082] Exemplarily, the multi-quantum-well layer 213 includes multiple alternating quantum well layers and quantum barrier layers. Optionally, the number of alternating stacked quantum well layers and quantum barrier layers can be 3 to 8. Exemplarily, in this embodiment of the present disclosure, the number of alternating stacked quantum well layers and quantum barrier layers is 5.

[0083] In step S24, a P-type layer 214 is formed on the multi-quantum well layer 213.

[0084] For example, the P-type layer 214 may be a P-type GaN layer.

[0085] Optionally, the growth temperature of the P-type layer 214 can be 850℃~1050℃; the growth pressure of the P-type layer 214 can be 100Torr~600Torr.

[0086] Through steps S22 to S24, an epitaxial structure 21 is formed on the substrate 10.

[0087] In step S25, a groove 21a is formed on the P-type layer 214 to expose the N-type layer 212.

[0088] For example, a groove 21a can be formed on the P-type layer 214 by plasma etching.

[0089] In step S26, a transparent conductive layer 23 is formed on the P-type layer 214.

[0090] like Figure 5 As shown, a transparent conductive layer 23 is formed on the P-type layer 214.

[0091] For example, the transparent conductive layer 23 can be formed by deposition using a transparent conductive material such as indium tin oxide (ITO).

[0092] In step S27, electrode 22 is formed.

[0093] like Figure 5 As shown, electrode 22 includes a first electrode 221 and a second electrode 222. The first electrode 221 is a P electrode located on the transparent conductive layer 23, and the second electrode 222 is an N electrode located in the groove 21a and electrically connected to the N-type layer 212.

[0094] For example, electrode 22 can be deposited by metal sputtering.

[0095] In step S28, a reflective layer 24 is formed on the surface of the epitaxial structure 21 and the electrode 22.

[0096] like Figure 6 As shown, a reflective layer 24 is formed on the epitaxial structure 21 and the electrode 22.

[0097] For example, the reflective layer 24 can be a distributed Bragg reflector (DBR). Vias can be provided on the reflective layer 24 at positions corresponding to the electrode 22 to facilitate the subsequent connection of the solder joint 25 to the electrode 22.

[0098] In step S29, solder joints 25 are formed on the reflective layer 24.

[0099] like Figure 6 As shown, solder joint 25 may include a first solder joint 251 and a second solder joint 252. The first solder joint 251 is electrically connected to the first electrode 221, and the second solder joint 252 is electrically connected to the second electrode 222. Solder joint 25 may be deposited on the surface of reflective layer 24 by metal sputtering.

[0100] The fabrication of the light-emitting structure 20 is now complete.

[0101] In step S30, an antireflection layer 30 is formed on the surface of the substrate 10 away from the light-emitting structure 20.

[0102] like Figure 7 As shown, the antireflective layer 30 includes a plurality of high refractive index layers 31 and a plurality of low refractive index layers 32. The plurality of high refractive index layers 31 and the plurality of low refractive index layers 32 are alternately stacked on the substrate 10.

[0103] Optionally, the high refractive index layer 31 can be a TiO2 layer, a Ga2O2 layer, or a SiN layer. x The low-refractive-index layer 32 can be a SiO2 layer.

[0104] In step S31, a plurality of recesses 30a are formed on the antireflective layer 30.

[0105] like Figure 7As shown, the concave hole 30a is a blind hole, and the blind end of the concave hole 30a is located in the low refractive index layer 32.

[0106] For example, the recessed hole 30a can be formed on the antireflection layer 30 by etching.

[0107] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the element or object preceding “comprising” or “including” encompasses the element or object listed following “comprising” or “including” and its equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0108] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A light-emitting diode chip, characterized in that, The device includes a substrate (10), a light-emitting structure (20), and an anti-reflection layer (30). The light-emitting structure (20) and the anti-reflection layer (30) are located on opposite sides of the substrate (10). The anti-reflection layer (30) includes a plurality of high refractive index layers (31) and a plurality of low refractive index layers (32). The plurality of high refractive index layers (31) and the plurality of low refractive index layers (32) are alternately stacked on the substrate (10). The surface of the anti-reflection layer (30) away from the substrate (10) has a plurality of recesses (30a). The blind end of the concave hole (30a) is located in the low refractive index layer (32); The side of the antireflective layer (30) closest to the substrate (10) is the high refractive index layer (31), the refractive index of the high refractive index layer (31) is higher than the refractive index of the substrate (10), and the side away from the substrate (10) is the low refractive index layer (32). The recess (30a) is formed on the high refractive index layer (31) and the low refractive index layer (32), except for the one high refractive index layer (31) and the one low refractive index layer (32) closest to the substrate (10).

2. The light-emitting diode chip according to claim 1, characterized in that, The cross-sectional area of ​​the recess (30a) is positively correlated with the distance from the cross-section to the substrate (10).

3. The light-emitting diode chip according to claim 2, characterized in that, The bottom surface of the recess (30a) is parallel to the surface of the substrate (10) near the antireflection layer (30), and the angle between the sidewall of the recess (30a) and the bottom surface of the recess (30a) is not less than the total reflection angle of the low refractive index layer (32).

4. The light-emitting diode chip according to claim 3, characterized in that, The concave hole (30a) is frustum shaped.

5. The light-emitting diode chip according to any one of claims 1 to 4, characterized in that, The ratio of the total area of ​​the openings of the plurality of recesses (30a) to the area of ​​the surface of the antireflective layer (30) away from the substrate (10) is 10% to 20%.

6. The light-emitting diode chip according to any one of claims 1 to 4, characterized in that, The low refractive index layer (32) is a SiO2 layer.

7. The light-emitting diode chip according to claim 6, characterized in that, In the antireflection layer (30), the high refractive index layer (31) closest to the substrate (10) has a thickness of 100 Å to 500 Å.

8. A method for fabricating a light-emitting diode chip, characterized in that, include: A light-emitting structure (20) is formed on one side of the substrate (10); An antireflective layer (30) is formed on the other side of the substrate (10). The antireflective layer (30) includes a plurality of high refractive index layers (31) and a plurality of low refractive index layers (32). The plurality of high refractive index layers (31) and the plurality of low refractive index layers (32) are alternately stacked on the substrate (10). The side of the antireflective layer (30) closer to the substrate (10) is the high refractive index layer (31), and the refractive index of the high refractive index layer (31) is higher than that of the substrate (10). The side away from the substrate (10) is the low refractive index layer (32). A plurality of recesses (30a) are formed on the surface of the antireflection layer (30) away from the substrate (10), and the blind ends of the recesses (30a) are located in the low refractive index layer (32); the recesses (30a) are formed on the high refractive index layer (31) and the low refractive index layer (32) except for the one high refractive index layer (31) and the one low refractive index layer (32) closest to the substrate (10).

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