Power management system and method

Abstract

A power management system and method are disclosed. When an under-voltage lockout circuit determines that a shared voltage of the power management system is less than a first lockout voltage, the under-voltage lockout circuit outputs a first under-voltage lockout signal to control a power converter supplying a highest output voltage to rapidly ramp down the supplied output voltage to zero. Subsequently, the under-voltage lockout circuit outputs a second under-voltage lockout signal to control a power converter supplying a lowest output voltage to gradually ramp down the supplied output voltage to zero.

Description

Technical Field

[0001] This invention relates to power supplies, and more specifically to a power management system and method. Background Technology

[0002] System-on-a-Chip (SoC) devices increasingly utilize advanced manufacturing processes (below 28 nanometers). The shrinking transistor size and limitations of component manufacturing processes, coupled with the fact that the corresponding operating voltages and signal levels for the system specifications have not decreased accordingly, have created difficulties and challenges in circuit design. SoCs obtain the power required for operation from a power management system (Power Management System). However, the multiple output voltages supplied by the Power Management System may fall within a wide range, such as 1.8V to 3.3V. During hot-swapping / hot-plugging operations, the maximum voltage difference between two of the output voltages supplied to the SoC may exceed the voltage threshold that the SoC can withstand, causing damage to some functions within the SoC or even rendering the entire SoC unusable. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a power management system that addresses the shortcomings of existing technologies, including a power conversion circuit and an undervoltage lockout circuit. The power conversion circuit includes multiple power converters. These multiple power converters are configured to supply multiple output voltages. The power converter supplying the lowest output voltage is defined as the first power converter. The power converter supplying the highest output voltage is defined as the second power converter. When the undervoltage lockout circuit determines that the shared voltage has dropped below a first lockout voltage, the undervoltage lockout circuit outputs a first undervoltage lockout signal to the second power converter. The second power converter rapidly reduces its supplied output voltage to zero based on the first undervoltage lockout signal. After the output voltage of the second power converter drops to zero, the undervoltage lockout circuit outputs a second undervoltage lockout signal to the first power converter, and the first power converter gradually reduces its supplied output voltage to zero based on the second undervoltage lockout signal.

[0004] In this embodiment, after the second power converter rapidly reduces the supplied output voltage to zero, the undervoltage lockout circuit determines whether the shared voltage has decreased to below a second lockout voltage. The second lockout voltage is lower than the first lockout voltage. Until the shared voltage decreases to below the second lockout voltage, the undervoltage lockout circuit outputs a second undervoltage lockout signal to the first power converter to control the first power converter to gradually reduce the supplied output voltage to zero.

[0005] In one embodiment, the power management system further includes a main control circuit. The main control circuit is connected to a power conversion circuit and an undervoltage lockout circuit. The main control circuit is configured to control a second power converter based on a first undervoltage lockout signal received from the undervoltage lockout circuit, and to control a first power converter based on a second undervoltage lockout signal.

[0006] In this embodiment, the power management system further includes a timing circuit. The timing circuit is connected to the main control circuit. The main control circuit controls the timing circuit to start timing after the output voltage of the second power converter begins to decrease. When the timing circuit reaches a default time, it outputs a timing signal to the main control circuit. Based on the timing signal, the main control circuit controls the first power converter to gradually reduce the supplied output voltage to zero.

[0007] In this embodiment, when the shared voltage drops below the first locking voltage, the undervoltage lockout circuit outputs a voltage reduction indication signal to the main control circuit. The main control circuit then controls the power converter supplying the highest output voltage among the multiple power converters to reduce its output voltage according to the reference voltage indicated by the voltage reduction indication signal.

[0008] In this embodiment, the power management system further includes a differential voltage detection circuit. The differential voltage detection circuit is connected to the main control circuit and the power conversion circuit. The differential voltage detection circuit is configured to calculate the difference between the highest and lowest output voltages among multiple output voltages. When the differential voltage detection circuit determines that the difference is greater than a default differential voltage, it outputs a differential voltage detection signal to the main control circuit. The main control circuit controls the operation of the multiple power converters based on the differential voltage detection signal, such that the time at which the highest output voltage begins to gradually rise differs from the time at which the lowest output voltage begins to gradually rise, or the time at which the highest output voltage begins to gradually fall differs from the time at which the lowest output voltage begins to gradually fall.

[0009] In this embodiment, the differential pressure detection circuit includes a multiplexer, an error amplifier, and a comparator. The input of the multiplexer is connected to a power conversion circuit. The output of the multiplexer is connected to the first and second inputs of the error amplifier. The first input of the comparator is connected to the output of the error amplifier. The second input of the comparator is coupled to a preset differential pressure. The output of the comparator is connected to the input of the main control circuit. The multiplexer selects the highest and lowest output voltages from multiple output voltages and transmits them to the first and second inputs of the error amplifier, respectively. The error amplifier amplifies the difference between the highest and lowest output voltages to output an amplified error signal to the first input of the comparator. The comparator compares the voltage of the amplified error signal with the default differential pressure to output a differential pressure detection signal to the main control circuit.

[0010] In this embodiment, each power converter includes an upper bridge switch, a lower bridge switch, and a drive circuit. The first terminal of the upper bridge switch is coupled to the input voltage. The second terminal of the upper bridge switch is connected to the first terminal of the lower bridge switch. The second terminal of the lower bridge switch is grounded. The node between the upper and lower bridge switches is connected to the first terminal of an inductor. The second terminal of the inductor is connected to the first terminal of a capacitor. The second terminal of the capacitor is grounded. The drive circuit is connected to the control terminals of both the upper and lower bridge switches. The main control circuit is connected to the drive circuit.

[0011] In one embodiment, each power converter further includes an operational amplifier. A first input of the operational amplifier is connected to a digital-to-analog converter (DAC) and receives analog signals from the DAC. A second input of the operational amplifier is connected to a node between a second terminal of an inductor and a first terminal of a capacitor.

[0012] In this embodiment, each power converter further includes a voltage divider circuit. The input of the voltage divider circuit is connected to the node between the second terminal of the inductor and the first terminal of the capacitor. The output of the voltage divider circuit is connected to the input of the multiplexer. The second input of the operational amplifier is connected through the voltage divider circuit to the node between the second terminal of the inductor and the first terminal of the capacitor.

[0013] In one embodiment, each power converter further includes a discharge circuit. The discharge circuit is connected to a node between a second terminal of an inductor and a first terminal of a capacitor. The discharge circuit is configured to adjust the voltage at the node between the second terminal of the inductor and the first terminal of the capacitor.

[0014] In this embodiment, the discharge circuit includes multiple resistors. These resistors are connected in parallel. The first terminal of each resistor is connected to a node between the second terminal of an inductor and the first terminal of a capacitor. The second terminal of each resistor is grounded.

[0015] In this embodiment, the discharge circuit of each power converter further includes a switching component. The control terminal of the switching component is connected to the main control circuit. The first terminal of the switching component is connected to the second terminal of each resistor, and the second terminal of the switching component is grounded.

[0016] In one embodiment, when the shared voltage drops below the first locking voltage, the drive circuit in the second power converter turns on the lower bridge switch to accelerate the output voltage of the second power converter down to zero.

[0017] In addition, the present invention provides a power management method comprising the following steps: configuring multiple power converters to supply multiple output voltages respectively; defining the power converter supplying the lowest output voltage as a first power converter; defining the power converter supplying the highest output voltage as a second power converter; detecting a shared voltage used by the power management system; determining whether the shared voltage has decreased to less than a first locking voltage; if not, continuously detecting the shared voltage; if so, proceeding to the next step; rapidly reducing the output voltage supplied by the second power converter to zero; and gradually reducing the output voltage supplied by the first power converter to zero.

[0018] In an embodiment, the power management method further includes the following steps: after the second power converter rapidly reduces the supplied output voltage to zero, it is determined whether the shared voltage has decreased to less than the second locking voltage; if not, the shared voltage is continuously monitored and the process returns to the previous step; if yes, the next step is executed; and the output voltage supplied by the first power converter is gradually reduced to zero.

[0019] In an embodiment, the power management method further includes the following steps: starting a timer after the second power converter rapidly reduces the supplied output voltage to zero; and determining whether the timer has reached a preset time. If not, returning to the previous step and continuing the timer; if so, controlling the first power converter to gradually reduce the supplied output voltage to zero.

[0020] In an embodiment, the power management method further includes the following steps: determining whether the shared voltage has dropped below a first locking voltage; if not, continuously detecting the shared voltage and returning to the previous step; if yes, executing the next step; and controlling the power converter that supplies the highest output voltage among the multiple power converters to reduce the output voltage according to a reference voltage.

[0021] In an embodiment, the power management method further includes the following steps: selecting the highest output voltage and the lowest output voltage from multiple output voltages of multiple power converters; calculating the difference between the highest output voltage and the lowest output voltage; determining whether the difference is greater than a preset voltage difference; if not, returning to the previous step; if so, executing the next step; and controlling the operation of multiple power converters such that the time point at which the highest output voltage begins to gradually rise is different from the time point at which the lowest output voltage begins to gradually rise.

[0022] In an embodiment, the power management method further includes the following steps: selecting the highest output voltage and the lowest output voltage from multiple output voltages of multiple power converters; calculating the difference between the highest output voltage and the lowest output voltage; determining whether the difference is greater than a preset voltage difference; if not, returning to the previous step; if so, executing the next step; and controlling the operation of multiple power converters such that the time point at which the highest output voltage begins to gradually decrease is different from the time point at which the lowest output voltage begins to gradually decrease.

[0023] As described above, the present invention provides a power management system and method that can control multiple power converters to start increasing or decreasing their output voltage at different times, specifically allowing the highest and lowest output voltages of the power conversion circuit to decrease to zero within different time intervals. This prevents excessive voltage differences between the multiple output voltages supplied by the power conversion circuit within the same time interval, thereby preventing damage to circuit components (e.g., system chips) receiving the multiple output voltages supplied by the power converters due to excessive voltage differences.

[0024] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0025] Figure 1 This is a flowchart of the first step of the power management method according to an embodiment of the present invention.

[0026] Figure 2 This is a flowchart of the second step of the power management method according to an embodiment of the present invention.

[0027] Figure 3 This is a flowchart of the third step of the power management method according to an embodiment of the present invention.

[0028] Figure 4 This is a flowchart of the fourth step of the power management method according to an embodiment of the present invention.

[0029] Figure 5 This is a block diagram of a power management system according to an embodiment of the present invention.

[0030] Figure 6 This is a circuit layout diagram of the power management system according to an embodiment of the present invention.

[0031] Figure 7 The waveform diagram is shown for the power management system and method according to an embodiment of the present invention. Detailed Implementation

[0032] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. Furthermore, the accompanying drawings of the present invention are for simple illustrative purposes only and are not depictions of actual dimensions, as stated in advance. The following embodiments will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the scope of protection of the present invention. In addition, the term "or" as used herein may, depending on the actual situation, include any combination of any one or more of the associated listed items.

[0033] Please see Figure 1 , Figure 5 and Figure 7 ,in Figure 1 This is a flowchart of the first step of the power management method according to an embodiment of the present invention; Figure 5 This is a block diagram of the power management system according to an embodiment of the present invention; Figure 7 The waveform diagram is shown for the power management system and method according to an embodiment of the present invention.

[0034] The power management method of this invention may include, as in the following embodiments: Figure 1 Steps S101 to S109 shown can be performed by, as follows Figure 5 The power management system shown includes a power conversion circuit 10, an undervoltage lockout circuit 20, and a main control circuit 30.

[0035] The main control circuit 30 can be connected to the power conversion circuit 10 and the undervoltage lockout circuit 20. The power conversion circuit 10 may include multiple power converters PT1 to PTn. The multiple power converters PT1 to PTn are configured to supply multiple output voltages to external circuit components such as a system-on-a-chip (not shown in the figure).

[0036] For example, such as Figure 1 The number of power converters PT1 to PTn shown is 6, i.e., n=6, which supply power to various applications such as power supplies to ... Figure 7The multiple output voltages Vout1 to Vout6 shown are used to define the power converter PT1, which supplies the lowest output voltage VL among the multiple power converters PT1 to PT6. This power converter PT1 is defined as the first power converter PT1 described herein. The power converter PT2, which supplies the highest output voltage VH among the multiple power converters PT1 to PT6, is defined as the second power converter PT2 described herein. The difference between the lowest output voltage VL supplied by the first power converter PT1 and the highest output voltage VH supplied by the second power converter PT2 is defined herein as the limiting voltage difference. The purpose of this invention is to prevent the difference between two output voltages received by a single system chip from the power conversion circuit 10 from being the limiting voltage difference.

[0037] It should be understood that the number of power converters PT1 to PTn included in the power conversion circuit 10 may depend on actual needs, and in actual operation, some of the power converters may supply the same output voltage. The above is only an example and the present invention is not limited thereto.

[0038] In step S101, the power management system enters the power-off mode.

[0039] If necessary, before executing step S103, the following step can be performed first: the undervoltage lockout circuit 20 determines whether the shared voltage VCC is decreasing. For example, the undervoltage lockout circuit 20 determines whether the shared voltage VCC used by the power management system has decreased to below a lockout voltage, for example... Figure 7 The shared voltage VCC shown is gradually decreasing. If the shared voltage VCC is less than the locking voltage UVLO, proceed to step S103.

[0040] In step S103, the undervoltage lockout circuit 20 determines whether the shared voltage VCC has dropped below the first lockout voltage, for example... Figure 7 The first locking voltage UVLOH is shown. For example, the first locking voltage UVLOH is less than the locking voltage UVLO.

[0041] If the shared voltage VCC does not drop below the first locking voltage, the undervoltage lockout circuit 20 continues to monitor the shared voltage VCC and executes step S103 again. Conversely, if the shared voltage VCC is less than the first locking voltage, step S105 is executed.

[0042] In step S105, when the shared voltage VCC drops below the first locking voltage, the undervoltage lockout circuit 20 can output a first undervoltage lockout signal to the main control circuit 30. The main control circuit 30 can quickly reduce the highest output voltage VH (or the power converter PT2) according to the first undervoltage lockout signal, and quickly reduce all output voltages except the minimum output voltage VL to zero.

[0043] For example, when the shared voltage VCC is less than the first locking voltage, the undervoltage lockout circuit 20 can output a voltage reduction indication signal to the main control circuit 30. The main control circuit 30 can then control the power converter PT2 to quickly reduce the maximum output voltage VH supplied by the power converter PT2 according to a reference voltage indicated by the voltage reduction indication signal. Figure 7 As shown, compared to other power converters, the output voltages Vout3 to Vout6 of PT3 to PT6 drop faster and begin to drop earlier than the lowest output voltage VL.

[0044] In step S107, after the power converters PT2 to PTn reduce the supplied output voltage to zero, the undervoltage lockout circuit 20 determines whether the shared voltage VCC is less than the second lockout voltage, for example... Figure 7 The second locking voltage, UVLOL. For example... Figure 7 As shown, the second locking voltage UVLOL is less than the first locking voltage UVLOH.

[0045] If the shared voltage VCC does not drop below the second lockout voltage, the undervoltage lockout circuit 20 continues to monitor the shared voltage VCC and executes step S107 again. Conversely, if the shared voltage VCC is less than the second lockout voltage, step S109 is executed.

[0046] In step S109, the undervoltage lockout circuit 20 outputs a second undervoltage lockout signal to the main control circuit 30. The main control circuit 30 can control the power converter PT1 to gradually reduce the supplied minimum output voltage VL to zero based on the second undervoltage lockout signal.

[0047] In power-off mode, if the power management system sets both the first lockout voltage and the second lockout voltage, steps S101 to S109 described above can be executed. In power-off mode, if the power management system sets only the first lockout voltage but not the second lockout voltage, steps S201 to S211 described below can be executed.

[0048] Whether performing steps S101 to S109 or steps S201 to S211, the highest output voltage VH and the lowest output voltage VL of the power conversion circuit 10 can gradually decrease within different time intervals or begin decreasing at different time points. This avoids situations where the voltage difference between the multiple output voltages supplied by the power conversion circuit 10 is too large at the same time point, which could damage the circuit components receiving the multiple output voltages of the power conversion circuit 10.

[0049] Please see Figure 2 and Figure 5 ,in Figure 2 This is a flowchart of the second step of the power management method according to an embodiment of the present invention; Figure 5This is a block diagram of a power management system according to an embodiment of the present invention.

[0050] The power management method of this invention may include, as in the following embodiments: Figure 2 Steps S201 to S211 shown can be performed by, for example Figure 5 The power management system shown includes a power conversion circuit 10, an undervoltage lockout circuit 20, a main control circuit 30, and a timing circuit 40. The main control circuit 30 can be connected to the power conversion circuit 10, the undervoltage lockout circuit 20, and the timing circuit 40. The multiple power converters PT1 to PTn of the power conversion circuit 10 are configured to supply multiple output voltages.

[0051] In step S201, the power management system enters the power-off mode.

[0052] In step S203, the undervoltage lockout circuit 20 determines whether the shared voltage VCC has dropped below the first lockout voltage, for example... Figure 7 The first locking voltage UVLOH is shown.

[0053] If the shared voltage VCC is not less than the first locking voltage UVLOH, the undervoltage lockout circuit 20 continues to monitor the shared voltage VCC and executes step S203 again. Conversely, if the shared voltage VCC is less than the first locking voltage, step S205 is executed.

[0054] In step S205, when the shared voltage VCC is less than the first locking voltage, the undervoltage lockout circuit 20 outputs a first undervoltage lockout signal to the main control circuit 30. Based on the first undervoltage lockout signal, the main control circuit 30 quickly reduces the highest output voltage VH (or the power converter PT2) and quickly reduces all output voltages except the minimum output voltage to zero.

[0055] In step S207, after the power converters PT2 to PTn begin to reduce the supplied output voltage to zero, the main control circuit 30 controls the timing circuit 40 to start timing.

[0056] In step S209, during the timing process of the timing circuit 40, the timing circuit 40 determines whether the timing time has reached a preset time. If the timing time has not yet reached the preset time, the timing circuit 40 continues timing. Conversely, if the timing time has reached the preset time, step S211 is executed.

[0057] In step S211, the timing circuit 40 outputs a timing signal to the main control circuit 30. Based on the timing signal, the main control circuit 30 controls the power converter PT1, which supplies the lowest output voltage VL, to gradually reduce the supplied output voltage to zero.

[0058] Please see Figure 3This is a flowchart illustrating the third step of the power management method according to an embodiment of the present invention. The power management method according to an embodiment of the present invention may include, for example: Figure 3 The steps S301 to S307 shown apply to multiple power converters in a power management system. The multiple power converters are configured to supply multiple output voltages.

[0059] In step S301, the power management system enters the power-on mode.

[0060] In step S303, the differential pressure detection circuit calculates the difference between the highest output voltage of the power conversion circuit 10 (i.e., the highest output voltage VH of the power converter PT2) and the lowest output voltage of the power conversion circuit 10 (i.e., the lowest output voltage VL of the power converter PT1).

[0061] In step S305, the differential pressure detection circuit determines whether the difference between the highest output voltage VH and the lowest output voltage VL is greater than a preset differential pressure. If the differential pressure detection circuit determines that the difference between the highest output voltage VH and the lowest output voltage VL is not greater than the preset differential pressure, step S305 is executed again. Conversely, if the differential pressure detection circuit determines that the difference between the highest output voltage VH and the lowest output voltage VL is greater than the preset differential pressure, the differential pressure detection circuit outputs a differential pressure detection signal to the main control circuit, and then step S307 is executed.

[0062] In step S307, the main control circuit quickly reduces the highest output voltage VH (or power converter PT2) based on the differential pressure detection signal, and quickly reduces the output voltage supplied by other power converters PT3 to PTn to zero.

[0063] Please see Figure 6 and Figure 7 ,in Figure 6 This is a circuit layout diagram of the power management system according to an embodiment of the present invention; Figure 7 The waveform diagram is shown for the power management system and method according to an embodiment of the present invention.

[0064] like Figure 3 Steps S301 to S307 of the power management method shown can be derived from, for example: Figure 6 The power management system shown is executed. The configuration of power converters PT2 to PTn in the power management system is the same as or similar to that of power converter PT1. The following description only focuses on power converter PT1, and the same or similar content will not be repeated in this article.

[0065] like Figure 6As shown, the power converter PT1 may include an upper bridge switch UG1, a lower bridge switch LG1, an inductor L1 and a capacitor C1, a drive circuit D1, an operational amplifier OP1, a digital-to-analog converter A1, and a voltage divider circuit VRD1, but the present invention is not limited thereto. In actual operation, the circuit components included in the power converter PT1, such as, but not limited to, the voltage divider circuit VRD1, may be appropriately omitted.

[0066] The node between the second terminal of inductor L1 and the first terminal of capacitor C1 is the output terminal of power converter PT1. The first terminal of upper bridge switch UG1 is coupled to the input voltage Vin. The second terminal of upper bridge switch UG1 is connected to the first terminal of lower bridge switch LG1. The node between the second terminal of upper bridge switch UG1 and the first terminal of lower bridge switch LG1 can be connected to the first terminal of inductor L1. The second terminal of inductor L1 is connected to the first terminal of capacitor C1. The second terminal of capacitor C1 is grounded.

[0067] The control terminals of the upper bridge switch UG1 and the lower bridge switch LG1 can be connected to the output terminal of the drive circuit D1. The input terminal of the drive circuit D1 can be connected to the output terminal of the operational amplifier OP1 and the output terminal of the main control circuit 30. The first input terminal of the operational amplifier OP1, such as the inverting input terminal, can be connected to the digital-to-analog converter A1. The second input terminal of the operational amplifier OP1, such as the non-inverting input terminal, can be connected (through the voltage divider circuit VRD1) to the node between the second terminal of the inductor L1 and the first terminal of the capacitor C1.

[0068] The digital-to-analog converter A1 can be connected to an external digital signal supply circuit (not shown in the figure) and receive the digital signal DS1 from the external digital signal supply circuit. The digital-to-analog converter A1 can convert the digital signal DS1 into an analog signal and input it to the first input terminal of the operational amplifier OP1.

[0069] The second input terminal of the operational amplifier OP1 of the power converter PT1, such as the non-inverting input terminal, can receive the output voltage Vout1 from the output terminal of the power converter PT1, or, as in this embodiment, the voltage divided by the voltage divider circuit VRD1 after the output voltage Vout1 is divided. That is, as... Figure 6 The minimum output voltage VL shown is the output voltage Vout1 of power converter PT1 or a voltage divider of output voltage Vout1. Similarly, as... Figure 6 The highest output voltage VH shown is the output voltage Vout2 of the power converter PT2 or the voltage divider of the output voltage Vout2.

[0070] In this embodiment, the multiple power converters PT1 to PTn of the power conversion circuit 10 supply output voltages Vout1 to Voutn respectively, with output voltage Vout1 being the lowest output voltage VL and Vout2 being the highest output voltage VH.

[0071] For example, such as Figure 6 As shown, the differential voltage detection circuit 50 of the power management system may include a multiplexer 501, an error amplifier 502, and a comparator 503. Multiple inputs of the multiplexer 501 can be connected (respectively via multiple voltage divider circuits VRD1 to VRDn) to multiple outputs of multiple power converters PT1 to PTn. The multiple inputs of the multiplexer 501 can receive multiple output voltages Vout1 to Voutn from the multiple power converters PT1 to PTn, or receive multiple divided voltages from the multiple output voltages Vout1 to Voutn from the multiple voltage divider circuits VRD1 to VRDn.

[0072] The multiplexer 501 selects the highest and lowest output voltages from multiple output voltages Vout1 to Voutn of multiple power converters PT1 to PTn, or selects the maximum and minimum voltage divider voltages from multiple voltage dividers, as follows: Figure 6 The highest output voltage VH and the lowest output voltage VL are shown. Next, the multiplexer 501 transmits the highest output voltage VH to the first input terminal of the error amplifier 502, such as the inverting input terminal, and transmits the lowest output voltage VL to the second input terminal of the error amplifier 502, such as the non-inverting input terminal.

[0073] Error amplifier 502 calculates the difference between the highest output voltage VH and the lowest output voltage VL. This difference is then amplified to output an amplified error signal to the first input of comparator 503, such as a non-inverting input. The second input of comparator 503, such as an inverting input, can be coupled to a preset voltage difference Vx. Comparator 503 compares the voltage of the amplified error signal with the preset voltage difference Vx to output a voltage difference detection signal to the main control circuit 30. The main control circuit 30 uses this voltage difference detection signal to adjust the timing and magnitude of the output voltages of the multiple power converters PT1 to PTn.

[0074] Please see Figure 4 , Figure 5 and Figure 7 ,in Figure 4 This is a flowchart of the fourth step of the power management method according to an embodiment of the present invention; Figure 5 This is a block diagram of the power management system according to an embodiment of the present invention; Figure 7 The waveform diagram is shown for the power management system and method according to an embodiment of the present invention.

[0075] The power management method of this invention may include, as in the following embodiments: Figure 4 Steps S401 to S407 shown can be performed by, for example Figure 5 The power management system shown is executed.

[0076] In step S401, the power management system enters the power-on mode.

[0077] In step S403, the undervoltage lockout circuit 20 determines whether the shared voltage VCC used by the power management system is greater than a lockout voltage, for example... Figure 7 The locking voltage UVLO is shown.

[0078] If the shared voltage VCC is not greater than the lockout voltage, continue to monitor the shared voltage VCC and execute step S403 again. Conversely, if the shared voltage VCC is greater than the lockout voltage, execute step S405.

[0079] In step S405, the order in which the output voltages Vout1 to Voutn of the multiple power converters PT1 to PTn are sequentially increased is determined.

[0080] In step S407, following the sequence determined in step S405, the output voltages Vout1 to Voutn of the multiple power converters PT1 to PTn are gradually increased sequentially. For example... Figure 7 As shown, the timing of the start of the increase of the multiple output voltages Vout1 to Vout6 of the multiple power converters PT1 to PT6 are different from each other, especially the timing of the start of the increase of the highest output voltage VH and the lowest output voltage VL are different from each other.

[0081] For example, such as Figure 7 As shown, the time when the minimum output voltage VL starts to increase can be earlier than the time when the maximum output voltage VH starts to increase.

[0082] Please refer to it again. Figure 6 This is a circuit layout diagram of the power management system according to an embodiment of the present invention.

[0083] like Figure 6 As shown, the power converters PT1 to PTn of the power management system in this embodiment of the invention may each include discharge circuits H1 to Hn.

[0084] The configuration of power converters PT2 to PTn in the power management system is the same as or similar to that of power converter PT1. The following description focuses only on power converter PT1, and the same or similar content will not be repeated in this article.

[0085] In the power converter PT1, a discharge circuit H1 can be connected to the node between the second terminal of inductor L1 and the first terminal of capacitor C1. The discharge circuit H1 can be configured to adjust the discharge rate of the output voltage Vout1 (of the node between the second terminal of inductor L1 and the first terminal of capacitor C1).

[0086] For example, such as Figure 6As shown, the discharge circuit H1 may include multiple resistors R11 to R1n and a switching component SW1, but the invention is not limited thereto. The multiple resistors R11 to R1n may have the same or different resistance values. The multiple resistors R11 to R1n may be connected in parallel (in practice, they may be connected in series). The first terminal of each resistor R11 to R1n may be connected to the node between the second terminal of inductor L1 and the first terminal of capacitor C1. The second terminal of each resistor R11 to R1n may be grounded.

[0087] The control terminal of the switching component SW1 can be connected to the main control circuit 30. The first terminal of the switching component SW1 can be connected to the second terminals of each resistor R11 to R1n. The second terminal of the switching component SW1 can be grounded. When the main control circuit 30 determines that it is necessary to adjust the output voltage Vout1 (discharge rate) of the node between the second terminal of inductor L1 and the first terminal of capacitor C1, the main control circuit 30 can control the opening and closing of the switching component SW1.

[0088] It should be understood that the number of resistors included in the discharge circuit H1 can be adjusted according to actual needs. In practice, the discharge circuit H1 may contain only one resistor. The switching component SW1 may be omitted depending on actual needs.

[0089] Alternatively, in practice, the discharge circuit H1 may include multiple switching components. The first terminals of the multiple switching components may be connected to the first terminals of multiple resistors R11 to R1n respectively. The second terminal of each switching component is grounded. The control terminals of the multiple switching components are connected to the main control circuit 30. The main control circuit 30 may selectively control the multiple switching components to turn on according to the desired discharge rate of the output voltage Vout1 of the node between the second terminal of inductor L1 and the first terminal of capacitor C1, so as to selectively ground the node between the second terminal of inductor L1 and the first terminal of capacitor C1 through any one or more of resistors R11 to R1n.

[0090] In addition, the main control circuit 30 can determine the opening and closing time of the lower bridge switch LG1 based on the desired discharge rate of the output voltage Vout1 at the node between the second terminal of inductor L1 and the first terminal of capacitor C1, and control the opening and closing of the lower bridge switch LG1 accordingly. For example, when the main control circuit 30 determines that it is necessary to speed up the discharge rate of the output voltage Vout1 at the node between the second terminal of inductor L1 and the first terminal of capacitor C1, the main control circuit 30 can keep the lower bridge switch LG1 open for a period of time.

[0091] In summary, this invention provides a power management system and method that can control multiple power converters to increase or decrease their output voltage at different times. Specifically, it allows the highest and lowest output voltages of the power conversion circuit to decrease to zero within different time intervals. This prevents excessive voltage differences between the multiple output voltages supplied by the power conversion circuit within the same time interval, thereby preventing damage to circuit components (e.g., system chips) receiving the multiple output voltages supplied by the power converters due to excessive voltage differences.

[0092] The above-disclosed content is only a preferred embodiment of the present invention and is not intended to limit the claims of the present invention. Therefore, all equivalent technical changes made based on the description and drawings of the present invention are included in the claims of the present invention.

Claims

1. A power management system, characterized in that, The power management system includes: A power conversion circuit includes multiple power converters, each configured to supply multiple output voltages. The power converter supplying the lowest output voltage among the multiple power converters is defined as a first power converter, and the power converter supplying the highest output voltage among the multiple power converters is defined as a second power converter. as well as An undervoltage lockout circuit is configured to output a first undervoltage lockout signal to a second power converter when it determines that the shared voltage has dropped below a first lockout voltage. The second power converter then rapidly reduces the supplied output voltage to zero based on the first undervoltage lockout signal. After the output voltage of the second power converter drops to zero, the undervoltage lockout circuit outputs a second undervoltage lockout signal to the first power converter, and the first power converter gradually reduces the supplied output voltage to zero according to the second undervoltage lockout signal.

2. The power management system according to claim 1, characterized in that, After the second power converter rapidly reduces the supplied output voltage to zero, the undervoltage lockout circuit determines whether the shared voltage has dropped below the second lockout voltage, which is less than the first lockout voltage. Until the shared voltage drops below the second lockout voltage, the undervoltage lockout circuit outputs the second undervoltage lockout signal to the first power converter to control the first power converter to gradually reduce the supplied output voltage to zero.

3. The power management system according to claim 1, characterized in that, The power management system further includes a main control circuit connected to the power conversion circuit and the undervoltage lockout circuit. The main control circuit is configured to control the second power converter based on a first undervoltage lockout signal received from the undervoltage lockout circuit, and to control the first power converter based on the second undervoltage lockout signal.

4. The power management system according to claim 3, characterized in that, The power management system further includes a timing circuit connected to the main control circuit. The main control circuit controls the timing circuit to start timing after the output voltage of the second power converter begins to decrease. When the timing circuit reaches a default time, the timing circuit outputs a timing signal to the main control circuit. The main control circuit controls the first power converter to gradually reduce the supplied output voltage to zero based on the timing signal.

5. The power management system according to claim 3, characterized in that, When the shared voltage drops below the first locking voltage, the undervoltage lockout circuit outputs a voltage reduction indication signal to the main control circuit. The main control circuit then controls the power converter that supplies the highest output voltage among the plurality of power converters to reduce its output voltage according to a reference voltage indicated by the voltage reduction indication signal.

6. The power management system according to claim 3, characterized in that, The power management system further includes a differential voltage detection circuit connected to the main control circuit and the power conversion circuit. The differential voltage detection circuit is configured to calculate the difference between the highest and lowest output voltages among a plurality of output voltages. Specifically, when the differential pressure detection circuit determines that the difference between the highest and lowest output voltages among the multiple output voltages is greater than a preset differential pressure, the differential pressure detection circuit outputs a differential pressure detection signal to the main control circuit. The main control circuit controls the operation of multiple power converters based on the differential pressure detection signal, such that the time point at which the highest output voltage begins to gradually rise is different from the time point at which the lowest output voltage begins to gradually rise, or the time point at which the highest output voltage begins to gradually fall is different from the time point at which the lowest output voltage begins to gradually fall.

7. The power management system according to claim 6, characterized in that, The differential pressure detection circuit includes a multiplexer, an error amplifier, and a comparator. The input terminal of the multiplexer is connected to the power conversion circuit, the output terminal of the multiplexer is connected to the first and second input terminals of the error amplifier, the first input terminal of the comparator is connected to the output terminal of the error amplifier, the second input terminal of the comparator is coupled to the preset differential pressure, and the output terminal of the comparator is connected to the input terminal of the main control circuit. The multiplexer selects the highest and lowest output voltages from the plurality of output voltages and transmits them to the first and second input terminals of the error amplifier, respectively. The error amplifier amplifies the difference between the highest and lowest output voltages to output an error amplification signal to the first input terminal of the comparator. The comparator compares the voltage of the error amplification signal with the preset voltage difference to output the voltage difference detection signal to the main control circuit.

8. The power management system according to claim 3, characterized in that, Each of the power converters includes an upper bridge switch, a lower bridge switch, and a drive circuit. The first terminal of the upper bridge switch is coupled to an input voltage. The second terminal of the upper bridge switch is connected to the first terminal of the lower bridge switch. The second terminal of the lower bridge switch is grounded. The node between the upper bridge switch and the lower bridge switch is connected to the first terminal of an inductor. The second terminal of the inductor is connected to the first terminal of a capacitor. The second terminal of the capacitor is grounded. The drive circuit is connected to the control terminal of the upper bridge switch and the control terminal of the lower bridge switch. The main control circuit is connected to the drive circuit.

9. The power management system according to claim 8, characterized in that, Each of the power converters further includes an operational amplifier, the first input of which is connected to and receives analog signals from a digital-to-analog converter, and the second input of which is connected to a node between the second end of the inductor and the first end of the capacitor.

10. The power management system according to claim 9, characterized in that, Each of the power converters further includes a voltage divider circuit, the input of which is connected to the node between the second end of the inductor and the first end of the capacitor, the output of which is connected to the input of the multiplexer, and the second input of the operational amplifier is connected to the node between the second end of the inductor and the first end of the capacitor through the voltage divider circuit.

11. The power management system according to claim 8, characterized in that, Each of the power converters further includes a discharge circuit connected to a node between a second terminal of the inductor and a first terminal of the capacitor, the discharge circuit being configured to adjust the voltage at the node between the second terminal of the inductor and the first terminal of the capacitor.

12. The power management system according to claim 11, characterized in that, The discharge circuit includes multiple resistors connected in parallel. The first end of each resistor is connected to the node between the second end of the inductor and the first end of the capacitor, and the second end of each resistor is grounded.

13. The power management system according to claim 12, characterized in that, The discharge circuit of each of the power converters further includes a switching component, the control terminal of which is connected to the main control circuit, the first terminal of which is connected to the second terminal of each of the resistors, and the second terminal of which is grounded.

14. The power management system according to claim 8, characterized in that, When the shared voltage drops below the first locking voltage, the drive circuit in the second power converter turns on the lower bridge switch to accelerate the reduction of the output voltage of the second power converter to zero.

15. A power management method, characterized in that, The power management method includes the following steps: Multiple power converters are configured to supply multiple output voltages respectively. The power converter that supplies the lowest output voltage among the multiple power converters is defined as the first power converter, and the power converter that supplies the highest output voltage among the multiple power converters is defined as the second power converter. Configure an undervoltage lockout circuit to detect a shared voltage used by the power management system; Using the undervoltage lockout circuit, it is determined whether the shared voltage has dropped below the first lockout voltage. If not, the shared voltage is continuously monitored. If so, the first undervoltage lockout signal is output to the second power converter. Using the second power converter, the output voltage supplied by the second power converter is rapidly reduced to zero based on the first undervoltage lockout signal; Using the undervoltage lockout circuit, after the output voltage of the second power converter drops to zero, a second undervoltage lockout signal is output to the first power converter. as well as Using the first power converter, the output voltage supplied by the first power converter is gradually reduced to zero based on the second undervoltage lockout signal.

16. The power management method according to claim 15, characterized in that, The power management method further includes the following steps: After the second power converter rapidly reduces the supplied output voltage to zero, it is determined whether the shared voltage has decreased to less than the second locking voltage. If not, the shared voltage is continuously monitored, and the process returns to the previous step. If yes, the next step is executed. as well as The output voltage supplied by the first power converter is gradually reduced to zero.

17. The power management method according to claim 15, characterized in that, The power management method further includes the following steps: Timing begins after the second power converter rapidly reduces the supplied output voltage to zero; and Determine whether the timing has reached the preset time. If not, return to the previous step and continue timing. If yes, control the first power converter to gradually reduce the supplied output voltage to zero.

18. The power management method according to claim 15, characterized in that, The power management method further includes the following steps: Determine whether the shared voltage has decreased to less than the first locking voltage. If not, continue to detect the shared voltage and return to the previous step. If yes, proceed to the next step. as well as The power converter that supplies the highest output voltage among the plurality of power converters is controlled to reduce the output voltage based on a reference voltage.

19. The power management method according to claim 15, characterized in that, The power management method further includes the following steps: Select the highest and lowest output voltage from the plurality of output voltages of the plurality of power converters; Calculate the difference between the highest output voltage and the lowest output voltage; Determine whether the difference between the output voltage and the lowest output voltage is greater than a preset voltage difference. If not, return to the previous step; if yes, proceed to the next step. as well as The operation of multiple power converters is controlled such that the time at which the highest output voltage begins to gradually rise is different from the time at which the lowest output voltage begins to gradually rise.

20. The power management method according to claim 15, characterized in that, The power management method further includes the following steps: Select the highest and lowest output voltage from the plurality of output voltages of the plurality of power converters; Calculate the difference between the highest output voltage and the lowest output voltage; Determine whether the difference between the output voltage and the minimum output voltage is greater than a preset voltage difference. If not, return to the previous step; if yes, proceed to the next step. as well as The operation of multiple power converters is controlled such that the time at which the highest output voltage begins to gradually decrease is different from the time at which the lowest output voltage begins to gradually decrease.

Images