buffer

Abstract

The application relates to a buffer. The buffer comprises a buffer circuit, a voltage compensation circuit and a switch circuit, the buffer circuit comprises a multi-stage MOS tube group, the buffer circuit and the voltage compensation circuit are connected with the switch circuit respectively, and the switch circuit and the buffer circuit are further connected with a power supply; the switch circuit is used for conducting a passage between the power supply and the voltage compensation circuit to charge the voltage compensation circuit in a charging stage; and the switch circuit is used for conducting a passage between the buffer circuit and the voltage compensation circuit to enable the power supply and the voltage compensation circuit to provide voltage for the multi-stage MOS tube group in a discharging stage. The buffer can reduce the nonlinearity of an output signal of the buffer.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a buffer. Background Technology

[0002] With the development of integrated circuit technology, high-speed, high-precision analog-to-digital converters (ADCs) are becoming increasingly widely used. In an ADC, a buffer is placed between the input signal and the sampling circuit. Changes in the frequency or amplitude of the input signal in an ADC can cause high nonlinearity in the buffer's output signal, and may even lead to output signal distortion.

[0003] In related technologies, a MOSFET is set in the buffer. In order to improve the linearity of the output signal of the buffer, a multi-stage MOSFET group can be added to the input buffer to change the correlation between the drain-source voltage of the source follower transistor and the input signal, thereby improving the linearity of the output signal of the buffer.

[0004] However, the above method still suffers from the problem of high nonlinearity in the output signal of the buffer. Summary of the Invention

[0005] Therefore, it is necessary to provide a buffer that can reduce the nonlinearity of the buffer's output signal to address the aforementioned technical problems.

[0006] In a first aspect, this application provides a buffer, which includes a buffer circuit, a voltage compensation circuit and a switching circuit. The buffer circuit includes a multi-stage MOSFET group. The buffer circuit and the voltage compensation circuit are respectively connected to the switching circuit. The switching circuit and the buffer circuit are also connected to a power supply.

[0007] The switching circuit is used to connect the power supply and the voltage compensation circuit during the charging phase, so as to charge the voltage compensation circuit; during the discharging phase, it connects the buffer circuit and the voltage compensation circuit, so that the power supply and the voltage compensation circuit can provide voltage to the multi-stage MOSFET group.

[0008] In one embodiment, the switching circuit includes a first switching circuit and a second switching circuit. The first switching circuit is connected to the power supply and the voltage compensation circuit, respectively, and the second switching circuit is connected to the buffer circuit and the voltage compensation circuit, respectively.

[0009] During the charging phase, the first switching circuit is turned on and the second switching circuit is turned off.

[0010] During the discharge phase, the first switching circuit is disconnected, and the second switching circuit is turned on.

[0011] In one embodiment, the first switching circuit includes a first switch and a second switch. The first terminal of the first switch is connected to a power supply, the second terminal of the first switch is connected to the first terminal of a voltage compensation circuit, the first terminal of the second switch is connected to the second terminal of the voltage compensation circuit, and the second terminal of the second switch is grounded.

[0012] In one embodiment, the second switching circuit includes a third switch and a fourth switch. The first terminal of the third switch is connected to a buffer circuit, the second terminal of the third switch is connected to the second terminal of a voltage compensation circuit, the first terminal of the fourth switch is connected to the first terminal of the voltage compensation circuit, and the second terminal of the fourth switch is grounded.

[0013] In one embodiment, the voltage compensation circuit includes a negative power supply circuit, the first terminal of which is connected to the second terminal of the first switch and the first terminal of the fourth switch, and the second terminal of which is connected to the second terminal of the third switch and the first terminal of the second switch.

[0014] In one embodiment, the negative power supply circuit includes a capacitor, the first end of which is connected to the second end of the first switch and the first end of the fourth switch, respectively, and the second end of which is connected to the second end of the third switch and the first end of the second switch, respectively.

[0015] In one embodiment, each stage of the multi-stage MOS transistor group includes an NMOS transistor and a PMOS transistor.

[0016] In one embodiment, the buffer circuit further includes a level conversion circuit, which is connected to the signal input terminal and the multi-stage MOS transistor group respectively.

[0017] A level conversion circuit is used to convert the level of the input signal at the signal input terminal.

[0018] In one embodiment, the level conversion circuit includes a first level converter and a second level converter. The multi-stage MOSFET group includes an initial MOSFET group, a first MOSFET group, and a second MOSFET group. The first terminal of the first level converter is connected to the signal input terminal, and the second terminal of the first level converter is connected to the gate of the initial MOSFET group and the gate of the first MOSFET group. The first terminal of the second level converter is connected to the gate of the second MOSFET group, and the second terminal of the second level converter is connected to the drain of the initial MOSFET group.

[0019] In one embodiment, the drain of the second MOS transistor group is connected to the power supply and the switching circuit, the source of the second MOS transistor group is connected to the drain of the first MOS transistor group, the source of the first MOS transistor group is connected to the drain of the initial MOS transistor group, and the source of the initial MOS transistor group is connected to the signal output terminal.

[0020] The aforementioned buffer includes a buffer circuit, a voltage compensation circuit, and a switching circuit. The buffer circuit comprises a multi-stage MOSFET group. The buffer circuit and the voltage compensation circuit are respectively connected to the switching circuit, which is also connected to a power supply. The switching circuit is used to open the path between the power supply and the voltage compensation circuit during the charging phase, charging the voltage compensation circuit; and during the discharging phase, it opens the path between the buffer circuit and the voltage compensation circuit, allowing the power supply and the voltage compensation circuit to provide voltage to the multi-stage MOSFET group. By incorporating the voltage compensation circuit, during the charging phase, the power supply charges the voltage compensation circuit; and during the discharging phase, the voltage compensation circuit and the power supply can simultaneously provide voltage to the multi-stage MOSFET group. A larger voltage, corresponding to a higher number of MOSFETs, can further reduce the nonlinearity of the buffer's output signal and prevent signal distortion. Attached Figure Description

[0021] Figure 1 This is a circuit diagram of a buffer in a conventional technique in one embodiment;

[0022] Figure 2 This is a circuit diagram of a buffer in a related art in one embodiment;

[0023] Figure 3 This is a circuit diagram of a buffer in one embodiment;

[0024] Figure 4 This is a circuit diagram of a buffer in one embodiment;

[0025] Figure 5 This is a circuit diagram of a buffer in one embodiment;

[0026] Figure 6 This is a circuit diagram of a buffer in one embodiment;

[0027] Figure 7 This is a circuit diagram of a buffer in one embodiment;

[0028] Figure 8 This is a circuit diagram of a buffer in one embodiment;

[0029] Figure 9 This is a circuit diagram of a buffer in one embodiment;

[0030] Figure 10 This is a circuit diagram of a buffer in one embodiment.

[0031] Explanation of reference numerals in the attached figures:

[0032] 10: Buffer; 11: Buffer circuit;

[0033] 111: Multi-stage MOSFET group; 1111: Initial MOSFET group;

[0034] 1112: First MOSFET group; 1113: Second MOSFET group;

[0035] 112: Level conversion circuit; LS1: First level converter;

[0036] LS2: Second level converter; 12: Voltage compensation circuit;

[0037] 121: Negative power supply circuit; C1: Capacitor;

[0038] 13: Switching circuit; 131: First switching circuit;

[0039] S1: First switch; S2: Second switch;

[0040] 132: Second switching circuit; S3: Third switch;

[0041] S4: Fourth switch; V in Signal input terminal;

[0042] VDD: Power supply; V out Signal output terminal. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0044] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0045] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0046] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0047] Before describing the embodiments of this application, the technical background of this application will be introduced first.

[0048] With the continuous development of integrated circuits, the accuracy requirements for analog-to-digital converters (ADCs) are becoming increasingly stringent. In high-speed, high-precision ADCs, buffers are placed between the signal input terminal and the sampling circuit. These buffers separate the input signal from the sampling circuit. Changes in the frequency or amplitude of the input signal can cause high nonlinearity in the buffer's output signal, and may even lead to output signal distortion.

[0049] Figure 1 A circuit diagram illustrating a buffer in conventional technology. Figure 1 In this buffer, only a single-stage MOSFET group and a level shifter (LS) are included. The MOSFET group consists of one NMOS transistor and one PMOS transistor. The sources of both the NMOS and PMOS transistors are connected to the signal output terminal, the drain of the NMOS transistor is connected to the power supply, and the drain of the PMOS transistor is grounded. The gates of both the NMOS and PMOS transistors are connected to the level shifter. The input signal enters the buffer from the signal input terminal. After passing through the level shifter, the bias voltage of the NMOS transistor is V1, and the bias voltage of the PMOS transistor is V2. When the signal input terminal changes, the bias voltages V1 and V2 of the NMOS transistor and PMOS transistor will change, causing the drain-source voltages of the NMOS and PMOS transistors to change as well. This change can lead to higher non-linearity of the output signal and may also cause distortion of the output signal.

[0050] To reduce the nonlinearity of the output signal and avoid distortion, related technologies can increase the number of MOSFET stages in the buffer. Figure 2 This is a circuit diagram illustrating a buffer with a multi-stage MOS transistor group in related technologies. Figure 2It includes a 3-stage MOS transistor group. Based on the original NMOS and PMOS transistors, two more NMOS and PMOS transistors are added. The second-stage NMOS transistor is connected to the signal input terminal through LS. The source of the second-stage NMOS transistor provides sufficient drain-source voltage to the first-stage NMOS transistor, so that the drain-source voltage of the first-stage NMOS transistor does not change with the input signal. This allows the drain voltage of the NMOS and PMOS transistors to not be fixed at a certain power supply voltage, reducing the nonlinearity of the output signal.

[0051] However, the circuits of related technologies are limited by the limited voltage provided by VDD, which restricts the number of NMOS and PMOS transistors that can be added. As a result, the buffer still has the problem of high nonlinearity of the output signal.

[0052] To further reduce the nonlinearity of the output signal and avoid distortion of the output signal, this application proposes a buffer, the details of which will be described below.

[0053] In one embodiment, Figure 3 A circuit diagram of a buffer is provided. The buffer 10 includes a buffer circuit 11, a voltage compensation circuit 12, and a switching circuit 13. The buffer circuit 11 includes a multi-stage MOSFET group 111. The buffer circuit 11 and the voltage compensation circuit 12 are respectively connected to the switching circuit 13. The switching circuit 13 and the buffer circuit 11 are also connected to the power supply VDD. The switching circuit 13 is used to open the path between the power supply VDD and the voltage compensation circuit 12 during the charging phase to charge the voltage compensation circuit 12. During the discharging phase, it opens the path between the buffer circuit 11 and the voltage compensation circuit 12 so that the power supply VDD and the voltage compensation circuit 12 provide voltage to the multi-stage MOSFET group 111.

[0054] In this embodiment, the number of MOSFET stages in the buffer circuit 11 is determined by the voltage provided by the power supply VDD and the voltage compensation circuit 12. The number of MOSFET stages is greater than the number of stages corresponding to a voltage provided solely by the power supply VDD. A higher number of MOSFET stages reduces the degree to which the drain-source voltage of a single-stage NMOS transistor changes with the input signal, further preventing the drain voltages of the NMOS and PMOS transistors from being fixed at a specific power supply voltage, thereby further reducing the nonlinearity of the output signal. The buffer circuit 11 may include a multi-stage MOSFET group, a level shifting circuit, and other electronic components.

[0055] Furthermore, during the charging phase, the voltage compensation circuit 12 is connected to the power supply VDD and charged via VDD; during the discharging phase, both the voltage compensation circuit 12 and the power supply VDD provide voltage to the multi-stage MOSFET group. The voltage compensation circuit 12 includes chargeable and dischargeable electronic components; for example, the voltage compensation circuit 12 can be a circuit composed of capacitors and other electronic components.

[0056] It is understood that the switching circuit 13 can be implemented using a switching transistor, such as a bipolar transistor or a MOSFET, which turns on the switching transistor by providing a turn-on voltage. Alternatively, the switching circuit 13 can also be implemented using a single-pole single-throw switch, a single-pole double-throw switch, or a single-pole multi-throw switch. By controlling the closing of the switch, during the charging phase of the buffer, the path between the power supply VDD and the voltage compensation circuit 12 is opened; during the discharging phase of the buffer, the path between the buffer circuit 11 and the voltage compensation circuit 12 is opened. Alternatively, the switching circuit 13 can also be implemented using a switching chip. By sending a control signal to the switching chip, during the charging phase of the buffer, the switching chip controls the path between the power supply VDD and the voltage compensation circuit 12 to be opened according to the control signal; during the discharging phase of the buffer, the switching chip controls the path between the buffer circuit 11 and the voltage compensation circuit 12 to be opened according to the control signal. The type of switching circuit 13 is not limited in the embodiments of this application.

[0057] The aforementioned buffer includes a buffer circuit, a voltage compensation circuit, and a switching circuit. The buffer circuit comprises a multi-stage MOSFET group. The buffer circuit and the voltage compensation circuit are respectively connected to the switching circuit, which is also connected to a power supply. During the charging phase, the switching circuit opens the path between the power supply and the voltage compensation circuit, charging the voltage compensation circuit. During the discharging phase, it opens the path between the buffer circuit and the voltage compensation circuit, allowing the power supply and the voltage compensation circuit to provide voltage to the multi-stage MOSFET group. By incorporating the voltage compensation circuit, during the charging phase, the power supply charges the voltage compensation circuit; during the discharging phase, the voltage compensation circuit and the power supply can simultaneously provide voltage to the multi-stage MOSFET group. Because the provided voltage is larger, the corresponding number of MOSFET stages is higher, which further reduces the nonlinearity of the buffer's output signal and avoids signal distortion.

[0058] In one embodiment, Figure 4A circuit diagram of a buffer is provided. The switching circuit 13 in the buffer 10 includes a first switching circuit 131 and a second switching circuit 132. The first switching circuit 131 is connected to the power supply VDD and the voltage compensation circuit 12, respectively. The second switching circuit 132 is connected to the buffer circuit 11 and the voltage compensation circuit 12, respectively. During the charging stage, the first switching circuit 131 is turned on and the second switching circuit 132 is turned off. During the discharging stage, the first switching circuit 131 is turned off and the second switching circuit 132 is turned on.

[0059] In this embodiment, the conduction states of the first switching circuit 131 and the second switching circuit 132 are opposite: when the first switching circuit 131 is on, the second switching circuit 132 is not on; when the first switching circuit 131 is not on, the second switching circuit 132 is on. During the charging phase, the first switching circuit 131 connects the power supply VDD to the voltage compensation circuit 12, while the second switching circuit 132 disconnects the connection between the buffer circuit 11 and the voltage compensation circuit 12, allowing the power supply VDD to charge the voltage compensation circuit 12. During the discharging phase, the second switching circuit connects the buffer circuit 11 to the voltage compensation circuit 12, while the first switching circuit 131 disconnects the connection between the power supply VDD and the voltage compensation circuit 12, allowing both the voltage compensation circuit 12 and the power supply VDD to simultaneously provide voltage to the buffer circuit 11.

[0060] For example, the first switching circuit 131 and the second switching circuit 132 can be switching transistor circuits, such as transistors, MOSFETs, etc. Alternatively, the first switching circuit 131 and the second switching circuit 132 can also be single-pole single-throw switches, single-pole double-throw switches, single-pole multi-throw switches, etc. Alternatively, the first switching circuit 131 and the second switching circuit 132 can be switching chips.

[0061] The aforementioned switching circuit includes a first switching circuit and a second switching circuit. The first switching circuit is connected to both the power supply and the voltage compensation circuit, while the second switching circuit is connected to both the buffer circuit and the voltage compensation circuit. During the charging phase, the first switching circuit is on, and the second switching circuit is off. During the discharging phase, the first switching circuit is off, and the second switching circuit is on. This circuit uses two switching circuits to control the opening and closing of the switch during charging and discharging. The use of two switching circuits allows for more accurate control of the current flow, improving the accuracy of the charging and discharging process.

[0062] In one embodiment, Figure 5A circuit diagram of a buffer is provided. The first switch circuit 131 includes a first switch S1 and a second switch S2. The first end of the first switch S1 is connected to the power supply VDD, the second end of the first switch S1 is connected to the first end of the voltage compensation circuit 12, the first end of the second switch S2 is connected to the second end of the voltage compensation circuit 12, and the second end of the second switch S2 is grounded.

[0063] In this embodiment, the first switch S1 is set between the power supply VDD and the voltage compensation circuit 12, and the second switch S2 is set between the second terminal of the voltage compensation circuit 12 and ground. The first switch S1 and the second switch S2 are in the same conduction state, that is, when the first switch S1 is on, the second switch S2 is on; when the first switch S1 is not on, the second switch S2 is not on.

[0064] Understandably, during charging, both the first switch S1 and the second switch S2 are on, forming a circuit with the power supply VDD, the first switch S1, the voltage compensation circuit 12, and the second switch S2. The power supply VDD can then charge the voltage compensation circuit 12 normally. When not charging, neither the first switch S1 nor the second switch S2 is on.

[0065] The aforementioned first switching circuit includes a first switch and a second switch. The first terminal of the first switch is connected to the power supply, the second terminal of the first switch is connected to the first terminal of the voltage compensation circuit, the first terminal of the second switch is connected to the second terminal of the voltage compensation circuit, and the second terminal of the second switch is grounded. The first switching circuit in this system, composed of the first and second switches, allows the power supply to provide voltage to the voltage compensation circuit. The two switches further ensure the safety of the voltage compensation circuit during charging.

[0066] In one embodiment, Figure 6 A circuit diagram of a buffer is provided. The second switch circuit 132 includes a third switch S3 and a fourth switch S4. The first end of the third switch S3 is connected to the buffer circuit 11, the second end of the third switch S3 is connected to the second end of the voltage compensation circuit 12, the first end of the fourth switch S4 is connected to the first end of the voltage compensation circuit 12, and the second end of the fourth switch S4 is grounded.

[0067] In this embodiment, the third switch S3 is disposed between the buffer circuit 11 and the voltage compensation circuit 12, and the fourth switch S4 is disposed between the first terminal of the voltage compensation circuit 12 and ground. The conduction states of the third switch S3 and the fourth switch S4 are the same, that is, the third switch S3 is on and the fourth switch S4 is on; the third switch S3 is not on and the fourth switch S4 is not on.

[0068] In the discharge state, both the third switch S3 and the fourth switch S4 are turned on, while both the first switch S1 and the second switch S2 are turned off. The third switch S3 connects the buffer circuit 11 and the voltage compensation circuit 12, and the fourth switch S4 connects the voltage compensation circuit 12 and the ground. The power supply VDD, the buffer circuit 11, the third switch S3, the voltage compensation circuit 12 and the fourth switch S4 form a loop.

[0069] The aforementioned second switching circuit includes a third switch and a fourth switch. The first terminal of the third switch is connected to the buffer circuit, the second terminal of the third switch is connected to the second terminal of the voltage compensation circuit, and the first terminal of the fourth switch is connected to the first terminal of the voltage compensation circuit. The second terminal of the fourth switch is grounded. The second switching circuit in this system, composed of the third and fourth switches, allows the voltage compensation circuit to provide voltage to the buffer circuit. These two switches further ensure the safety of the voltage compensation circuit during discharge.

[0070] In one embodiment, Figure 7 A circuit diagram of a buffer is provided. The voltage compensation circuit 12 includes a negative power supply circuit 121. The first end of the negative power supply circuit 121 is connected to the first switch S1 and the fourth switch S4, respectively. The second end of the negative power supply circuit 121 is connected to the third switch S3 and the second switch S2, respectively.

[0071] In this embodiment, since the first terminal of the buffer circuit 11 is connected to the power supply VDD, and the second terminal of the buffer circuit 11 is connected to the third switch S3 and the voltage compensation circuit 121, when the third switch S3 is not turned on, the voltage across the third switch S3 is negative; when the third switch S3 is turned on, the negative power supply circuit 121 provides a negative voltage to the buffer circuit 121. During the charging phase, the first switch S1 and the second switch S2 are turned on, while the third switch S3 and the fourth switch S4 are not turned on. The power supply VDD, the first switch S1, the negative power supply circuit 121, and the second switch S2 form a closed loop, and the power supply VDD provides voltage to the voltage compensation circuit 121. During the discharging phase, the first switch S1 and the second switch S2 are not turned on, while the third switch S3 and the fourth switch S4 are turned on. The power supply VDD, the buffer circuit 11, the third switch S3, the negative power supply circuit 121, and the fourth switch S4 form a closed loop, and the power supply VDD and the voltage compensation circuit 12 provide voltage to the buffer circuit 11.

[0072] The voltage compensation circuit mentioned above includes a negative power supply circuit. The first end of the negative power supply circuit is connected to the first switch and the fourth switch, respectively. The second end of the negative power supply circuit is connected to the third switch and the second switch, respectively. This circuit connects four switches to the two ends of the negative power supply circuit. By controlling the conduction and disconnection of the four switches, it is possible to more accurately determine whether the negative power supply circuit is in the charging or discharging stage, so as to charge the buffer more accurately.

[0073] In one embodiment, Figure 8 A circuit diagram of a buffer is provided. The negative power supply circuit 121 includes a capacitor C1. The first end of the capacitor C1 is connected to the second end of the first switch S1 and the first end of the fourth switch S4, respectively. The second end of the capacitor C1 is connected to the second end of the third switch S3 and the first end of the second switch S2, respectively.

[0074] In this embodiment, the negative power supply circuit 121 includes only capacitor C1. Capacitor C1 can be a single capacitor or a group of multiple capacitors. The material of capacitor C1 can be polyester, polystyrene, polypropylene, etc.

[0075] Taking the negative power supply circuit 121, which includes only one capacitor C1, as an example, during the charging phase, the first switch S1 and the second switch S2 are turned on, while the third switch S3 and the fourth switch S4 are turned off. The power supply VDD, the first switch S1, the capacitor C1, and the second switch S2 form a closed loop, and the power supply VDD provides voltage to the capacitor C1. During the discharging phase, the first switch S1 and the second switch S2 are turned off, while the third switch S3 and the fourth switch S4 are turned on. The power supply VDD, the buffer circuit 11, the third switch S3, the capacitor C1, and the fourth switch S4 form a closed loop, and the power supply VDD and the capacitor C1 provide voltage to the buffer circuit 11.

[0076] The aforementioned negative power supply circuit includes a capacitor. The first terminal of the capacitor is connected to the second terminal of the first switch and the first terminal of the fourth switch, respectively. The second terminal of the capacitor is connected to the second terminal of the third switch and the first terminal of the second switch, respectively. This circuit connects four switches to the two ends of the capacitor. By controlling the on and off states of the four switches, the charging or discharging phase of the capacitor can be determined more accurately, thus enabling more precise charging of the buffer.

[0077] In one embodiment, Figure 9 A circuit diagram of a buffer is provided. The buffer circuit 11 further includes a level conversion circuit 112, which is connected to the signal input terminal V. in A multi-stage MOSFET group 111 is connected; a level conversion circuit 112 is used to convert the signal input terminal V. in The input signal undergoes level conversion.

[0078] In this embodiment, the signal input terminal V in The input voltage signal is different from the voltage signal provided by the voltage source VDD. In order to adjust the signal input terminal V... in The input voltage is converted, and the level conversion circuit 112 is set at the signal input terminal V. inBetween the multi-stage MOSFET group 111 and the level conversion circuit 112. The level conversion circuit 112 can be a conversion circuit composed of diodes, a conversion circuit composed of transistors, or a bidirectional conversion circuit composed of bidirectional MOSFETs. This embodiment does not limit the type of level conversion circuit 12.

[0079] The aforementioned buffer circuit also includes a level conversion circuit, which is connected to the signal input terminal and the multi-stage MOS transistor group. The level conversion circuit can convert the level of the input signal at the signal input terminal, which can, to a certain extent, avoid the influence of input signal fluctuations on the buffer and ensure the normal operation of the buffer.

[0080] In one embodiment, Figure 10 A circuit diagram of a buffer is provided. The level conversion circuit 112 includes a first level converter LS1 and a second level converter LS2. The multi-stage MOSFET group 111 includes an initial MOSFET group 1111, a first MOSFET group 1112, and a second MOSFET group 1113. The first terminal of the first level converter LS1 is connected to the signal input terminal V. in The second terminal of the first level converter LS1 is connected to the gate of the initial MOS transistor group 1111 and the gate of the first MOS transistor group 1112. The first terminal of the second level converter LS2 is connected to the gate of the second MOS transistor group 1113, and the second terminal of the second level converter LS2 is connected to the drain of the initial MOS transistor group 1111.

[0081] In this embodiment, with Figure 10 For example, Figure 10 In this configuration, each stage of the multi-stage MOSFET group 111 includes one NMOS transistor and one PMOS transistor. The initial MOSFET group 1111 includes an NMOS transistor and a PMOS transistor, the first MOSFET group 1112 includes an NMOS transistor and a PMOS transistor, and the second MOSFET group 1113 includes an NMOS transistor and a PMOS transistor. There are four first level converters LS1 and two second level converters LS2. The first terminals of the four first level converters LS1 are connected to the signal input terminal V. in The four first-level converters LS1 are connected, with their second terminals connected to the gates of the NMOS transistor, PMOS transistor, NMOS transistor 1, and PMOS transistor 2, respectively. The first terminals of the two second-level converters LS2 are connected to the gates of the NMOS transistor 2 and PMOS transistor 3, respectively, and their second terminals are connected to the drains of the NMOS transistor and PMOS transistor 4, respectively. Figure 10 The example uses a 3-stage MOSFET. The number of stages of a MOSFET with a negative power supply voltage is greater than the number of stages of a MOSFET that is supplied with voltage only through the power supply VDD.

[0082] The aforementioned level conversion circuit includes a first level converter and a second level converter. The multi-stage MOSFET group includes an initial MOSFET group, a first MOSFET group, and a second MOSFET group. The first terminal of the first level converter is connected to the signal input terminal, and the second terminal of the first level converter is connected to the gates of both the initial and first MOSFET groups. The first terminal of the second level converter is connected to the gate of the second MOSFET group, and the second terminal of the second level converter is connected to the drain of the initial MOSFET group. This method, through the connection relationship between the level converter and different MOSFETs, can better avoid the impact of input voltage fluctuations on the buffer, ensuring the normal operation of the buffer.

[0083] In one embodiment, please see [link to previous article]. Figure 10 , Figure 10 The drain of the second MOSFET group 1113 is connected to the power supply VDD and the switching circuit 13, respectively. The source of the second MOSFET group 1113 is connected to the drain of the first MOSFET group 1112. The source of the first MOSFET group 1112 is connected to the drain of the initial MOSFET group 1111. The source of the initial MOSFET group 1111 is connected to the signal output terminal VDD. out connect.

[0084] In this embodiment, the drain of NMOS2 in the second MOS transistor group 1113 is connected to the power supply VDD, the source of NMOS2 is connected to the drain of NMOS1, the source of NMOS1 is connected to the drain of the NMOS transistor, and the source of the NMOS transistor is connected to the drain of the NMOS transistor. The sources of the NMOS transistors are respectively connected to the signal output terminal VDD. out The source of PMOS transistor is connected, the drain of PMOS transistor is connected to the source of PMOS1 transistor, the drain of PMOS1 transistor is connected to the source of PMOS2 transistor, and the drain of PMOS2 transistor is connected to the third switch S3.

[0085] In the aforementioned buffer, the drain of the second MOSFET group is connected to the power supply VDD, the source of the second MOSFET group is connected to the drain of the first MOSFET group, the source of the first MOSFET group is connected to the drain of the initial MOSFET group, and the source of the initial MOSFET group is connected to the signal output terminal. The multiple MOSFET groups in this circuit are connected in series, ensuring that the drain-source voltage of the initial MOSFET group does not change with variations in the input signal. This prevents the drain voltage of the initial MOSFET group from being fixed at a specific power supply voltage, reducing the non-linearity of the output signal.

[0086] The buffer 10 described above increases the negative power supply voltage at the negative terminal of the buffer circuit. During the charging phase, the power supply charges the buffer with the negative power supply voltage. During the discharging phase, the negative power supply voltage and the power supply can simultaneously provide voltage to the multi-stage MOSFET group. The larger the voltage provided, the higher the corresponding number of MOSFET stages, which can further reduce the nonlinearity of the buffer's output signal and avoid signal distortion.

[0087] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0088] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A buffer, characterized in that, The buffer includes a buffer circuit, a capacitor, and a switching circuit. The buffer circuit includes a multi-stage MOSFET group. The buffer circuit and the capacitor are respectively connected to the switching circuit. The switching circuit and the buffer circuit are also connected to a power supply. The multi-stage MOS transistor group includes an initial MOS transistor group, a first MOS transistor group, and a second MOS transistor group; the drain of the NMOS transistor in the second MOS transistor group is connected to the power supply, the drain of the PMOS transistor in the second MOS transistor group is connected to the first terminal of the third switch in the switching circuit, the source of the second MOS transistor group is connected to the drain of the first MOS transistor group, the source of the first MOS transistor group is connected to the drain of the initial MOS transistor group, and the source of the initial MOS transistor group is connected to the signal output terminal. The switching circuit includes a first switching circuit and a second switching circuit; the first switching circuit includes a first switch and a second switch, the first terminal of the first switch is connected to the power supply, the second terminal of the first switch is connected to the first terminal of the capacitor, the first terminal of the second switch is connected to the second terminal of the capacitor, and the second terminal of the second switch is grounded; the second switching circuit includes a third switch and a fourth switch, the second terminal of the third switch is connected to the second terminal of the capacitor, the first terminal of the fourth switch is connected to the first terminal of the capacitor, and the second terminal of the fourth switch is grounded; During the charging phase, the first switch and the second switch are turned on, while the third switch and the fourth switch are turned off, to charge the capacitor; During the discharge phase, the first switch and the second switch are disconnected, and the third switch and the fourth switch are turned on, so that the power supply provides a positive voltage to the NMOS transistor of the second MOS transistor group, and the capacitor provides a negative voltage to the PMOS transistor of the second MOS transistor group.

2. The buffer according to claim 1, characterized in that, Each stage of the multi-stage MOS transistor group includes one NMOS transistor and one PMOS transistor.

3. The buffer according to claim 1 or 2, characterized in that, The buffer circuit also includes a level conversion circuit, which is connected to the signal input terminal and the multi-stage MOS transistor group respectively. The level conversion circuit is used to convert the level of the input signal at the signal input terminal.

4. The buffer according to claim 3, characterized in that, The level conversion circuit includes a first level converter and a second level converter. The first terminal of the first level converter is connected to the signal input terminal, and the second terminal of the first level converter is connected to the gate of the initial MOS transistor group and the gate of the first MOS transistor group. The first terminal of the second level converter is connected to the gate of the second MOS transistor group, and the second terminal of the second level converter is connected to the drain of the initial MOS transistor group.

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