A novel switching method based on Vcm voltage

Abstract

The application discloses a novel switching method based on Vcm voltage applied to a SAR ADC, energy consumption on vref is saved by 100%, a high-bit MSB capacitor array is split to replace vcm with vref and gnd, that is, the common-mode input voltage of the comparator input end is constant during the switching process of the lower plate voltage of the high-bit MSB capacitor. At the same time, the energy consumed on the positive and negative ends of the comparator is equal in size and opposite in sign, that is, one end consumes energy on vref and the other end releases energy on vref, and no energy is consumed on the driving vref voltage during each setting. On the other hand, a low-bit LSB capacitor array adopts a switching strategy using only vcm and gnd, and no energy is consumed on vref.

Description

Technical Field

[0001] This invention relates to the technical field of switching of SAR ADCs, and specifically to a novel switching method based on Vcm voltage. Background Technology

[0002] Currently, common switching techniques for SAR ADCs include traditional switching, Vcm-based switching, and monotonic switching. Traditional switching involves setting the bit first, then resetting it based on a comparison result, adding a setting cost to the vref, resulting in significant energy consumption. Vcm-based switching eliminates the pre-setting operation, keeping the input common-mode level constant during switching, resulting in moderate energy consumption. Monotonic switching minimizes energy consumption on the vref throughout the switching process, but its input common-mode level fluctuates considerably. While Vcm-based switching consumes energy to switch from Vcm to Vref, reducing average power consumption by approximately 87.5% compared to traditional switching, it still consumes some energy during switching. On the other hand, monotonic switching also incurs energy loss on the vref during the switching process, as one end of the capacitor array switches from vref to gnd or vice versa. Therefore, reducing energy consumption on the vref and minimizing input common-mode level shift are crucial issues. Summary of the Invention

[0003] To address the shortcomings of the above technologies, this invention provides a novel switching method based on Vcm voltage. Energy consumption on vref is reduced by 100%. The high-order MSB capacitor array is constructed by splitting capacitors, replacing vcm with vref and gnd, i.e., vcm = During the switching process of the lower plate voltage of the high-order MSB capacitor, the common-mode input voltage at the comparator input remains constant. Simultaneously, the energy consumed at the positive and negative terminals of the comparator is equal in magnitude but opposite in sign; that is, energy is consumed at one end and released at the other end. Each set operation consumes no energy in driving the vref voltage. On the other hand, the low-order LSB capacitor array employs a switching method using only vcm and gnd, which, compared to previous switching methods, consumes absolutely no energy at vref, achieving 100% energy saving at vref overall.

[0004] To achieve the above-mentioned objective, this invention provides a novel switching method based on Vcm voltage, comprising the following steps: S1. Construct a positive terminal capacitor array and a negative terminal capacitor array with identical structures; S2. Use a sampling switch to acquire two sets of input signals, and connect the two sets of input signals to the upper plate of the positive terminal capacitor array and the upper plate of the negative terminal capacitor array, respectively. S3. Disconnect the sampling switch, and use the comparator to directly compare the input signals held on the upper plates of the positive and negative capacitor arrays to obtain the first digital output code. Control the voltage connection relationship of the lower plates of the positive and negative capacitor arrays according to the obtained first digital output code. S4. Based on the voltage connection relationship determined in step S3, the voltage of the upper plate of the positive terminal and the voltage of the upper plate of the negative terminal are compared by a comparator to obtain the second digital output code. The first digital output code and the second digital output code are combined in sequence to obtain a digital output code string. The connection method of the lower plate of the capacitors of the positive terminal capacitor array and the negative terminal capacitor array is determined according to the digital output code string. S5. Based on the different comparison voltages at both ends of the comparator, the lower plates of the positive terminal capacitor array and the negative terminal capacitor array are switched sequentially to the reference voltage, common mode voltage, or ground state until the least significant bit of the comparison result is output. Finally, the multi-bit digital output code result is output in sequence.

[0005] Furthermore, the positive terminal capacitor array includes a first bridging capacitor C, a first high-segment capacitor array MSB, and a first low-segment capacitor array LSB, wherein the first high-segment capacitor array MSB includes... and Subarray, the first low-segment capacitor array LSB includes and Subarray; the negative terminal capacitor array includes a second bridging capacitor C, a second high-segment capacitor array MSB, and a second low-segment capacitor array LSB, wherein the second high-segment capacitor array MSB includes and Subarray, the second low-segment capacitor array LSB includes and Subarray.

[0006] Furthermore, the aforementioned Subarray includes capacitors The Subarray includes capacitors The Subarray includes capacitors The Subarray includes capacitors The Subarray includes capacitors The Subarray includes capacitors The Subarray includes capacitors The Subarray includes capacitors Where M and N are the numbers of the capacitors in the subarray, respectively.

[0007] Furthermore, the aforementioned Subarray and The lower plates of all capacitors in the subarray are connected to a reference voltage vref via a switch; Subarray and The lower plates of all capacitors in the subarray are connected to the reference voltage gnd via switches; Subarray, Subarray, Subarray and The lower plates of all capacitors in the subarray are connected to the common-mode voltage VCM via a switch.

[0008] Furthermore, step S3 specifically includes the following steps; S31, If ​​the first digital output code =1, then the capacitor of the positive terminal capacitor array and The lower plate switches from the vref and gnd states to the gnd and gnd states, while maintaining the capacitance. and All lower plates of the capacitors except those in the negative terminal capacitor array are in their original state; and The lower plate switches from the vref and gnd states to the vref and vref states, while maintaining the capacitance. and The lower plates of all low-level capacitors are in their original state, thus generating a voltage offset. In the subsequent low-level conversion process, the high-level capacitor array of the capacitor array continues to execute this strategy. S32, If the first digital output code =0, then the capacitor of the positive terminal capacitor array and The lower plate switches from the vref and gnd states to the vref and vref states, while maintaining the capacitance. and The lower plates of all low-voltage capacitors are in their original state; the capacitors of the negative terminal capacitor array are... and The lower plate switches from the vref and gnd states to the gnd and gnd states, while maintaining the capacitance. and All the lower plates of the capacitors except those in the low-position capacitors are in their original state, thus generating a voltage offset. In the subsequent low-position conversion process, the high-position capacitor array of the capacitor array continues to execute this strategy.

[0009] Furthermore, step S4 specifically includes the following steps: S41, When the digital output encoding string At that time, among them The second digital output code will convert the capacitors of the positive terminal capacitor array... and The lower plate switches from the vref and gnd states to the gnd and gnd states, thus changing the capacitance of the negative terminal capacitor array. and The lower plate switches from the vref and gnd states to the vref and vref states respectively, generating voltage offsets. S42, When the digital output encoding string At that time, the capacitors of the positive terminal capacitor array will be... and The lower plate switches from the vref and gnd states to the vref and vref states, thus changing the capacitance of the negative terminal capacitor array. and The lower plate switches from the vref and gnd states to the gnd and gnd states, and generates voltage offsets respectively; S43, When the digital output encoding string At that time, the capacitors of the positive terminal capacitor array will be... and The lower plate switches from the vref and gnd states to the gnd and gnd states, thus changing the capacitance of the negative terminal capacitor array. and The lower plate switches from the vref and gnd states to the vref and vref states respectively, generating voltage offsets. S44, When the digital output encoding string At that time, the capacitors of the positive terminal capacitor array will be... and The lower plate switches from the vref and gnd states to the vref and vref states, thus changing the capacitance of the negative terminal capacitor array. and The lower plate switches from the vref and gnd states to the gnd and gnd states, generating voltage offsets respectively.

[0010] Furthermore, S5 specifically includes the following steps: S51, When outputting a multi-digit code At that time, among them After the last capacitor in the high-segment capacitor array switches its lower plate, the A+1th digital output code obtained from the comparison is used to set the capacitor in the positive terminal of the capacitor array. and The lower plate switches from the VCM and VCM states to the GND and GND states, while maintaining the capacitance. and All the lower plates of the capacitors except those in the negative terminal capacitor array are in their original state. and The lower plate remains in its original vcm and vcm states, while maintaining the capacitance. and The lower plates of all low-level capacitors are in their original state. After all the lower plates of the high-level capacitor array have been switched, i.e. after switching A times, voltage offsets are generated on the upper plates of the positive and negative capacitor arrays respectively. S52, When outputting multi-digit codes At that time, the capacitors of the positive terminal capacitor array will be... and The lower plate remains in its original vcm and vcm states, while maintaining the capacitance. and All the lower plates of the capacitors except those in the negative terminal capacitor array are in their original state. and The lower plate switches from the VCM and VCM states to the GND and GND states, while maintaining the capacitance. and The lower plates of all low-position capacitors are in their original state. After switching the lower plates of the capacitor array A times, voltage offsets are generated on the upper plates of the positive and negative capacitor arrays, respectively.

[0011] The present invention has the following beneficial effects: (1) The present invention proposes a novel switching method based on Vcm voltage for SAR ADC, which requires three reference levels: voltage vref, vcm, and gnd. The high-order MSB realizes the equivalent split capacitance based on the Vcm voltage, and the low-order LSB realizes the switching based on the Vcm voltage. (2) Since the corresponding capacitors of the positive and negative terminals operate each time the switch is switched, and the absolute value of energy consumed is the same, the total energy loss of each switch is 0. Since the LSB part of the low position is at the vcm potential, no energy is consumed on vref when switching from the vcm potential to the gnd potential. Moreover, the switching only occurs at one end of the differential terminal of the comparator, which reduces the switching complexity and improves its economic efficiency. (3) The potential shift introduced by the capacitor array when comparing the low-order LSB part, i.e. the change of common mode level, has almost negligible effect on the comparator, thus relaxing the design of the comparator. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the overall process of the method of the present invention; Figure 2 This is a schematic diagram of the structure of the N-bit resolution differential SAR ADC implemented by the method of the present invention.

[0013] Figure 3 This is a schematic diagram of the first part of the method of the present invention for switching a 4-bit SAR ADC.

[0014] Figure 4 This is a schematic diagram of the second part of the method of the present invention for switching a 4-bit SAR ADC.

[0015] Figure 5 This is a schematic diagram illustrating the energy consumption effect of the method of the present invention when switching a 12-bit SAR ADC. Detailed Implementation

[0016] The specific embodiments of the present invention are described below to enable those skilled in the art to understand the present invention. However, it should be understood that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the present invention as defined and determined by the appended claims. All inventions utilizing the concept of the present invention are protected.

[0017] A novel switching method based on Vcm voltage, such as Figure 1 As shown, it includes the following steps: S1. Construct a positive terminal capacitor array and a negative terminal capacitor array with identical structures; Specifically, such as Figure 2 As shown, the positive terminal capacitor array includes a first bridging capacitor C, a first high-segment capacitor array MSB, and a first low-segment capacitor array LSB, wherein the first high-segment capacitor array MSB includes... and Subarray, the first low-segment capacitor array LSB includes and Subarray; the negative terminal capacitor array includes a second bridging capacitor C, a second high-segment capacitor array MSB, and a second low-segment capacitor array LSB, wherein the second high-segment capacitor array MSB includes and Subarray, the second low-segment capacitor array LSB includes and Subarray, where: The positive terminal capacitor array used includes bridging capacitors ( The MSB and LSB portions, where the MSB portion contains ( )and ( Two subarrays, the LSB portion contains ( )and ( ) sub-array; the negative terminal capacitor array includes bridging capacitors ( The MSB and LSB portions, where the MSB portion contains ( )and ( Two subarrays, the LSB portion contains ( )and ( (Subarray. Taking the positive terminal capacitor array as an example,) The part contains A split capacitors, composed of [ , Composed of binary weighted unit capacitor arrays, Some are similar; The part contains B split capacitors, composed of [ , Composed of binary weighted capacitor arrays, Some are similar. Generally, A>B, A+B=N-1, C is the selected unit capacitance size, and the composition of the negative terminal capacitor array is similar to that of the positive terminal capacitor array described above.

[0018] S2. Use a sampling switch to acquire two sets of input signals, and connect the two sets of input signals to the upper plate of the positive terminal capacitor array and the upper plate of the negative terminal capacitor array, respectively. The sampling switch acquires the input signals vip and vin, which are connected to the upper plates of the positive and negative capacitor arrays, respectively. Both capacitor arrays are identical. Specifically, this method uses two identical capacitor arrays: a positive terminal capacitor array and a negative terminal capacitor array. The input signal vip is connected to the upper plate of the positive capacitor array via a sampling switch, and the input signal vin is connected to the upper plate of the negative capacitor array via a sampling switch. The positive capacitor array LSB, wherein the second high-segment capacitor array MSB includes... and Subarray, the second low-segment capacitor array LSB includes and Sub-arrays; the upper plate of the positive terminal capacitor array is connected to the non-inverting terminal of the subsequent comparator, and the upper plate of the negative terminal capacitor array is connected to the inverting terminal of the subsequent comparator; the output of the comparator generates digital codewords after a series of delays, which are then transmitted to the control logic to control the switching voltage of the lower plates of the two capacitor arrays.

[0019] S3. Disconnect the sampling switch, and use the comparator to directly compare the input signals held on the upper plates of the positive and negative capacitor arrays to obtain the first digital output code. Control the voltage connection relationship of the lower plates of the positive and negative capacitor arrays according to the obtained first digital output code. Specifically, it includes the following: S31, If ​​the first digital output code =1, that is, when vip-vin>0, then the capacitor of the positive terminal capacitor array will be... and The lower plate switches from the vref and gnd states to the gnd and gnd states, while maintaining the capacitance. and The lower plates of all low-voltage capacitors are in their original state; the capacitors of the negative terminal capacitor array are... and The lower plate switches from the vref and gnd states to the vref and vref states, while maintaining the capacitance. and All the lower plates of the capacitors except those in the low-position capacitors are in their original state, thus generating... and Voltage offset. And in the subsequent low-order transition process, the high-order array of the capacitor array... - This strategy is consistently executed, connecting the lower plates of the positive and negative terminals to the corresponding voltages to generate the desired comparison voltage for the comparator to compare.

[0020] S32, If the first digital output code When =0, i.e., vip-vin<0, then the capacitor of the positive terminal capacitor array will be... and The lower plate switches from the vref and gnd states to the vref and vref states, while maintaining the capacitance. and The lower plates of all low-voltage capacitors are in their original state; the capacitors of the negative terminal capacitor array are... and The lower plate switches from the vref and gnd states to the gnd and gnd states, while maintaining the capacitance. and All the lower plates of the capacitors except those in the low-position capacitors are in their original state, thus generating... and Voltage offset, and in the subsequent low-order transition process, the high-order array of the capacitor array. - This strategy is consistently executed, connecting the lower plates of the positive and negative terminals to the corresponding voltages to generate the desired comparison voltage for the comparator to compare.

[0021] S4. Based on the voltage connection relationship determined in step S3, the voltage of the upper plate of the positive terminal and the voltage of the upper plate of the negative terminal are compared by a comparator to obtain the second digital output code. The first digital output code and the second digital output code are combined in sequence to obtain a digital output code string. The connection method of the lower plate of the positive terminal capacitor array and the negative terminal capacitor array MSB-1 capacitor is determined according to the digital output code string. Specifically, it includes the following: S41, When the digital output encoding string At that time, i.e., vip-vin> At that time, among them The second digital output code will convert the capacitors of the positive terminal capacitor array... and The lower plate switches from the vref and gnd states to the gnd and gnd states, thus changing the capacitance of the negative terminal capacitor array. and The lower electrode plate switches from the vref and gnd states to the vref and vref states respectively, generating and Voltage offset.

[0022] S42, When the digital output encoding string That is, vip-vin< At that time, the capacitors of the positive terminal capacitor array will be... and The lower plate switches from the vref and gnd states to the vref and vref states, thus changing the capacitance of the negative terminal capacitor array. and The lower electrode plate switches from the vref and gnd states to the gnd and gnd states respectively, generating and Voltage offset.

[0023] S43, When the digital output encoding string , i.e., vip-vin> At that time, the capacitors of the positive terminal capacitor array will be... and The lower plate switches from the vref and gnd states to the gnd and gnd states, thus changing the capacitance of the negative terminal capacitor array. and The lower electrode plate switches from the vref and gnd states to the vref and vref states respectively, generating and Voltage offset.

[0024] S44, When the digital output encoding string That is, vip-vin< At that time, the capacitors of the positive terminal capacitor array will be... and The lower plate switches from the vref and gnd states to the vref and vref states, thus changing the capacitance of the negative terminal capacitor array. and The lower electrode plate switches from the vref and gnd states to the gnd and gnd states respectively, generating vref and Voltage offset.

[0025] S5. Based on the different comparison voltages at both ends of the comparator, the lower plates of the positive terminal capacitor array and the negative terminal capacitor array are switched sequentially to the reference voltage, common mode voltage, or ground state until the least significant bit of the comparison result is output. Finally, the multi-bit digital output code result is output in sequence.

[0026] Based on the different comparison voltages across the comparator, the lower plates of the positive and negative capacitors in the high-segment capacitor array are sequentially switched to either the reference voltage or grounded until the first A+1 bits of the comparison result are obtained. Finally, the A+1 bits of digital output code result are output in sequence, as shown below. S51, When outputting a multi-digit code That is, when vxpA - vxnA > 0 (vxpA and vxnA are the voltages on the upper plates of the positive and negative terminals after the Ath switching of the lower plate of the capacitor array), where After the last capacitor in the high-segment capacitor array switches its lower plate, the A+1th digital output code obtained from the comparison is used to set the capacitor in the positive terminal of the capacitor array. and The lower plate switches from the VCM and VCM states to the GND and GND states, while maintaining the capacitance. and All the lower plates of the capacitors except those in the negative terminal capacitor array are in their original state. and The lower plate remains in its original vcm and vcm states, while maintaining the capacitance. and The lower plates of all low-voltage capacitors are in their original state. At this time, based on the voltages vxpA and vxnA, respectively, the following voltages are generated: And 0 V voltage offset, based on this strategy, the desired comparison voltage is generated until the low-level switching of the low-segment capacitor array is completed; S52, When outputting multi-digit codes When vxpA - vxnA < 0, the capacitors of the positive terminal capacitor array will be... and The lower plate remains in its original vcm and vcm states, while maintaining the capacitance. and All the lower plates of the capacitors except those in the negative terminal capacitor array are in their original state. and The lower plate switches from the VCM and VCM states to the GND and GND states, while maintaining the capacitance. and The lower plates of all the low-voltage capacitors are in their original state. At this time, based on the voltages vxpA and vxnA, 0 V and 0 V are generated respectively. Voltage offset, based on this strategy, generates the desired comparison voltage until the low-level switching of the low-segment capacitor array is completed.

[0027] Specifically, such as Figure 2 As shown, based on the different comparison voltages across the comparator, the lower plate of the capacitor array MSB is sequentially switched to the vref and gnd states, and the lower plate of the capacitor array LSB is switched to the gnd and gnd states, until the least significant bit digital output code is obtained. Final output , ,… , of N The output code result is a digit number.

[0028] As can be seen, the digital code output by the comparator in this invention is transmitted to the control logic, and then the control signal controls the switching of the lower plate of the capacitor array, connecting it to the corresponding reference voltage. In the proposed algorithm, a split capacitor is constructed, and the energy consumed during the switching of the lower plate voltage of the capacitor array between the high and low segments is greatly reduced.

[0029] To further illustrate the method of the present invention, in conjunction with Figure 3 and Figure 4 The diagram illustrates the specific conversion process of a 4-bit SAR ADC: During the sampling phase, the input signals Vip and Vin are connected to the upper plates of the capacitor array at the positive and negative terminals respectively through sampling switches. , The lower plate of all capacitors in the subarray section is connected to vref. , The lower plate of all capacitors in the subarray section is connected to GND. , , , The lower plate of all capacitors in the subarray section is connected to VCM; During the conversion phase, the sampling switch is first disconnected, and then the comparator directly performs an MSB bit comparison on the input signals Vip and Vin, which are held on the upper plates of the capacitor array at the positive and negative terminals, to obtain the digital code. According to the digital code Controlling the connection relationship of the lower plates of capacitors in the positive and negative capacitor arrays, and operating according to different situations, specifically including: like =1, meaning vip-vin>0, will set the MSB portion of the positive terminal capacitor array to 1. The lower electrode plate is switched to GND. Keeping the lower plate constant (gnd), the negative terminal capacitor array MSB section... The lower plate keeps vref constant. The lower electrode switches to vref, generating respectively vref and Voltage offset of vref; like =0, that is, vip-vin<0, will reduce the MSB portion of the positive terminal capacitor array. The lower plate keeps vref constant. Switching the lower plate to vref will change the MSB section of the negative terminal capacitor array. The lower electrode plate is switched to GND. With the lower electrode plate keeping gnd constant, respectively generate vref and Voltage offset of vref; The comparator derives a digital code by comparing the voltages on the upper plates of the capacitor array at the positive and negative terminals obtained through the above process. According to the digital code Controlling the connection relationship of the lower plates of capacitors in the positive and negative capacitor arrays includes the following cases: like =11, i.e., vip-vin> vref, which will be the MSB portion of the positive terminal capacitor array. The lower electrode plate is switched to GND. Keeping the lower plate constant (gnd), the negative terminal capacitor array MSB section... The lower plate keeps vref constant. The lower electrode switches to vref, generating respectively vref and Voltage offset of vref; like =10, i.e., vip-vin< vref, which will be the MSB portion of the positive terminal capacitor array. The lower plate keeps vref constant. Switching the lower plate to vref will change the MSB section of the negative terminal capacitor array. The lower electrode plate is switched to GND. With the lower electrode plate keeping gnd constant, respectively generate vref and Voltage offset of vref; like =01, i.e., vip-vin> vref, which will be the MSB portion of the positive terminal capacitor array. The lower electrode plate is switched to GND. Keeping the lower plate constant (gnd), the negative terminal capacitor array MSB section... The lower plate keeps vref constant. The lower electrode switches to vref, generating respectively vref and Voltage offset of vref; like =00, i.e., vip-vin< vref, which will be the MSB portion of the positive terminal capacitor array. The lower plate keeps vref constant. Switching the lower plate to vref will change the MSB section of the negative terminal capacitor array. The lower electrode plate is switched to GND. With the lower electrode plate keeping gnd constant, respectively generate vref and Voltage offset of vref; The comparator derives a digital code by comparing the voltages on the upper plates of the capacitor array at the positive and negative terminals obtained through the above process. According to the digital code Controlling the connection relationship of the lower plates of capacitors in the positive and negative capacitor arrays includes the following cases: like =111, i.e., vip-vin> vref, which will be the LSB portion of the positive terminal capacitor array. The lower electrode plate is switched to GND. Switching the lower plate to GND will change the negative terminal capacitor array LSB section. The lower electrode plate keeps vcm constant. With the lower electrode plate keeping vcm constant, it generates... vref and Voltage offset of vref; like =110, i.e., vip-vin< vref, which will be the LSB portion of the positive terminal capacitor array. The lower electrode plate keeps vcm constant. With the lower electrode plate keeping Vcm constant, the negative terminal capacitor array LSB section... The lower electrode plate is switched to GND. The lower electrode is switched to GND, generating... vref and Voltage offset of vref; like =101, i.e., vip-vin> vref, which will be the LSB portion of the positive terminal capacitor array. The lower electrode plate is switched to GND. Switching the lower plate to GND will change the negative terminal capacitor array LSB section. The lower electrode plate keeps vcm constant. With the lower electrode plate keeping vcm constant, it generates... vref and Voltage offset of vref; like =100, i.e., vip-vin< vref, which will be the LSB portion of the positive terminal capacitor array. The lower electrode plate keeps vcm constant. With the lower electrode plate keeping Vcm constant, the negative terminal capacitor array LSB section... The lower electrode plate is switched to GND. The lower electrode is switched to GND, generating... vref and Voltage offset of vref; like =011, i.e., vip-vin> vref, which will be the LSB portion of the positive terminal capacitor array. The lower electrode plate is switched to GND. Switching the lower plate to GND will change the negative terminal capacitor array LSB section. The lower electrode plate keeps vcm constant. With the lower electrode plate keeping vcm constant, it generates... vref and Voltage offset of vref; like =010, i.e., vip-vin< vref, which will be the LSB portion of the positive terminal capacitor array. The lower electrode plate keeps vcm constant. With the lower electrode plate keeping Vcm constant, the negative terminal capacitor array LSB section... The lower electrode plate is switched to GND. The lower electrode is switched to GND, generating... vref and Voltage offset of vref; like =001, i.e., vip-vin> vref, which will be the LSB portion of the positive terminal capacitor array. The lower electrode plate is switched to GND. Switching the lower plate to GND will change the negative terminal capacitor array LSB section. The lower electrode plate keeps vcm constant. With the lower electrode plate keeping vcm constant, it generates... vref and Voltage offset of vref; like =000, i.e., vip-vin< vref, which will be the LSB portion of the positive terminal capacitor array. The lower electrode plate keeps vcm constant. With the lower electrode plate keeping Vcm constant, the negative terminal capacitor array LSB section... The lower electrode plate is switched to GND. The lower electrode is switched to GND, generating... vref and Voltage offset of vref; The comparator derives a digital code by comparing the voltages on the upper plates of the capacitor array at the positive and negative terminals obtained through the above process. The final output is a digital code. Final output , , , Four-digit code.

[0030] like Figure 5 As shown, taking a 12-bit SAR ADC as an example, the energy switching results demonstrate that the novel switching method based on Vcm voltage proposed in this invention consumes zero energy on vref, further verifying the effectiveness of the switching scheme.

[0031] In summary, this invention proposes a novel switching strategy. During the sampling phase, the capacitor array is pre-charged; during the conversion phase, the switch is turned off; the comparator compares the voltages of the upper plates at the positive and negative terminals to derive the output digital codeword; and then, based on the output codeword, the voltage switching of the lower plates of the corresponding capacitors at the positive and negative terminals is controlled. The required voltage offset can be obtained in each capacitor switching. Using this method with three voltages—vref, vcm, and gnd—energy consumption on the driving voltage vref can reach zero. That is, switching of the high-order and low-order capacitor arrays consumes no energy on vref, significantly reducing the switching power consumption of the capacitor DAC.

[0032] Specific embodiments have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this invention. Therefore, the content of this specification should not be construed as a limitation of this invention.

[0033] Those skilled in the art will recognize that the embodiments described herein are intended to help the reader understand the principles of the invention, and should be understood that the scope of protection of the invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this invention without departing from the spirit of the invention, and these modifications and combinations are still within the scope of protection of this invention.

Claims

1. A novel switching method based on Vcm voltage, characterized in that, Includes the following steps: S1. Construct a positive terminal capacitor array and a negative terminal capacitor array with identical structures; S2. Use a sampling switch to acquire two sets of input signals, and connect the two sets of input signals to the upper plate of the positive terminal capacitor array and the upper plate of the negative terminal capacitor array, respectively. S3. Disconnect the sampling switch, and use a comparator to directly compare the input signals held on the upper plates of the positive and negative capacitor arrays to obtain the first digital output code. Control the voltage connection relationship of the lower plates of the positive and negative capacitor arrays according to the obtained first digital output code. The specific steps include the following: S31, If ​​the first digital output code =1, then the capacitor of the positive terminal capacitor array and The lower plate switches from the vref and gnd states to the gnd and gnd states, while maintaining the capacitance. and All lower plates of the capacitors except those in the negative terminal capacitor array are in their original state; and The lower plate switches from the vref and gnd states to the vref and vref states, while maintaining the capacitance. and The lower plates of all low-level capacitors are in their original state, thus generating a voltage offset. In the subsequent low-level conversion process, the high-level capacitor array of the capacitor array continues to execute this strategy. S32, If the first digital output code =0, then the capacitor of the positive terminal capacitor array and The lower plate switches from the vref and gnd states to the vref and vref states, while maintaining the capacitance. and The lower plates of all low-voltage capacitors are in their original state; the capacitors of the negative terminal capacitor array are... and The lower plate switches from the vref and gnd states to the gnd and gnd states, while maintaining the capacitance. and The lower plates of all low-level capacitors are in their original state, thus generating a voltage offset. In the subsequent low-level conversion process, the high-level capacitor array of the capacitor array continues to execute this strategy. S4. Based on the voltage connection relationship determined in step S3, the voltage of the upper plate of the positive terminal and the voltage of the upper plate of the negative terminal are compared by a comparator to obtain the second digital output code. The first digital output code and the second digital output code are combined in sequence to obtain a digital output code string. The connection method of the lower plate of the capacitors of the positive terminal capacitor array and the negative terminal capacitor array is determined according to the digital output code string. S5. Based on the different comparison voltages across the comparator, sequentially switch the lower plates of the positive and negative capacitor arrays to the reference voltage, common-mode voltage, or ground state until the least significant bit of the comparison result is output. Finally, output the multi-bit digital output code result in sequence. The specific steps include the following: S51, When outputting a multi-digit code At that time, among them After the last capacitor in the high-segment capacitor array switches its lower plate, the A+1th digital output code obtained from the comparison is used to set the capacitor in the positive terminal of the capacitor array. and The lower plate switches from the VCM and VCM states to the GND and GND states, while maintaining the capacitance. and All the lower plates of the capacitors except those in the negative terminal capacitor array are in their original state. and The lower plate remains in its original vcm and vcm states, while maintaining the capacitance. and The lower plates of all low-level capacitors are in their original state. After all the lower plates of the high-level capacitor array have been switched, i.e. after switching A times, voltage offsets are generated on the upper plates of the positive and negative capacitor arrays respectively. S52, When outputting multi-digit codes At that time, the capacitors of the positive terminal capacitor array will be... and The lower plate remains in its original vcm and vcm states, while maintaining the capacitance. and All the lower plates of the capacitors except those in the negative terminal capacitor array are in their original state. and The lower plate switches from the VCM and VCM states to the GND and GND states, while maintaining the capacitance. and The lower plates of all low-position capacitors are in their original state. After switching the lower plates of the capacitor array A times, voltage offsets are generated on the upper plates of the positive and negative capacitor arrays, respectively.

2. The novel switching method based on Vcm voltage according to claim 1, characterized in that, The positive terminal capacitor array includes a first bridging capacitor C, a first high-segment capacitor array MSB, and a first low-segment capacitor array LSB, wherein the first high-segment capacitor array MSB includes... and Subarray, the first low-segment capacitor array LSB includes and Subarray; the negative terminal capacitor array includes a second bridging capacitor C, a second high-segment capacitor array MSB, and a second low-segment capacitor array LSB, wherein the second high-segment capacitor array MSB includes and Subarray, the second low-segment capacitor array LSB includes and Subarray.

3. The novel switching method based on Vcm voltage according to claim 2, characterized in that, The Subarray includes capacitors The Subarray includes capacitors The Subarray includes capacitors The Subarray includes capacitors The Subarray includes capacitors The Subarray includes capacitors +…+ The Subarray includes capacitors The Subarray includes capacitors Where M and N are the numbers of the capacitors in the subarray, respectively.

4. A novel switching method based on Vcm voltage according to claim 2, characterized in that, The Subarray and The lower plates of all capacitors in the subarray are connected to a reference voltage vref via a switch; Subarray and The lower plates of all capacitors in the subarray are connected to the reference voltage gnd via switches; Subarray, Subarray, Subarray and The lower plates of all capacitors in the subarray are connected to the common-mode voltage VCM via a switch.

5. A novel switching method based on Vcm voltage according to claim 2, characterized in that, S4 specifically includes the following steps: S41, When the digital output encoding string At that time, among them The second digital output code will convert the capacitors of the positive terminal capacitor array... and The lower plate switches from the vref and gnd states to the gnd and gnd states, thus changing the capacitance of the negative terminal capacitor array. and The lower plate switches from the vref and gnd states to the vref and vref states respectively, generating voltage offsets. S42, When the digital output encoding string At that time, the capacitors of the positive terminal capacitor array will be... and The lower plate switches from the vref and gnd states to the vref and vref states, thus changing the capacitance of the negative terminal capacitor array. and The lower plate switches from the vref and gnd states to the gnd and gnd states, and generates voltage offsets respectively; S43, When the digital output encoding string At that time, the capacitors of the positive terminal capacitor array will be... and The lower plate switches from the vref and gnd states to the gnd and gnd states, thus changing the capacitance of the negative terminal capacitor array. and The lower plate switches from the vref and gnd states to the vref and vref states respectively, generating voltage offsets. S44, When the digital output encoding string At that time, the capacitors of the positive terminal capacitor array will be... and The lower plate switches from the vref and gnd states to the vref and vref states, thus changing the capacitance of the negative terminal capacitor array. and The lower plate switches from the vref and gnd states to the gnd and gnd states, generating voltage offsets respectively.

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