Multichannel sampling circuit and its indication circuit

Abstract

Disclosed is a multi-channel sampling circuit including N sampling circuits and a level setting output circuit. The N sampling circuits provide N analog signals, and the level setting output circuit receives the N analog signals and a setting signal, and sets the N analog signals to a first level and a second level according to the setting signal, and selectively outputs the N analog signals, wherein the output frequency of the analog signal set to the first level is greater than the output frequency of the analog signal set to the second level. The multi-channel sampling circuit further includes an analog-to-digital conversion circuit for converting the received analog signals into digital output signals. The multi-channel sampling circuit improves the update speed of partial channel data without increasing the sampling rate or number of the analog-to-digital conversion circuit.

Description

Technical Field

[0001] This invention relates to sampling circuits, and more specifically, to multi-channel sampling circuits. Background Technology

[0002] Switching power supplies require the sampling and recording of numerous analog parameters, such as current and voltage information. Therefore, multi-channel sampling circuits are widely used in switching power supplies to detect various parameters. In multi-channel sampling circuits applied to switching power supplies, shorter data update cycles for certain channels are preferable. Given a fixed sampling rate for the analog-to-digital converter (ADC), the common practice is to increase the number of ADCs to shorten the data update cycle, which increases the cost of the switching power supply.

[0003] Therefore, a multi-channel sampling circuit is needed that can improve the data update cycle of certain channels without increasing the number of analog-to-digital converters. Summary of the Invention

[0004] One embodiment of the present invention proposes a multi-channel sampling circuit, which includes N sampling circuits and a level setting output circuit, wherein the N sampling circuits provide N analog signals. The level setting output circuit receives the N analog signals and a setting signal, and sets the N analog signals to a first level and a second level respectively according to the setting signal, and selectively outputs the N analog signals, wherein the output frequency of the analog signal set to the first level is greater than the output frequency of the analog signal set to the second level; the multi-channel sampling circuit also includes an analog-to-digital conversion circuit for converting the received analog signals into digital output signals.

[0005] One embodiment of the present invention provides a multi-channel sampling circuit for a switching power supply. The switching power supply has an input terminal, and the multi-channel sampling circuit includes N sampling circuits, a level setting output circuit, and an analog-to-digital conversion circuit. The N sampling circuits provide N analog signals, wherein at least one analog signal represents the current flowing through the input terminal. The level setting output circuit receives the N analog signals and a setting signal, and sets the N analog signals to a first level and a second level respectively according to the setting signal, and selectively outputs the N analog signals. The analog signal representing the current flowing through the input terminal is set to the first level, and the output frequency of the analog signal set to the first level is greater than the output frequency of the analog signal set to the second level. The analog-to-digital conversion circuit converts the received analog signals into digital output signals.

[0006] An embodiment of the present invention provides an indicator circuit, which includes a multi-channel sampling circuit and a data processing circuit. The multi-channel sampling circuit includes N sampling circuits and a level setting output circuit, wherein the N sampling circuits provide N analog signals. The level setting output circuit receives the N analog signals and a setting signal, and sets the N analog signals to a first level and a second level respectively according to the setting signal, and selectively outputs the N analog signals, wherein the output frequency of the analog signal set to the first level is greater than the output frequency of the analog signal set to the second level. The multi-channel sampling circuit also includes an analog-to-digital conversion circuit that converts the received analog signals into digital output signals. The data processing circuit receives the digital output signal output by the analog-to-digital conversion circuit and generates an indicator signal based on the digital output signal.

[0007] The multi-channel sampling circuit provided by the present invention improves the data update cycle of certain channels without increasing the number of analog-to-digital converters. Attached Figure Description

[0008] To better understand the present invention, embodiments of the invention will be described with reference to the following accompanying drawings, which are for illustrative purposes only. The drawings typically show only some features of the embodiments and are not necessarily drawn to scale.

[0009] Figure 1 A schematic diagram of an indicator circuit 100 according to an embodiment of the present invention is provided.

[0010] Figure 2 A timing diagram of the digital output signal DATA of a 16-channel sampling circuit according to an embodiment of the present invention is provided.

[0011] Figure 3 A timing diagram of the digital output signal DATA of a 16-channel sampling circuit according to another embodiment of the present invention is provided.

[0012] Figure 4 A timing diagram of the digital output signal DATA of a 16-channel sampling circuit according to another embodiment of the present invention is provided.

[0013] Figure 5 A schematic diagram of the circuit structure of a switching power supply 200 including a multi-channel sampling circuit 20 according to an embodiment of the present invention is provided.

[0014] Figure 6 A schematic diagram of the circuit structure of a data processing circuit according to an embodiment of the present invention is provided.

[0015] Figure 7 A schematic diagram of the circuit structure of a data processing circuit according to another embodiment of the present invention is provided.

[0016] The same reference numerals in different schematic diagrams indicate the same or similar parts or features. Detailed Implementation

[0017] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other embodiments, well-known circuits, materials, or methods have not been specifically described in order to avoid obscuring the invention.

[0018] In this specification and claims, the use of terms such as "left," "right," "inner," "outer," "upper," "lower," "above," and "below" is merely for descriptive convenience and does not indicate a necessary or permanent relative position of components / structures. Those skilled in the art should understand that such terms are interchangeable where appropriate, for example, so that embodiments of this disclosure can still operate in orientations different from those depicted in this specification. In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, the term "coupled" means a connection, directly or indirectly, electrically or non-electrically. "A / this / that" is not used specifically to refer to the singular but may encompass the plural form. The phrases "an embodiment," "embodiment," "an example," and "example" appearing throughout the specification do not necessarily refer to the same embodiment or example. Those skilled in the art should understand that the various useful terms "and / or" disclosed in one or more embodiments of this disclosure include any and all combinations of one or more of the associated listed items.

[0019] Figure 1 A schematic diagram of an indicator circuit 100 according to an embodiment of the present invention is provided. Figure 1As shown, the indicator circuit 100 includes a multi-channel sampling circuit 10, which includes N sampling circuits CH1-CHN and a level setting output circuit 11. The N sampling circuits CH1-CHN provide N analog signals ALG1-ALGN, where N is a natural number greater than 1. In the illustrated embodiment, the i-th analog signal ALGi can be a current signal or a voltage signal, where 1 ≤ i ≤ N. The level setting output circuit 11 receives the N analog signals ALG1-ALGN and a setting signal SET1, and sets the N analog signals ALG1-ALGN to a first level and a second level respectively according to the setting signal SET1. It then selectively outputs the N analog signals ALG1-ALGN, wherein the output frequency of the analog signal set to the first level is greater than the output frequency of the analog signal set to the second level. Specifically, at different times, according to the setting signal SET1, the level setting output circuit 11 selectively outputs the i-th analog signal ALGi from the N analog signals ALG1-ALGN. More specifically, the level setting output circuit 11 sets the N analog signals ALG1-ALGN to a first level and a second level respectively through the setting signal SET1, according to actual circuit control needs or sampling requirements. The output frequency of the analog signal set to the first level is greater than the output frequency of the analog signal set to the second level. In one embodiment, the external control circuit can output the setting signal SET1 through data transmission protocols such as I2C or PMBUS to define the level of each analog signal among the N analog signals ALG1-ALGN. In this invention, the number of times the i-th analog signal ALGi is output from the level setting circuit per unit time is defined as the output frequency of the i-th analog signal ALGi. In one embodiment, the output frequency of the analog signal set to the second level is zero, that is, the number of times the analog signal set to the second level is output from the level setting output circuit 11 is zero. In another embodiment, the output frequency of the analog signal set to the second level is zero for a period of time and not zero for another period of time. In one embodiment, M of the N analog signals ALG1-ALGN are current signals, and (NM) are voltage signals, where 1 ≤ M ≤ N. The multi-channel sampling circuit 10 also includes an analog-to-digital converter circuit 12, which receives the i-th analog signal ALGi output by the level setting output circuit 11 and converts the i-th analog signal ALGi into a digital output signal DATA. Figure 1 In the process, the indicator circuit 100 also includes a data processing circuit, which receives the digital output signal DATA output by the multi-channel sampling circuit 10 and generates an indicator signal Fault based on the digital output signal DATA.

[0020] Figure 2 A timing diagram of the digital output signal DATA of a 16-channel sampling circuit according to an embodiment of the present invention is provided. Figure 2 In this circuit, the setting signal SET1 sets the first analog signal ALG1 and the second analog data ALG2 as the first level, and the analog data ALG3-ALG16 as the second level. The output frequency of the analog data ALG3-ALG16 set to the second level is zero. That is, the level setting output circuit 11 only outputs the first analog data ALG1 and the second analog data ALG2 of the first level. Compared with the 16-channel sampling circuit without the level setting output circuit 11, the sampling output of the first analog signal ALG1 in the digital output signal DATA needs to wait for 16 sampling cycles before the data is updated (the sampling output of the first analog signal ALG1 in the digital output signal DATA needs to wait for the analog signals ALG2-ALG15 to be sampled and output once before it is updated). Figure 2 In the embodiment shown, the data update cycle of the first analog signal ALG1 and the second analog data ALG2 in the digital output signal DATA is faster. From Figure 2 As can be seen from the data, the first analog signal ALG1 and the second analog data ALG2 are updated every two sampling cycles. In this application, the sampling cycle refers to the duration for the digital output signal DATA to output one data.

[0021] Figure 3 A timing diagram of the digital output signal DATA of a 16-channel sampling circuit according to another embodiment of the present invention is provided. Figure 3 In the illustrated embodiment, the setting signal SET1 sets the first analog signal ALG1 and the second analog data ALG2 as the first level, and sets the analog signals ALG3-ALG16 as the second level. Figure 2 The difference between the illustrated embodiment and the one shown is that, in Figure 3 In one embodiment, the ratio of the output frequencies of the first analog signal ALG1 and the second analog signal ALG2 (set as the first level) to the output frequencies of the analog signals ALG3-ALG16 (set as the second level) is 7:1. Figure 3 As can be seen, the first analog signal ALG1 and the second analog signal ALG2 are updated every 4 sampling cycles, while the analog signals ALG3-ALG16 in the second level are updated every 28 sampling cycles.

[0022] Figure 4 A timing diagram of the digital output signal DATA of a 16-channel sampling circuit according to another embodiment of the present invention is given. Figure 4 In the illustrated embodiment, the setting signal SET1 sets the first analog signal ALG1 and the second analog signal ALG2 as the first level, and sets the analog signals ALG3-ALG16 as the second level. Figure 2 as well as Figure 3 The difference between the illustrated embodiment and the one shown is that, in Figure 4In one embodiment, the ratio of the output frequency of the analog signals ALG1-ALG2 (set as the first level) to the output frequency of the analog data ALG3-ALG16 (set as the second level) is 10:3. Figure 3 As can be seen, the first analog signal ALG1 and the second analog signal ALG2 are updated every 6 sampling cycles, while the analog signals ALG3-ALG16 in the second level are updated every 20 sampling cycles.

[0023] Figure 5 A circuit diagram of a switching power supply 200 including a multi-channel sampling circuit 20 according to an embodiment of the present invention is provided. The switching power supply 200 has an input terminal IN, and the current flowing into the input terminal is the input current I. IN In one embodiment, the switching power supply is a buck circuit; in another embodiment, it is a boost circuit; and in yet another embodiment, it is a buck-boost circuit. Figure 5 In this circuit, the bus power supply (BUS) supplies power to the input terminal IN of the switching power supply, and a sampling circuit 23 is located between the bus power supply (BUS) and the input terminal IN of the switching power supply. Figure 5 In the illustrated embodiment, the sampling circuit 23 includes a sampling resistor Rsen and an error amplifier CS. The sampling circuit 23 is used to generate a characterization of the input current I. IN The detection signal VCS. In one embodiment, the sampling resistor Rsen and the multi-channel sampling circuit 20 are concentrated on the same semiconductor substrate. In another embodiment, the sampling resistor Rsen is a discrete device and is not concentrated on the same semiconductor substrate as the multi-channel sampling circuit 20. In one embodiment, the gain of the error amplifier CS is user-defined, that is, the user can adjust the gain of the error amplifier CS according to data communication protocols such as I2C. The level setting output circuit 21 receives N analog signals ALG1-ALGN and a setting signal SET1, and sets the N analog signals ALG1-ALGN to the first level and the second level respectively according to the setting signal, and selectively outputs the N analog signals, wherein the output frequency of the analog signal set to the first level is greater than the output frequency of the analog signal set to the second level. Figure 5 In this circuit, the detection signal VCS is input as the first analog signal ALG1 to the level setting output circuit 21. In one embodiment, the multi-channel sampling circuit 200 can also detect various parameters of the switching power supply, such as input voltage, output voltage, and output current, generating analog signals to the level setting output circuit 21. Figure 5 In the process, the analog-to-digital conversion circuit 12 receives the i-th analog signal ALGi output by the level setting output circuit 21 and converts the i-th analog signal ALGi into a digital output signal DATA.

[0024] Figure 6A schematic diagram of the circuit structure of a data processing circuit according to an embodiment of the present invention is provided. Figure 6 The data processing circuit includes a averaging circuit and a digital comparator (CMP). The averaging circuit receives the digital output signal DATA and generates an average signal AVG according to the averaging formula. In one embodiment, the averaging formula is as follows: , where DATA new This refers to the value of the digital output signal DATA after updating one sample value, AVG. old It refers to the value of the mean signal AVG before the digital output signal DATA is updated by one sample value. new This refers to the value of the mean signal AVG after the digital output signal DATA updates a sample value, where P is a user-defined natural number. In one embodiment, P is 6, and in another embodiment, P can be 16. The digital comparator CMP has a first input to receive the mean signal AVG and a second input to receive a threshold signal Vth, and generates an indication signal fault based on the mean signal AVG and the threshold signal Vth to indicate whether an event has occurred. In one embodiment, when the mean signal AVG is greater than the threshold signal Vth, the indication signal Fault is in a first state to indicate that the event has occurred. Figure 6 In the illustrated embodiment, the data processing circuit further includes a threshold setting circuit. An external control circuit sends commands to the threshold setting circuit via data communication protocols such as I2C or PBUS to customize the value of the threshold signal Vth. In one embodiment, the data processing circuit also includes a register for storing the digital output signal DATA output by the analog-to-digital converter circuit.

[0025] Figure 7 A schematic diagram of the circuit structure of a data processing circuit according to another embodiment of the present invention is provided. Figure 7In the illustrated embodiment, the digital processing circuit includes a first comparator CMP1, a counter, and a second comparator CMP2. The first comparator CMP1 has a first input to receive a digital output signal DATA and a second input to receive a reference signal Vref. The first comparator CMP1 compares the reference signal Vref and the digital output signal DATA to generate a comparison signal COM. The counter receives the comparison signal COM and outputs a count signal Num based on COM. If the digital output signal DATA is greater than the reference signal Vref, the value of the count signal Num increases; if the digital output signal DATA is less than the reference signal Vref, the value of the count signal Num decreases. In one embodiment, if the digital output signal DATA is greater than the reference signal Vref, the value of the count signal Num increases by 1; if the digital output signal DATA is less than the reference signal Vref, the value of the count signal Num decreases by 1. The second comparator CMP2 has a first input to receive a base signal Nth and a second input to receive the count signal Num. It compares the count signal Num and the base signal Nth to generate an indication signal Fault. In one embodiment, the signal processing circuit further includes a radix setting circuit, wherein an external control circuit sets the value of the radix signal Nth via I2C or other data transmission protocols. In one embodiment, the data processing circuit further includes a register for storing the digital output signal DATA output by the analog-to-digital conversion circuit.

[0026] The multi-channel sampling circuit of the present invention records data from multiple channels simultaneously when the sampling rate of the analog-to-digital converter is fixed. By setting a first level and a second level for different analog signals, the data update cycle of the channel in the first level is faster than that of the channel in the second level. Therefore, the multi-channel sampling circuit of the present invention can improve the update cycle of data for certain channels without increasing the number of analog-to-digital converters.

[0027] The specific embodiments described above are merely exemplary illustrations of the high-voltage devices and manufacturing methods of the present invention. These embodiments are not exhaustive and are not intended to limit the scope of the invention. Variations and modifications to the disclosed embodiments are possible, and other feasible alternative embodiments and equivalent variations of elements in the embodiments can be understood by those skilled in the art. Other variations and modifications to the embodiments disclosed in this invention do not depart from the spirit of the invention and the scope of protection defined by the claims.

Claims

1. A multi-channel sampling circuit, comprising: N sampling circuits are used to detect N signals from the switching power supply and provide N analog signals; The level setting output circuit receives N analog signals and a setting signal, sets the N analog signals to the first level and the second level respectively according to the setting signal, and selectively outputs the N analog signals, wherein the output frequency of the analog signal set to the first level is greater than the output frequency of the analog signal set to the second level. as well as An analog-to-digital converter circuit converts a received analog signal into a digital output signal.

2. The multi-channel sampling circuit as described in claim 1, wherein the output frequency of the analog signal set as the second stage is zero.

3. In the multi-channel sampling circuit as described in claim 1, M of the N analog signals are current signals, and (NM) analog signals are voltage signals, where M is a natural number less than or equal to N.

4. An indicator circuit, comprising: The multi-channel sampling circuit as described in claims 1-3; as well as The data processing circuit receives the digital output signal from the analog-to-digital converter circuit and generates an indication signal based on the digital output signal.

5. The indicating circuit as claimed in claim 4, wherein the data processing circuit comprises: The averaging circuit receives the digital output signal from the analog-to-digital converter circuit and generates an average signal. as well as A digital comparator compares a mean signal with a threshold signal and generates an indication signal based on the mean and threshold signals.

6. The indicator circuit as claimed in claim 5, wherein the value of the threshold signal is user-defined.

7. The indicating circuit as claimed in claim 4, wherein the data processing circuit further includes a register for storing the digital output signal output by the analog-to-digital conversion circuit.

8. The indicating circuit of claim 4, wherein the data processing circuit comprises: The first comparator receives a digital output signal and a reference signal, and compares the digital output signal and the reference signal to generate a comparison signal; A counter receives a comparison signal and generates a counting signal based on the comparison signal. The count signal increments when the received digital output signal is greater than a reference signal, and decrements when the digital output signal is less than the reference signal. The second comparator receives the count signal and the base signal, and compares the count signal and the base signal to generate an indication signal.

9. The indicating circuit as claimed in claim 8, wherein the values ​​of the reference signal and the base signal are user-defined.

10. A multi-channel sampling circuit for a switching power supply, the switching power supply having an input terminal, the multi-channel sampling circuit comprising: N sampling circuits are used to detect N signals of the switching power supply and provide N analog signals, wherein at least one analog signal represents the current flowing through the input terminal; The level setting output circuit receives N analog signals and a setting signal, sets the N analog signals to the first level and the second level respectively according to the setting signal, and selectively outputs the N analog signals. The analog signal representing the current flowing through the input terminal is set to the first level, and the output frequency of the analog signal set to the first level is greater than the output frequency of the analog signal set to the second level. as well as An analog-to-digital converter circuit converts a received analog signal into a digital output signal.

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