Synaptic transistor and method of manufacturing the same

Abstract

The application belongs to the technical field of transistors, and particularly relates to a synapse transistor and a preparation method thereof. The synapse transistor provided by the application comprises a gate electrode, a square contact end of the gate electrode is covered with a piezoelectric layer, and a synapse post current IDS is generated under the action of pressure. The piezoelectric layer acts on different positions of the gate electrode, and different post currents are generated, so that the detection of the pressure position is realized, and the simulation of the touch is realized. The setting of the gel electrolyte can realize the simulation of the touch. The synapse transistor provided by the application can simulate the human perception system, realize the common perception of two different types of stimulation signals of the touch and the smell, improve the perception accuracy of the synapse transistor, and enhance the judgment accuracy of the external information.

Description

Technical Field

[0001] This invention belongs to the field of transistor technology, specifically relating to a synaptic transistor and its fabrication method. Background Technology

[0002] For biological sensory systems, each sense provides a unique piece of information. For example, force is a tactile experience, and light is a visual experience. Although force and other stimuli such as light are information of different attributes, cells in the hypothalamus combine information from different sensory channels and integrate this information, making the sum of multiple sensory inputs more useful than information obtained from a single channel.

[0003] However, current sensors (including mechanical sensors and optical sensors) and artificial synaptic devices (including synaptic transistors and memristors) are simple in structure and have limited functionality, which restricts the accuracy of sensing devices in judging the surrounding environment. Summary of the Invention

[0004] The purpose of this invention is to provide a synaptic transistor and its fabrication method. The synaptic transistor provided by this invention can achieve the simultaneous perception of two different types of stimulus signals, namely touch and smell, thereby improving the perception accuracy and enhancing the accuracy of judging external information.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] The present invention provides a synaptic transistor, comprising a substrate 1 and a source electrode 2, a drain electrode 3, a first gate electrode 4, a second gate electrode 5 and a third gate electrode 6 disposed on the surface of the substrate 1;

[0007] The source electrode 2, drain electrode 3, first gate electrode 4, second gate electrode 5, and third gate electrode 6 each include a linear end and a square contact end;

[0008] The linear ends of the source electrode 2, drain electrode 3, first gate electrode, second gate electrode 5, and third gate electrode 6 are parallel to each other;

[0009] An active layer 7 is provided on the linear end region of the source electrode 2 and the linear end region of the drain electrode 3.

[0010] An insulating layer 8 is provided on the remaining region of the linear end of the source electrode 2, the remaining region of the linear end of the drain electrode 3, the end region of the linear end of the first gate electrode 4, the end region of the linear end of the second gate electrode 5, and the end region of the linear end of the third gate electrode 6.

[0011] A gel electrolyte layer 9 is disposed on the remaining region of the linear end of the first gate electrode 4, the remaining region of the linear end of the second gate electrode 5, the remaining region of the linear end of the third gate electrode 6, and the active layer 7.

[0012] A first piezoelectric layer 10, a second piezoelectric layer 11, and a third piezoelectric layer 12 are respectively disposed on the square contact end of the first gate electrode 4, the square contact end of the second gate electrode 5, and the square contact end of the third gate electrode 6.

[0013] Preferably, the source electrode 2, drain electrode 3, first gate electrode 4, second gate electrode 5 and third gate electrode 6 each include a first electrode layer and a second electrode layer stacked sequentially.

[0014] The material of the first electrode layer includes one or more of molybdenum, aluminum, and titanium;

[0015] The material of the second electrode layer includes indium tin oxide.

[0016] Preferably, the thickness of the source electrode 2, drain electrode 3, first gate electrode 4, second gate electrode 5 and third gate electrode 6 is 200 nm.

[0017] Preferably, the active layer 7 is made of one or more of ZnO, InZnO, and InGaZnO;

[0018] The active layer 7 has a thickness of 60 nm.

[0019] Preferably, the material of the gel electrolyte layer 9 includes polyvinyl alcohol hydrogel; the thickness of the gel electrolyte layer 9 is 500 μm.

[0020] Preferably, the method for preparing the polyvinyl alcohol hydrogel includes the following steps:

[0021] Polyvinyl alcohol, glycerol, calcium chloride and water were mixed and then freeze-dried to obtain the polyvinyl alcohol hydrogel.

[0022] Preferably, the material of the insulating layer 8 includes silicon nitride and / or silicon oxide;

[0023] The thickness of the insulating layer 8 is 200 nm.

[0024] Preferably, the first piezoelectric layer 10, the second piezoelectric layer 11, and the third piezoelectric layer 12 each include a PVDF-TrFE piezoelectric film disposed on a square contact end and an electrode layer disposed on the PVDF-TrFE piezoelectric film.

[0025] Preferably, the thickness of the PVDF-TrFE piezoelectric film is 100 μm; the thickness of the electrode layer is 150 nm.

[0026] The present invention also provides a method for fabricating the synaptic transistor described in the above technical solution, comprising the following steps:

[0027] Source electrode 2, drain electrode 3, first gate electrode 4, second gate electrode 5 and third gate electrode 6 are fabricated on the substrate surface;

[0028] An active layer 7 is prepared on the linear end region of the source electrode 2 and the linear end region of the drain electrode 3.

[0029] A gel electrolyte layer 9 is prepared on the linear end region of the first gate electrode 4, the linear end region of the second gate electrode 5, the linear end region of the third gate electrode 6, and the active layer 7.

[0030] An insulating layer 8 is prepared on the remaining linear end regions of the source electrode 2, drain electrode 3, first gate electrode 4, second gate electrode 5, and third gate electrode 6;

[0031] A first piezoelectric layer 10, a second piezoelectric layer 11, and a third piezoelectric layer 12 are respectively fabricated on the square contact ends of the first gate electrode 4, the second gate electrode 5, and the third gate electrode 6 to obtain the synaptic transistor.

[0032] This invention provides a synaptic transistor, comprising a substrate 1 and a source electrode 2, a drain electrode 3, a first gate electrode 4, a second gate electrode 5, and a third gate electrode 6 on the surface of the substrate 1; each of the source electrode 2, drain electrode 3, first gate electrode 4, second gate electrode 5, and third gate electrode 6 includes a linear end and a square contact end; the linear ends of the source electrode 2, drain electrode 3, first gate electrode 4, second gate electrode 5, and third gate electrode 6 are parallel to each other; an active layer 7 is disposed on the end regions of the linear ends of the source electrode 2 and the drain electrode 3; the remaining regions of the linear ends of the source electrode 2 and the drain electrode 3... An insulating layer 8 is disposed on the remaining region of the linear end of the first gate electrode 4, the end region of the linear end of the second gate electrode 5, and the end region of the linear end of the third gate electrode 6; a gel electrolyte layer 9 is disposed on the remaining region of the linear end of the first gate electrode 4, the remaining region of the linear end of the second gate electrode 5, the remaining region of the linear end of the third gate electrode 6, and the active layer 7; a first piezoelectric layer 10, a second piezoelectric layer 11, and a third piezoelectric layer 12 are respectively disposed on the square contact end of the first gate electrode 4, the square contact end of the second gate electrode 5, and the square contact end of the third gate electrode 6. The synaptic transistor provided by the present invention can realize the simultaneous perception of two different types of stimulation signals, namely tactile and olfactory, thereby improving the perception accuracy of the synaptic transistor and enhancing the accuracy of judging external information. Attached Figure Description

[0033] Figure 1A schematic diagram of the structure of the synaptic transistor provided by the present invention, wherein 1-substrate, 2-source electrode, 3-drain electrode, 4-first gate electrode, 5-second gate electrode, 6-third gate electrode, 7-active layer, 8-insulating layer, 9-gel electrolyte layer, 10-first piezoelectric layer, 11-second piezoelectric layer, 12-third piezoelectric layer;

[0034] Figure 2 The diagram shows a cross-sectional view of the gel electrolyte layer, where 2 is the source electrode, 3 is the drain electrode, 4 is the first gate electrode, 5 is the second gate electrode, 6 is the third gate electrode, 7 is the active layer, and 9 is the gel electrolyte layer.

[0035] Figure 3 This is a comparison diagram of the changes in ions in the gel electrolyte layer before and after the interaction of the synaptic transistor and gas obtained in this invention, where a-before the interaction and b-after the interaction.

[0036] Figure 4 The transfer curve of the synaptic transistor obtained in Example 1 is shown.

[0037] Figure 5 This is a graph showing the change in current of the synaptic transistor obtained in Example 1 under different pulse widths;

[0038] Figure 6 This is a graph showing the change in current of the synaptic transistor obtained in Example 1 at different pressing positions;

[0039] Figure 7 The graph shows the current changes of the synaptic transistor obtained in Example 1 when no gas is introduced, gas is introduced, and gas is removed. Detailed Implementation

[0040] The present invention provides a synaptic transistor, including a substrate 1 and a source electrode 2, a drain electrode 3, a first gate electrode 4, a second gate electrode 5 and a third gate electrode 6 disposed on the surface of the substrate 1;

[0041] The source electrode 2, drain electrode 3, first gate electrode 4, second gate electrode 5, and third gate electrode 6 each include a linear end and a square contact end;

[0042] The linear ends of the source electrode 2, drain electrode 3, first gate electrode, second gate electrode 5, and third gate electrode 6 are parallel to each other;

[0043] An active layer 7 is provided on the linear end region of the source electrode 2 and the linear end region of the drain electrode 3.

[0044] An insulating layer 8 is provided on the remaining region of the linear end of the source electrode 2, the remaining region of the linear end of the drain electrode 3, the end region of the linear end of the first gate electrode 4, the end region of the linear end of the second gate electrode 5, and the end region of the linear end of the third gate electrode 6.

[0045] A gel electrolyte layer 9 is disposed on the remaining region of the linear end of the first gate electrode 4, the remaining region of the linear end of the second gate electrode 5, the remaining region of the linear end of the third gate electrode 6, and the active layer 7.

[0046] A first piezoelectric layer 10, a second piezoelectric layer 11, and a third piezoelectric layer 12 are respectively disposed on the square contact end of the first gate electrode 4, the square contact end of the second gate electrode 5, and the square contact end of the third gate electrode 6.

[0047] In this invention, the source electrode 2, drain electrode 3, first gate electrode 4, second gate electrode 5, and third gate electrode 6 preferably each comprise a first electrode layer and a second electrode layer stacked sequentially. In this invention, the material of the first electrode layer preferably includes one or more of molybdenum, aluminum, and titanium; the thickness of the first electrode layer is preferably 150 nm. In this invention, the material of the second electrode layer preferably includes indium tin oxide; the thickness of the second electrode layer is preferably 50 nm. In this invention, the thickness of the source electrode 2, drain electrode 3, first gate electrode 4, second gate electrode 5, and third gate electrode 6 is independently 200 nm.

[0048] In this invention, the material of the active layer 7 preferably includes one or more of ZnO, InZnO, and InGaZnO. In this invention, the thickness of the active layer 7 is preferably 60 nm.

[0049] In this invention, the material of the gel electrolyte layer 9 preferably includes polyvinyl alcohol hydrogel.

[0050] In this invention, the preparation method of the polyvinyl alcohol hydrogel preferably includes the following steps:

[0051] Polyvinyl alcohol, glycerol, calcium chloride and water were mixed and then freeze-dried to obtain the polyvinyl alcohol hydrogel.

[0052] In this invention, the preferred mass ratio of polyvinyl alcohol, glycerol, and water is 2:4:6. In this invention, the preferred mass ratio of calcium chloride and polyvinyl alcohol is 1:20.

[0053] In this invention, the mixing temperature is preferably 80°C. In this invention, the mixing is preferably carried out under stirring conditions. This invention does not impose any special limitations on the stirring conditions; those well-known to those skilled in the art can be used. In this invention, the freeze-drying temperature is preferably -20°C. In this invention, the freeze-drying process is preferably performed three times.

[0054] In this invention, the thickness of the gel electrolyte layer 9 is preferably 500 μm.

[0055] In this invention, the material of the insulating layer 8 preferably includes silicon nitride and / or silicon oxide. In this invention, the thickness of the insulating layer 8 is preferably 200 nm.

[0056] In this invention, the first piezoelectric layer 10, the second piezoelectric layer 11, and the third piezoelectric layer 12 independently include a PVDF-TrFE piezoelectric film disposed on a square contact end and an electrode layer disposed on the PVDF-TrFE piezoelectric film. In this invention, the material of the electrode layer preferably includes one or more of molybdenum, aluminum, and titanium. In this invention, the thickness of the PVDF-TrFE piezoelectric film is preferably 100 μm; the thickness of the electrode layer is preferably 150 nm. In this invention, the side of the PVDF-TrFE piezoelectric film without the electrode layer is in contact with the square contact end.

[0057] In this invention, the first piezoelectric layer 10, the second piezoelectric layer 11, and the third piezoelectric layer 12 are preferably obtained by fabrication; the fabrication method preferably includes the following steps:

[0058] PVDF, N,N-dimethylformamide and acetone were mixed, and the resulting mixture was electrospun to obtain a PVDF-TrFE piezoelectric film.

[0059] An electrode layer is prepared on one side of the PVDF-TrFE piezoelectric film to obtain the piezoelectric layer.

[0060] In this invention, the preferred mass ratio of N,N-dimethylformamide to acetone is 1.83:1. In this invention, the preferred mass concentration of PVDF in the resulting mixture is 18 wt%.

[0061] In this invention, the mixing temperature is preferably 60°C, and the mixing time is preferably 2 hours. The mixing is preferably carried out under stirring conditions. This invention does not have a specific limitation on the stirring speed, as long as it is sufficient to completely dissolve the PVDF.

[0062] In this invention, the preferred parameters for electrospinning include: a spinning voltage of 20kV, a needle of 26G, a liquid dispensing rate of 0.5mL / h, a collection time of 2.5h, a round trip distance of 6cm, and a spinning distance of 7cm.

[0063] In this invention, the electrode layer is preferably prepared by sputtering. The sputtering process is not particularly limited in this invention; any process well-known to those skilled in the art can be used.

[0064] In this invention, the substrate 1 preferably comprises a glass substrate or a polyimide substrate.

[0065] In this invention, the polyimide substrate is preferably obtained by preparation, and the preparation method preferably includes the following steps:

[0066] A polyimide solution is spin-coated onto a glass substrate, followed by annealing to obtain a polyimide film.

[0067] A silicon nitride and silicon dioxide buffer layer is prepared on the polyimide film to obtain the polyimide substrate.

[0068] The present invention does not impose any particular limitation on the concentration of the polyimide solution; any method well-known to those skilled in the art can be used. The present invention also does not impose any particular limitation on the spin-coating process; any method well-known to those skilled in the art can be used. In the present invention, the annealing temperature is preferably 430°C, and the annealing time is preferably 3 hours. In the present invention, the thickness of the polyimide film is preferably 10 μm.

[0069] In this invention, the silicon nitride and silicon dioxide buffer layers are preferably prepared by plasma-enhanced chemical vapor deposition (PECVD). This invention does not impose any particular limitation on the PECVD process; any process well-known to those skilled in the art can be used. In this invention, the thickness of the silicon nitride and silicon dioxide buffer layers is preferably 350 nm.

[0070] The present invention also provides a method for fabricating the synaptic transistor described in the above technical solution, comprising the following steps:

[0071] Source electrode 2, drain electrode 3, first gate electrode 4, second gate electrode 5 and third gate electrode 6 are fabricated on the substrate surface;

[0072] An active layer 7 is prepared on the linear end region of the source electrode 2 and the linear end region of the drain electrode 3.

[0073] An insulating layer 8 is prepared on the remaining region of the linear end of the source electrode 2, the remaining region of the linear end of the drain electrode 3, the end region of the linear end of the first gate electrode 4, the end region of the linear end of the second gate electrode 5, and the end region of the linear end of the third gate electrode 6.

[0074] A gel electrolyte layer 9 is prepared on the remaining region of the linear end of the first gate electrode 4, the remaining region of the linear end of the second gate electrode 5, the remaining region of the linear end of the third gate electrode 6, and the active layer 7.

[0075] A first piezoelectric layer 10, a second piezoelectric layer 11, and a third piezoelectric layer 12 are respectively fabricated on the square contact ends of the first gate electrode 4, the second gate electrode 5, and the third gate electrode 6 to obtain the synaptic transistor.

[0076] The present invention prepares a source electrode 2, a drain electrode 3, a first gate electrode 4, a second gate electrode 5 and a third gate electrode 6 on the surface of a substrate.

[0077] In this invention, the fabrication of the source electrode 2, drain electrode 3, first gate electrode 4, second gate electrode 5, and third gate electrode 6 preferably includes the following steps:

[0078] A first electrode layer and a second electrode layer are sequentially prepared on the surface of the substrate 1 by magnetron sputtering.

[0079] A mask is placed on the surface of the second electrode layer, and wet etching is performed to obtain the source electrode 2, drain electrode 3, first gate electrode 4, second gate electrode 5 and third gate electrode 6.

[0080] The present invention does not impose any special limitations on the magnetron sputtering and wet etching processes, and any processes well known to those skilled in the art can be used.

[0081] In this invention, an active layer 7 is prepared on the linear end region of the source electrode 2 and the linear end region of the drain electrode 3.

[0082] In this invention, the preparation of the active layer 7 preferably includes the following steps:

[0083] Semiconductor layers are fabricated on the surfaces of the source electrode 2, drain electrode 3, first gate electrode 4, second gate electrode 5, and third gate electrode 6 by magnetron sputtering.

[0084] A mask is placed on the surface of the semiconductor layer, and the active layer 7 is obtained by wet etching.

[0085] In this invention, the material of the semiconductor layer is preferably the same as the material of the active layer 7 defined in the above technical solution, and will not be described again here.

[0086] The present invention does not impose any special limitations on the magnetron sputtering and wet etching processes, and any processes well known to those skilled in the art can be used.

[0087] In this invention, an insulating layer 8 is prepared on the remaining region of the linear end of the source electrode 2, the remaining region of the linear end of the drain electrode 3, the end region of the linear end of the first gate electrode 4, the end region of the linear end of the second gate electrode 5, and the end region of the linear end of the third gate electrode 6.

[0088] In this invention, the preparation of the insulating layer 8 preferably includes the following steps:

[0089] A protective layer is prepared on the surface of the source electrode 2, drain electrode 3, active layer 7, first gate electrode 4, second gate electrode 5 and third gate electrode 6 by plasma-enhanced chemical vapor deposition.

[0090] A mask plate is placed on the surface of the protective layer, and the insulating layer 8 is obtained by dry etching through holes.

[0091] In this invention, the material of the protective layer is the same as the material of the insulating layer 8 defined in the above technical solution, and will not be described again here.

[0092] The present invention does not impose any special limitations on the plasma-enhanced chemical vapor deposition and dry etching process, and any process known to those skilled in the art can be used.

[0093] The present invention prepares a gel electrolyte layer 9 on the remaining region of the linear end of the first gate electrode 4, the remaining region of the linear end of the second gate electrode 5, the remaining region of the linear end of the third gate electrode 6, and the active layer 7.

[0094] The present invention does not impose any special limitations on the preparation process of the gel electrolyte layer 9; the material of the gel electrolyte layer 9 can be directly applied for covering.

[0095] The present invention prepares a first piezoelectric layer 10, a second piezoelectric layer 11, and a third piezoelectric layer 12 on the square contact ends of the first gate electrode 4, the second gate electrode 5, and the third gate electrode 6, respectively, to obtain the synaptic transistor.

[0096] The present invention does not have any special limitations on the preparation process of the first piezoelectric layer 10, the second piezoelectric layer 11 and the third piezoelectric layer 12. The materials of the first piezoelectric layer 10, the second piezoelectric layer 11 and the third piezoelectric layer 12 can be directly attached.

[0097] During use, the synaptic transistor obtained by this invention applies a fixed bias voltage to the source electrode 2 and the drain electrode 3. When either piezoelectric layer is subjected to external pressure, a pulse voltage is generated on the corresponding gate electrode, causing ions in the gel electrolyte layer 9 to move and forming an electric double layer at the interface between the gate electrode and the active layer 7. This results in the electron configuration in the active layer 7 forming a conductive channel. Under the action of the bias voltage, a current I is generated at the source electrode 2 and the drain electrode 3. DS Using current I DS The change in pressure signal is converted into an electrical signal; simultaneously, because ions move slowly, the conductive channels formed in the active layer 7 do not immediately disappear after the pressure is removed, and the generated current I... DS It will not disappear immediately either, thus utilizing the subsequent current I DS This enables the learning and memorization of pressure. Furthermore, due to the presence of three gate electrodes, each with a different distance from the active layer 7, when the piezoelectric layer acts on different gate electrodes, the difference in the double electric layers results in different conductive channels, thereby inducing a post-current I in the synaptic transistor. DSThey are different. Therefore, by pressing the corresponding gate electrode with different piezoelectric layers, the sense of touch can be simulated, and intelligent sensing of the pressing position can be achieved.

[0098] During use, the synaptic transistor obtained by this invention applies a fixed bias voltage to the source electrode 2 and drain electrode 3, and a fixed pulse voltage to the three gate electrodes. When external NO2 or ammonia gas comes into contact with the gel electrolyte layer 9 of the synaptic transistor, the number of mobile ions in the gel electrolyte layer 9 decreases (e.g., Figure 3 As shown in the figure (where a represents before the action and b represents after the action), this alters the double-layer effect formed at the interface between the gate electrode and the active layer 7, leading to a change in the conductive channel. Therefore, under the same pulse voltage and different gas concentrations, the change in the conductive channel results in a post-current I generated at the source electrode 2 and the drain electrode 3. DS Changes occur; using I DS The change in gas concentration signal is converted into an electrical signal; simultaneously, because ions move slowly, the conductive channels formed in the active layer 7 do not immediately disappear after the gas stimulus is removed. Therefore, the generated I DS The current will not disappear immediately either, thus utilizing the subsequent current I DS To achieve simulated olfactory learning and memory.

[0099] To further illustrate the present invention, a synaptic transistor and its fabrication method provided by the present invention will be described in detail below with reference to the accompanying drawings and embodiments, but these should not be construed as limiting the scope of protection of the present invention.

[0100] Example 1

[0101] A polyimide solution was spin-coated onto a glass substrate and annealed at 430°C to obtain a polyimide film. A silicon nitride and silicon dioxide buffer layer was prepared on the surface of the polyimide film by plasma-enhanced chemical vapor deposition to obtain a polyimide substrate (where the thickness of the buffer layer is 350 nm and the thickness of the polyimide film is 10 μm).

[0102] A 150 nm thick molybdenum metal layer and a 50 nm thick indium tin oxide layer are sequentially sputtered onto the surface of a polyimide substrate using magnetron sputtering. A mask is placed on the surface of the indium tin oxide layer, and wet etching is performed to obtain a source electrode 2, a drain electrode 3, a first gate electrode 4, a second gate electrode 5, and a third gate electrode 6. Each of the source electrode 2, drain electrode 3, first gate electrode 4, second gate electrode 5, and third gate electrode 6 includes a linear end and a square contact end.

[0103] A 60 nm thick InGaZnO semiconductor layer is sputtered on the surfaces of the source electrode 2, drain electrode 3, first gate electrode 4, second gate electrode 5 and third gate electrode 6 using magnetron sputtering; a mask is placed on the surface of the InGaZnO semiconductor layer, and the active layer 7 is obtained by wet etching.

[0104] A SiO2 layer is deposited on the surfaces of the source electrode 2, drain electrode 3, active layer 7, first gate electrode 4, second gate electrode 5, and third gate electrode 6 using plasma-enhanced chemical vapor deposition. A mask is placed on the surface of the SiO2 layer, and the insulating layer 8 is obtained by dry etching through holes.

[0105] 2g of polyvinyl alcohol, 4g of glycerol, 0.1g of calcium chloride, and 6g of water were mixed at 80°C and magnetically stirred until homogeneous. The resulting solution was then freeze-dried three times at -20°C to obtain a polyvinyl alcohol hydrogel. The polyvinyl alcohol hydrogel was then applied to the linear end regions of the first gate electrode 4, the second gate electrode 5, the third gate electrode 6, and the active layer 7 to obtain a gel electrolyte layer 9. A schematic diagram of the cross-section of the gel electrolyte layer 9 is shown below. Figure 2 As shown;

[0106] PVDF, N,N-dimethylformamide, and acetone were mixed (PVDF concentration was 18 wt%, and the mass ratio of N,N-dimethylformamide to acetone was 1.83:1). The mixture was magnetically stirred at 60°C for 2 h. The resulting mixture was then electrospun (parameters: spinning voltage 20 kV, needle size 26 G, feed rate 0.5 mL / h, collection time 2.5 h, round trip distance 6 cm, spinning distance 7 cm) to obtain a PVDF-TrFE piezoelectric film. A 150 nm thick Mo electrode layer was sputtered onto one side of the PVDF-TrFE piezoelectric film to obtain the piezoelectric layer material.

[0107] The piezoelectric layer material is attached to the square contact ends of the first gate electrode 4, the second gate electrode 5, and the third gate electrode 6, respectively, to obtain the synaptic transistor.

[0108] Performance testing

[0109] Test Example 1

[0110] The synaptic transistor obtained in Example 1 was subjected to transfer curve testing. The testing method was based on the gate voltage V. GS Scan from -2V to 2V, then from 2V to -2V, V DS With a bias voltage of 0.1V, the test results are as follows: Figure 4 As shown, from Figure 4 A clear hysteresis curve can be observed.

[0111] Test Example 2

[0112] The postsynaptic current of the synaptic transistor obtained in Example 1 was tested using the following method: V DS With a fixed bias voltage of 0.1V, pulse voltages with a fixed amplitude of 1V and different pulse widths are applied at the gate. The test results are as follows. Figure 5 As shown, from Figure 5 It can be seen that the synaptic transistor has good performance response.

[0113] Test Example 3

[0114] The synaptic transistor obtained in Example 1 was tested for spatial location recognition. The test method was V. DS With a fixed bias voltage of 0.1V, the piezoelectric layer in contact with different gate electrodes was pressed three times consecutively (1-1-1 (three consecutive presses of the piezoelectric layer in contact with the first gate electrode), 2-2-2 (three consecutive presses of the piezoelectric layer in contact with the second gate electrode), 3-3-3 (three consecutive presses of the piezoelectric layer in contact with the third gate electrode)). The resulting postsynaptic current change curves are shown below. Figure 6 As shown, from Figure 6 It can be seen that the synaptic transistor provided by the present invention can identify spatial location by the difference in subsequent current.

[0115] Test Example 4

[0116] The synaptic transistor obtained in Example 1 was tested for olfactory detection. The test method was V. DS With a fixed bias voltage of 0.1V and controlled gas flow, the current change curve after the surge was tested, and the test results are as follows. Figure 7 As shown, from Figure 7 It can be seen that synaptic transistors can identify gases by the difference in post-current.

[0117] Although the above embodiments have provided a detailed description of the present invention, they are only some embodiments of the present invention, and not all embodiments. Other embodiments can be obtained based on these embodiments without creative effort, and these embodiments all fall within the protection scope of the present invention.

Claims

1. A synaptic transistor, characterized in that, It includes a substrate (1) and a source electrode (2), a drain electrode (3), a first gate electrode (4), a second gate electrode (5) and a third gate electrode (6) disposed on the surface of the substrate (1); The source electrode (2), drain electrode (3), first gate electrode (4), second gate electrode (5) and third gate electrode (6) all include a linear end and a square contact end; The linear ends of the source electrode (2), drain electrode (3), first gate electrode (4), second gate electrode (5) and third gate electrode (6) are parallel to each other; An active layer (7) is provided on the end region of the linear end of the source electrode (2) and the end region of the linear end of the drain electrode (3); An insulating layer (8) is provided on the remaining region of the linear end of the source electrode (2), the remaining region of the linear end of the drain electrode (3), a portion of the linear end of the first gate electrode (4), a portion of the linear end of the second gate electrode (5), and a portion of the linear end of the third gate electrode (6). A gel electrolyte layer (9) is provided on the remaining region of the linear end of the first gate electrode (4), the remaining region of the linear end of the second gate electrode (5), the remaining region of the linear end of the third gate electrode (6), and the active layer (7). A first piezoelectric layer (10), a second piezoelectric layer (11), and a third piezoelectric layer (12) are respectively provided on the square contact end of the first gate electrode (4), the square contact end of the second gate electrode (5), and the square contact end of the third gate electrode (6).

2. The synaptic transistor according to claim 1, characterized in that, The source electrode (2), drain electrode (3), first gate electrode (4), second gate electrode (5) and third gate electrode (6) each independently include a first electrode layer and a second electrode layer stacked sequentially. The material of the first electrode layer includes one or more of molybdenum, aluminum, and titanium; The material of the second electrode layer includes indium tin oxide.

3. The synaptic transistor according to claim 1 or 2, characterized in that, The thickness of the source electrode (2), drain electrode (3), first gate electrode (4), second gate electrode (5) and third gate electrode (6) is 200 nm.

4. The synaptic transistor according to claim 1, characterized in that, The active layer (7) is made of one or more of ZnO, InZnO and InGaZnO; The active layer (7) has a thickness of 60 nm.

5. The synaptic transistor according to claim 1, characterized in that, The material of the gel electrolyte layer (9) includes polyvinyl alcohol hydrogel; the thickness of the gel electrolyte layer (9) is 500 μm.

6. The synaptic transistor according to claim 5, characterized in that, The preparation method of the polyvinyl alcohol hydrogel includes the following steps: Polyvinyl alcohol, glycerol, calcium chloride and water were mixed and then freeze-dried to obtain the polyvinyl alcohol hydrogel.

7. The synaptic transistor according to claim 1, characterized in that, The material of the insulating layer (8) includes silicon nitride and / or silicon oxide; The thickness of the insulating layer (8) is 200 nm.

8. The synaptic transistor according to claim 1, characterized in that, The first piezoelectric layer (10), the second piezoelectric layer (11), and the third piezoelectric layer (12) each independently include a PVDF-TrFE piezoelectric film disposed on a square contact end and an electrode layer disposed on the PVDF-TrFE piezoelectric film.

9. The synaptic transistor according to claim 8, characterized in that, The thickness of the PVDF-TrFE piezoelectric film is 100 μm; the thickness of the electrode layer is 150 nm.

10. A method for fabricating a synaptic transistor according to any one of claims 1 to 9, characterized in that, Includes the following steps: A source electrode (2), a drain electrode (3), a first gate electrode (4), a second gate electrode (5), and a third gate electrode (6) are fabricated on the substrate surface; An active layer (7) is prepared on the linear end region of the source electrode (2) and the linear end region of the drain electrode (3); An insulating layer (8) is prepared on the remaining region of the linear end of the source electrode (2), the remaining region of the linear end of the drain electrode (3), the end region of the linear end of the first gate electrode (4), the end region of the linear end of the second gate electrode (5), and the end region of the linear end of the third gate electrode (6). A gel electrolyte layer (9) is prepared on the remaining region of the linear end of the first gate electrode (4), the remaining region of the linear end of the second gate electrode (5), the remaining region of the linear end of the third gate electrode (6), and the active layer (7). A first piezoelectric layer (10), a second piezoelectric layer (11), and a third piezoelectric layer (12) are respectively fabricated on the square contact end of the first gate electrode (4), the square contact end of the second gate electrode (5), and the square contact end of the third gate electrode (6) to obtain the synaptic transistor.

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