Semiconductor devices

Abstract

In a semiconductor device with a trench gate structure having dual gates, a first impurity region (13) extends from the cell portion (1) to the outer periphery portion (2). In the interlayer insulating film (21), a second contact hole (21b) is formed in the portion of the outer periphery portion (2) that is one direction away from the cell portion (1), exposing the first impurity region (13). Furthermore, a first electrode (22) is electrically connected to the first impurity region (13) in the outer periphery portion (2) via the second contact hole (21b).

Description

[0001] Cross-referencing of related applications

[0002] This application is based on Japanese Patent Application No. 2020-142628, filed on August 26, 2020, the contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor device having a trench gate configuration with dual gates. Background Technology

[0004] Previously, techniques have been proposed for semiconductor devices having a cell portion and an outer peripheral portion, and forming a trench gate structure with dual gates in the cell portion (see, for example, Patent Document 1). Specifically, such a semiconductor device utilizes n + An n-type drain layer is formed on top of the drain layer. - The device is constructed using a semiconductor substrate with a drift layer. A body region and a source region are formed on the surface of the semiconductor substrate. Furthermore, a trench gate structure is formed in the semiconductor substrate such that the body region and the source region are connected to reach the drift layer. This trench gate structure in the semiconductor device has dual gates. A shielding electrode, set to the source potential, is disposed at the bottom side of the gate trench, separated by a shielding insulating film, and a gate electrode is disposed at the opening side of the gate trench, separated by a gate insulating film. This reduces the parasitic capacitance generated between the gate electrode and the drain electrode. Additionally, an intermediate insulating film is formed between the shielding electrode and the gate electrode.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2014-197702 Summary of the Invention

[0008] Furthermore, under the current circumstances, it is desirable to improve the withstand voltage of semiconductor devices with a trench gate structure having dual gates as described above.

[0009] The purpose of this disclosure is to provide a semiconductor device that can improve voltage withstand capability.

[0010] According to one aspect of this disclosure, a semiconductor device having a semiconductor element with a trench gate structure having dual gates includes a unit portion having a semiconductor element and an outer peripheral portion surrounding the unit portion. The unit portion has a drift layer of a first conductivity type, a first impurity region of a second conductivity type formed on the drift layer, a surface portion of the first impurity region formed in the first impurity region having a second impurity region of the first conductivity type with a higher impurity concentration than the drift layer, and a trench gate structure having a shielding electrode, an intermediate insulating film, and a gate electrode sequentially stacked in a strip-shaped arrangement of multiple gate trenches arranged in a length direction and penetrating from the second impurity region to the drift layer, thereby forming a dual gate structure. In a semiconductor device, a high-concentration layer of a first conductivity type or a second conductivity type is disposed on the opposite side of the first impurity region and has a higher impurity concentration than the drift layer; an interlayer insulating film disposed on the trench gate structure and the first and second impurity regions and having a first contact hole formed thereon connected to the first and second impurity regions; a first electrode electrically connected to the second and first impurity regions via the first contact hole; and a second electrode electrically connected to the high-concentration layer. In the semiconductor device, the first impurity region extends from the cell portion to the outer periphery. In the interlayer insulating film, a second contact hole is formed in the portion of the outer periphery that is one direction away from the cell portion, exposing the first impurity region. The first electrode is electrically connected to the first impurity region in the outer periphery via the second contact hole.

[0011] Therefore, the first impurity region extends to the outer periphery, where the first electrode is electrically connected to the first impurity region. Thus, when the semiconductor device undergoes avalanche operation, charge carriers (e.g., holes) are easily extracted from the first electrode connected to the first impurity region in the outer periphery. Consequently, the operation of parasitic bipolar transistors formed within the semiconductor device can be suppressed, improving avalanche tolerance and thereby increasing the breakdown voltage of the semiconductor device.

[0012] In addition, the parenthesized reference numerals attached to each constituent element indicate an example of the correspondence between that constituent element and the specific constituent element described in the embodiments described later. Attached Figure Description

[0013] Figure 1 This is a schematic diagram showing the overall structure of the semiconductor device according to the first embodiment.

[0014] Figure 2 This is a layout diagram of the upper surface of the semiconductor device according to the first embodiment.

[0015] Figure 3 It is along Figure 2 A cross-sectional view of line III-III in the diagram.

[0016] Figure 4It is along Figure 2 A cross-sectional view of line IV-IV in the image.

[0017] Figure 5 It is along Figure 2 A cross-sectional view of the V-V line in the diagram.

[0018] Figure 6 It is along Figure 2 A cross-sectional view of line VI-VI in the diagram.

[0019] Figure 7 This is a three-dimensional schematic diagram of the semiconductor device according to the first embodiment.

[0020] Figure 8 This is a schematic diagram showing the current path when a semiconductor device is in the on state. Detailed Implementation

[0021] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. Furthermore, in the following embodiments, the same or equivalent parts will be described using the same reference numerals.

[0022] (First Embodiment)

[0023] The first embodiment will be described with reference to the accompanying drawings. The first embodiment will be described as follows. In this embodiment, a semiconductor device having an n-channel vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with a trench gate structure having dual gates will be described as an example.

[0024] First, the semiconductor device of this embodiment, such as Figure 1 As shown, the device includes a cell portion 1 having a main cell region Rm that serves as a main cell and a sensing cell region Rs that serves as a sensing cell, as well as an outer peripheral portion 2. The main cell region Rm and the sensing cell region Rs are equipped with MOSFETs of the same structure, and the regions are separated by element separation.

[0025] Furthermore, the area ratio of the main cell region Rm and the sensing cell region Rs is adjusted so that the drain current flowing through the main cell region Rm flows through the sensing cell region Rs at a predetermined rate. While not particularly limited, the sensing cell region Rs is set to a size of several hundred to tens of thousands of times that of the main cell region Rm. In the semiconductor device, the main current flowing through the main cell region Rm is detected based on the sensing current flowing through the sensing cell region Rs. Furthermore, the semiconductor device of this embodiment has a source region 14, which will be described in detail later. In this embodiment, the cell portion 1 and the outer peripheral portion 2 are divided according to whether the source region 14 is formed; the portion where the source region 14 is formed is designated as the cell portion 1.

[0026] The following, such as Figures 2-7 As shown, the structure of the semiconductor device is explained with the width direction of the MOSFET as the x-direction and the depth direction of the MOSFET intersecting the x-direction as the y-direction. Furthermore, as described above, the main cell region Rm and the sensing cell region Rs in cell section 1 have the same structure. Therefore, the structure of cell section 1 described below applies to both the main cell region Rm and the sensing cell region Rs.

[0027] like Figures 3-7 As shown, the semiconductor device of this embodiment utilizes n with a high impurity concentration. + The substrate 11 is formed from a semiconductor substrate 10, which is composed of a silicon substrate or the like. On the surface of the substrate 11, an impurity concentration lower than that of the substrate 11 is formed, such as n... - A drift layer 12 of the type. In addition, in this embodiment, the substrate 11 functions as a drain layer, which is equivalent to a high-concentration layer.

[0028] At a desired location on the surface of the drift layer 12, a p-type bulk region 13 with a relatively low impurity concentration is formed. The bulk region 13 is formed, for example, by ion implantation of p-type impurities into the drift layer 12, and also functions as a channel layer forming the channel region. Furthermore, the bulk region 13, as... Figure 2 As shown, multiple trench gate structures described later are formed with the y-direction as the length direction. Furthermore, the volume region 13 is as follows... Figure 2 As shown, it extends from the unit part 1 to the outer periphery part 2. Figure 2 In the diagram, the boundary between the portion forming the volume region 13 and the portion not forming the volume region 13 is represented by a dashed line as the volume region boundary 13a.

[0029] In the surface portion of the bulk region 13, there is an n-type source region 14 with a higher impurity concentration than the drift layer 12. Furthermore, the source region 14... Figure 2 As shown, the trench gate structures described later are formed with the y-direction as the length direction. However, the source region 14 is formed in a manner that terminates within the bulk region 13. Furthermore, in this embodiment, the portion in which the source region 14 is formed is designated as unit portion 1. Figure 2 In this embodiment, the boundary between the portion where the source electrode region 14 is formed and the portion where the source electrode region 14 is not formed is represented as the source electrode region boundary portion 14a. Furthermore, in this embodiment, the body region 13 corresponds to the first impurity region, and the source electrode region 14 corresponds to the second impurity region.

[0030] Furthermore, a plurality of contact trenches 15 are formed in the semiconductor substrate 10, extending from the source region 14 to the body region 13. Consequently, the body region 13 is exposed at the bottom surface of the contact trenches 15. Furthermore, a p-shaped contact portion is formed in the portion of the body region 13 exposed from the bottom surface of the contact trenches 15, serving as a body contact. + The body region of the type uses contact region 13b. In the portion of the source region 14 exposed from the side of the contact trench 15, a source contact portion n is formed. + The source region contact region 14b is of the type. Furthermore, in this embodiment, the source region contact region 14b corresponds to the contact region for the second impurity region.

[0031] Here, contact groove 15, as Figure 2 As shown, the multiple trench gate structures described later are formed with the y-direction as the length direction. Specifically, the contact trenches 15 are formed in the y-direction in a manner that protrudes from the source region 14. That is, the contact trenches 15 are formed from the cell portion 1 to the outer peripheral portion 2. However, the contact trenches 15 are formed in the y-direction in a manner that terminates inside the bulk region 13. Furthermore, the contact trenches 15 are arranged in the x-direction, and are formed between the multiple trench gate structures described later. That is, the contact trenches 15 are arranged in a strip-like layout with equal intervals.

[0032] Furthermore, the source region uses contact region 14b, such as Figure 7 As shown, it is formed around the contact groove 15. Therefore, in this embodiment, the source region contact region 14b protrudes beyond the source region 14 in the y direction. That is, the source region contact region 14b extends to the outer periphery 2.

[0033] Between the body region 13 and the source region 14 in the surface portion of the drift layer 12, a plurality of gate trenches 16 are formed with the y-direction (i.e., one direction) as the length direction and arranged along the x-direction. These gate trenches 16 are trenches used to form a trench gate structure. In this embodiment, the gate trenches 16 are arranged in parallel at equal intervals to form a strip-shaped layout.

[0034] Furthermore, each gate trench 16 extends from the cell portion 1 to the outer peripheral portion 2 in the y-direction. In this embodiment, the gate trench 16 is as follows: Figure 2 As shown, the outer peripheral portion 2 is formed in a manner that protrudes beyond the body region 13. In other words, the body region 13 terminates inside the extension direction of the gate trench 16 in the y-direction.

[0035] The gate trench 16 is formed deeper than the body region 13. That is, the gate trench 16 is configured to penetrate the source region 14 and the body region 13 from one side 10a of the semiconductor substrate 10 to the depth of the drift layer 12. Furthermore, in this embodiment, the gate trench 16 gradually narrows towards the bottom, becoming a rounded shape at the bottom.

[0036] Furthermore, the multiple gate trenches 16 are formed such that the gate trenches 16 at both ends in the x-direction are located in the outer peripheral portion 2. Therefore, the gate trenches 16 at both ends in the x-direction are formed to penetrate the body region 13 and reach the drift layer 12.

[0037] The inner wall surface of the gate trench 16 is covered by an insulating film 17. In this embodiment, the insulating film 17 has a shielding insulating film 17a that covers the lower portion of the gate trench 16 and a gate insulating film 17b that covers the upper portion. Specifically, the shielding insulating film 17a is formed to cover the side surface of the lower portion from the bottom of the gate trench 16. The gate insulating film 17b is formed to cover the side surface of the upper portion of the gate trench 16.

[0038] Here, in this embodiment, as Figures 3-5 As shown, the portion of the gate insulating film 17b formed on the outer periphery 2 is thicker than the portion formed on the cell portion 1. Furthermore, the portion of the gate insulating film 17b formed on the outer periphery 2b is thicker than the portion formed on the inner edge portion 2a of the outer periphery 2. In other words, the gate insulating film 17b becomes thicker in the order of cell portion 1, inner edge portion 2a of the outer periphery 2, and outer edge portion 2b of the outer periphery 2.

[0039] In addition, in this embodiment, such as Figure 2 As shown, when viewed from the normal direction of the surface of the semiconductor substrate 10, in the y-direction, the portion of the outer peripheral portion 2 that is closer to the unit portion 1 than the gate wiring 23 described later is designated as the inner edge portion 2a. Furthermore, when viewed from the normal direction of the surface of the semiconductor substrate 10, in the y-direction, the portion of the outer peripheral portion 2 that is opposite to the unit portion 1 of the gate wiring 23 described later is designated as the outer edge portion 2b. While not particularly limiting, when changing the thickness of the gate insulating film 17b in this way, for example, after forming the insulating film by thermal oxidation, the thickness can be adjusted by further depositing or otherwise configuring the insulating film in the desired thicker portion.

[0040] Within the gate trench 16, a shielding electrode 18 and a gate electrode 19, both made of doped polysilicon (Poly-Si), are stacked and disposed with an insulating film 17 in between. That is, a dual gate is disposed within the gate trench 16.

[0041] As described later, the shielding electrode 18 is fixed at the source potential by being connected to the upper electrode 22. Therefore, the semiconductor device of this embodiment can reduce the gate-drain capacitance and improve the electrical characteristics of the MOSFET. The gate electrode 19 performs the switching operation of the MOSFET, and a channel region is formed in the body region 13 on the side of the gate trench 16 when a gate voltage is applied.

[0042] An intermediate insulating film 20 is formed between the shielding electrode 18 and the gate electrode 19. Thus, the shielding electrode 18 is insulated from the gate electrode 19. Furthermore, the gate trenches 16, the insulating film 17, the shielding electrode 18, the gate electrode 19, and the intermediate insulating film 20 constitute a trench gate structure. Because the gate trenches 16 are formed as described above, this trench gate structure... Figure 2 The y-direction of the plane of the paper is the length direction, and the length direction is the horizontal direction. Figure 2 Multiple strips are arranged in the x-direction along the vertical direction on the paper, thus forming a strip-like layout.

[0043] Furthermore, as described above, an active electrode region 14 is formed on the inner side of the trench gate structure along its length, and this portion constitutes the cell section 1 that functions as a MOSFET. In addition, the front end portion of the trench gate structure, which is located on the outer periphery 2, is located on the outer side of the cell section 1.

[0044] And, as Figure 6 As shown, at the end of the gate trench 16 along its length, the shielding electrode 18 extends outward from the gate electrode 19. Furthermore, these portions are exposed from the surface side of the body region 13 and the source region 14 as a shielding liner 18a. Additionally, at the end of the gate trench 16 along its length, the portion of the shielding electrode 18 extending outward from the gate electrode 19 is also insulated from the front end portion 20a of the intermediate insulating film 20.

[0045] In addition, in this embodiment, the shielding pad 18a is wound around the unit part 1 in a manner that surrounds it. Figure 2 In the image, for ease of understanding, a shading line has been applied to the shielding pad 18a.

[0046] Furthermore, an interlayer insulating film 21, composed of an oxide film or the like, is formed on one side 10a of the semiconductor substrate 10 to cover the gate electrode 19. And, in the interlayer insulating film 21, such as... Figure 3 As shown, a first contact hole 21a is formed that communicates with a contact trench 15 formed on the semiconductor substrate 10.

[0047] In this embodiment, the contact trench 15, the contact area 14b for the source region, and the contact area 13b for the body region are formed as follows.

[0048] That is, firstly, a first contact hole 21a is formed in the interlayer insulating film 21. Next, using the interlayer insulating film 21 as a mask, impurities constituting the source region contact region 14b are ion-implanted into the semiconductor substrate 10 through the first contact hole 21a to form the source region contact region 14b. Then, using the interlayer insulating film 21 as a mask, a contact trench 15 is formed that penetrates the source region contact region 14b and communicates with the first contact hole 21a. In other words, the source region contact region 14b and the contact trench 15 are formed using the same interlayer insulating film 21 as a mask. Therefore, the source region contact region 14b is formed around the contact trench 15.

[0049] Then, using the interlayer insulating film 21 as a mask again, impurities constituting the contact region 13b for the body region are ion-implanted into the bottom surface of the contact trench 15 to form the contact region 13b for the body region. In this embodiment, the contact trench 15, the contact region 14b for the source region, and the contact region 13b for the body region are formed in this way.

[0050] Furthermore, in the interlayer insulating film 21, such as Figure 4 As shown, a second contact hole 21b is formed in the outer peripheral portion 2, exposing the surface of the body region 13. In the interlayer insulating film 21, as... Figure 6 As shown, a third contact hole 21c is formed in the outer peripheral portion 2 to expose the gate electrode 19 and a fourth contact hole 21d to expose the shielding pad 18a.

[0051] Furthermore, an upper electrode 22, corresponding to the source electrode, a gate wiring 23, and a shielding wiring 24 are formed on the interlayer insulating film 21. Specifically, the upper electrode 22 is as follows: Figure 2 and Figure 3 As shown, in unit 1, it is electrically connected to body region 13 (i.e., body region contact region 13b) and source region 14 (i.e., source region contact region 14b) via first connection portion 22a. Furthermore, the first connection portion 22a is made of tungsten (W) inserts or the like and is embedded in the first contact hole 21a and contact trench 15 formed in the interlayer insulating film 21. In this embodiment, the upper electrode 22 corresponds to the first electrode.

[0052] Upper electrode 22 as Figure 4 As shown, the outer peripheral portion 2 is connected to the body region 13 via a second connecting portion 22b, such as a W plug, embedded in a second contact hole 21b formed in the interlayer insulating film 21. That is, the body region 13 formed in the outer peripheral portion 2 has a contact portion C that is connected to the upper electrode 22.

[0053] Furthermore, the gate wiring 23 is as follows Figure 6As shown, the wire is formed such that it is electrically connected to the gate electrode 19 via a W-type connector or similar connection portion 23a embedded in the third contact hole 21c formed in the interlayer insulating film 21. The shielding wiring 24 is formed such that it is electrically connected to the shielding electrode 18 via a W-type connector or similar connection portion 24a embedded in the fourth contact hole 21d formed in the interlayer insulating film 21. Furthermore, Figure 2 In order to make it easier to understand, shading lines are applied to the contact portion C in the body region 13 that is connected to the upper electrode 22, the portion in the gate electrode 19 that is connected to the gate wiring 23, and the portion in the shield electrode 18 that is connected to the shield wiring 24.

[0054] A lower electrode 25, corresponding to the drain electrode, is formed on the side of the substrate 11 opposite to the drift layer 12. That is, the lower electrode 25 is formed on the other side 10b of the semiconductor substrate 10. In this embodiment, the lower electrode 25 corresponds to the second electrode. With this structure, a vertical MOSFET of this embodiment is formed.

[0055] The above describes the structure of the semiconductor device according to this embodiment. Furthermore, in this embodiment, n - Type, n-type, n + p-type is equivalent to the first conductivity type, p-type, p-type + This type corresponds to the second conductivity type. Furthermore, in this embodiment, as described above, the semiconductor substrate 10 is constructed by including the substrate 11, the drift layer 12, the bulk region 13, the source region 14, etc.

[0056] Next, the operation and effect of the aforementioned semiconductor device will be explained. First, like a typical MOSFET, this semiconductor device forms a channel in the body region 13 connected to the gate trench 16 by applying a predetermined voltage to the gate electrode 19, allowing current to flow between the source and drain, thus becoming an on-state. Furthermore, if the voltage applied to the gate electrode 19 falls below the predetermined voltage, the channel formed in the body region 13 disappears, the current is cut off, and the device becomes an off-state.

[0057] Furthermore, in such a semiconductor device, a parasitic bipolar transistor is formed by the drift layer 12, the body region 13, and the source region 14. Therefore, in such a semiconductor device, when changing from the on state to the off state, the parasitic bipolar transistor may operate through avalanche action, resulting in an excessive current flowing between the source and drain.

[0058] Therefore, in the semiconductor device of this embodiment, the body region 13 extends to the outer periphery 2. Furthermore, in the outer periphery 2, the body region 13 has a contact portion C that is electrically connected to the upper electrode 22. In other words, the upper electrode 22 is connected to the contact portion C of the body region 13 in the outer periphery 2. Therefore, when the semiconductor device undergoes avalanche operation, holes can be easily extracted from the upper electrode 22 via the contact portion C in the outer periphery 2. This suppresses the operation of parasitic bipolar transistors, improves avalanche tolerance, and thus increases the withstand voltage of the semiconductor device.

[0059] Furthermore, in this embodiment, the contact trench 15 and the source region are formed to the outer peripheral portion 2 using the contact region 14b. Therefore, when the semiconductor device undergoes an avalanche operation, holes generated in the outer peripheral portion 2 can be easily extracted from the source region formed in the outer peripheral portion 2 using the contact region 14b. As a result, the operation of parasitic bipolar transistors can be suppressed, and avalanche tolerance can be further improved.

[0060] Here, it is also possible to improve avalanche resistance by making the protruding length of the contact groove 15 protruding outward from the periphery 2 longer, so as not to form the contact portion C. For example, it is also possible to improve avalanche resistance by making the contact groove 15 protrude to the vicinity of the portion forming the contact portion C in this embodiment, so as not to form the contact portion C.

[0061] However, in this embodiment, when forming the contact region 14b for the source region, the mask used to form the contact region 14b and the mask used to form the contact trench 15 are the same mask. Furthermore, the contact region 14b for the source region is formed around the contact trench 15. Therefore, when the protrusion length of the contact trench 15 protruding outwards from the outer periphery 2 is relatively long, the protrusion length of the contact region 14b for the source region protruding outwards from the outer periphery 2 also becomes longer.

[0062] Furthermore, when the semiconductor device is turned on, current flows between the source and drain. In this case, such as Figure 8 As shown, current flows in the main path R1 in the order of substrate 11, drift layer 12, bulk region 13, source region 14, and source region contact region 14b. Furthermore, current flows in the parasitic path R2 in the order of drift layer 12, bulk region 13, and source region contact region 14b. The main path R1 is where current flows only in the cell portion 1, while the parasitic path R2 is where current flows through the outer periphery 2. Moreover, by making the protrusion length of the source region contact region 14b protruding outwards into the outer periphery 2 longer, the current flowing in the parasitic path R2 increases, while the current flowing through the main path R1 decreases.

[0063] In this case, the sensing unit region Rs is extremely small in area compared to the main unit region Rm, as described above. Therefore, the current deviation caused by the increase in current through the parasitic path R2 compared to the main unit region Rm can no longer be ignored. Thus, as in this embodiment, by connecting the body region 13 to the upper electrode 22 in the outer peripheral portion 2, the reduction in current flowing through the unit portion 1 can be suppressed, and avalanche tolerance can be improved. That is, the reduction in current flowing through the sensing unit region Rs of the unit portion 1 can be suppressed, and avalanche tolerance can be improved. Therefore, in this embodiment, the decrease in current detection accuracy can be suppressed, and avalanche tolerance can be improved.

[0064] Furthermore, in the aforementioned semiconductor device, the gate insulating film 17b is thicker in the outer peripheral portion 2 than in the unit portion 1. That is, the gate insulating film 17b in the outer peripheral portion 2, which is prone to electric field concentration in the length direction during an avalanche operation, is thicker. Therefore, breakdown of the gate insulating film 17b can be suppressed, thereby improving avalanche tolerance.

[0065] According to the embodiment described above, the body region 13 extends into the outer peripheral portion 2. Furthermore, the body region 13 has a contact portion C electrically connected to the upper electrode 22 within the outer peripheral portion 2. Therefore, when the semiconductor device undergoes avalanche operation, holes can be easily extracted from the upper electrode 22 via the contact portion C within the outer peripheral portion 2. Thus, the operation of parasitic bipolar transistors can be suppressed, avalanche tolerance can be improved, and consequently, the withstand voltage of the semiconductor device can be increased.

[0066] Furthermore, by connecting the body region 13 and the upper electrode 22 in the outer peripheral portion 2, compared to the case where the protrusion length of the contact groove 15 protruding outward into the outer peripheral portion 2 is longer, it is possible to suppress the reduction of current flowing through the unit portion 1 and improve avalanche resistance. In this case, in particular, it is possible to reduce the rate of reduction of current flowing through the sensing unit region Rs.

[0067] Furthermore, in this embodiment, the outer peripheral portion 2 of the gate insulating film 17b is thicker than the unit portion 1. That is, the gate insulating film 17b of the outer peripheral portion 2, which is prone to electric field concentration in the length direction during an avalanche operation, is thicker. Therefore, breakdown of the gate insulating film 17b can be suppressed, thereby improving avalanche tolerance.

[0068] (Other implementation methods)

[0069] This disclosure describes embodiments, but it should be understood that this disclosure is not limited to these embodiments and structures. This disclosure also includes various modifications and variations within the same range. Furthermore, various combinations and forms, and even combinations and forms containing only one element, or more or less thereof, also fall within the scope and spirit of this disclosure.

[0070] For example, in the first embodiment described above, a MOSFET with an n-channel trench gate structure, where the first conductivity type is n-type and the second conductivity type is p-type, was described as an example of a semiconductor device. However, this is only one example, and other semiconductor devices with different structures can also be described, such as a p-channel trench gate MOSFET where the conductivity types of each component are reversed relative to the n-channel type. Furthermore, in addition to MOSFETs, semiconductor devices can also be IGBTs with the same structure. In the case of IGBTs, in addition to the n-channel type described in the first embodiment... + The substrate 11 of type 11 is changed to P + Apart from the collector layer, it is the same as the vertical MOSFET described in the first embodiment above.

[0071] Furthermore, in the first embodiment described above, the gate insulating film 17b may also be provided with the same thickness in the cell portion 1 and the outer peripheral portion 2.

Claims

1. A semiconductor device comprising a semiconductor element having a trench gate structure with dual gates, characterized in that, It has a unit portion on which the aforementioned semiconductor element is formed and an outer peripheral portion surrounding the unit portion. The above-mentioned unit has: Drift layer of the first conductivity type; The first impurity region of the second conductivity type is formed on the aforementioned drift layer; The second impurity region of the first conductivity type is formed on the surface portion of the first impurity region within the first impurity region, and the impurity concentration is higher than that of the drift layer. The above-mentioned trench gate structure is configured as a dual gate by sequentially stacking a shielding electrode, an intermediate insulating film and a gate electrode in a strip-shaped arrangement of multiple gate trenches arranged in a strip-like manner with one direction as the length direction and penetrating from the second impurity region to the drift layer. A high-concentration layer of the first or second conductivity type is formed on the opposite side of the first impurity region, separated from the drift layer, and the impurity concentration is higher than that of the drift layer. An interlayer insulating film is disposed on the trench gate structure and the first impurity region and the second impurity region, and a first contact hole is formed that is connected to the first impurity region and the second impurity region. The first electrode is electrically connected to the second impurity region and the first impurity region via the first contact hole; and The second electrode is electrically connected to the aforementioned high-concentration layer. The first impurity region extends from the aforementioned unit portion to the aforementioned outer periphery portion. In the aforementioned interlayer insulating film, a second contact hole is formed in the portion of the outer periphery that is closer to the aforementioned unit portion in one direction, exposing the aforementioned first impurity region. The first electrode is electrically connected to the first impurity region in the outer peripheral portion via the second contact hole.

2. The semiconductor device as claimed in claim 1, characterized in that, Between the aforementioned trench grid structures, contact trenches are formed extending from the aforementioned unit portion to the aforementioned outer periphery in one of the aforementioned directions as their length direction, and penetrating the aforementioned second impurity region to reach the aforementioned first impurity region. Around the aforementioned contact groove, a second impurity region with a higher impurity concentration than the second impurity region is formed along the wall surface of the aforementioned contact groove. The first contact hole formed in the interlayer insulating film is connected to the contact trench.

3. The semiconductor device as claimed in claim 1, characterized in that, The aforementioned insulating film includes a gate insulating film disposed between the aforementioned gate trench and the aforementioned gate electrode. The portion of the gate insulating film located at the outer periphery is thicker than the portion located at the unit portion.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The aforementioned unit section has a main unit region and a sensing unit region that has the same structure as the main unit region, through which a smaller current flows than the current flowing in the main unit region.

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