Ranking network and ranking method

Abstract

Provided are a sorting network and a sorting method. The sorting network comprises: one or more complete sorting modules configured to sort a plurality of disordered sequences to obtain a plurality of ordered sequences; and one or more merge sorting modules configured to perform partial merge sorting on the plurality of ordered sequences to obtain a target ordered sequence. The one or more merge sorting modules are configured to perform partial merge sorting on the plurality of ordered sequences, which can simplify the sorting network, reduce the complexity of the sorting network, and help reduce power consumption.

Description

Technical Field

[0001] This application relates to the field of digital circuit technology, and more specifically, to a sorting network and sorting method. Background Technology

[0002] Sorting methods have wide applications in scientific and engineering fields such as computer science, communications, and semiconductors. Designing efficient sorting algorithms is fundamental to many algorithms. Sorting methods are the most basic algorithms, arranging disordered sequences into ordered sequences. Existing sorting algorithms are broadly classified into software sorting and hardware sorting. Commonly used hardware sorting networks include bitonic sorting, odd-even sorting, and pairwise sorting. Currently, using sorting networks for partial sorting consumes significant hardware resources, resulting in wasted power consumption. Summary of the Invention

[0003] This application provides a sorting network and a sorting method. The various aspects involved in this application embodiment are described below.

[0004] In a first aspect, a sorting network is provided, comprising: one or more fully sorted modules for sorting multiple disordered sequences to obtain multiple ordered sequences; and one or more merge sort modules for performing partial merge sort on the multiple ordered sequences to obtain a target ordered sequence.

[0005] Secondly, a sorting method is provided for use in a sorting network, the sorting network comprising: one or more fully sorted modules; one or more merge sorted modules; the sorting method comprising: sorting multiple disordered sequences to obtain multiple ordered sequences; and performing partial merge sort on the multiple ordered sequences to obtain a target ordered sequence.

[0006] This application employs one or more merge sort modules to partially merge sort multiple sequential sequences to obtain the target sequential sequence. Compared to traditional sorting methods, using a partial merge sort network simplifies the sorting network, reduces its complexity, and helps reduce power consumption and hardware resources. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a 16-bit bitonetic sorting network.

[0008] Figure 2 This is a schematic diagram of an 8-bit parity sorting network.

[0009] Figure 3 This is a schematic diagram of the merge sort framework.

[0010] Figure 4 This is a schematic diagram of a (4, 4, 8) merge network.

[0011] Figure 5 is a schematic diagram of a (32,8) full sorting network.

[0012] Figure 6 is a schematic diagram of a sorting network provided in the embodiments of the present application.

[0013] Figure 7 is Figure 6 a schematic diagram of a possible implementation of the sorting network.

[0014] Figure 8 is a schematic diagram of a (4,4,4) simplified bitonic merge network provided in the embodiments of the present application.

[0015] Figure 9 is a schematic diagram of a (32,8) simplified hybrid sorting network provided in the embodiments of the present application.

[0016] Figure 10 is Figure 9 a timing schematic diagram of full reuse of the sorting network.

[0017] Figure 11 is Figure 9 a timing schematic diagram of partial reuse of the sorting network.

[0018] Figure 12 is a schematic diagram of the relationship between hardware overhead and latency of a (128,8) simplified hybrid sorting network provided in the embodiments of the present application.

[0019] Figure 13 is a schematic flowchart of a sorting method provided in the embodiments of the present application. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

[0021] Sorting methods are widely used in scientific and engineering fields such as computer, communication and semiconductor, and designing efficient sorting algorithms is the basis of many algorithms. The sorting method is the most basic algorithm, which arranges a disordered sequence into an ordered sequence. For example, (N, M) sorting outputs M smallest elements in order from N disordered elements, where M ≤ N. When M = N, it is called full sorting, and when M < N, it is called partial sorting.

[0022] Existing sorting algorithms can be broadly categorized into software sorting and hardware sorting. Commonly used software sorting methods include bubble sort, quick sort, selection sort, insertion sort, and merge sort. In the hardware field, such as in application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs), sorting networks (SEs) are generally used to process data in parallel to reduce latency.

[0023] A sorting network is a comparison network in which the output sequence is monotonically increasing for any input sequence. Based on the comparison network model, a sorting network can perform multiple comparison operations simultaneously. A sorting network consists of lines and comparators; a line transmits a value from one location to another, and the input and output of the comparators are connected.

[0024] Commonly used hardware sorting methods based on sorting networks include: bitonic sorting, odd-even sorting, and pairwise sorting.

[0025] Bitone sort is based on Batcher's theorem. Any bitoneic sequence A of length N is divided into two equal halves, X and Y. Elements in X are compared one by one with elements in Y in their original order, i.e., element [i] is compared with element [i+N / 2] (i≤N / 2). The larger element is placed in the MAX sequence, and the smaller element is placed in the MIN sequence. The resulting MAX and MIN sequences are still bitoneic sequences, and any element in the MAX sequence is no less than any element in the MIN sequence. A bitoneic sequence is a sequence that is first monotonically increasing and then monotonically decreasing (or first monotonically decreasing and then monotonically increasing).

[0026] Figure 1 This is a schematic diagram of a 16-bit bitonic sorting network. (Example) Figure 1 As shown, the arrows represent comparison exchangers. After two data items pass through the comparison exchanger, the data at the tail of the arrow is the smaller data, and the data at the head of the arrow is the larger data. The input is a randomized sequence of 16 elements (data), and after multiple comparisons, the output is a sequential sequence of 16 elements (data).

[0027] Odd-even sorting, also known as odd-even transposition sorting, is a relatively simple sorting algorithm. Odd-even sorting performs two passes of sorting repeatedly on a sequence. For a data sequence of length N, the first pass of sorting selects all data item pairs, data item [i] and data item [i+1], where i is an odd number (j=1, 3, 5...). If the values of the data items are in inverted order, they are swapped. The second pass of sorting performs the same operation on all even-numbered data items (i=2, 4, 6...). These two passes of sorting are repeated until the entire sequence is ordered.

[0028] Figure 2 is a schematic diagram of an 8-bit odd-even sorting network. As shown in Figure 2 , the arrows represent compare-exchangers. After two pieces of data pass through the compare-exchanger, the data at the tail of the arrow is the smaller data, and the data at the head of the arrow is the larger data. The input is an out-of-order sequence with a length of 8, and the output is an ordered sequence with a length of 8.

[0029] For a specific algorithm, it is usually necessary to consider the complexity of the algorithm. The complexity of an algorithm is divided into time complexity and space complexity. Time complexity refers to the computational workload required to execute the algorithm, and is used to qualitatively describe the running time of the algorithm. Space complexity refers to the memory space required to execute the algorithm. To calculate the time complexity, the number of operation units of the algorithm is usually estimated, and each unit runs for the same time. Therefore, the total running time differs from the number of operation units of the algorithm by a constant coefficient. The time complexity of a sorting network can be measured by the number of comparators.

[0030] Corresponding to (2 n , 2 n ) complete sorting network, the bitonic sorting network requires 2 n―2 n(n+1) exchangers, while the odd-even sorting network requires fewer exchangers, which is 2 n―2 n(n+1)-(2 n―1 n-2 n +1) exchangers.

[0031] Both bitonic sorting and odd-even sorting are merge sorting. Merge sorting refers to merging two or more ordered sequences into one still ordered sequence. If two ordered sequences are merged into one ordered sequence, it is called two-way merge.

[0032] Hardware merge sorting networks usually merge two ordered sequences into one ordered sequence. The (p, q, l) merge outputs l maximum (minimum) ordered sequences from an ordered sequence of size p and an ordered sequence of size q. When l=p+q, it is called complete merge sorting; when l<p+q, it is called partial merge sorting. For example, (8, 8, 16) is complete merge sorting, and (8, 8, 8) is partial merge sorting.

[0033] Figure 3 This is a schematic diagram of the merge sort framework, applicable to bitonic sort and odd / even sort. For example... Figure 3 As shown, for an input random sequence of n elements (data), we first obtain two ordered sequences of equal length. In bitonic sort, the two ordered sequences are bitonic; in odd-even sort, the two ordered sequences are in the same order. Then, we perform merge sort on the two ordered sequences. After multiple levels of merge sort, the output is a sequential sequence of n elements (data).

[0034] It can be seen that a (2) n ,2 n The sorting can be decomposed into two (2) n―1 ,2 n―1 ) sequential sorting and a (2 n―1 ,2 n―1 ,2 n Merge sort problem. Specifically, merge sort... n Top 2 n―1 The elements and the last 2 n―1 Sort each element separately, and then combine the two groups of size 2. n―1 The sorting problem can be further recursively broken down into sorting multiple sequences of size 2 and multi-level merge sort.

[0035] The main difference between odd-even sorting and bitonic sorting lies in the difference in the merge network. Taking the (4, 4, 8) complete merge network as an example, we will illustrate the difference. Figure 4 This is a schematic diagram of a (4, 4, 8) merge network. (Example) Figure 4 As shown in diagram a, the input to the bitonic merge network is a bitonic sequence, meaning the upper half of the sequence is a sequential sequence of elements arranged in ascending order, and the lower half is a reverse sequence of elements arranged in descending order. After one stage of merge processing, for example, if the upper half of the sequence is the smallest half and the lower half is the largest half, then any element in the upper half of the sequence is no greater than any element in the lower half of the sequence. Figure 4 As shown in the parity merge network, the input to the parity merge network is two sets of sequential sequences.

[0036] For (2) n ,2 n ,2 n+1 Complete merge sort requires (n+1)^2 bitonic merge networks. n One comparator is needed, while the parity merge network requires (n+1)² comparators. n ―(2 n —1) comparators. It is evident that for a complete merge sort of the same specifications, a bitone merge network requires more comparators than an even-odd merge network.

[0037] Existing sorting networks typically use all submodules to output a fully sorted sequence. Figure 5 This is a schematic diagram of a (32, 8) fully sorted network. (See diagram below.) Figure 5 As shown, the two (8, 8, 16) merge sorts and one (16, 16, 32) merge sort in the merge sort part are all complete sorts.

[0038] In practical applications, it's not always necessary to sort all the data in a sequence; often, only the smallest subset of the sequence needs to be output. For (N, M) sorting, the input is an unordered sequence containing N elements, and the output is a sequential sequence consisting of the M smallest elements from the input sequence. However, existing sorting networks typically output fully sorted sequences, which consumes significant hardware resources and results in wasted power.

[0039] Therefore, developing a low-power partial sorting network scheme is a problem that needs to be solved.

[0040] Based on this, this application proposes a sorting network that simplifies the sorting network according to different sorting requirements, thereby reducing power consumption and hardware resources. Figure 6 This is a schematic diagram of the sorting network provided in an embodiment of this application. The following is in conjunction with... Figure 6 The sorting network of this application embodiment will be described in detail. The sorting network 600 can be, but is not limited to, a bitonic sort, an even-odd sort, and a pairwise sort. For example... Figure 6 As shown, the sorting network 600 may include a full sorting module 610 and a merge sorting module 620.

[0041] There can be one or more complete sorting modules 610. The complete sorting module 610 is used to sort multiple disordered sequences to obtain multiple ordered sequences, also known as ordered sequences. In some embodiments, the ordered sequences can be monotonically increasing sequences; in other embodiments, the ordered sequences can be monotonically decreasing sequences. In some embodiments, the multiple ordered sequences may include both monotonically increasing and monotonically decreasing sequences. For example, when using a bitonic sort, the multiple ordered sequences can be bitonic sequences. Similarly, when using an odd-even sort, the multiple ordered sequences can be monotonically increasing sequences.

[0042] The multiple sequential sequences obtained by the complete sorting module 610 are completely sorted sequences. The parameters of the multiple sequential sequences can be the same, that is, the number of input data and the number of output data are the same.

[0043] The number of ordered sequences depends on the parameters of the resulting ordered sequence. Typically, for (2... n ,2 m Before sorting and merging, we only need to keep the smallest value of 2. m If there are sequential sequences of data, then the number of sequential sequences can be 2.n―m For example, for a (32, 8) sort, only the sequence of the minimum 8 data points needs to be retained during each merge. In some implementations, the sequence of data points can be more than 2 before merging. m and less than 2 n / 2 indivual.

[0044] For example, when performing a (64, 8) partial sort, the full sorting module 610 sorts the disordered (or unordered) input sequence containing 64 data points, resulting in eight (8, 8) sequential sequences, each of which only needs to retain a minimum of eight data points. In some embodiments, four (16, 16) sequential sequences can also be obtained.

[0045] There can be one or more merge sort modules 620. The merge sort module 620 is used to perform partial merge sort on multiple sequential sequences to obtain the target sequential sequence.

[0046] The merge sort module 620 employs a merge sort method. In some implementations, one or more merge sort modules 620 may all be partial merge sort modules. In some embodiments, some of the multiple merge sort modules 620 may be partial merge sort modules. The merge sort module 620 may employ a bitonic merge sort or an odd-even merge sort.

[0047] The target sequence is the final desired output sequence. In some implementations, the target sequence can be the sequence of the smallest M data items. In other implementations, the target sequence can also be the sequence of the largest M data items.

[0048] The complete sorting module 610 and the merge sorting module 620 employ different sorting methods. The complete sorting module 610 uses a complete sorting method, while the merge sorting module 620 uses a partial merge sorting method. It should be understood that the complete sorting module 610 can use a merge sorting method in its sorting implementation.

[0049] In some implementations, the complete sorting module 610 and the merge sorting module 620 in the sorting network 600 can both be bitonic sorting modules or both be odd-even sorting modules. In some implementations, the complete sorting module 610 in the sorting network 600 can be a sorting module based on odd-even sorting, and the merge sorting module 620 can be a sorting module based on bitonic sorting.

[0050] In some implementations, some or all of the disordered sequences in multiple disordered sequences can reuse the same complete sorting module 610; and / or, some or all of the sequential sequences in multiple sequential sequences can reuse the same merge sorting module 620, which can save hardware resources and reduce the area occupied.

[0051] In some implementations, the sorting network 600 may also include a control module. The control module is used to control the processing timing of the full sorting module 610 and the merge sorting module 620, so that during the calculation of the target sequence, the full sorting module 610 and the merge sorting module 620 execute the sorting task simultaneously in at least one clock cycle, which can reduce the latency caused by reusing modules, etc.

[0052] This application employs one or more merge sort modules to partially merge sort multiple sequential sequences to obtain the target sequential sequence. Compared to traditional sorting methods, using a partial merge sort network simplifies the sorting network, reduces its complexity, and helps reduce power consumption and hardware resources.

[0053] Figure 7 yes Figure 6 A schematic diagram of one possible implementation of a sorting network. Figure 7 Let's take the (32, 8) partial sorting network as an example. For the (32, 8) partial sort, only the order sequence of the minimum 8 data points needs to be retained during each merge process. For example... Figure 7 As shown, the left side contains multiple complete sorting modules 710, which are four (8, 8) complete sequential sorting modules. The right side contains multiple merge sorting modules 720, which can include two levels of merging, where the first level of merging includes two (8, 8, 8) partial merge sorting modules, and the second level of merging includes one (8, 8, 8) partial merge sorting module.

[0054] refer to Figure 5 ,and Figure 5 Compared to the (32, 8) fully sorted network, the (8, 8, 16) fully merged and (16, 16, 32) fully merged networks can be simplified to the (8, 8, 8) partially merged network. This reduces the number of input data points involved in the comparison, thus reducing the number of comparators required and lowering computational complexity. For example, the 32 input data points from the (16, 16, 32) fully merged network are reduced to the 16 input data points from the (8, 8, 8) partially merged network.

[0055] Typically for (2) n ,2 m Before sorting and merging, you only need to keep 2. m The sequential sequence of the smallest data. Furthermore, for (2... n ,2 m In a partial merge sort network, there can be a total of (2 n―m ―1) of (2) m ,2 m ,2 m Partial merging module and 2 n―m (2) m ,2m ) full sorting module. For example, for a (32, 8) sorting network, there may be 3 (8, 8, 8) partial merging modules and 4 (8, 8) full sorting modules.

[0056] In some implementations, for partial merging, the network can be further simplified for a bitonic merging network. According to the characteristics of bitonic merging, the output of each stage can be divided into two parts of equal size, for example, the elements in the upper part are always smaller than the elements in the lower part. Therefore, for partial merging, if a bitonic merging network is adopted, only the upper half part of the network can be retained, and the lower half part of the network is no longer retained, which helps to further reduce power consumption and hardware overhead. Such a simplified bitonic merging network may be referred to as a simplified bitonic merging network to distinguish it from a conventional bitonic merging network. The simplified bitonic merging network is also referred to as a merging module based on bitonic sorting, or a sorting module based on bitonic sorting, which is not distinguished in the embodiments of the present application.

[0057] Figure 8 is a schematic diagram of a (4, 4, 4) simplified bitonic merging network provided by an embodiment of the present application. As shown in Figure 8 , the target output data of the (4, 4, 4) simplified bitonic merging network is the smallest 4 pieces, and after the first step of merging, the smallest 4 pieces are all located in the upper half of the sorting network. Therefore, in some embodiments, for partial merging, if a bitonic merging network is adopted, only the upper half part of the network can be retained to reduce power consumption and hardware overhead.

[0058] More generally, for a (2 n ,2 n ,2 m+1 ) simplified bitonic merging network, where m<n, 2 n+1 +(m-1)2 m comparators are required. For a (2 n ,2 n ,2 n+1 ) full merging network, the bitonic merging network requires (n+1)2 n comparators; the odd-even merging network requires (n+1)2 n -(2 n -1) comparators. That is, when m<n, the number of comparators using the simplified bitonic merging network is always less than that using the full merging network.

[0059] It is evident that for complete sorting, odd-even merge sort requires fewer hardware resources compared to bitonic merge sort. For partial merge sort, simplified bitonic merge networks require fewer hardware resources. Therefore, in some implementations, the merge sort module can use a simplified bitonic merge network (i.e., a merge module based on bitonic sorting) to further reduce power consumption and hardware overhead. For ease of distinction, in the embodiments of this application, sorting networks employing different sorting methods and simplified bitonic merge sorting are also referred to as simplified hybrid sorting networks.

[0060] In some implementations, the sorting network is a simplified hybrid sorting network, where the complete sorting module can be a sorting module based on parity sorting, and the merge sorting module can be a sorting module based on bitonic sorting (i.e., a simplified bitonic merge network).

[0061] Figure 9 This is a schematic diagram of the (32, 8) simplified hybrid sorting network provided in the embodiments of this application. The following is in conjunction with... Figure 9 The (32,8) simplified hybrid sorting network is illustrated as an example. The (32,8) simplified hybrid sorting network combines odd-even sorting and bitonic sorting. The complete sorting module consists of four (8,8) complete odd-even sorting algorithms, and the merge sort module consists of three (8,8,8) simplified bitonic merge sorting algorithms. Table 1 lists the number of comparators used in different sorting networks for the (32,8) sorting. As shown in Table 1, for the (32,8) sorting, it can be seen that the simplified hybrid sorting network has the fewest comparators, at 136.

[0062] Table 1

[0063] Number of comparators 240 191 136

[0064] More generally, for (2) n ,2 m For partial sorting, the number of comparators required for a simplified hybrid sorting network is 2. n―m (2 m―2 m(m+1)―(2 m―1 m―2 m +1))+(2 m +2 m―1 m)(2 n―m ―1).

[0065] In some implementations, for (2) n ,2 m Partial sorting, simplifying hybrid sorting networks typically requires two basic computational units (2...). m ,2 m Odd-even sorting and (2) m ,2 m ,2 m Bitone merge sort. Among them, (2) m,2 m Odd-even sorting requires 2 m―2 m(m+1)―(2 m―1 m―2 m +1) comparators; (2) m ,2 m ,2 m Bitone merging requires 2 m +2 m―1 There are m comparators. Among them, multiple (2) m ,2 m The odd-even sorting has the same specification, and multiple (2) m ,2 m ,2 m The specifications for bitone merging are also the same. Sorting units with the same specifications can be reused to further reduce hardware overhead, allowing hardware resources to be used serially to implement the sorting network.

[0066] In some implementations, some or all of the out-of-order sequences in multiple out-of-order sequences can reuse the same complete sorting module; and / or, some or all of the sequential sequences in multiple sequential sequences can reuse the same merge sorting module, which helps to further save hardware resources and reduce the area occupied.

[0067] Reusing sorting units can reduce hardware overhead, but it can also increase processing latency. Therefore, during the design process, the reuse method can be reasonably designed to achieve a balance and trade-off between hardware overhead and latency.

[0068] In some implementations, the sorting network may also include a control module. The control module is used to control the processing timing of the full sorting module and the merge sorting module, so that during the calculation of the target sequence, the full sorting module and the merge sorting module execute the sorting task simultaneously in at least one clock cycle, which can reduce the latency caused by reuse modules, etc.

[0069] Combination Figure 9 It can be seen that different (2) m ,2 m The odd-even sorting module is parallel and has no data dependencies. The input to the merge network is the data from the previous stage, such as (2 m ,2 m ,2 m The input to the bitone merge network is (2 m ,2 m The output data of the odd-even sorting module has data dependencies. (2) m ,2 m ,2 m In a bitone merging network, the peers are parallel, but the input of the subsequent merging network is the output data of the previous stage, which has a data dependency relationship.

[0070] In some implementations, the sorting network can be fully reused. Only one (2) can be used. m ,2 m ) odd-even sorting unit and a (2 m ,2 m ,2 m Bi-tuned merging unit. Required delay is 2. n―m +2 n―m ―1, of which 2 n―m It is the time delay required for a complete sorting unit, 2 n―m -1 is the delay required for some merged units.

[0071] In some implementations, the sorting network can be partially reused. Multiple (2) m ,2 m ) odd-even sorting unit and a (2 m ,2 m ,2 m Bitone merging unit. Assume using 2 h (2) m ,2 m Odd / even sorting unit and 2 k Two parallel (level) m ,2 m ,2 m Partial bimodal merging unit. Required delay is 2. n―m―k +2 n―m―k ―1+k, where 2 n―m―k It is the time delay required for a complete sorting unit, 2 n―m―k -1+k is the time delay required for a partial merge unit. Here, h and k are called the parallelism of the odd-even sorting network and the bitonic merge network, respectively.

[0072] See Figure 9 The simplified (32,8) hybrid sorting network can compute the (8,8,8) bitonic merge sort of the upper half while computing the two (8,8) parity sorts of the lower half. Therefore, reused sorting units can be processed in the same time to reduce latency.

[0073] Figure 10 yes Figure 9 A timing diagram illustrating the complete reuse of a sorting network. (e.g.) Figure 10 As shown, the (32, 8) simplified hybrid sorting network, when fully reused, has a parallelism of k = 1 and h = 1. The timing diagram can also be visualized as using a pipelined approach. In timing period 3, while calculating the two (8, 8) parity sorts in the lower half, the (8, 8, 8) bitone merging in the upper half can be calculated simultaneously. This reduces the latency of the (32, 8) simplified hybrid sorting network from 7 to 6.

[0074] More generally, for (2) n ,2 m The simplified hybrid sorting network has a latency of 2 for full reuse. n―m +(n―m).

[0075] It can be seen that, in order to effectively utilize time sequences, the parallelism of a partial merge network is less than that of a fully sorted network. Otherwise, while the partial merge network computes faster, it requires a longer wait time for the fully sorted network to output data. In some implementations, when partially reusing sorting units, if 2 h (2) m ,2 m Odd-even sorting network and 2 h Two parallel (level) m ,2 m ,2 m Partial bimodal merge network with a latency of 2 n―m―h +(n―m).

[0076] Figure 11 yes Figure 9 A timing diagram illustrating partial multiplexing in a sorting network. The parallelism degree is k = 2, and h = 1. When partial multiplexing is used, 2(2) m ,2 m ) odd-even sorting unit and 1 parallel (2 m ,2 m ,2 m Some bitone merging units can be processed in the same time sequence. For example... Figure 11 As shown, in time period 2, two (8,8) odd-even sorting units and one parallel (8,8,8) partially bitone merging unit can be processed in the same time, which can reduce the latency of the (32,8) simplified hybrid sorting network from 5 to 4.

[0077] It should be understood that the partial merge sorting network and simplified hybrid sorting network in the embodiments of this application can reduce power consumption and hardware overhead without increasing latency. However, the multiplexing sorting unit in the embodiments of this application increases processing latency and reduces hardware overhead. The timing optimization method can reduce latency for specific multiplexing methods.

[0078] Table 2 shows the number of comparators used by different sorting methods for sorting networks with different parameters. As shown in Table 2, the bitonic sorting method and the parity sorting method are conventional sorting methods. The simplified hybrid method and the fully reused method are two special cases provided in the embodiments of this application. The simplified hybrid method does not reuse sorting units, while the fully reused method uses fully reused sorting units. It can be seen that for any part of the sorting, the simplified hybrid sorting network method provided in the embodiments of this application uses fewer comparators than the traditional bitonic sorting method and the parity sorting method. For any part of the sorting, the fully reused sorting network method uses the fewest comparators. Using the simplified hybrid sorting network method provided in the embodiments of this application can effectively reduce power consumption and hardware overhead without increasing latency. If the fully reused method is used, hardware overhead can be further reduced while increasing latency.

[0079] Table 2

[0080] Sort (32, 8) 240 191 136 39 Sort (64, 8) 672 543 292 39 Sort (64, 16) 672 543 396 111 Sort by (128, 8) 1792 1471 604 39 Sort by (128, 16) 1792 1471 840 111 Sort by (128, 32) 1792 1471 1100 303

[0081] When using partial multiplexing, latency and hardware overhead are usually negatively correlated; that is, the higher the hardware overhead, the lower the latency. Figure 12 This is a schematic diagram illustrating the relationship between hardware overhead and latency in a simplified hybrid sorting network (128, 8) provided in an embodiment of this application. Figure 12 As shown, the horizontal axis represents latency (period), and the vertical axis represents hardware overhead (number of comparators). For example, when the latency is 1, the number of comparators is 600; when the latency is greater than 12, the number of comparators drops to below 100. It can be seen that when using a partially reused sorting network, the reuse rate of the simplified sorting network can be reasonably designed according to the specific latency and hardware overhead requirements to achieve a balance between latency and hardware overhead.

[0082] It should be understood that the simplified hybrid sorting network of this application embodiment is also applicable to general sorting scenarios where the number of inputs and outputs is not a power of 2. The general sorting problem where the number of inputs and outputs is not a power of 2 can be solved by padding. In some embodiments, padding (e.g., padding with all zeros) can be used to pad sequences where the maximum number of inputs is not a power of 2 to a power of 2.

[0083] The above text combined Figures 1 to 12 The device embodiments of this application have been described in detail below, in conjunction with... Figure 13 The method embodiments of this application are described in detail below. It should be understood that the description of the method embodiments corresponds to the description of the apparatus embodiments; therefore, any parts not described in detail can be referred to the foregoing apparatus embodiments.

[0084] Figure 13This is a flowchart illustrating the sorting method provided in an embodiment of this application. The sorting method is applied to a sorting network, which may include one or more full sorting modules and one or more merge sorting modules.

[0085] Figure 13 The sorting method may include steps S1310 to S1320, which are described in detail below.

[0086] In step S1310, the multiple disordered sequences are sorted to obtain multiple ordered sequences.

[0087] In step S1320, a partial merge sort is performed on multiple sequential sequences to obtain the target sequential sequence.

[0088] Optionally, the complete sorting module and the merge sorting module in the sorting network use different sorting methods.

[0089] Optionally, the complete sorting module in the sorting network is a sorting module based on parity sorting; the merge sorting module is a sorting module based on bitonic sorting. In some embodiments, the sorting module based on parity sorting can sort multiple disordered sequences to obtain multiple ordered sequences; the sorting module based on bitonic sorting (simplified bitonic sorting module) performs partial merge sorting on the multiple ordered sequences.

[0090] Optionally, some or all of the disordered sequences in multiple disordered sequences may reuse the same complete sorting module; and / or, some or all of the sequential sequences in multiple sequential sequences may reuse the same merge sorting module.

[0091] Optionally, the sorting method further includes controlling the processing timing of the full sorting module and the merge sorting module, such that during the calculation of the target sequence, the full sorting module and the merge sorting module execute the sorting task simultaneously in at least one clock cycle.

[0092] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any other combination. When implemented in software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this disclosure are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a machine-readable storage medium or transmitted from one machine-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The machine-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs (DVDs)), or semiconductor media (e.g., solid-state drives (SSDs)).

[0093] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments of this disclosure can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0094] In the several embodiments provided in this disclosure, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0095] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0096] In addition, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0097] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A sorting network, characterized in that, The sorting network is applied to an application-specific integrated circuit (ASIC) and / or a field-programmable gate array (FPGA), wherein the ASIC and / or the FPGA comprises: One or more fully sorted modules, wherein each fully sorted module includes a first comparator network formed by connecting multiple comparators in a topology of parity sorting, the first comparator network being used to sort multiple disordered sequences to obtain multiple ordered sequences; One or more merge sort modules, wherein each merge sort module includes a second comparator network formed by multiple comparators in a bitonic sort topology, the second comparator network being used to perform partial merge sort on the multiple sequential sequences to obtain a target sequential sequence, wherein the number of comparators included in the second comparator network is less than the number of comparators required to perform a complete merge sort on the multiple sequential sequences. The merge sort module performs partial merge sort based on a simplified bitonic sorting network. The output of the partial merge sort is different from that of the complete merge sort. The result of the complete merge sort includes an upper half sequence and a lower half sequence. No element in the upper half sequence is greater than any element in the lower half sequence. The result of the partial merge sort only includes the upper half sequence.

2. The sorting network according to claim 1, characterized in that, The complete sorting module and the merge sorting module use different sorting methods.

3. The sorting network according to claim 2, characterized in that, The complete sorting module is a sorting module based on odd-even sorting; the merge sorting module is a sorting module based on bitonic sorting.

4. The sorting network according to claim 1, characterized in that, Some or all of the disordered sequences in the plurality of disordered sequences reuse the same complete sorting module; and / or Some or all of the sequential sequences in the plurality of sequential sequences reuse the same merge sort module.

5. The sorting network according to claim 4, characterized in that, The sorting network also includes: The control module is used to control the processing timing of the full sorting module and the merge sorting module, so that during the calculation of the target sequence, the full sorting module and the merge sorting module execute sorting tasks simultaneously in at least one clock cycle.

6. A sorting method, characterized in that, Applications to Application-Specific Integrated Circuits (ASICs) and / or Field-Programmable Gate Arrays (FPGAs), wherein the ASIC and / or the FPGA comprises: One or more fully sorted modules, each fully sorted module comprising a first comparator network formed by connecting multiple comparators in a topology sorted by parity; One or more merge sort modules, each merge sort module including a second comparator network consisting of multiple comparators arranged in a bitone sort topology; The sorting method includes: The first comparator network sorts multiple disordered sequences to obtain multiple ordered sequences; The second comparator network performs partial merge sorting on the plurality of sequential sequences to obtain the target sequential sequence; The number of comparators in the second comparator network is less than the number of comparators required to perform a complete merge sort on the plurality of sequential sequences. The merge sort module performs the partial merge sort based on a simplified bitonic sorting network. The output of the partial merge sort is different from the result of the complete merge sort. The result of the complete merge sort includes an upper half sequence and a lower half sequence. No element in the upper half sequence is greater than any element in the lower half sequence. The result of the partial merge sort only includes the upper half sequence.

7. The sorting method according to claim 6, characterized in that, The complete sorting module and the merge sorting module use different sorting methods.

8. The sorting method according to claim 7, characterized in that, The complete sorting module is a sorting module based on odd-even sorting; the merge sorting module is a sorting module based on bitonic sorting.

9. The sorting method according to claim 6, characterized in that, Some or all of the disordered sequences in the plurality of disordered sequences reuse the same complete sorting module; and / or Some or all of the sequential sequences in the plurality of sequential sequences reuse the same merge sort module.

10. The sorting method according to claim 9, characterized in that, The sorting method further includes: The processing timing of the full sorting module and the merge sorting module is controlled so that, during the calculation of the target sequence, the full sorting module and the merge sorting module simultaneously perform sorting tasks in at least one clock cycle.

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